Changeset 99956 in vbox for trunk/src/VBox/VMM

Timestamp:

May 24, 2023 11:39:15 AM (21 months ago)

Author:

vboxsync

Message:

VMM/CPUM-armv8: Implement OSDLR_EL1, OSLAR_EL1 and OSLSR_EL1 accessed by Linux guests, bugref:10387

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/CPUMAllSysRegs-armv8.cpp (modified) (7 diffs)
• VMMR3/CPUM-armv8.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMAll/CPUMAllSysRegs-armv8.cpp

@@ -37 +37 @@
 #include <VBox/err.h>
 
+#include <iprt/armv8.h>
+
 
 /*********************************************************************************************************************************
@@ -160 +162 @@
 
 
+
+/** @callback_method_impl{FNCPUMRDSYSREG} */
+static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_OslsrEl1(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue)
+{
+    RT_NOREF(idSysReg, pRange);
+    *puValue = pVCpu->cpum.s.Guest.fOsLck ? ARMV8_OSLSR_EL1_AARCH64_OSLK : 0;
+    return VINF_SUCCESS;
+}
+
+
+/** @callback_method_impl{FNCPUMWRSYSREG} */
+static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_OslarEl1(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue)
+{
+    RT_NOREF(idSysReg, pRange, uRawValue);
+    Assert(!(uValue & ~ARMV8_OSLAR_EL1_AARCH64_OSLK));
+    pVCpu->cpum.s.Guest.fOsLck = RT_BOOL(uValue);
+    return VINF_SUCCESS;
+}
+
+
 /**
  * System register read function table.
@@ -170 +192 @@
     { cpumSysRegRd_WriteOnly },
     { cpumSysRegRd_GicV3Icc  },
+    { cpumSysRegRd_OslsrEl1  },
 };
 
@@ -183 +206 @@
     { NULL }, /* Alias */
     { cpumSysRegWr_GicV3Icc },
+    { cpumSysRegWr_OslarEl1 },
 };
 
@@ -402 +426 @@
         STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWrites);
         STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWritesUnknown);
-        rcStrict = VERR_CPUM_RAISE_GP_0;
+        rcStrict = VERR_CPUM_RAISE_GP_0; /** @todo Better status code. */
     }
     return rcStrict;
@@ -425 +449 @@
     CPUM_ASSERT_RD_SYSREG_FN(WriteOnly);
     CPUM_ASSERT_RD_SYSREG_FN(GicV3Icc);
+    CPUM_ASSERT_RD_SYSREG_FN(OslsrEl1);
 
     AssertReturn(g_aCpumWrSysRegFns[kCpumSysRegWrFn_Invalid].pfnWrSysReg == NULL, VERR_CPUM_IPE_2);
@@ -430 +455 @@
     CPUM_ASSERT_WR_SYSREG_FN(ReadOnly);
     CPUM_ASSERT_WR_SYSREG_FN(GicV3Icc);
+    CPUM_ASSERT_WR_SYSREG_FN(OslarEl1);
 
     return VINF_SUCCESS;

trunk/src/VBox/VMM/VMMR3/CPUM-armv8.cpp

@@ -71 +71 @@
 
 /*********************************************************************************************************************************
+*   Defined Constants And Macros                                                                                                 *
+*********************************************************************************************************************************/
+
+/** Internal form used by the macros. */
+#ifdef VBOX_WITH_STATISTICS
+# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
+    { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
+      { 0 }, { 0 }, { 0 }, { 0 } }
+#else
+# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
+    { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
+#endif
+
+/** Function handlers, extended version. */
+#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
+    RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
+/** Function handlers, read-only. */
+#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
+    RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
+/** Read-only fixed value, ignores all writes. */
+#define MVI(a_uMsr, a_szName, a_uValue) \
+    RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_FixedValue, kCpumSysRegWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
+
+
+/*********************************************************************************************************************************
 *   Structures and Typedefs                                                                                                      *
 *********************************************************************************************************************************/
@@ -103 +128 @@
 *   Global Variables                                                                                                             *
 *********************************************************************************************************************************/
+/**
+ * System register ranges.
+ */
+static CPUMSYSREGRANGE const g_aSysRegRanges[] =
+{
+    MFX(ARMV8_AARCH64_SYSREG_OSLAR_EL1, "OSLAR_EL1", WriteOnly, OslarEl1, 0, UINT64_C(0xfffffffffffffffe), UINT64_C(0xfffffffffffffffe)),
+    MFO(ARMV8_AARCH64_SYSREG_OSLSR_EL1, "OSLSR_EL1", OslsrEl1),
+    MVI(ARMV8_AARCH64_SYSREG_OSDLR_EL1, "OSDLR_EL1", 0)
+};
+
+
 #if 0 /** @todo Will come later. */
 /** Saved state field descriptors for CPUMCTX. */
@@ -185 +221 @@
 
 /**
+ * Initializes the guest system register states.
+ *
+ * @returns VBox status code.
+ * @param   pVM         The cross context VM structure.
+ */
+static int cpumR3InitSysRegs(PVM pVM)
+{
+    for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges); i++)
+    {
+        int rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges[i]);
+        AssertLogRelRCReturn(rc, rc);
+    }
+
+    return VINF_SUCCESS;
+}
+
+
+/**
  * Initializes the CPUM.
  *
@@ -228 +282 @@
 
     rc = cpumR3DbgInit(pVM);
+    if (RT_FAILURE(rc))
+        return rc;
+
+    /*
+     * Initialize the Guest system register states.
+     */
+    rc = cpumR3InitSysRegs(pVM);
     if (RT_FAILURE(rc))
         return rc;