Changeset 99984 in vbox for trunk/src/VBox/VMM/include

Timestamp:

May 26, 2023 1:20:46 AM (21 months ago)

Author:

vboxsync

Message:

VMM/IEM: Fixed a few places in IEMAllCImpl.cpp and IEMAllCImplSvmInstr.cpp where decoder state was used directly instead of being passed as arguments. bugref:10369

Location:

trunk/src/VBox/VMM/include

Files:

• IEMInline.h (modified) (2 diffs)
• IEMInternal.h (modified) (8 diffs)

trunk/src/VBox/VMM/include/IEMInline.h

@@ -2368 +2368 @@
 
 
-#ifndef IEM_WITH_OPAQUE_DECODER_STATE
-/**
- * Updates the FOP, FPU.CS and FPUIP registers.
+/**
+ * Updates the FOP, FPU.CS and FPUIP registers, extended version.
  *
  * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
  * @param   pFpuCtx             The FPU context.
- */
-DECLINLINE(void) iemFpuUpdateOpcodeAndIpWorker(PVMCPUCC pVCpu, PX86FXSTATE pFpuCtx) RT_NOEXCEPT
-{
-    Assert(pVCpu->iem.s.uFpuOpcode != UINT16_MAX);
-    pFpuCtx->FOP = pVCpu->iem.s.uFpuOpcode;
+ * @param   uFpuOpcode          The FPU opcode value (see IEMCPU::uFpuOpcode).
+ */
+DECLINLINE(void) iemFpuUpdateOpcodeAndIpWorkerEx(PVMCPUCC pVCpu, PX86FXSTATE pFpuCtx, uint16_t uFpuOpcode) RT_NOEXCEPT
+{
+    Assert(uFpuOpcode != UINT16_MAX);
+    pFpuCtx->FOP = uFpuOpcode;
     /** @todo x87.CS and FPUIP needs to be kept seperately. */
     if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
@@ -2395 +2395 @@
         *(uint64_t *)&pFpuCtx->FPUIP = pVCpu->cpum.GstCtx.rip;
 }
+
+
+#ifndef IEM_WITH_OPAQUE_DECODER_STATE
+/**
+ * Updates the FOP, FPU.CS and FPUIP registers.
+ *
+ * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
+ * @param   pFpuCtx             The FPU context.
+ */
+DECLINLINE(void) iemFpuUpdateOpcodeAndIpWorker(PVMCPUCC pVCpu, PX86FXSTATE pFpuCtx) RT_NOEXCEPT
+{
+    Assert(pVCpu->iem.s.uFpuOpcode != UINT16_MAX);
+    iemFpuUpdateOpcodeAndIpWorkerEx(pVCpu, pFpuCtx, pVCpu->iem.s.uFpuOpcode);
+}
 #endif /* !IEM_WITH_OPAQUE_DECODER_STATE */
-
-
 
 

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -3816 +3816 @@
  *  NRIP if needed.
  */
-# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
+# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
     do \
     { \
         if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
         { \
-            IEM_SVM_UPDATE_NRIP(a_pVCpu); \
+            IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
             IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
         } \
@@ -3827 +3827 @@
 
 /** Checks and handles SVM nested-guest CR0 read intercept. */
-# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
+# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
     do \
     { \
@@ -3834 +3834 @@
         else \
         { \
-            IEM_SVM_UPDATE_NRIP(a_pVCpu); \
+            IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
             IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
         } \
@@ -3842 +3842 @@
  * Updates the NextRIP (NRI) field in the nested-guest VMCB.
  */
-# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
+# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
     do { \
         if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
-            CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
+            CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
     } while (0)
 
 #else
-# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)                              (false)
-# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr)                                 (false)
-# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr)                                (false)
-# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr)                                 (false)
-# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr)                                (false)
-# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector)                                (false)
-# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2)             do { return VERR_SVM_IPE_1; } while (0)
-# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg)            do { return VERR_SVM_IPE_1; } while (0)
-# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2)   do { } while (0)
-# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2)                          do { } while (0)
-# define IEM_SVM_UPDATE_NRIP(a_pVCpu)                                                     do { } while (0)
+# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)                                (false)
+# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr)                                   (false)
+# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr)                                  (false)
+# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr)                                   (false)
+# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr)                                  (false)
+# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector)                                  (false)
+# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2)               do { return VERR_SVM_IPE_1; } while (0)
+# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg)              do { return VERR_SVM_IPE_1; } while (0)
+# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
+                                       a_uExitInfo1, a_uExitInfo2, a_cbInstr)               do { } while (0)
+# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr)   do { } while (0)
+# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr)                                            do { } while (0)
 
 #endif
@@ -4178 +4179 @@
 IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
 IEM_CIMPL_PROTO_0(iemCImpl_syscall);
-IEM_CIMPL_PROTO_0(iemCImpl_sysret);
+IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
 IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
 IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
@@ -4219 +4220 @@
 IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
 IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
-IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
-IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
-IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
-IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
+IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
+IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
+IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
+IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
 IEM_CIMPL_PROTO_0(iemCImpl_cli);
 IEM_CIMPL_PROTO_0(iemCImpl_sti);
@@ -4256 +4257 @@
 IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
 IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
-IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
-IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
+IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
+IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, uint32_t, uPopAndFpuOpcode);
 /** @} */
 
@@ -4450 +4451 @@
 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
 VBOXSTRICTRC    iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
-VBOXSTRICTRC    iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
+VBOXSTRICTRC    iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
 VBOXSTRICTRC    iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
                                         uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
-VBOXSTRICTRC    iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
+VBOXSTRICTRC    iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
 IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
 IEM_CIMPL_PROTO_0(iemCImpl_vmload);