/* $Id: bs3-cpu-instr-3.c32 106300 2024-10-12 04:40:07Z vboxsync $ */ /** @file * BS3Kit - bs3-cpu-instr-3 - MMX, SSE and AVX instructions, C code template. */ /* * Copyright (C) 2007-2024 Oracle and/or its affiliates. * * This file is part of VirtualBox base platform packages, as * available from https://www.virtualbox.org. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation, in version 3 of the * License. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, see . * * The contents of this file may alternatively be used under the terms * of the Common Development and Distribution License Version 1.0 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included * in the VirtualBox distribution, in which case the provisions of the * CDDL are applicable instead of those of the GPL. * * You may elect to license modified versions of this file under the * terms and conditions of either the GPL or the CDDL or both. * * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0 */ /********************************************************************************************************************************* * Header Files * *********************************************************************************************************************************/ #include #include "bs3-cpu-instr-3-asm-auto.h" #include #include /********************************************************************************************************************************* * Defined Constants And Macros * *********************************************************************************************************************************/ /** Converts an execution mode (BS3_MODE_XXX) into an index into an array * initialized by BS3CPUINSTR3_TEST1_MODES_INIT, * BS3CPUINSTR3_TEST2_MODES_INIT, BS3CPUINSTR3_TEST3_MODES_INIT, ... . */ #define BS3CPUINSTR3_TEST_MODES_INDEX(a_bMode) (BS3_MODE_IS_16BIT_CODE(bMode) ? 0 : BS3_MODE_IS_32BIT_CODE(bMode) ? 1 : 2) /********************************************************************************************************************************* * Structures and Typedefs * *********************************************************************************************************************************/ /** Instruction set type and operand width. */ typedef enum { T_INVALID, T_MMX, T_MMX_SSE, /**< MMX instruction, but require the SSE CPUID to work. */ T_MMX_SSE2, /**< MMX instruction, but require the SSE2 CPUID to work. */ T_MMX_SSSE3, /**< MMX instruction, but require the SSSE3 CPUID to work. */ T_AXMMX, T_AXMMX_OR_SSE, T_SSE, T_128BITS = T_SSE, T_SSE2, T_SSE3, T_SSSE3, T_SSE4_1, T_SSE4_2, T_SSE4A, T_PCLMUL, T_SHA, T_AVX_128, T_AVX2_128, T_AVX_PCLMUL, T_AVX_256, T_256BITS = T_AVX_256, T_AVX2_256, T_MAX } INPUT_TYPE_T; /** Memory or register rm variant. */ enum { RM_REG = 0, RM_MEM, RM_RANGE, /**< Instruction may fault anywhere within the memory address range. Hack for vmaskmov[sd], vpmaskmov[dq]. */ RM_MEM_DI, /**< Memory operand pointer is implicitly RDI and may fault anywhere in range. Hack for maskmovq, [v]maskmovdqu. */ RM_MEM8, /**< Memory operand is 8 bits. Hack for movss and similar. */ RM_MEM16, /**< Memory operand is 16 bits. Hack for movss and similar. */ RM_MEM32, /**< Memory operand is 32 bits. Hack for movss and similar. */ RM_MEM64 /**< Memory operand is 64 bits. Hack for movss and similar. */ }; /** * Execution environment configuration. */ typedef struct BS3CPUINSTR3_CONFIG_T { uint16_t fCr0Mp : 1; uint16_t fCr0Em : 1; uint16_t fCr0Ts : 1; uint16_t fCr4OsFxSR : 1; uint16_t fCr4OsXSave : 1; uint16_t fXcr0Sse : 1; uint16_t fXcr0Avx : 1; /** x87 exception pending (IE + something unmasked). */ uint16_t fX87XcptPending : 1; /** Aligned memory operands. If zero, they will be misaligned and tests w/o memory ops skipped. */ uint16_t fAligned : 1; uint16_t fAlignCheck : 1; uint16_t fMxCsrMM : 1; /**< AMD only */ uint8_t bXcptMmx; uint8_t bXcptSse; uint8_t bXcptAvx; } BS3CPUINSTR3_CONFIG_T; /** Pointer to an execution environment configuration. */ typedef BS3CPUINSTR3_CONFIG_T const BS3_FAR *PCBS3CPUINSTR3_CONFIG_T; /** State saved by bs3CpuInstr3ConfigReconfigure. */ typedef struct BS3CPUINSTR3_CONFIG_SAVED_T { uint32_t uCr0; uint32_t uCr4; uint32_t uEfl; uint16_t uFcw; uint16_t uFsw; uint32_t uMxCsr; } BS3CPUINSTR3_CONFIG_SAVED_T; typedef BS3CPUINSTR3_CONFIG_SAVED_T BS3_FAR *PBS3CPUINSTR3_CONFIG_SAVED_T; typedef BS3CPUINSTR3_CONFIG_SAVED_T const BS3_FAR *PCBS3CPUINSTR3_CONFIG_SAVED_T; /********************************************************************************************************************************* * Global Variables * *********************************************************************************************************************************/ static bool g_afTypeSupports[T_MAX] = { false, false, false, false, false, false, false, false, false, false }; static bool g_fAmdMisalignedSse = false; /** Size of g_pbBuf - at least three pages. */ static uint32_t g_cbBuf; /** Buffer of g_cbBuf size. */ static uint8_t BS3_FAR *g_pbBuf; /** RW alias for the buffer memory at g_pbBuf. Set up by bs3CpuInstr3BufSetup. */ static uint8_t BS3_FAR *g_pbBufAlias; /** RW alias for the memory at g_pbBuf. */ static uint8_t BS3_FAR *g_pbBufAliasAlloc; /** Exception type \#1 test configurations, 16 & 32 bytes strictly aligned. */ static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig1[] = { /* * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to * +AVX +AMD/SSE * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */ { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */ { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */ { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */ { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */ { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */ { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */ { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */ { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */ { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */ /* Memory misalignment and alignment checks: */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_GP, X86_XCPT_GP }, /* #10 */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_GP, X86_XCPT_GP }, /* #11 */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ /* AMD only: */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */ }; /** Exception type \#4 test configurations, 16 & 32 byte not strictly aligned. */ static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig4[] = { /* * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to * +AVX +AMD/SSE * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */ { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */ { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */ { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */ { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */ { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */ { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */ { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */ { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */ { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */ /* Memory misalignment and alignment checks: */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_GP, X86_XCPT_DB }, /* #10 */ /* [Avx]:DB */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_GP, X86_XCPT_AC }, /* #11 */ /* [Avx]:AC */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ /* AMD only: */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */ /* [Avx]:DB */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */ /* [Avx]:AC */ }; /** Exception type \#4 test configurations, for the SSE version of movups. */ /** Tests 10:SSE & 11:SSE expect success, not GP */ static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig4Unaligned[] = { /* * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to * +AVX +AMD/SSE * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */ { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */ { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */ { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */ { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */ { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */ { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */ { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */ { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */ { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */ /* Memory misalignment and alignment checks: */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */ /* [Sse,Avx]:DB */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_DB, X86_XCPT_AC }, /* #11 */ /* [Sse]:DB, [Avx]:AC */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ /* AMD only: */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */ /* [Avx]:DB */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */ /* [Avx]:AC */ }; /** Exception type \#5 test configurations, less than 16 byte operands. */ static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig5[] = { /* * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to * +AVX +AMD/SSE * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */ { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */ { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */ { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */ { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */ { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */ { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */ { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */ { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */ { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */ /* Memory misalignment and alignment checks: */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */ /* [Sse,Avx]:DB */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #11 */ /* [Sse,Avx]:AC */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ /* AMD only: */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */ /* [Avx]:DB */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */ /* [Avx]:AC */ }; /** Exception type \#6 test configurations, VEX encoded instructions without legacy SSE analogues. */ static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig6[] = { /* * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to * +AVX +AMD/SSE * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #0 */ /* All rows: [Mmx,Sse]:UD */ { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #1 */ { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */ { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #3 */ { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */ { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */ { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_UD }, /* #6 */ { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_UD }, /* #7 */ { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_UD }, /* #8 */ { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #9 - pending x87 exception */ /* Memory misalignment and alignment checks: */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #10 */ /* [Avx]:DB */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_AC }, /* #11 */ /* [Avx]:AC */ { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #12 */ /* AMD only: */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #13 */ /* [Avx]:DB */ { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_AC }, /* #14 */ /* [Avx]:AC */ }; /** * Reconfigures the execution environment according to @a pConfig. * * Call bs3CpuInstr3ConfigRestore to undo the changes. * * @returns true on success, false if the configuration cannot be applied. In * the latter case, no context changes are made. * @param pSavedCfg Where to save state we modify. * @param pCtx The register context to modify. * @param pExtCtx The extended register context to modify. * @param pConfig The configuration to apply. * @param bMode The target mode. */ static bool bs3CpuInstr3ConfigReconfigure(PBS3CPUINSTR3_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx, PCBS3CPUINSTR3_CONFIG_T pConfig, uint8_t bMode) { /* * Save context bits we may change here */ pSavedCfg->uCr0 = pCtx->cr0.u32; pSavedCfg->uCr4 = pCtx->cr4.u32; pSavedCfg->uEfl = pCtx->rflags.u32; pSavedCfg->uFcw = Bs3ExtCtxGetFcw(pExtCtx); pSavedCfg->uFsw = Bs3ExtCtxGetFsw(pExtCtx); pSavedCfg->uMxCsr = Bs3ExtCtxGetMxCsr(pExtCtx); /* * Can we make these changes? */ if (pConfig->fMxCsrMM && !g_fAmdMisalignedSse) return false; /* Currently we skip pending x87 exceptions in real mode as they cannot be caught, given that we preserve the bios int10h. */ if (pConfig->fX87XcptPending && BS3_MODE_IS_RM_OR_V86(bMode)) return false; /* * Modify the test context. */ if (pConfig->fCr0Mp) pCtx->cr0.u32 |= X86_CR0_MP; else pCtx->cr0.u32 &= ~X86_CR0_MP; if (pConfig->fCr0Em) pCtx->cr0.u32 |= X86_CR0_EM; else pCtx->cr0.u32 &= ~X86_CR0_EM; if (pConfig->fCr0Ts) pCtx->cr0.u32 |= X86_CR0_TS; else pCtx->cr0.u32 &= ~X86_CR0_TS; if (pConfig->fCr4OsFxSR) pCtx->cr4.u32 |= X86_CR4_OSFXSR; else pCtx->cr4.u32 &= ~X86_CR4_OSFXSR; /** @todo X86_CR4_OSXMMEEXCPT? */ if (pConfig->fCr4OsXSave) pCtx->cr4.u32 |= X86_CR4_OSXSAVE; else pCtx->cr4.u32 &= ~X86_CR4_OSXSAVE; if (pConfig->fXcr0Sse) pExtCtx->fXcr0Saved |= XSAVE_C_SSE; else pExtCtx->fXcr0Saved &= ~XSAVE_C_SSE; if (pConfig->fXcr0Avx && g_afTypeSupports[T_AVX_256]) pExtCtx->fXcr0Saved |= XSAVE_C_YMM; else pExtCtx->fXcr0Saved &= ~XSAVE_C_YMM; if (pConfig->fAlignCheck) { pCtx->rflags.u32 |= X86_EFL_AC; pCtx->cr0.u32 |= X86_CR0_AM; } else { pCtx->rflags.u32 &= ~X86_EFL_AC; pCtx->cr0.u32 &= ~X86_CR0_AM; } if (!pConfig->fX87XcptPending) Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw & ~(X86_FSW_ES | X86_FSW_B)); else { Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw & ~X86_FCW_ZM); Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw | X86_FSW_ZE | X86_FSW_ES | X86_FSW_B); pCtx->cr0.u32 |= X86_CR0_NE; } if (pConfig->fMxCsrMM) Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr | X86_MXCSR_MM); else Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr & ~X86_MXCSR_MM); return true; } /** * Undoes changes made by bs3CpuInstr3ConfigReconfigure. */ static void bs3CpuInstr3ConfigRestore(PCBS3CPUINSTR3_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx) { pCtx->cr0.u32 = pSavedCfg->uCr0; pCtx->cr4.u32 = pSavedCfg->uCr4; pCtx->rflags.u32 = pSavedCfg->uEfl; pExtCtx->fXcr0Saved = pExtCtx->fXcr0Nominal; Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw); Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw); Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr); } /** * Allocates two extended CPU contexts and initializes the first one * with random data. * @returns First extended context, initialized with randomish data. NULL on * failure (complained). * @param ppExtCtx2 Where to return the 2nd context. */ static PBS3EXTCTX bs3CpuInstr3AllocExtCtxs(PBS3EXTCTX BS3_FAR *ppExtCtx2) { /* Allocate extended context structures. */ uint64_t fFlags; uint16_t cb = Bs3ExtCtxGetSize(&fFlags); PBS3EXTCTX pExtCtx1 = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 2); PBS3EXTCTX pExtCtx2 = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx1 + cb); if (pExtCtx1) { Bs3ExtCtxInit(pExtCtx1, cb, fFlags); /** @todo populate with semi-random stuff. */ Bs3ExtCtxInit(pExtCtx2, cb, fFlags); *ppExtCtx2 = pExtCtx2; return pExtCtx1; } Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 2); *ppExtCtx2 = NULL; return NULL; } static void bs3CpuInstr3FreeExtCtxs(PBS3EXTCTX pExtCtx1, PBS3EXTCTX BS3_FAR pExtCtx2) { RT_NOREF_PV(pExtCtx2); Bs3MemFree(pExtCtx1, pExtCtx1->cb * 2); } /** * Sets up SSE and maybe AVX. */ static void bs3CpuInstr3SetupSseAndAvx(PBS3REGCTX pCtx, PCBS3EXTCTX pExtCtx) { /* CR0: */ uint32_t cr0 = Bs3RegGetCr0(); cr0 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM); cr0 |= X86_CR0_NE; Bs3RegSetCr0(cr0); /* If real mode context, the cr0 value will differ from the current one (we're in PE32 mode). */ pCtx->cr0.u32 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM); pCtx->cr0.u32 |= X86_CR0_NE; /* CR4: */ if (pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT) { uint32_t cr4 = Bs3RegGetCr4(); if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE) { cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT | X86_CR4_OSXSAVE; Bs3RegSetCr4(cr4); Bs3RegSetXcr0(pExtCtx->fXcr0Nominal); } else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE) { cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT; Bs3RegSetCr4(cr4); } pCtx->cr4.u32 = cr4; } } /** * Configures the buffer with electrict fences in paged modes. * * @returns Adjusted buffer pointer. * @param pbBuf The buffer pointer. * @param pcbBuf Pointer to the buffer size (input & output). * @param bMode The testing target mode. */ DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstr3BufSetup(uint8_t BS3_FAR *pbBuf, uint32_t *pcbBuf, uint8_t bMode) { if (BS3_MODE_IS_PAGED(bMode)) { int rc; uint32_t cbBuf = *pcbBuf; Bs3PagingProtectPtr(&pbBuf[0], X86_PAGE_SIZE, 0, X86_PTE_P); Bs3PagingProtectPtr(&pbBuf[cbBuf - X86_PAGE_SIZE], X86_PAGE_SIZE, 0, X86_PTE_P); pbBuf += X86_PAGE_SIZE; cbBuf -= X86_PAGE_SIZE * 2; *pcbBuf = cbBuf; g_pbBufAlias = g_pbBufAliasAlloc; rc = Bs3PagingAlias((uintptr_t)g_pbBufAlias, (uintptr_t)pbBuf, cbBuf + X86_PAGE_SIZE, /* must include the tail guard pg */ X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW); if (RT_FAILURE(rc)) Bs3TestFailedF("Bs3PagingAlias failed on %p/%p LB %#x: %d", g_pbBufAlias, pbBuf, cbBuf, rc); } else g_pbBufAlias = pbBuf; return pbBuf; } /** * Undoes what bs3CpuInstr3BufSetup did. * * @param pbBuf The buffer pointer. * @param cbBuf The buffer size. * @param bMode The testing target mode. */ DECLINLINE(void) bs3CpuInstr3BufCleanup(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t bMode) { if (BS3_MODE_IS_PAGED(bMode)) { Bs3PagingProtectPtr(&pbBuf[-X86_PAGE_SIZE], X86_PAGE_SIZE, X86_PTE_P, 0); Bs3PagingProtectPtr(&pbBuf[cbBuf], X86_PAGE_SIZE, X86_PTE_P, 0); } } /** * Gets a buffer of a @a cbMemOp sized operand according to the given * configuration and alignment restrictions. * * @returns Pointer to the buffer. * @param pbBuf The buffer pointer. * @param cbBuf The buffer size. * @param cbMemOp The operand size. * @param cbAlign The operand alignment restriction. * @param pConfig The configuration. * @param fPageFault The \#PF test setting. */ DECLINLINE(PRTUINT256U) bs3CpuInstr3BufForOperand(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t cbMemOp, uint8_t cbAlign, PCBS3CPUINSTR3_CONFIG_T pConfig, unsigned fPageFault) { /* All allocations are at the tail end of the buffer, so that we've got a guard page following the operand. When asked to consistenly trigger a #PF, we slide the buffer into that guard page. */ if (fPageFault) cbBuf += X86_PAGE_SIZE; if (pConfig->fAligned) { if (!pConfig->fAlignCheck) return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp]; return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp - cbAlign]; } return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp - 1]; } /** * Determins the size of memory operands. */ DECLINLINE(uint8_t) bs3CpuInstr3MemOpSize(uint8_t cbOperand, uint8_t enmRm) { if (enmRm <= RM_MEM_DI) return cbOperand; if (enmRm == RM_MEM8) return sizeof(uint8_t); if (enmRm == RM_MEM16) return sizeof(uint16_t); if (enmRm == RM_MEM32) return sizeof(uint32_t); if (enmRm == RM_MEM64) return sizeof(uint64_t); BS3_ASSERT(0); return cbOperand; } #include #include DECLINLINE(uint32_t) bs3CpuInstrX_SimpleRand(void) { /* * A simple Lehmer linear congruential pseudo-random number * generator using the constants suggested by Park & Miller: * * modulus = 2^31 - 1 (INT32_MAX) * multiplier = 7^5 (16807) * * It produces numbers in the range [1..INT32_MAX-1] and is * more chaotic in the higher bits. * * Note! Runtime/common/rand/randparkmiller.cpp is also use this algorithm, * though the zero handling is different. */ static uint32_t s_uSeedMemory = 0; uint32_t uVal = s_uSeedMemory; if (!uVal) { uVal = (uint32_t)ASMReadTSC(); Bs3TestPrintf("PRNG initial seed: 0x%08lx\n", uVal); } uVal = ASMModU64ByU32RetU32(ASMMult2xU32RetU64(uVal, 16807), INT32_MAX); s_uSeedMemory = uVal; return uVal; } /* * Code to make testing the tests faster. `bs3CpuInstrX_SkipIt()' randomly * skips a fraction of the micro-tests. It is sufficiently random that * over a large number of runs, all micro-tests will be hit. * * Full test runs take ever longer as we add more instructions and fancier * ways of testing them. In one example scenario, a debug build running * bs3-cpu-instr-3 under interpreted IEM went from 9000 to 800 seconds, * with BS3_SKIPIT_AVG_SKIP set to 26. * * To activate this 'developer's speed-testing mode', define * `BS3_SKIPIT_AVG_SKIP' to a positive integer like 10 or 200. * * BS3_SKIPIT_AVG_SKIP governs approximately how many micro-tests are * skipped in a row; e.g. if set to 100, an average of 100 micro-tests * in a row are skipped. (This is not a full 100x faster, due to other * activities which are not skipped!) Note this is only an average; * the actual skips are random. * * You can also modify bs3CpuInstrX_SkipIt() to focus on specific sub-tests, * using its (currently ignored) `bRing, iCfg, iTest, iVal, iVariant' args * (to enable this: turn on `#define BS3_SKIPIT_DO_ARGS': which costs about * 3% performance). * * Note! For testing the native recompiler, configure the VM to invoke * native recompilation quickly with: * * VBoxManage setextradata vmname VBoxInternal/Devices/VMMDev/0/Config/TestingEnabled 1 * VBoxManage setextradata vmname VBoxInternal/Devices/VMMDev/0/Config/TestingThresholdNativeRecompiler 2 * VBoxManage setextradata vmname VBoxInternal/IEM/NativeRecompileAtUsedCount 1 */ #define BS3_SKIPIT_AVG_SKIP 0 #define BS3_SKIPIT_REPORT_COUNT 1000000 #undef BS3_SKIPIT_DO_ARGS static unsigned g_cSeen, g_cSkipped; static void bs3CpuInstrX_ShowTallies(bool always) { if (!g_cSkipped && !always) return; Bs3TestPrintf("Micro-tests %d: tested %d / skipped %d\n", g_cSeen, g_cSeen - g_cSkipped, g_cSkipped); } # ifdef BS3_SKIPIT_DO_ARGS # define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt(bRing, iCfg, iTest, iVal, iVariant) static bool bs3CpuInstrX_SkipIt(uint8_t bRing, unsigned iCfg, unsigned iTest, unsigned iVal, unsigned iVariant) # else # define BS3_SKIPIT(bRing, iCfg, iTest, iVal, iVariant) bs3CpuInstrX_SkipIt() static bool bs3CpuInstrX_SkipIt(void) # endif { static unsigned s_uTimes = 0; bool fSkip; /* Cache calls to the relatively expensive random routine */ if (!s_uTimes) s_uTimes = bs3CpuInstrX_SimpleRand() % (BS3_SKIPIT_AVG_SKIP * 2 + 1) + 1; fSkip = --s_uTimes > 0; if (fSkip) ++g_cSkipped; if (++g_cSeen % BS3_SKIPIT_REPORT_COUNT == 0) bs3CpuInstrX_ShowTallies(false); return fSkip; } /* * Test type #1. */ typedef struct BS3CPUINSTR3_TEST1_VALUES_T { RTUINT256U uSrc2; RTUINT256U uSrc1; /**< uDstIn for MMX & SSE */ RTUINT256U uDstOut; } BS3CPUINSTR3_TEST1_VALUES_T; typedef struct BS3CPUINSTR3_TEST1_T { FPFNBS3FAR pfnWorker; uint8_t bAvxMisalignXcpt; uint8_t enmRm; uint8_t enmType; uint8_t iRegDst; uint8_t iRegSrc1; uint8_t iRegSrc2; uint8_t cValues; BS3CPUINSTR3_TEST1_VALUES_T const BS3_FAR *paValues; } BS3CPUINSTR3_TEST1_T; typedef struct BS3CPUINSTR3_TEST1_MODE_T { BS3CPUINSTR3_TEST1_T const BS3_FAR *paTests; unsigned cTests; } BS3CPUINSTR3_TEST1_MODE_T; /** Initializer for a BS3CPUINSTR3_TEST1_MODE_T array (three entries). */ #define BS3CPUINSTR3_TEST1_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } /** * Test type #1 worker. */ static uint8_t bs3CpuInstr3_WorkerTestType1(uint8_t bMode, BS3CPUINSTR3_TEST1_T const BS3_FAR *paTests, unsigned cTests, PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) { BS3REGCTX Ctx; BS3TRAPFRAME TrapFrame; const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; uint8_t BS3_FAR *pbBuf = g_pbBuf; uint32_t cbBuf = g_cbBuf; PBS3EXTCTX pExtCtxOut; PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); if (!pExtCtx) return 0; /* Ensure the structures are allocated before we sample the stack pointer. */ Bs3MemSet(&Ctx, 0, sizeof(Ctx)); Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); /* * Create test context. */ pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]); /* * Run the tests in all rings since alignment issues may behave * differently in ring-3 compared to ring-0. */ for (;;) { unsigned fPf = 0; do { unsigned iCfg; for (iCfg = 0; iCfg < cConfigs; iCfg++) { unsigned iTest; BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) continue; /* unsupported config */ /* * Iterate the tests. */ for (iTest = 0; iTest < cTests; iTest++) { BS3CPUINSTR3_TEST1_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; unsigned const cValues = paTests[iTest].cValues; bool const fMmxInstr = paTests[iTest].enmType < T_SSE; bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm); uint8_t const cbAlign = cbMemOp; PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf); PRTUINT256U puMemOpAlias = (PRTUINT256U)&g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf]; uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD : fMmxInstr ? paConfigs[iCfg].bXcptMmx : fSseInstr ? paConfigs[iCfg].bXcptSse : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; unsigned cRecompRuns = 0; unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues; unsigned iVal; /* If testing unaligned memory accesses (or #PF), skip register-only tests. This allows setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ if ((paTests[iTest].enmRm == RM_REG || paTests[iTest].enmRm == RM_MEM8) && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf)) continue; /* #AC is only raised in ring-3.: */ if (bXcptExpect == X86_XCPT_AC) { if (bRing != 3) bXcptExpect = X86_XCPT_DB; else if (fAvxInstr) bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ } if (fPf && bXcptExpect == X86_XCPT_DB) bXcptExpect = X86_XCPT_PF; Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); /* * Iterate the test values and do the actual testing. */ while (cRecompRuns < cMaxRecompRuns) for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++) { uint16_t cErrors; uint16_t uSavedFtw = 0xff; RTUINT256U uMemOpExpect; if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0)) continue; /* * Set up the context and some expectations. */ /* dest */ if (paTests[iTest].iRegDst == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); Bs3MemSet(puMemOpAlias, 0xcc, cbMemOp); if (bXcptExpect == X86_XCPT_DB) uMemOpExpect = paValues[iVal].uDstOut; else Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO); /* source #1 (/ destination for MMX and SSE) */ if (paTests[iTest].iRegSrc1 == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); Bs3MemCpy(puMemOpAlias, &paValues[iVal].uSrc1, cbMemOp); if (paTests[iTest].iRegDst == UINT8_MAX) BS3_ASSERT(fSseInstr); else uMemOpExpect = paValues[iVal].uSrc1; } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32); /* source #2 */ if (paTests[iTest].iRegSrc2 == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX && paTests[iTest].iRegSrc1 != UINT8_MAX); Bs3MemCpy(puMemOpAlias, &paValues[iVal].uSrc2, cbMemOp); uMemOpExpect = paValues[iVal].uSrc2; } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32); /* Memory pointer. */ if (paTests[iTest].enmRm >= RM_MEM) { BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX || paTests[iTest].iRegSrc1 == UINT8_MAX || paTests[iTest].iRegSrc2 == UINT8_MAX); if (paTests[iTest].enmRm != RM_MEM_DI) Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); else Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rdi, &Ctx.fs, puMemOp); } /* * Execute. */ g_uBs3TrapEipHint = Ctx.rip.u32 + (bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0); Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); /* CPUs are inconsistent about FTW modification during these exceptions */ if (bXcptExpect == X86_XCPT_PF || bXcptExpect == X86_XCPT_AC) Bs3ExtCtxSetAbridgedFtw(pExtCtx, Bs3ExtCtxGetAbridgedFtw(pExtCtxOut)); /* * Check the result: */ cErrors = Bs3TestSubErrorCount(); if (fMmxInstr && bXcptExpect == X86_XCPT_DB) { uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); /* Observed on 10980xe after pxor mm1, mm2. */ } if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX) { if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand); } #if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */ if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE && pExtCtx->Ctx.x.Hdr.bmXState == 0x7 && pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3) pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7; #endif Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); if (TrapFrame.bXcpt != bXcptExpect) Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) { if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; } if (bXcptExpect == X86_XCPT_PF) Ctx.cr2.u = (uintptr_t)puMemOp; Ctx.cr2Range = (paTests[iTest].enmRm == RM_MEM_DI || paTests[iTest].enmRm == RM_RANGE) ? cbMemOp - 1 : 0; Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, pszMode, idTestStep); Ctx.cr2.u = 0; Ctx.cr2Range = 0; if ( paTests[iTest].enmRm >= RM_MEM && Bs3MemCmp(puMemOpAlias, &uMemOpExpect, cbMemOp) != 0) Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOpAlias); if (cErrors != Bs3TestSubErrorCount()) { if (paConfigs[iCfg].fAligned) Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", bRing, iCfg, iTest, iVal, bXcptExpect); else Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); Bs3TestPrintf("\n"); } if (uSavedFtw != 0xff) Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); } } bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); } } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode)); /* * Next ring. */ bRing++; if (bRing > 3 || bMode == BS3_MODE_RM) break; Bs3RegCtxConvertToRingX(&Ctx, bRing); } /* * Cleanup. */ bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); return 0; } /* * PAND, VPAND, ANDPS, VANDPS, ANDPD, VANDPD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_andps_andpd_pand(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x5555666677770000, 0x1111222233334444, 0x1111222233334444, 0x5555666677770000) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x0c09d02808403294, 0x385406c840621622, 0x8000290816080282, 0x0050c020030090b9) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pand_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pand_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pand_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * PANDN, VPANDN, ANDNPS, VANDNPS, ANDNPD, VANDNPD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_andnps_andnpd_pandn(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x0000000000008888, 0x0000000000000000, 0x0000000000000000, 0x0000000000008888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x41002002649c4141, 0x06a01100260929c4, 0x342106a040449920, 0x9c0c205390090602) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pandn_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pandn_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pandn_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vandnpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * POR, VPOR, PORPS, VORPS, PORPD, VPORPD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_orps_orpd_por(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0xddddeeeeffff8888, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff8888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x5fddfdae6dff73d5, 0xfffc9fec667b7ff7, 0xbc21effbffddfbe3, 0xdfdfedf3b38d9fff) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_por_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_por_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_por_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_por_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_por_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_por_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_por_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_por_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_por_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vorpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * PXOR, VPXOR, XORPS, VXORPS, XORPD, VXORPD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_xorps_xorpd_pxor(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x8888888888888888, 0x8888888888888888, 0x8888888888888888, 0x8888888888888888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x53d42d8665bf4141, 0xc7a89924261969d5, 0x3c21c6f3e9d5f961, 0xdf8f2dd3b08d0f46) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pxor_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pxor_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pxor_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vxorpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * PCMPGTB, VPCMPGTB, PCMPGTW, VPCMPGTW, PCMPGTD, VPCMPGTD, PCMPGTQ, VPCMPGTQ. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd_pcmpgtq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* < */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x000000000000ffff, 0x0000000000000000, 0x0000000000000000, 0x000000000000ffff) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* < */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x0000000000ff0000, 0x00ff00ff00ffffff, 0x000000ff0000ffff, 0xff000000ff00ffff) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* < */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x000000000000ffff, 0x0000000000000000, 0x0000000000000000, 0x000000000000ffff) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* ^ */ RTUINT256_INIT_C(0x1eddddac77733294, 0xf95c8eec40725633, 0x3333e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st and 3rd value */ /* = */ RTUINT256_INIT_C(0x00000000ffff0000, 0x000000000000ffff, 0xffff00000000ffff, 0xffff0000ffffffff) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* < */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* < */ RTUINT256_INIT_C(0x555dddac09633294, 0xf95c8eec77725633, 0x7770e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st, 2nd and 3rd value */ /* = */ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0xffffffffffffffff) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* < */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* < */ RTUINT256_INIT_C(0x77ddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st value */ /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0x0000000000000000, 0xffffffffffffffff) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpgtd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, { bs3CpuInstr3_vpcmpgtq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * PCMPEQB, VPCMPEQB, PCMPEQW, VPCMPEQW, PCMPEQD, VPCMPEQD, PCMPEQQ, VPCMPEQQ. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd_pcmpeqq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { RTUINT256_INIT_C(0x4dddf02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* ==*/ RTUINT256_INIT_C(0x1eddddac09dc3294, 0xf95c17ec667256e6, 0xb400e95bbf999bc3, 0x9cd3cda0230999fd), /* modified all to get some matches */ /* = */ RTUINT256_INIT_C(0x00ff000000ff0000, 0x0000ff00ff0000ff, 0xff0000000000ff00, 0xff00000000ff0000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* ==*/ RTUINT256_INIT_C(0x1eddf02a6cdc3294, 0x3ef48eec666b5633, 0x88002fa8bf999ba2, 0x9c5ccda0238496bb), /* modified all to get some matches */ /* = */ RTUINT256_INIT_C(0x0000ffffffff0000, 0xffff0000ffff0000, 0x0000ffff0000ffff, 0xffff00000000ffff) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* ==*/ RTUINT256_INIT_C(0x4d09f02a09633294, 0x3ef417c8666b3fe6, 0x8800e95b564c9ba2, 0x9c5ce073238499fd), /* modified all to get some matches */ /* = */ RTUINT256_INIT_C(0xffffffff00000000, 0xffffffffffffffff, 0x00000000ffffffff, 0xffffffff00000000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* ==*/ RTUINT256_INIT_C(0x1eddddac09633294, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x43d3cda0238499fd), /* modified 2nd and 3rd to get some matches */ /* = */ RTUINT256_INIT_C(0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000000) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpcmpeqd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpcmpeqq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * PADDB, VPADDB, PADDW, VPADDW, PADDD, VPADDD, PADDQ, VPADDQ. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_paddb_paddw_paddd_paddq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* + */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x3232545476768888, 0xaaaacccceeee1010, 0xaaaacccceeee1010, 0x3232545476768888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x6be6cdd6753fa569, 0x3750a5b4a6dd9519, 0x3c21180315e5fd65, 0xdf2fad13b68d2fb8) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* + */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x3332555477768888, 0xaaaacccceeee1110, 0xaaaacccceeee1110, 0x3332555477768888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x6be6cdd6763fA669, 0x3850A6B4A6DD9619, 0x3C21190315E5FE65, 0xE02FAE13B68D30B8) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* + */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x3333555477768888, 0xAAAACCCCEEEF1110, 0xAAAACCCCEEEF1110, 0x3333555477768888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x6BE7CDD6763FA669, 0x3850A6B4A6DD9619, 0x3C22190315E5FE65, 0xE030AE13B68E30B8) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* + */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x3333555577768888, 0xAAAACCCCEEEF1110, 0xAAAACCCCEEEF1110, 0x3333555577768888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x6BE7CDD6763FA669, 0x3850A6B4A6DD9619, 0x3C22190415E5FE65, 0xE030AE13B68E30B8) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_paddb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_paddb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_paddb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_paddw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_paddd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpaddd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_paddq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpaddq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * PSUBB, VPSUBB, PSUBW, VPSUBW, PSUBD, VPSUBD, PSUBQ, VPSUBQ. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psubb_psubw_psubd_psubq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* + */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x8888888888887878, 0x8888888888888888, 0x8888888888888888, 0x8888888888887878) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0xd1d4ed829d87bfbf, 0xbb687724da07174d, 0xd4dfbab3694dc721, 0xa777ed2d907b0342) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* + */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x8888888888887778, 0x8888888888888888, 0x8888888888888888, 0x8888888888887778) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0xd1d4ed829c87bebf, 0xba687724da07164d, 0xd3dfb9b3694dc721, 0xa777ed2d907b0342) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* + */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x8888888888877778, 0x8888888888888888, 0x8888888888888888, 0x8888888888877778) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0xd1d3ed829c86bebf, 0xba687724da07164d, 0xd3dfb9b3694cc721, 0xa776ed2d907b0342) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* + */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x8888888888877778, 0x8888888888888888, 0x8888888888888888, 0x8888888888877778) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0xd1d3ed819c86bebf, 0xba687723da07164d, 0xd3dfb9b3694cc721, 0xa776ed2c907b0342) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_psubb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_psubb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_psubb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psubw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psubd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsubd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psubq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, { bs3CpuInstr3_vpsubq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * PMULLW, VPMULLW, PMULLD, VPMULLD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmullw_pmulld(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* * */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x0b6106d488890000, 0x5c293e94a7419630, 0x5c293e94a7419630, 0x0b6106d488890000) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x8ec59e38d5149124, 0xf3b0dc605ba6fed2, 0x8800d8b8476c9066, 0xf3d45ee00ba4b9cf) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* * */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x2ea606d477780000, 0x6e5d3e9430ec9630, 0x6e5d3e9430ec9630, 0x2ea606d477780000) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x97439e3846719124, 0x8216dc606340fed2, 0x7c2bd8b8f1c09066, 0x31915ee054fbb9cf) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pmullw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pmullw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pmullw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmullw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmullw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmullw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmulld_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmulld_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmulld_YMM10_YMM8_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 10, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * PMULHW, VPMULHW. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmulhw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* * */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0xf49ff92cffff0000, 0xf92cf49ff258f258, 0xf92cf49ff258f258, 0xf49ff92cffff0000) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x0949021f03fd16e2, 0xfe5df57e19c81583, 0x2390fbc8ea4ad947, 0xe5990635f0e229f2) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * PMULHUW, VPMULHUW. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmulhuw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* * */ RTUINT256_INIT_C(0, 0, 0, 0), /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* = */ RTUINT256_INIT_C(0x49f45f9277760000, 0x0a3d16c1258b369c, 0x0a3d16c1258b369c, 0x49f45f9277760000) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* = */ RTUINT256_INIT_C(0x0949cff503fd16e2, 0x3d510d4619c81583, 0x5fb12b7040963c0a, 0x296cb44814665aaa) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhuw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmulhuw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmulhuw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * PSHUFB */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_pshufb(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*mask*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*val*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*mask*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff), /*val*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0000000000000000) }, { /*mask*/ RTUINT256_INIT_C( 1, 2, 3, 0x7f7f7f7f7f7f7f7f), /*val*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff) }, { /*mask*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*val*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 8, 10, 11, 0xeeeedddddddd0000) }, { /*mask*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*val*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00a0002300990000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), /*val*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*val*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { /*mask*/ RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), /*val*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { /*mask*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*val*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0xaaaa999999990000, 0xccccbbbbbbbbaaaa, 0x0000ffffffffeeee, 0xeeeedddddddd0000) }, { /*mask*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*val*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xdd320063ac004000, 0xdd00f9005c091e00, 0x00998800d35b0000, 0x005b002300620000) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_pshufb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_pshufb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpshufb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PUNPCKHBW */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhbw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1e1f2e2f3e3f4e4) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x55dd55dd66ee66ee) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c435cd3e0cd73a0) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1b1f2b2f3b3f4b4, 0xf5b5f6b6f7b7f8b8, 0xd191d292d393d494, 0xd595d696d797d898) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x55dd55dd66ee66ee, 0x77ff77ff88008800, 0x1199119922aa22aa, 0x33bb33bb44cc44cc) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d1e09ddf0dd2aac, 0x6c09dc637332d594, 0xb48821002fe9a85b, 0x56bf4c999b62a2c3) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhbw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhbw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PUNPCKHWD */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhwd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2e1e2f3f4e3e4) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x5555dddd6666eeee) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c5c43d3e073cda0) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2b1b2f3f4b3b4, 0xf5f6b5b6f7f8b7b8, 0xd1d29192d3d49394, 0xd5d69596d7d89798) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x5555dddd6666eeee, 0x7777ffff88880000, 0x111199992222aaaa, 0x3333bbbb4444cccc) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d091eddf02addac, 0x6cdc096373d53294, 0xb42188002fa8e95b, 0x564cbf999ba262c3) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhwd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhwd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PUNPCKHDQ */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhdq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4e1e2e3e4) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x55556666ddddeeee) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c5ce07343d3cda0) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4b1b2b3b4, 0xf5f6f7f8b5b6b7b8, 0xd1d2d3d491929394, 0xd5d6d7d895969798) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x55556666ddddeeee, 0x77778888ffff0000, 0x111122229999aaaa, 0x33334444bbbbcccc) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a1eddddac, 0x6cdc73d509633294, 0xb4212fa88800e95b, 0x564c9ba2bf9962c3) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PUNPCKHQDQ */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhqdq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xb1b2b3b4b5b6b7b8, 0xd1d2d3d4d5d6d7d8, 0x9192939495969798) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x5555666677778888, 0xddddeeeeffff0000, 0x1111222233334444, 0x9999aaaabbbbcccc) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x1eddddac09633294, 0xb4212fa8564c9ba2, 0x8800e95bbf9962c3) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhqdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckhqdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PUNPCKLBW */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklbw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5e5f6e6f7e7f8e8) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x77ff77ff88008800) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x932309849699bbfd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xe1a1e2a2e3a3e4a4, 0xe5a5e6a6e7a7e8a8, 0xc181c282c383c484, 0xc585c686c787c888) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x1199119922aa22aa, 0x33bb33bb44cc44cc, 0x55dd55dd66ee66ee, 0x77ff77ff88008800) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3ef9f45c178ec8ec, 0x66406b723f56e633, 0x9c435cd3e0cd73a0, 0x932309849699bbfd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklbw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklbw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PUNPCKLWD */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklwd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5f6e5e6f7f8e7e8) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7777ffff88880000) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9309238496bb99fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xe1e2a1a2e3e4a3a4, 0xe5e6a5a6e7e8a7a8, 0xc1c28182c3c48384, 0xc5c68586c7c88788) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x111199992222aaaa, 0x3333bbbb4444cccc, 0x5555dddd6666eeee, 0x7777ffff88880000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3ef4f95c17c88eec, 0x666b40723fe65633, 0x9c5c43d3e073cda0, 0x9309238496bb99fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklwd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklwd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PUNPCKLDQ */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckldq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5f6f7f8e5e6e7e8) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x77778888ffff0000) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x930996bb238499fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xe1e2e3e4a1a2a3a4, 0xe5e6e7e8a5a6a7a8, 0xc1c2c3c481828384, 0xc5c6c7c885868788) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x111122229999aaaa, 0x33334444bbbbcccc, 0x55556666ddddeeee, 0x77778888ffff0000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3ef417c8f95c8eec, 0x666b3fe640725633, 0x9c5ce07343d3cda0, 0x930996bb238499fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckldq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpckldq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpckldq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PUNPCKLQDQ */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklqdq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xe1e2e3e4e5e6e7e8, 0xa1a2a3a4a5a6a7a8, 0xc1c2c3c4c5c6c7c8, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x1111222233334444, 0x9999aaaabbbbcccc, 0x5555666677778888, 0xddddeeeeffff0000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0xf95c8eec40725633, 0x9c5ce073930996bb, 0x43d3cda0238499fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklqdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_punpcklqdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PACKSSWB */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packsswb(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x8080808080808080) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7f7f7f808080ff00) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x808080807f807f80) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xFF820064fffe0042), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x8264fe4222808081) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x7f7f7f807f7f7f7f, 0x8080ff0080808080, 0x7f7f7f7f7f7f7f80, 0x808080808080ff00) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x7f807f7f7f7f7f7f, 0x7f807f7f80807f7f, 0x807f7f8080808080, 0x8080807f7f807f80) }, { /*src2*/ RTUINT256_INIT_C(0x002200250079007e, 0xfffffffeff88ff7f, 0x0064003200160008, 0x0042004600880080), /*src1*/ RTUINT256_INIT_C(0x0001000200030005, 0x0007000b000d0011, 0x00130017001d0025, 0x0029002b002f0035), /* => */ RTUINT256_INIT_C(0x2225797efffe8880, 0x01020305070b0d11, 0x6432160842467f7f, 0x13171d25292b2f35) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packsswb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packsswb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpacksswb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PACKSSDW */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packssdw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x8000800080008000) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7fff7fff80008000) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x800080007fff7fff) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xffff898400007495), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x00002222ffff9485), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x8984749522229485) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x8000800080008000, 0x8000800080008000, 0x8000800080008000, 0x8000800080008000) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x7fff7fff7fff7fff, 0x8000800080008000, 0x7fff7fff7fff7fff, 0x8000800080008000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x7fff7fff7fff7fff, 0x7fff7fff80007fff, 0x80007fff80008000, 0x800080007fff7fff) }, { /*src2*/ RTUINT256_INIT_C(0x0000349000002349, 0xffffa230ffffe384, 0xffff348300007ffe, 0x00008000ffff7fff), /*src1*/ RTUINT256_INIT_C(0xffff800100007ffe, 0xffffcbaffffffffe, 0x0000643200001608, 0xffffffe0ffffffc0), /* => */ RTUINT256_INIT_C(0x34902349a230e384, 0x80017ffecbaffffe, 0x80007ffe7fff8000, 0x64321608ffe0ffc0) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packssdw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packssdw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackssdw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PACKUSWB */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packuswb(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0000000000000000) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 8, 10, 11, 0xffffff0000000000) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00000000ff00ff00) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xFF820064fffe0042), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x0064004222000000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0xffffff00ffffffff, 0x0000000000000000, 0xffffffffffffff00, 0x000000000000000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xff00ffffffffffff, 0xff00ffff0000ffff, 0x00ffff0000000000, 0x000000ffff00ff00) }, { /*src2*/ RTUINT256_INIT_C(0x002200250079007e, 0xfffffffeff88ff7f, 0x0064003200160008, 0x0042004600880080), /*src1*/ RTUINT256_INIT_C(0x0001000200030005, 0x0007000b000d0011, 0x00130017001d0025, 0x0029002b002f0035), /* => */ RTUINT256_INIT_C(0x2225797e00000000, 0x01020305070b0d11, 0x6432160842468880, 0x13171d25292b2f35) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packuswb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packuswb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackuswb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PACKUSDW */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packusdw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffff0000ffff, 0x0000ffff00000000, 0x00000000ffffffff) }, { /*src2*/ RTUINT256_INIT_C(0x0000349000002349, 0xffffa230ffffe384, 0xffff348300007ffe, 0x00008000ffff7fff), /*src1*/ RTUINT256_INIT_C(0xffff800100007ffe, 0xffffcbaffffffffe, 0x0000643200001608, 0xffffffe0ffffffc0), /* => */ RTUINT256_INIT_C(0x3490234900000000, 0x00007ffe00000000, 0x00007ffe80000000, 0x6432160800000000) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packusdw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_packusdw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, { bs3CpuInstr3_vpackusdw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PMAXUB - Compare unsigned byte integers and returns maximum values. * [V]PMAXUW - Compare unsigned word integers and returns maximum values. * [V]PMAXUD - Compare unsigned double word integers and returns maximum values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaxub_pmaxuw_pmaxud(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff8888) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9cd3e0a0938499fd) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), /* => */ RTUINT256_INIT_C(12, 13, 14, 0xff82fe64fffeff81) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4dddf0ac6cdc73d5, 0xf9f48eec667256e6, 0xb421e9a8bf999bc3, 0x9cd3e0a0938499fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0xf95c8eec666b5633, 0xb421e95bbf999ba2, 0x9c5ce073930999fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0xf95c8eec666b3fe6, 0xb4212fa8bf9962c3, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxuw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxud_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmaxud_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxuw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxud_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmaxud_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxub_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxub_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxub_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxuw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxuw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxuw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxuw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxud_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmaxud_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmaxud_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmaxud_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxud_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PMAXSB - Compare signed byte integers and returns maximum values. * [V]PMAXSW - Compare signed word integers and returns maximum values. * [V]PMAXSD - Compare signed double word integers and returns maximum values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaxsb_pmaxsw_pmaxsd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 4, 6, 7, 0x5555666677770000) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x43d3e073238499fd) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00220064fffe0042) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6c6373d5, 0x3e5c17ec66725633, 0xb4212f5b564c62c3, 0x435ce073230999fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b5633, 0xb4212fa8564c62c3, 0x43d3e073238499fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x43d3cda0238499fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pmaxsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxsb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmaxsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pmaxsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxsb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmaxsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pmaxsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxsb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxsb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxsb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpmaxsb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pmaxsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pmaxsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpmaxsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pmaxsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmaxsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmaxsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pmaxsd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpmaxsd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PMINUB - Compare unsigned byte integers and returns minimum values. * [V]PMINUW - Compare unsigned word integers and returns minimum values. * [V]PMINUD - Compare unsigned double word integers and returns minimum values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pminub_pminuw_pminud(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 4, 6, 7, 0x5555666677770000) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x435ccd73230996bb) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00220000ff800042) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1e09dd2a09633294, 0x3e5c17c8406b3f33, 0x88002f5b564c62a2, 0x435ccd73230996bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0x3ef417c840723fe6, 0x88002fa8564c62c3, 0x43d3cda0238496bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0x3ef417c840725633, 0x8800e95b564c9ba2, 0x43d3cda0238499fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pminub_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminub_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminub_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminub_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminuw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminud_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pminud_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pminub_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminub_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminub_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminub_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminuw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminud_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pminud_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pminub_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminub_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminub_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminub_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminub_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminub_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminub_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminuw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminuw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminuw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminuw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminud_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pminud_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pminud_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pminud_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminud_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PMINSB - Compare signed byte integers and returns minimum values. * [V]PMINSW - Compare signed word integers and returns minimum values. * [V]PMINSD - Compare signed double word integers and returns minimum values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pminsb_pminsw_pminsd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8) }, { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff8888) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c5ccda0930996bb) }, { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042), /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), /* => */ RTUINT256_INIT_C(12, 13, 14, 0xff82fe00ff80ff81) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09dc3294, 0xf9f48ec8406b3fe6, 0x8800e9a8bf999ba2, 0x9cd3cda0938496bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40723fe6, 0x8800e95bbf999ba2, 0x9c5ccda0930996bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pminsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminsb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pminsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pminsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminsb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pminsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pminsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminsb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminsb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminsb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpminsb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pminsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, { bs3CpuInstr3_pminsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpminsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pminsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pminsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pminsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pminsd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpminsd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]MOVSS - move (mem) or merge (reg) scalar single-precision floating-point value. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movss(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesR[] = { { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0), /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x81828384c5c6c7c8) }, { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeee77778888) }, { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0930996bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesM[] = { { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0), /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000c5c6c7c8) }, { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000077778888) }, { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000930996bb) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_movss_XMM11_XMM8_icebp_c64, 255, RM_REG, T_SSE, 11, 11, 8, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_movss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_movss_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_vmovss_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 9, 9, 10, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovss_XMM10_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 10, 10, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovss_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesM), s_aValuesM }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * [V]MOVSD - move (mem) or merge (reg) scalar double-precision floating-point value. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movsd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesR[] = { { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0), /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8), /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) }, { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesM[] = { { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0), /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xc1c2c3c4c5c6c7c8) }, { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x5555666677778888) }, { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_movsd_XMM11_XMM8_icebp_c64, 255, RM_REG, T_SSE, 11, 11, 8, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_movsd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_movsd_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_vmovsd_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 9, 9, 10, RT_ELEMENTS(s_aValuesR), s_aValuesR }, { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovsd_XMM10_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 10, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, { bs3CpuInstr3_vmovsd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesM), s_aValuesM }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * [V]MOVLPS - Merge a low qword (two single precision floating-point values) * from memory with the high qword from a register (SSE destination * or VEX 2nd source). * The store variant just stores the high qword. * [V]MOVLPD - Same, just using double precision floating-point unit. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movlps_movlpd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesLd[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSt[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_movlpd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movlpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, { bs3CpuInstr3_vmovlpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovlpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_movlpd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movlpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, { bs3CpuInstr3_vmovlpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovlpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movlps_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_movlps_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_movlpd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movlpd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movlpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_movlpd_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovlps_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, { bs3CpuInstr3_vmovlps_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, { bs3CpuInstr3_vmovlpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovlpd_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovlpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, { bs3CpuInstr3_vmovlpd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * [V]MOVHPS - Merge a high qword (two single precision floating-point values) * from memory with the low qword from a register (SSE destination * or VEX 2nd source). * The store variant just stores the high qword. * [V]MOVHPD - Same, just using double precision floating-point unit. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movhps_movhpd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesLd[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xc1c2c3c4c5c6c7c8, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x5555666677778888, 0xddddeeeeffff0000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9c5ce073930996bb, 0x43d3cda0238499fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSt[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*ign*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*ign*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xd1d2d3d4d5d6d7d8) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8), /*ign*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x1111222233334444) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*ign*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xb4212fa8564c9ba2) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_movhps_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movhps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_movhpd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movhpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_vmovhps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovhps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, { bs3CpuInstr3_vmovhpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovhpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_movhps_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movhps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_movhpd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movhpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_vmovhps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovhps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, { bs3CpuInstr3_vmovhpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovhpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_movhps_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movhps_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movhps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_movhps_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_movhpd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movhpd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_movhpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_movhpd_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, { bs3CpuInstr3_vmovhps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovhps_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovhps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, { bs3CpuInstr3_vmovhps_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, { bs3CpuInstr3_vmovhpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovhpd_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, { bs3CpuInstr3_vmovhpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, { bs3CpuInstr3_vmovhpd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * [V]MOVHLPS - Move high qword in source (2) to low qword in destination, leaving * the high qword in the destination as it was. The VEX variant * takes the high qword from the first source operand. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movhlps(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xd1d2d3d4d5d6d7d8) }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x1111222233334444) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0xb4212fa8564c9ba2) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_movhlps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovhlps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_movhlps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovhlps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_movhlps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movhlps_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 12, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovhlps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovhlps_XMM10_XMM14_XMM12_icebp_c64, 255, RM_REG, T_AVX_128, 10, 14, 12, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * [V]PAVGB - Average unsigned packed byte integers with rounding. * [V]PAVGW - Average unsigned packed word integers with rounding. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pavgb_pavgw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8, 0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3673e76b3ba053b5, 0x9ca853da536f4b8d, 0x9e118c828b737fb3, 0x7098d78a5b4798dc) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8, 0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x35f3e6eb3b205335, 0x9c28535a536f4b0d, 0x9e118c828af37f33, 0x7018d70a5b47985c) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pavgb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pavgw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pavgw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pavgw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pavgb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pavgw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pavgw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pavgw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pavgb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpavgb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pavgw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pavgw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pavgw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pavgw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pavgw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pavgw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpavgw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PSIGNB - Negate/Zero/Keep the destination packed byte integers based on the sign of the corresponding source operand. * [V]PSIGNW - Negate/Zero/Keep the destination packed word integers based on the sign of the corresponding source operand. * [V]PSIGND - Negate/Zero/Keep the destination packed doubleword integers based on the sign of the corresponding source operand. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psignb_psignw_psignd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x4f4e4d4c4b4a4948, 0x5f5e5d5c5b5a5958, 0x6f6e6d6c6b6a6968, 0x7f7e7d7c7b7a7978) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1edd23ac099d326c, 0xf9a48e14407256cd, 0x7800e9a5bf999e3d, 0xbdd333a0dd846703) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x4e4e4c4c4a4a4848, 0x5e5e5c5c5a5a5858, 0x6e6e6c6c6a6a6868, 0x7e7e7c7c7a7a7878) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1edd225409633294, 0xf95c8eec40725633, 0x7800e95bbf999d3d, 0xbc2d3260dc7c6603) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x4e4d4c4c4a494848, 0x5e5d5c5c5a595858, 0x6e6d6c6c6a696868, 0x7e7d7c7c7a797878) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x77ff16a5bf9962c3, 0xbc2c3260dc7b6603) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_psignb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psignd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psignd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psignd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_psignb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psignd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psignd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psignd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_psignb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpsignb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_psignw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpsignw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_psignd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psignd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psignd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psignd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psignd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_psignd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpsignd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PHADDW - Horizontally add word sized signed integers. * [V]PHADDD - Horizontally add doubleword sized signed integers. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phaddw_phaddd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x85868d8e05060d0e) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x7ccf29c41173bd81) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 9, 10, 0xa5a6adae85868d8e, 0x25262d2e05060d0e) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 13, 14, 0xe3c9f1ee7ccf29c4, 0x715b225c1173bd81) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xe5e6edeec5c6cdce, 0x65666d6e45464d4e, 0xa5a6adae85868d8e, 0x25262d2e05060d0e) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3d33e0b156bca651, 0xfc893bf7884896a5, 0xe3c9f1ee7ccf29c4, 0x715b225c1173bd81) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64D[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x87898b8c07090b0c) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x2f66772e6758679d) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128D[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 9, 10, 0xa7a9abac87898b8c, 0x27292b2c07090b0c) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 13, 14, 0x0a6dcb4a2f66772e, 0x479a4c1e6758679d) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256D[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xe7e9ebecc7c9cbcc, 0x67696b6c47494b4c, 0xa7a9abac87898b8c, 0x27292b2c07090b0c) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xb9e663ffa55f57ae, 0x2841104039cee51f, 0x0a6dcb4a2f66772e, 0x479a4c1e6758679d) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phaddw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phaddw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphaddw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphaddw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_phaddd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_phaddd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphaddd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphaddd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, { bs3CpuInstr3_vphaddd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256D), s_aValues256D }, { bs3CpuInstr3_vphaddd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PHSUBW - Horizontally subtract word sized signed integers. * [V]PHSUBD - Horizontally subtract doubleword sized signed integers. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phsubw_phsubd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0202020202020202) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x441703b289cd7679) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 9, 10, 0x0202020202020202, 0x0202020202020202) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 13, 14, 0x7b874556441703b2, 0x615ba32a89cd7679) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0202020202020202, 0x0202020202020202, 0x0202020202020202, 0x0202020202020202) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xa32106f9d8d4d97b, 0xbecf2931959015c1, 0x7b874556441703b2, 0x615ba32a89cd7679) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64D[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0404040404040404) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 5, 6, 7, 0xf6acb648dfb0cc5d) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128D[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 9, 10, 0x0404040404040404, 0x0404040404040404) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 13, 14, 0xa22b6bfaf6acb648, 0x37987968dfb0cc5d) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256D[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0404040404040404, 0x0404040404040404, 0x0404040404040404, 0x0404040404040404) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1fd283ab2777281e, 0xea8554e84715c747, 0xa22b6bfaf6acb648, 0x37987968dfb0cc5d) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_phsubw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phsubw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphsubw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_phsubd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phsubd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phsubd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_phsubd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphsubd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphsubd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphsubd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, { bs3CpuInstr3_vphsubd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_phsubw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phsubw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphsubw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_phsubd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phsubd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phsubd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_phsubd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphsubd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphsubd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphsubd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, { bs3CpuInstr3_vphsubd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_phsubw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phsubw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phsubw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phsubw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphsubw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphsubw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphsubw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_phsubd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phsubd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, { bs3CpuInstr3_phsubd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_phsubd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_phsubd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_phsubd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphsubd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphsubd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphsubd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphsubd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, { bs3CpuInstr3_vphsubd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, { bs3CpuInstr3_vphsubd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, { bs3CpuInstr3_vphsubd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256D), s_aValues256D }, { bs3CpuInstr3_vphsubd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PHADDSW - Horizontally add and saturate word sized signed integers. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phaddsw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x85868d8e80008000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x800080001173bd81) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 9, 10, 0xa5a6adae85868d8e, 0x8000800080008000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 13, 14, 0xe3c9f1ee80008000, 0x8000225c1173bd81) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xe5e6edeec5c6cdce, 0x8000800080008000, 0xa5a6adae85868d8e, 0x8000800080008000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3d337fff56bc7fff, 0xfc893bf788487fff, 0xe3c9f1ee80008000, 0x8000225c1173bd81) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_phaddsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phaddsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphaddsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_phaddsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phaddsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphaddsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_phaddsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phaddsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phaddsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phaddsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phaddsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphaddsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphaddsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphaddsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphaddsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PHSUBSW - Horizontally subtract and saturate word sized signed integers. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phsubsw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0202020202020202) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x441703b289cd8000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 9, 10, 0x0202020202020202, 0x0202020202020202) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 13, 14, 0x7b878000441703b2, 0x615b7fff89cd8000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0202020202020202, 0x0202020202020202, 0x0202020202020202, 0x0202020202020202) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xa32106f9d8d4d97b, 0xbecf2931959015c1, 0x7b878000441703b2, 0x615b7fff89cd8000) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_phsubsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phsubsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphsubsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_phsubsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phsubsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphsubsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_phsubsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_phsubsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phsubsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phsubsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_phsubsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vphsubsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphsubsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphsubsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vphsubsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PMADDUBSW - Horizontally multiply signed by unsigned bytes, add and saturate to signed integer words. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaddubsw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xc0c5c1d9c2fdc431) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x31a82e40f5bd8000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 9, 10, 0xcb25ccb9ce5dd011, 0xc0c5c1d9c2fdc431) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 13, 14, 0xd7a00b7f6d9691bc, 0x31a82e40f5bd8000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xebe5ee79f11df3d1, 0xd985db99ddbddff1, 0xcb25ccb9ce5dd011, 0xc0c5c1d9c2fdc431) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x10cb0e68f5e0fd9a, 0x37fed92249260ffc, 0xd7a00b7f6d9691bc, 0x31a82e40f5bd8000) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pmaddubsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddubsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddubsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_pmaddubsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pmaddubsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddubsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddubsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_pmaddubsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pmaddubsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddubsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddubsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_pmaddubsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_pmaddubsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_pmaddubsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddubsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddubsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vpmaddubsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vpmaddubsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PMULHRSW - Vertically multiply, round and scale word sized signed integers and extract the high 16-bits. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmulhrsw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0899072e05d40489, 0x16341448126d10a1, 0x27d7256a230e20c1, 0x3d823a9437b734e9) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1293043f07fc2dc5, 0xfcbceafe33912b08, 0x4721f792d495b28f, 0xcb340c6be1c453e5) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pmulhrsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmulhrsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmulhrsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmulhrsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pmulhrsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmulhrsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmulhrsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmulhrsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pmulhrsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmulhrsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmulhrsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmulhrsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmulhrsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmulhrsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PSADBW - Compute sum of absolute differences of packed unsigned byte integers. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psadbw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000200, 0x0000000000000200, 0x0000000000000200, 0x0000000000000200) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x00000000000002f6, 0x00000000000002e5, 0x0000000000000264, 0x0000000000000240) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_psadbw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_psadbw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_psadbw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_psadbw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_psadbw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpsadbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PMULDQ - Multiply packed signed double word integers. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmuldq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x02e97bbaf7148240, 0x0935ee3369408840, 0x118666b3e1709040, 0x1bdae53c5fa49a40) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x03fdeed546719124, 0x19c88e386340fed2, 0xea4a418ff1c09066, 0xf0e1df0254fbb9cf) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pmuldq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuldq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pmuldq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuldq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pmuldq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuldq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuldq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuldq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuldq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PMULUDQ - Multiply packed unsigned double word integers. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmuludq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xae972b6af7148240, 0x94c37dc369408840, 0x7cf3d623e1709040, 0x6728348c5fa49a40) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x03fdeed546719124, 0x19c88e386340fed2, 0x4096dd31f1c09066, 0x146678ff54fbb9cf) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pmuludq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuludq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuludq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuludq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pmuludq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuludq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuludq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuludq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pmuludq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuludq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuludq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuludq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuludq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmuludq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmuludq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PUNPCKLPS - Unpack and interleave low packed single precision FP values. * [V]PUNPCKLPD - Unpack and interleave low packed double precision FP values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklps_punpcklpd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesS[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xe1e2e3e4a1a2a3a4, 0xe5e6e7e8a5a6a7a8, 0xc1c2c3c481828384, 0xc5c6c7c885868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3ef417c8f95c8eec, 0x666b3fe640725633, 0x9c5ce07343d3cda0, 0x930996bb238499fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xe1e2e3e4e5e6e7e8, 0xa1a2a3a4a5a6a7a8, 0xc1c2c3c4c5c6c7c8, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0xf95c8eec40725633, 0x9c5ce073930996bb, 0x43d3cda0238499fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_unpcklps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpcklps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpcklpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_unpcklpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_unpcklps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpcklps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpcklpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_unpcklpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_unpcklps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpcklps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpcklps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpcklps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpcklps_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpcklpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_unpcklpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_unpcklpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_unpcklpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpcklpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PUNPCKHPS - Unpack and interleave low packed single precision FP values. * [V]PUNPCKHPD - Unpack and interleave low packed double precision FP values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhps_punpckhpd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesS[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4b1b2b3b4, 0xf5f6f7f8b5b6b7b8, 0xd1d2d3d491929394, 0xd5d6d7d895969798) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a1eddddac, 0x6cdc73d509633294, 0xb4212fa88800e95b, 0x564c9ba2bf9962c3) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xb1b2b3b4b5b6b7b8, 0xd1d2d3d4d5d6d7d8, 0x9192939495969798) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x1eddddac09633294, 0xb4212fa8564c9ba2, 0x8800e95bbf9962c3) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_unpckhps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpckhps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpckhpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_unpckhpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_unpckhps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpckhps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpckhpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_unpckhpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_unpckhps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpckhps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpckhps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpckhps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_vunpckhps_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, { bs3CpuInstr3_unpckhpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_unpckhpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_unpckhpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_unpckhpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vunpckhpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]SHUFPS - Shuffle two pairs of single precision floating point values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_shufps(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f1f2f3f4, 0xb1b2b3b4b1b2b3b4, 0xd1d2d3d4d1d2d3d4, 0x9192939491929394) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a4d09f02a, 0x1eddddac1eddddac, 0xb4212fa8b4212fa8, 0x8800e95b8800e95b) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xe5e6e7e8e5e6e7e8, 0xa5a6a7a8a5a6a7a8, 0xc5c6c7c8c5c6c7c8, 0x8586878885868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x666b3fe6666b3fe6, 0x4072563340725633, 0x930996bb930996bb, 0x238499fd238499fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_shufps_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufps_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufps_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_shufps_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_shufps_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufps_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufps_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_shufps_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_shufps_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufps_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufps_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufps_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufps_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_shufps_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_shufps_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_shufps_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufps_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]SHUFPD - Shuffle two pairs of double precision floating point values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_shufpd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xb1b2b3b4b5b6b7b8, 0xd1d2d3d4d5d6d7d8, 0x9192939495969798) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x1eddddac09633294, 0xb4212fa8564c9ba2, 0x8800e95bbf9962c3) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xe1e2e3e4e5e6e7e8, 0xa1a2a3a4a5a6a7a8, 0xc1c2c3c4c5c6c7c8, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0xf95c8eec40725633, 0x9c5ce073930996bb, 0x43d3cda0238499fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_shufpd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufpd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufpd_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_shufpd_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_shufpd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufpd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufpd_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_shufpd_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_shufpd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufpd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufpd_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufpd_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_shufpd_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_shufpd_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_shufpd_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_shufpd_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vshufpd_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PALIGNR - Concatenate and align source operands to the right. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_palignr(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64B_03[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 17, 18, 19, 0x868788c1c2c3c4c5) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 21, 22, 23, 0x8499fd9c5ce07393) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64B_09[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 17, 18, 19, 0x0081828384858687) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 21, 22, 23, 0x0043d3cda0238499) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128B_03[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 17, 18, 0x868788d1d2d3d4d5, 0xd6d7d8c1c2c3c4c5) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 21, 22, 0x8499fdb4212fa856, 0x4c9ba29c5ce07393) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128B_13[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 17, 18, 0x0000009192939495, 0x9697988182838485) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 21, 22, 0x0000008800e95bbf, 0x9962c343d3cda023) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256B_03[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xa6a7a8f1f2f3f4f5, 0xf6f7f8e1e2e3e4e5, 0x868788d1d2d3d4d5, 0xd6d7d8c1c2c3c4c5) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x7256334d09f02a6c, 0xdc73d53ef417c866, 0x8499fdb4212fa856, 0x4c9ba29c5ce07393) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256B_13[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x000000b1b2b3b4b5, 0xb6b7b8a1a2a3a4a5, 0x0000009192939495, 0x9697988182838485) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000001eddddac09, 0x633294f95c8eec40, 0x0000008800e95bbf, 0x9962c343d3cda023) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_palignr_MM1_MM2_0FFh_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_MM1_MM2_000h_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_MM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_MM1_MM2_003h_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, { bs3CpuInstr3_palignr_MM1_FSxBX_003h_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, { bs3CpuInstr3_palignr_MM1_MM2_009h_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, { bs3CpuInstr3_palignr_MM1_FSxBX_009h_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, { bs3CpuInstr3_palignr_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_XMM1_XMM2_003h_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_palignr_XMM1_FSxBX_003h_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_palignr_XMM1_XMM2_013h_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_palignr_XMM1_FSxBX_013h_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_003h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_003h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_013h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_013h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_003h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_003h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_013h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_013h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_palignr_MM1_MM2_0FFh_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_MM1_MM2_000h_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_MM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_MM1_MM2_003h_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, { bs3CpuInstr3_palignr_MM1_FSxBX_003h_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, { bs3CpuInstr3_palignr_MM1_MM2_009h_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, { bs3CpuInstr3_palignr_MM1_FSxBX_009h_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, { bs3CpuInstr3_palignr_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_XMM1_XMM2_003h_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_palignr_XMM1_FSxBX_003h_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_palignr_XMM1_XMM2_013h_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_palignr_XMM1_FSxBX_013h_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_003h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_003h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_013h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_013h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_003h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_003h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_013h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_013h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_palignr_MM1_MM2_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_MM1_MM2_000h_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_MM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_MM1_MM2_003h_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, { bs3CpuInstr3_palignr_MM1_FSxBX_003h_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, { bs3CpuInstr3_palignr_MM1_MM2_009h_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, { bs3CpuInstr3_palignr_MM1_FSxBX_009h_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, { bs3CpuInstr3_palignr_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_palignr_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_palignr_XMM1_XMM2_003h_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_palignr_XMM1_FSxBX_003h_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_palignr_XMM8_XMM9_003h_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_palignr_XMM8_FSxBX_003h_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_palignr_XMM1_XMM2_013h_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_palignr_XMM1_FSxBX_013h_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_palignr_XMM8_XMM9_013h_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_palignr_XMM8_FSxBX_013h_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_003h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_003h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_013h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_013h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_013h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_013h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_003h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, { bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_003h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, { bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_013h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_013h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, { bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_013h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, { bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_013h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PBLENDW - Blend packed words based on an 8-bit immediate. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pblendw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues7A[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2f3f4f5f6f7f8, 0xe1e2a3a4e5e6a7a8, 0x9192d3d4d5d6d7d8, 0xc1c28384c5c68788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddf02a6cdc73d5, 0x3ef48eec666b5633, 0x88002fa8564c9ba2, 0x9c5ccda0930999fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pblendw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pblendw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pblendw_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pblendw_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pblendw_XMM1_XMM2_07Ah_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_pblendw_XMM1_FSxBX_07Ah_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_07Ah_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_07Ah_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_07Ah_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_07Ah_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pblendw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pblendw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pblendw_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pblendw_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pblendw_XMM1_XMM2_07Ah_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_pblendw_XMM1_FSxBX_07Ah_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_07Ah_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_07Ah_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_07Ah_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_07Ah_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pblendw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pblendw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pblendw_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pblendw_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pblendw_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pblendw_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pblendw_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pblendw_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pblendw_XMM1_XMM2_07Ah_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_pblendw_XMM1_FSxBX_07Ah_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_pblendw_XMM8_XMM9_07Ah_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_pblendw_XMM8_FSxBX_07Ah_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_07Ah_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_XMM8_XMM9_XMM10_07Ah_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_XMM8_XMM9_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_07Ah_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_YMM8_YMM9_YMM10_07Ah_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendw_YMM8_YMM9_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * VPBLENDD - Blend packed dwords based on an 8-bit immediate. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vpblendd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues7A[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d495969798, 0xc1c2c3c485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8bf9962c3, 0x9c5ce073238499fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_vpblendd_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_XMM3_07Ah_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_FSxBX_07Ah_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_YMM3_07Ah_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_FSxBX_07Ah_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_vpblendd_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_XMM3_07Ah_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_FSxBX_07Ah_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_YMM3_07Ah_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_FSxBX_07Ah_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_vpblendd_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_XMM3_07Ah_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_XMM1_XMM2_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_XMM8_XMM9_XMM10_07Ah_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_XMM8_XMM9_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_YMM3_07Ah_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_YMM1_YMM2_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_YMM8_YMM9_YMM10_07Ah_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vpblendd_YMM8_YMM9_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]BLENDPS - Blend packed single precision floating point values based on an 8-bit immediate. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_blendps(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues7A[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d495969798, 0xc1c2c3c485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8bf9962c3, 0x9c5ce073238499fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_blendps_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendps_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendps_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendps_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendps_XMM1_XMM2_07Ah_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_blendps_XMM1_FSxBX_07Ah_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_07Ah_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_07Ah_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_07Ah_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_07Ah_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_blendps_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendps_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendps_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendps_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendps_XMM1_XMM2_07Ah_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_blendps_XMM1_FSxBX_07Ah_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_07Ah_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_07Ah_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_07Ah_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_07Ah_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_blendps_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendps_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendps_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendps_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendps_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendps_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendps_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendps_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendps_XMM1_XMM2_07Ah_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_blendps_XMM1_FSxBX_07Ah_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_blendps_XMM8_XMM9_07Ah_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_blendps_XMM8_FSxBX_07Ah_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_07Ah_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_XMM8_XMM9_XMM10_07Ah_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_XMM8_XMM9_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_07Ah_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_YMM8_YMM9_YMM10_07Ah_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues7A), s_aValues7A }, { bs3CpuInstr3_vblendps_YMM8_YMM9_FSxBX_07Ah_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues7A), s_aValues7A }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]BLENDPD - Blend packed double precision floating point values based on an 8-bit immediate. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_blendpd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues06[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0x8182838485868788) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x43d3cda0238499fd) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_blendpd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendpd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendpd_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendpd_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendpd_XMM1_XMM2_006h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_blendpd_XMM1_FSxBX_006h_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_006h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_006h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_006h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_006h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_blendpd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendpd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendpd_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendpd_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendpd_XMM1_XMM2_006h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_blendpd_XMM1_FSxBX_006h_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_006h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_006h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_006h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_006h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_blendpd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendpd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendpd_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendpd_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_blendpd_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendpd_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendpd_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendpd_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_blendpd_XMM1_XMM2_006h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_blendpd_XMM1_FSxBX_006h_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_blendpd_XMM8_XMM9_006h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_blendpd_XMM8_FSxBX_006h_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_006h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_006h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_XMM8_XMM9_XMM10_006h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_XMM8_XMM9_FSxBX_006h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_006h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_006h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_YMM8_YMM9_YMM10_006h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues06), s_aValues06 }, { bs3CpuInstr3_vblendpd_YMM8_YMM9_FSxBX_006h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues06), s_aValues06 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PCLMULQDQ - Carry-less multiplication of a quadword. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pclmulqdq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 1, 2, 0x6541a5056544a512, 0x6753a7176756a740) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 5, 6, 0x5fb1fa02ce11d9e9, 0x547462ca50871166) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 9, 10, 0x6041a0056044a012, 0x6253a2176256a240) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 13, 14, 0x26d2ea34453fe24f, 0x2592f499ed1f651f) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pclmulqdq_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_PCLMUL, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pclmulqdq_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_PCLMUL, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pclmulqdq_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_PCLMUL, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_pclmulqdq_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_PCLMUL, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * SHA1NEXTE / SHA1MSG1 / SHA1MSG2 / SHA256MSG1 / SHA256MSG2 / SHA1RNDS4 */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_sha1nexte_sha1msg1_sha1msg2_sha256msg1_sha256msg2_sha1rnds4(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Nexte[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 5, 6, 0xf63778b9d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(11, 12, 0x962169fe564c9ba2, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Msg1[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 5, 6, 0x1010101010101010, 0x5050505050505050) }, { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(11, 12, 0xcbd324fb9c1dfb3e, 0xf7f2e20875c8025f) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Msg2[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 5, 6, 0x88888898a8a8a8b8, 0x888888981a1c1e20) }, { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(11, 12, 0xbc98e5f3478b0560, 0xa1b4b6373e38f81d) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha256Msg1[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 5, 6, 0xca53f79b358aeac9, 0x08025e3d3f58fc9f) }, { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(11, 12, 0x88eaae935be061bc, 0x0c10bf1bdf1a68d8) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha256Msg2[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 5, 6, 0xf7787989ecaccf3a, 0xb52709eb36a88d6c) }, { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(11, 12, 0x934e65a33794af02, 0xf5e0127f02358cc6) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Rnds4_00[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0xf4054bb3b4b8122e, 0x2ab46b3156a09e66) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 5, 6, 0x06d22bcd4846b4fd, 0x6f0a329ef80a90df) }, { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(11, 12, 0x9ba220d389ecd7df, 0xbabf326a8495ab9b) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Rnds4_01[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0x9475322b209fd10b, 0x9285d7f35bb67ae8) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 5, 6, 0x5b7c09a1f4668273, 0xe4796d15c1247166) }, { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(11, 12, 0xff4d24899413cadf, 0xda6c122200b99f56) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Rnds4_02[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0xe277565de186ca8a, 0x5ca4d61b23c6ef37) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 5, 6, 0x8b663a7f9465c97a, 0xe13b3e408631e2b2) }, { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(11, 12, 0x39eefe319badc2bb, 0xec8afdbd99baf875) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Rnds4_03[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0xf328407d6c25198e, 0xc5aebf2bb298b075) }, { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 5, 6, 0x1633e2343fedcafc, 0x17a2544e1806a6f4) }, { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(11, 12, 0xe4449478c8994eba, 0xcd94f95a579bd4e3) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_sha1nexte_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, { bs3CpuInstr3_sha1nexte_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, { bs3CpuInstr3_sha1msg1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, { bs3CpuInstr3_sha1msg1_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, { bs3CpuInstr3_sha1msg2_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, { bs3CpuInstr3_sha1msg2_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, { bs3CpuInstr3_sha256msg1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, { bs3CpuInstr3_sha256msg1_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, { bs3CpuInstr3_sha256msg2_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, { bs3CpuInstr3_sha256msg2_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_001h_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_002h_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_002h_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_003h_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_003h_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_sha1nexte_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, { bs3CpuInstr3_sha1nexte_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, { bs3CpuInstr3_sha1msg1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, { bs3CpuInstr3_sha1msg1_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, { bs3CpuInstr3_sha1msg2_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, { bs3CpuInstr3_sha1msg2_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, { bs3CpuInstr3_sha256msg1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, { bs3CpuInstr3_sha256msg1_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, { bs3CpuInstr3_sha256msg2_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, { bs3CpuInstr3_sha256msg2_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_001h_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_002h_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_002h_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_003h_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_003h_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_sha1nexte_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, { bs3CpuInstr3_sha1nexte_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, { bs3CpuInstr3_sha1nexte_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, { bs3CpuInstr3_sha1nexte_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, { bs3CpuInstr3_sha1msg1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, { bs3CpuInstr3_sha1msg1_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, { bs3CpuInstr3_sha1msg1_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, { bs3CpuInstr3_sha1msg1_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, { bs3CpuInstr3_sha1msg2_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, { bs3CpuInstr3_sha1msg2_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, { bs3CpuInstr3_sha1msg2_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, { bs3CpuInstr3_sha1msg2_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, { bs3CpuInstr3_sha256msg1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, { bs3CpuInstr3_sha256msg1_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, { bs3CpuInstr3_sha256msg1_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, { bs3CpuInstr3_sha256msg1_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, { bs3CpuInstr3_sha256msg2_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, { bs3CpuInstr3_sha256msg2_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, { bs3CpuInstr3_sha256msg2_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, { bs3CpuInstr3_sha256msg2_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_001h_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_002h_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_002h_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_003h_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_003h_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, { bs3CpuInstr3_sha1rnds4_XMM9_XMM8_000h_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, { bs3CpuInstr3_sha1rnds4_XMM9_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, { bs3CpuInstr3_sha1rnds4_XMM9_XMM8_001h_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, { bs3CpuInstr3_sha1rnds4_XMM9_FSxBX_001h_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, { bs3CpuInstr3_sha1rnds4_XMM9_XMM8_002h_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, { bs3CpuInstr3_sha1rnds4_XMM9_FSxBX_002h_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, { bs3CpuInstr3_sha1rnds4_XMM9_XMM8_003h_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, { bs3CpuInstr3_sha1rnds4_XMM9_FSxBX_003h_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]MPSADBW - Compute Multiple Packed Sums of Absolute Differences. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_mpsadbw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = { { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x00fc00f800f400f0, 0x01040118012c0140, 0x00fc00f800f400f0, 0x01040118012c0140) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x01c9025300f401c6, 0x016a00e1022f0223, 0x01bf010e01a700d1, 0x0155013300fa01c9) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x00d400e800fc0110, 0x010c010801040100, 0x00d400e800fc0110, 0x010c010801040100) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x00a401a1013100f7, 0x0180011e017400f7, 0x0104015600b9016c, 0x01a6017b005b0130) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_mpsadbw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_mpsadbw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_mpsadbw_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_mpsadbw_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_mpsadbw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_mpsadbw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_mpsadbw_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_mpsadbw_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_mpsadbw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_mpsadbw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_mpsadbw_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_mpsadbw_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_mpsadbw_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_mpsadbw_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_mpsadbw_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_mpsadbw_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vmpsadbw_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * VINSERTI128/VINSERTF128 - Insert Packed Integer Values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vinserti128_vinsertf128(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8, 0x9192939495969798, 0x8182838485868788) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinserti128_YMM8_YMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinserti128_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinserti128_YMM1_YMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinserti128_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinserti128_YMM8_YMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinserti128_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinsertf128_YMM8_YMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinsertf128_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinsertf128_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinsertf128_YMM8_YMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vinsertf128_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]INSERTPS. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_insertps(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesBth00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e, 0, 0), /*src1*/ RTUINT256_INIT_C(0xa110ca7ec01dce11, 0xdeadfacedecea5ed, 0, 0), /* => */ RTUINT256_INIT_C(0xbadf00d7a57e1e55, 0xba5eba11f007ba11, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xb01dface0ddba115, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), /*src1*/ RTUINT256_INIT_C(0xf0f1f2f3f4f5f6f7, 0xa5a5a5a5000f0ed0, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), /* => */ RTUINT256_INIT_C(0xf0f1f2f3f4f5f6f7, 0xa5a5a5a5000f0ed0, 0xa110ca7ec01dce11, 0xdeadfacebad7ab1e) }, { /*src2*/ RTUINT256_INIT_C(1, 2, 0xf00dfa5ef100df0e, 0xf7f7f7f700000000), /*src1*/ RTUINT256_INIT_C(3, 4, 0xf0f1f2f300000000, 0x81818181ffffffff), /* => */ RTUINT256_INIT_C(3, 4, 0xf0f1f2f300000000, 0x8181818100000000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesRegD5[] = { { /*src2*/ RTUINT256_INIT_C(1, 2, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), /*src1*/ RTUINT256_INIT_C(3, 4, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), /* => */ RTUINT256_INIT_C(3, 4, 0xa110ca7e00000000, 0xacce55ed00000000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesMemD5[] = { { /*src2*/ RTUINT256_INIT_C(1, 3, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), /*src1*/ RTUINT256_INIT_C(2, 4, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), /* => */ RTUINT256_INIT_C(2, 4, 0xa110ca7e00000000, 0xbad7ab1e00000000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesBth28[] = { { /*src2*/ RTUINT256_INIT_C(1, 2, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), /*src1*/ RTUINT256_INIT_C(3, 4, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), /* => */ RTUINT256_INIT_C(3, 4, 0x00000000bad7ab1e, 0xdeadfacedecea5ed) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesBthFF[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), /*src1*/ RTUINT256_INIT_C(0, 0, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xface1e55badb100d, 0xdeadfa11acc01ade, 0, 0), /*src1*/ RTUINT256_INIT_C(0xace0fdadca55e77e, 0xc105e1adf0015f0e, 0, 0), /* => */ RTUINT256_INIT_C(0xace0fdadca55e77e, 0xc105e1adf0015f0e, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), /*src1*/ RTUINT256_INIT_C(3, 4, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_insertps_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_insertps_XMM1_XMM2_0D5h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, { bs3CpuInstr3_insertps_XMM1_XMM2_028h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_insertps_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_insertps_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_insertps_XMM1_FSxBX_0D5h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, { bs3CpuInstr3_insertps_XMM1_FSxBX_028h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_insertps_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_000h_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0D5h_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_028h_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0FFh_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0D5h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_028h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_insertps_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_insertps_XMM1_XMM2_0D5h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, { bs3CpuInstr3_insertps_XMM1_XMM2_028h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_insertps_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, 2, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_insertps_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_insertps_XMM1_FSxBX_0D5h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, { bs3CpuInstr3_insertps_XMM1_FSxBX_028h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_insertps_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_SSE4_1, 1, 2, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_000h_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0D5h_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_028h_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0FFh_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0D5h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_028h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_insertps_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_insertps_XMM1_XMM2_0D5h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, { bs3CpuInstr3_insertps_XMM1_XMM2_028h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_insertps_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, 2, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_insertps_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_insertps_XMM1_FSxBX_0D5h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, { bs3CpuInstr3_insertps_XMM1_FSxBX_028h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_insertps_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 1, 2, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_000h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0D5h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_028h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0FFh_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0D5h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_028h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_insertps_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_insertps_XMM8_XMM9_0D5h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, { bs3CpuInstr3_insertps_XMM8_XMM9_028h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_insertps_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_insertps_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_insertps_XMM8_FSxBX_0D5h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, { bs3CpuInstr3_insertps_XMM8_FSxBX_028h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_insertps_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_vinsertps_XMM8_XMM9_XMM10_000h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_vinsertps_XMM8_XMM9_XMM10_0D5h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, { bs3CpuInstr3_vinsertps_XMM8_XMM9_XMM10_028h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_vinsertps_XMM8_XMM9_XMM10_0FFh_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, { bs3CpuInstr3_vinsertps_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, { bs3CpuInstr3_vinsertps_XMM8_XMM9_FSxBX_0D5h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, { bs3CpuInstr3_vinsertps_XMM8_XMM9_FSxBX_028h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, { bs3CpuInstr3_vinsertps_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * [V]PSUBSB/[V]PSUBSW - Subtract paced signed integers with signed saturation. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psubsb_psubsw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues8[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xc0c0c0c0c0c0c0c0, 0xc0c0c0c0c0c0c0c0, 0xc0c0c0c0c0c0c0c0, 0xc0c0c0c0c0c0c0c0) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xd1d4ed829d7fbfbf, 0xbb688024da07174d, 0xd4dfba7f80807f21, 0x7f80ed807f800342) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xbfc0bfc0bfc0bfc0, 0xbfc0bfc0bfc0bfc0, 0xbfc0bfc0bfc0bfc0, 0xbfc0bfc0bfc0bfc0) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xd1d4ed829c87bebf, 0xba688000da07164d, 0xd3dfb9b380007fff, 0x7fffed2d7fff0342) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_psubsb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_psubsb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_psubsb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubsb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PSUBUSB/[V]PSUBUSW - Subtract paced unsigned integers with unsigned saturation. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psubusb_psubusw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues8[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x00d4008200000000, 0xbb00772400071700, 0x0000ba00694d0021, 0x0077002d007b0342) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0xba6877240000164d, 0x0000b9b3694d0000, 0x0000000000000342) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_psubusb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubusw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubusw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubusw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_psubusb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubusw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubusw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubusw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_psubusb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpsubusb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_psubusw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubusw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubusw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubusw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubusw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psubusw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsubusw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PADDUSB/[V]PADDUSW - Add paced unsigned integers with unsigned saturation. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_paddusb_paddusw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues8[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x6be6ffd675ffa5ff, 0xffffa5ffa6dd95ff, 0xff21ffffffe5fdff, 0xdfffffffb68dffff) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x6be6ffff763fa669, 0xffffa6b4a6dd9619, 0xfffffffffffffe65, 0xe02fffffb68dffff) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_paddusb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddusw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddusw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddusw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_paddusb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddusw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddusw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddusw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_paddusb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddusb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddusw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddusw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddusw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddusw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddusw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddusw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddusw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PADDSB/[V]PADDSW - Add packed signed integers with signed saturation. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_paddsb_paddsw(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues8[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xa2a4a6a8aaacaeb0, 0x828486888a8c8e90, 0x8080808080808080, 0x8080808080808080) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x6be6cdd6753f7f80, 0x3750a5b47f7f7f19, 0x8021180315e5fd80, 0xdf2fad13b68d80b8) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xa3a4a7a8abacafb0, 0x838487888b8c8f90, 0x8000800080008000, 0x8000800080008000) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x6be6cdd6763f7fff, 0x3850a6b47fff7fff, 0x8000190315e5fe65, 0xe02fae13b68d8000) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_paddsb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_paddsb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_paddsb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpaddsb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_paddsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_paddsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpaddsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PSLLW/[V]PSLLD/[V]PSLLQ - Shift packed data left logical */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psllw_pslld_psllq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sll 0-by-16 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3dbabb5812c66528, 0xf2b81dd880e4ac66, 0x1000d2b67f32c586, 0x87a69b40470833fa) }, /* sll 1-by-16 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xb7406b0058c0a500, 0x5700bb001c808cc0, 0x000056c0e640b0c0, 0xf4c06800e1007f40) }, /* sll 6-by-16 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000543201), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* sll big-by-16 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_01[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3dbabb5812c66528, 0xf2b81dd880e4ac66, 0x1000d2b67f32c586, 0x87a69b40470833fa) }, /* sll 1-by-16 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_12[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* sll 0x12-by-16 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sll 0-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b67f32c586, 0x87a79b40470933fa) }, /* sll 1-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xb7776b0058cca500, 0x5723bb001c958cc0, 0x003a56c0e658b0c0, 0xf4f36800e1267f40) }, /* sll 6-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000fedca204), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* sll big-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_01[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b67f32c586, 0x87a79b40470933fa) }, /* sll 1-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_12[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x76b00000ca500000, 0x3bb0000058cc0000, 0xa56c00008b0c0000, 0x3680000067f40000) }, /* sll 0x12-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_big[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000fedca204), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* sll big-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sll 0-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b77f32c586, 0x87a79b40470933fa) }, /* sll 1-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xb7776b0258cca500, 0x5723bb101c958cc0, 0x003a56efe658b0c0, 0xf4f36808e1267f40) }, /* sll 6-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xf000000102030405), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* sll big-by-64 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64_01[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b77f32c586, 0x87a79b40470933fa) }, /* sll 1-by-64 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64_12[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x76b0258cca500000, 0x3bb101c958cc0000, 0xa56efe658b0c0000, 0x36808e1267f40000) }, /* sll 0x12-by-64 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64_big[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xf000000102030405), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* sll big-by-64 */ }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_psllw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psllw_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psllw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psllw_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_pslld_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_pslld_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_pslld_MM1_021h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_pslld_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_pslld_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_pslld_XMM1_021h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpslld_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_021h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpslld_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_021h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psllq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psllq_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psllq_MM1_045h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_psllq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psllq_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psllq_XMM1_045h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_045h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_045h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_psllw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psllw_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psllw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psllw_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_pslld_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_pslld_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_pslld_MM1_021h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_pslld_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_pslld_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_pslld_XMM1_021h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpslld_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_021h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpslld_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_021h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psllq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psllq_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psllq_MM1_045h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_psllq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psllq_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psllq_XMM1_045h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_045h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_045h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_psllw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psllw_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psllw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psllw_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psllw_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsllw_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsllw_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsllw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_XMM8_XMM9_001h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsllw_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsllw_YMM8_YMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsllw_YMM8_YMM9_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsllw_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_pslld_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_pslld_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_pslld_MM1_021h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_pslld_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_pslld_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_pslld_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_pslld_XMM1_021h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpslld_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpslld_XMM1_XMM2_021h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpslld_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpslld_YMM1_YMM2_021h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpslld_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_XMM8_XMM9_001h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpslld_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpslld_XMM8_XMM9_021h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpslld_YMM8_YMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpslld_YMM8_YMM9_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpslld_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpslld_YMM8_YMM9_021h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psllq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psllq_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psllq_MM1_045h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_psllq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psllq_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psllq_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psllq_XMM1_045h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsllq_XMM1_XMM2_045h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsllq_YMM1_YMM2_045h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsllq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_XMM8_XMM9_001h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsllq_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsllq_XMM8_XMM9_045h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsllq_YMM8_YMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllq_YMM8_YMM9_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsllq_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsllq_YMM8_YMM9_045h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PSRAW/[V]PSRAD - Shift packed data right arithmetic (PSRAQ doesn't exist until AVX512) */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psraw_psrad(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sra 0-by-16 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6eeed604b1194a, 0xfcaec77620392b19, 0xc400f4addfcc3161, 0x21e9e6d011c2ccfe) }, /* sra 1-by-16 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x007bff76002500ca, 0xffe5fe3b01010158, 0xfe20ffa5fefe018b, 0x010fff36008efe67) }, /* sra 6-by-16 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000543201), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000ffff00000000, 0xffffffff00000000, 0xffffffffffff0000, 0x0000ffff0000ffff) }, /* sra big-by-16 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_01[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6eeed604b1194a, 0xfcaec77620392b19, 0xc400f4addfcc3161, 0x21e9e6d011c2ccfe) }, /* sra 1-by-16 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_12[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000ffff00000000, 0xffffffff00000000, 0xffffffffffff0000, 0x0000ffff0000ffff) }, /* sra 0x12-by-16 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sra 0-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0xfcae477620392b19, 0xc40074addfccb161, 0x21e9e6d011c24cfe) }, /* sra 1-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x007b777600258cca, 0xffe5723b0101c958, 0xfe2003a5fefe658b, 0x010f4f36008e1267) }, /* sra 6-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000fedca204), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0xffffffff00000000, 0xffffffffffffffff, 0x0000000000000000) }, /* sra big-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_01[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0xfcae477620392b19, 0xc40074addfccb161, 0x21e9e6d011c24cfe) }, /* sra 1-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_12[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x000007b700000258, 0xfffffe570000101c, 0xffffe200ffffefe6, 0x000010f4000008e1) }, /* sra 0x12-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_big[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000fedca204), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0xffffffff00000000, 0xffffffffffffffff, 0x0000000000000000) }, /* sra big-by-32 */ }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_psraw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psraw_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psraw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psraw_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psrad_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrad_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrad_MM1_021h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psrad_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrad_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrad_XMM1_021h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_021h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_021h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_psraw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psraw_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psraw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psraw_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psrad_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrad_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrad_MM1_021h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psrad_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrad_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrad_XMM1_021h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_021h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_021h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_psraw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psraw_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psraw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psraw_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psraw_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsraw_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsraw_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsraw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_XMM8_XMM9_001h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsraw_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsraw_YMM8_YMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsraw_YMM8_YMM9_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsraw_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psrad_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrad_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrad_MM1_021h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psrad_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrad_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrad_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrad_XMM1_021h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrad_XMM1_XMM2_021h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrad_YMM1_YMM2_021h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrad_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_XMM8_XMM9_001h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrad_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrad_XMM8_XMM9_021h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrad_YMM8_YMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrad_YMM8_YMM9_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrad_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrad_YMM8_YMM9_021h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PSRLW/[V]PSRLD/[V]PSRLQ - Shift packed data right logical */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psrlw_psrld_psrlq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* srl 0-by-16 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6e6ed604b1194a, 0x7cae477620392b19, 0x440074ad5fcc3161, 0x21e966d011c24cfe) }, /* srl 1-by-16 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x007b0376002500ca, 0x03e5023b01010158, 0x022003a502fe018b, 0x010f0336008e0267) }, /* srl 6-by-16 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000543201), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* srl big-by-16 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_01[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6e6ed604b1194a, 0x7cae477620392b19, 0x440074ad5fcc3161, 0x21e966d011c24cfe) }, /* srl 1-by-16 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues16_12[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* srl 0x12-by-16 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* srl 0-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074ad5fccb161, 0x21e9e6d011c24cfe) }, /* srl 1-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x007b777600258cca, 0x03e5723b0101c958, 0x022003a502fe658b, 0x010f4f36008e1267) }, /* srl 6-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000fedca204), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* srl big-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_01[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074ad5fccb161, 0x21e9e6d011c24cfe) }, /* srl 1-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_12[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x000007b700000258, 0x00003e570000101c, 0x0000220000002fe6, 0x000010f4000008e1) }, /* srl 0x12-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32_big[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000fedca204), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* srl big-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* srl 0-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074addfccb161, 0x21e9e6d011c24cfe) }, /* srl 1-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x007b7776b0258cca, 0x03e5723bb101c958, 0x022003a56efe658b, 0x010f4f36808e1267) }, /* srl 6-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xf000000102030405), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* srl big-by-64 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64_01[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074addfccb161, 0x21e9e6d011c24cfe) }, /* srl 1-by-64 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64_12[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x000007b7776b0258, 0x00003e5723bb101c, 0x000022003a56efe6, 0x000010f4f36808e1) }, /* srl 0x12-by-64 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64_big[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xf000000102030405), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* srl big-by-64 */ }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_psrlw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psrlw_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psrlw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psrlw_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psrld_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrld_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrld_MM1_021h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psrld_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrld_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrld_XMM1_021h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_021h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_021h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psrlq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_MM1_001h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psrlq_MM1_012h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psrlq_MM1_045h_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_psrlq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psrlq_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psrlq_XMM1_045h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_045h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_045h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_psrlw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psrlw_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psrlw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psrlw_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psrld_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrld_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrld_MM1_021h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psrld_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrld_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrld_XMM1_021h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_021h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_021h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psrlq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_MM1_001h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psrlq_MM1_012h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psrlq_MM1_045h_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_psrlq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psrlq_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psrlq_XMM1_045h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_045h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_045h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_psrlw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psrlw_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psrlw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_psrlw_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_psrlw_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsrlw_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsrlw_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsrlw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_XMM8_XMM9_001h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsrlw_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_vpsrlw_YMM8_YMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpsrlw_YMM8_YMM9_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, { bs3CpuInstr3_vpsrlw_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, { bs3CpuInstr3_psrld_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrld_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrld_MM1_021h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psrld_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_psrld_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_psrld_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_psrld_XMM1_021h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrld_XMM1_XMM2_021h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrld_YMM1_YMM2_021h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrld_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_XMM8_XMM9_001h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrld_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrld_XMM8_XMM9_021h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_vpsrld_YMM8_YMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrld_YMM8_YMM9_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, { bs3CpuInstr3_vpsrld_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, { bs3CpuInstr3_vpsrld_YMM8_YMM9_021h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues32_big), s_aValues32_big }, { bs3CpuInstr3_psrlq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_MM1_001h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psrlq_MM1_012h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psrlq_MM1_045h_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_psrlq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_psrlq_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_psrlq_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_psrlq_XMM1_045h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsrlq_XMM1_XMM2_045h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsrlq_YMM1_YMM2_045h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsrlq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_XMM8_XMM9_001h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsrlq_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsrlq_XMM8_XMM9_045h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, { bs3CpuInstr3_vpsrlq_YMM8_YMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlq_YMM8_YMM9_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, { bs3CpuInstr3_vpsrlq_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, { bs3CpuInstr3_vpsrlq_YMM8_YMM9_045h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues64_big), s_aValues64_big }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * VPSLLVD/VPSLLVQ - Variable bit shift left logical */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vpsllvd_vpsllvq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sll 0-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000100000001, 0x0000000100000001, 0x0000000100000001, 0x0000000100000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b67f32c586, 0x87a79b40470933fa) }, /* sll 1-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000600000006, 0x0000000600000006, 0x0000000600000006, 0x0000000600000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xb7776b0058cca500, 0x5723bb001c958cc0, 0x003a56c0e658b0c0, 0xf4f36800e1267f40) }, /* sll 6-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000300000000, 0x000000160000001F, 0x0000000600000001, 0x0000300100000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xf6eeed6009633294, 0xbb00000080000000, 0x003a56c07f32c586, 0x00000000e1267f40) }, /* sll v-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sll 0-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000001, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b77f32c586, 0x87a79b40470933fa) }, /* sll 1-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000006, 0x0000000000000006, 0x0000000000000006, 0x0000000000000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0xb7776b0258cca500, 0x5723bb101c958cc0, 0x003a56efe658b0c0, 0xf4f36808e1267f40) }, /* sll 6-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x000000000000001F, 0x0000000000000001, 0xfedcba9876543210), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0x20392B1980000000, 0x1001d2b77f32c586, 0x0000000000000000) }, /* sll v-by-64 */ }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_vpsllvd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_vpsllvd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_vpsllvd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsllvq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsllvq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * VPSRAVD - Variable bit shift right arithmetic */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vpsravd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* sra 0-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000100000001, 0x0000000100000001, 0x0000000100000001, 0x0000000100000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0xfcae477620392b19, 0xc40074addfccb161, 0x21e9e6d011c24cfe) }, /* sra 1-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000600000006, 0x0000000600000006, 0x0000000600000006, 0x0000000600000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x007b777600258cca, 0xffe5723b0101c958, 0xfe2003a5fefe658b, 0x010f4f36008e1267) }, /* sra 6-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000300000000, 0x000000160000001F, 0x0000000600000001, 0x0000300100000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x03dbbbb509633294, 0xffffffe500000000, 0xfe2003a5dfccb161, 0x00000000008e1267) }, /* sra v-by-32 */ }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_vpsravd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_vpsravd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_vpsravd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsravd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * VPSRLVD/VPSRLVQ - Variable bit shift right logical */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vpsrlvd_vpsrlvq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* srl 0-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000100000001, 0x0000000100000001, 0x0000000100000001, 0x0000000100000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074ad5fccb161, 0x21e9e6d011c24cfe) }, /* srl 1-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000600000006, 0x0000000600000006, 0x0000000600000006, 0x0000000600000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x007b777600258cca, 0x03e5723b0101c958, 0x022003a502fe658b, 0x010f4f36008e1267) }, /* srl 6-by-32 */ { /*src2*/ RTUINT256_INIT_C(0x0000000300000000, 0x000000160000001F, 0x0000000600000001, 0x0000300100000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x03dbbbb509633294, 0x000003e500000000, 0x022003a55fccb161, 0x00000000008e1267) }, /* srl v-by-32 */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* srl 0-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000001, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074addfccb161, 0x21e9e6d011c24cfe) }, /* srl 1-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000006, 0x0000000000000006, 0x0000000000000006, 0x0000000000000006), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x007b7776b0258cca, 0x03e5723bb101c958, 0x022003a56efe658b, 0x010f4f36808e1267) }, /* srl 6-by-64 */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x000000000000001F, 0x0000000000000001, 0xfedcba9876543210), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0x00000001f2b91dd8, 0x440074addfccb161, 0x0000000000000000) }, /* srl v-by-64 */ }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_vpsrlvd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_vpsrlvd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_vpsrlvd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpsrlvq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpsrlvq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]PSLLDQ/[V]PSRLDQ - Shift Double Quadword Left / Right Logical */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pslldq_v_psrldq(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesX00[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, /* no shift */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesL05[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x633294f95c8eec40, 0x7256330000000000, 0x9962c343d3cda023, 0x8499fd0000000000) }, /* 5 bytes left */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesR05[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x00000000001edddd, 0xac09633294f95c8e, 0x00000000008800e9, 0x5bbf9962c343d3cd) }, /* 5 bytes right */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesX12[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, /* shift too far */ }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pslldq_XMM1_000h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_pslldq_XMM1_005h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_pslldq_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpslldq_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpslldq_XMM1_XMM2_005h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_vpslldq_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpslldq_YMM1_YMM2_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpslldq_YMM1_YMM2_005h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_vpslldq_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_psrldq_XMM1_000h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_psrldq_XMM1_005h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_psrldq_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpsrldq_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpsrldq_XMM1_XMM2_005h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_vpsrldq_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpsrldq_YMM1_YMM2_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpsrldq_YMM1_YMM2_005h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_vpsrldq_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pslldq_XMM1_000h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_pslldq_XMM1_005h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_pslldq_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpslldq_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpslldq_XMM1_XMM2_005h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_vpslldq_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpslldq_YMM1_YMM2_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpslldq_YMM1_YMM2_005h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_vpslldq_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_psrldq_XMM1_000h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_psrldq_XMM1_005h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_psrldq_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpsrldq_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpsrldq_XMM1_XMM2_005h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_vpsrldq_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpsrldq_YMM1_YMM2_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpsrldq_YMM1_YMM2_005h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_vpsrldq_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pslldq_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_pslldq_XMM1_005h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_pslldq_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpslldq_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpslldq_XMM1_XMM2_005h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_vpslldq_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpslldq_YMM1_YMM2_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpslldq_YMM1_YMM2_005h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_vpslldq_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_psrldq_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_psrldq_XMM1_005h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_psrldq_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpsrldq_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpsrldq_XMM1_XMM2_005h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_vpsrldq_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpsrldq_YMM1_YMM2_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpsrldq_YMM1_YMM2_005h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_vpsrldq_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_pslldq_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_pslldq_XMM8_005h_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_pslldq_XMM8_012h_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpslldq_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 8, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpslldq_XMM8_XMM9_005h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 8, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_vpslldq_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 8, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpslldq_YMM8_YMM9_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpslldq_YMM8_YMM9_005h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesL05), s_aValuesL05 }, { bs3CpuInstr3_vpslldq_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_psrldq_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_psrldq_XMM8_005h_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_psrldq_XMM8_012h_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpsrldq_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 8, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpsrldq_XMM8_XMM9_005h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 8, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_vpsrldq_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 8, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, { bs3CpuInstr3_vpsrldq_YMM8_YMM9_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesX00), s_aValuesX00 }, { bs3CpuInstr3_vpsrldq_YMM8_YMM9_005h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesR05), s_aValuesR05 }, { bs3CpuInstr3_vpsrldq_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesX12), s_aValuesX12 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * VPERM2I128/VPERM2F128 - Permute Packed Integer/Fp Values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vperm2i128_vperm2f128(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = { { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x9192939495969798, 0x8182838485868788, 0x9192939495969798, 0x8182838485868788) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues01[] = { { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x9192939495969798, 0x8182838485868788, 0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues02[] = { { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x9192939495969798, 0x8182838485868788, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues03[] = { { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x9192939495969798, 0x8182838485868788, 0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues08[] = { { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x9192939495969798, 0x8182838485868788, 0x0000000000000000, 0x0000000000000000) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues10[] = { { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues20[] = { { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8, 0x9192939495969798, 0x8182838485868788) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues30[] = { { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0x9192939495969798, 0x8182838485868788) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues80[] = { { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0x8182838485868788) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_001h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_002h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_002h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_003h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_003h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_008h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_008h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_010h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_010h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_020h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_020h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_030h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_030h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_080h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_080h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_001h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_001h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_002h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_002h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_003h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_003h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_008h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_008h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_010h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_010h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_020h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_020h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_030h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_030h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_080h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_080h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues80), s_aValues80 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_001h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_002h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_002h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_003h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_003h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_008h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_008h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_010h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_010h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_020h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_020h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_030h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_030h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_080h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_080h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_001h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_001h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_002h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_002h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_003h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_003h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_008h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_008h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_010h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_010h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_020h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_020h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_030h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_030h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_080h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_080h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues80), s_aValues80 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_001h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_YMM10_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_FSxBX_001h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_002h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_002h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_YMM10_002h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_FSxBX_002h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_003h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_YMM10_003h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_008h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_008h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_YMM10_008h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_FSxBX_008h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_010h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_010h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_YMM10_010h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_FSxBX_010h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_020h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_020h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_YMM10_020h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_FSxBX_020h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_030h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_030h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_YMM10_030h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_FSxBX_030h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_YMM3_080h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2i128_YMM1_YMM2_FSxBX_080h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_YMM10_080h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2i128_YMM8_YMM9_FSxBX_080h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_001h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_YMM10_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_FSxBX_001h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_002h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_002h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_YMM10_002h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_FSxBX_002h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_003h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_YMM10_003h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_008h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_008h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_YMM10_008h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_FSxBX_008h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues08), s_aValues08 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_010h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_010h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_YMM10_010h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_FSxBX_010h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues10), s_aValues10 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_020h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_020h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_YMM10_020h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_FSxBX_020h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues20), s_aValues20 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_030h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_030h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_YMM10_030h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_FSxBX_030h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues30), s_aValues30 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_YMM3_080h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2f128_YMM1_YMM2_FSxBX_080h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_YMM10_080h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues80), s_aValues80 }, { bs3CpuInstr3_vperm2f128_YMM8_YMM9_FSxBX_080h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues80), s_aValues80 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig6, RT_ELEMENTS(g_aXcptConfig6)); } /* * VPERMILPS - Permute In-Lane of Quadruples of Single Precision Floating-Point Values * - ('Single Precision Floating-Point Values' AKA 'uninterpreted strings of 32-bits') */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vpermilps(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xa5a6a7a8a5a6a7a8, 0xa5a6a7a8a5a6a7a8, 0x8586878885868788, 0x8586878885868788) }, /* lo => all 4 slots */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues1B[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000001, 0x0000000200000003, 0x0000000000000001, 0x0000000200000003), /*src1*/ RTUINT256_INIT_C(0xa5a6a7a8a1a2a3a4, 0xb5b6b7b8b1b2b3b4, 0x8586878881828384, 0x9596979891929394), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, /* reverse 4 slots */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesE4[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000300000002, 0x0000000100000000, 0x0000000300000002, 0x0000000100000000), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, /* straight copy */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues3D[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000003, 0x0000000300000001, 0x0000000000000003, 0x0000000300000001), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xa5a6a7a8b1b2b3b4, 0xb1b2b3b4a1a2a3a4, 0x8586878891929394, 0x9192939481828384) }, /* 'weird' order w/dup */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesAll[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xa5a6a7a8a5a6a7a8, 0xa5a6a7a8a5a6a7a8, 0x8586878885868788, 0x8586878885868788) }, /* all 4 of the */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000001, 0x0000000200000003, 0x0000000000000001, 0x0000000200000003), /*src1*/ RTUINT256_INIT_C(0xa5a6a7a8a1a2a3a4, 0xb5b6b7b8b1b2b3b4, 0x8586878881828384, 0x9596979891929394), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, /* above for testing */ { /*src2*/ RTUINT256_INIT_C(0x0000000300000002, 0x0000000100000000, 0x0000000300000002, 0x0000000100000000), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, /* non-imm8 opcodes, */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000003, 0x0000000300000001, 0x0000000000000003, 0x0000000300000001), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xa5a6a7a8b1b2b3b4, 0xb1b2b3b4a1a2a3a4, 0x8586878891929394, 0x9192939481828384) }, { /*src2*/ RTUINT256_INIT_C(0x0000000200000003, 0x0000000100000002, 0x0000000000000003, 0x0000000300000001), /* plus: permute lo & */ /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* hi 128 bits of ymm */ /* => */ RTUINT256_INIT_C(0xb5b6b7b8b1b2b3b4, 0xa1a2a3a4b5b6b7b8, 0x8586878891929394, 0x9192939481828384) }, /* reg differently. */ }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_vpermilps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_0E4h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_03Dh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_0E4h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_03Dh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_000h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_0E4h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_03Dh_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_0E4h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_03Dh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_vpermilps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_0E4h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_03Dh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_0E4h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_03Dh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_000h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_0E4h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_03Dh_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_0E4h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_03Dh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_vpermilps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_0E4h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_XMM1_XMM2_03Dh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_0E4h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_XMM1_FSxBX_03Dh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_000h_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_0E4h_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_YMM1_YMM2_03Dh_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_0E4h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_YMM1_FSxBX_03Dh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_XMM8_XMM9_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_XMM8_XMM9_0E4h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_XMM8_XMM9_03Dh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_XMM8_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_XMM8_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 255, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_XMM8_FSxBX_0E4h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 255, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_XMM8_FSxBX_03Dh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 255, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilps_YMM8_YMM9_000h_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_YMM8_YMM9_01Bh_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_YMM8_YMM9_0E4h_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_YMM8_YMM9_03Dh_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, { bs3CpuInstr3_vpermilps_YMM8_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilps_YMM8_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 255, 0, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpermilps_YMM8_FSxBX_0E4h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 255, 0, RT_ELEMENTS(s_aValuesE4), s_aValuesE4 }, { bs3CpuInstr3_vpermilps_YMM8_FSxBX_03Dh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 255, 0, RT_ELEMENTS(s_aValues3D), s_aValues3D }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig6, RT_ELEMENTS(g_aXcptConfig6)); } /* * VPERMILPD - Permute In-Lane of Pairs of Double Precision Floating-Point Values * - ('Double Precision Floating-Point Values' AKA 'uninterpreted strings of 64-bits') */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vpermilpd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xa1a2a3a4a5a6a7a8, 0xa1a2a3a4a5a6a7a8, 0x8182838485868788, 0x8182838485868788) }, /* lo => both slots */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesE7[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001), /* hi bits ignored; */ /*src1*/ RTUINT256_INIT_C(0xa5a6a7a8a1a2a3a4, 0xb5b6b7b8b1b2b3b4, 0x8586878881828384, 0x9596979891929394), /* lo bits 0111b == */ /* => */ RTUINT256_INIT_C(0xb5b6b7b8b1b2b3b4, 0xa5a6a7a8a1a2a3a4, 0x8586878881828384, 0x8586878881828384) }, /* Z.Y.X.W => Y.Z.X.X */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues91[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000001), /* hi bits ignored; */ /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* lo bits 0001b == */ /* => */ RTUINT256_INIT_C(0xa1a2a3a4a5a6a7a8, 0xa1a2a3a4a5a6a7a8, 0x8182838485868788, 0x9192939495969798) }, /* Z.Y.X.W => Y.Y.W.X */ }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesAll[] = { { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xa1a2a3a4a5a6a7a8, 0xa1a2a3a4a5a6a7a8, 0x8182838485868788, 0x8182838485868788) }, /* all 3 of the */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000002, 0x0000000000000002, 0x0000000000000002), /*src1*/ RTUINT256_INIT_C(0xa5a6a7a8a1a2a3a4, 0xb5b6b7b8b1b2b3b4, 0x8586878881828384, 0x9596979891929394), /* => */ RTUINT256_INIT_C(0xb5b6b7b8b1b2b3b4, 0xa5a6a7a8a1a2a3a4, 0x8586878881828384, 0x8586878881828384) }, /* above for testing */ { /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000002), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xa1a2a3a4a5a6a7a8, 0xa1a2a3a4a5a6a7a8, 0x8182838485868788, 0x9192939495969798) }, /* non-imm8 opcodes */ }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_vpermilpd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_0E7h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_091h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_XMM1_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_XMM1_FSxBX_0E7h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_XMM1_FSxBX_091h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_000h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_0E7h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_091h_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_YMM1_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_YMM1_FSxBX_0E7h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_YMM1_FSxBX_091h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_vpermilpd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_0E7h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_091h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_XMM1_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_XMM1_FSxBX_0E7h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_XMM1_FSxBX_091h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_000h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_0E7h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_091h_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_YMM1_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_YMM1_FSxBX_0E7h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_YMM1_FSxBX_091h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_vpermilpd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_0E7h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_XMM1_XMM2_091h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_XMM1_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_XMM1_FSxBX_0E7h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_XMM1_FSxBX_091h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_000h_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_0E7h_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_YMM1_YMM2_091h_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_YMM1_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_YMM1_FSxBX_0E7h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_YMM1_FSxBX_091h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_XMM8_XMM9_0E7h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_XMM8_XMM9_091h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_XMM8_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_XMM8_FSxBX_0E7h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 255, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_XMM8_FSxBX_091h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 255, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValuesAll), s_aValuesAll }, { bs3CpuInstr3_vpermilpd_YMM8_YMM9_000h_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_YMM8_YMM9_0E7h_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_YMM8_YMM9_091h_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, { bs3CpuInstr3_vpermilpd_YMM8_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 255, 0, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vpermilpd_YMM8_FSxBX_0E7h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 255, 0, RT_ELEMENTS(s_aValuesE7), s_aValuesE7 }, { bs3CpuInstr3_vpermilpd_YMM8_FSxBX_091h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 255, 0, RT_ELEMENTS(s_aValues91), s_aValues91 }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig6, RT_ELEMENTS(g_aXcptConfig6)); } /* * MASKMOVQ, [V]MASKMOVDQU - move selected bytes */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_maskmovq_v_maskmovdqu(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0x0000000000000000, 0x0000000000000000), /* mask */ /*src1*/ RTUINT256_INIT_C(0, 0, 0x9192939495969798, 0xfedcba9876543210), /* src */ /* => */ RTUINT256_INIT_C(0, 0, 0xcccccccccccccccc, 0xcccccccccccccccc) }, /* dest */ { /*src2*/ RTUINT256_INIT_C(0, 0, 0x89abcdeffedcba98, 0xffeeddccbbaa9988), /*src1*/ RTUINT256_INIT_C(0, 0, 0x9192939495969798, 0xfedcba9876543210), /* => */ RTUINT256_INIT_C(0, 0, 0x9192939495969798, 0xfedcba9876543210) }, { /*src2*/ RTUINT256_INIT_C(0, 0, 0x10204080c0e0f0ff, 0x8000800080008000), /*src1*/ RTUINT256_INIT_C(0, 0, 0x9192939495969798, 0xfedcba9876543210), /* => */ RTUINT256_INIT_C(0, 0, 0xcccccc9495969798, 0xfeccbacc76cc32cc) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_maskmovq_MM0_MM1_icebp_c16, 255, RM_MEM_DI, T_MMX_SSE, 255, 0, 1, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_maskmovdqu_XMM0_XMM1_icebp_c16, 255, RM_MEM_DI, T_SSE2, 255, 0, 1, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmaskmovdqu_XMM0_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM_DI, T_AVX_128, 255, 0, 1, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_maskmovq_MM0_MM1_icebp_c32, 255, RM_MEM_DI, T_MMX_SSE, 255, 0, 1, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_maskmovdqu_XMM0_XMM1_icebp_c32, 255, RM_MEM_DI, T_SSE2, 255, 0, 1, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmaskmovdqu_XMM0_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM_DI, T_AVX_128, 255, 0, 1, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_maskmovq_MM0_MM1_icebp_c64, 255, RM_MEM_DI, T_MMX_SSE, 255, 0, 1, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_maskmovdqu_XMM0_XMM1_icebp_c64, 255, RM_MEM_DI, T_SSE2, 255, 0, 1, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmaskmovdqu_XMM0_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM_DI, T_AVX_128, 255, 0, 1, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_maskmovdqu_XMM8_XMM9_icebp_c64, 255, RM_MEM_DI, T_SSE2, 255, 8, 9, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmaskmovdqu_XMM8_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM_DI, T_AVX_128, 255, 8, 9, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * Test type #2 - GPR <- MM/XMM/YMM, no VVVV. */ typedef struct BS3CPUINSTR3_TEST2_VALUES_T { RTUINT256U uMedia; uint64_t uGpr; } BS3CPUINSTR3_TEST2_VALUES_T; typedef struct BS3CPUINSTR3_TEST2_T { FPFNBS3FAR pfnWorker; uint8_t bAvxMisalignXcpt; uint8_t enmRm; uint8_t enmType; uint8_t cbGpr; uint8_t cBitsGprValMask; bool fInvalidEncoding; uint8_t fGprDst; uint8_t iGprReg; uint8_t iMediaReg; uint8_t cValues; BS3CPUINSTR3_TEST2_VALUES_T const BS3_FAR *paValues; } BS3CPUINSTR3_TEST2_T; typedef struct BS3CPUINSTR3_TEST2_MODE_T { BS3CPUINSTR3_TEST2_T const BS3_FAR *paTests; unsigned cTests; } BS3CPUINSTR3_TEST2_MODE_T; /** Initializer for a BS3CPUINSTR3_TEST2_MODE_T array (three entries). */ #define BS3CPUINSTR3_TEST2_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } /** * Test type #2 worker. */ static uint8_t bs3CpuInstr3_WorkerTestType2(uint8_t bMode, BS3CPUINSTR3_TEST2_T const BS3_FAR *paTests, unsigned cTests, PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) { BS3REGCTX Ctx; BS3TRAPFRAME TrapFrame; const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); uint8_t BS3_FAR *pbBuf = g_pbBuf; uint32_t cbBuf = g_cbBuf; uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; PBS3EXTCTX pExtCtxOut; PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); if (!pExtCtx) return 0; /* Ensure the structures are allocated before we sample the stack pointer. */ Bs3MemSet(&Ctx, 0, sizeof(Ctx)); Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); /* * Create test context. */ pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); /* * Run the tests in all rings since alignment issues may behave * differently in ring-3 compared to ring-0. */ for (;;) { unsigned fPf = 0; do { unsigned iCfg; for (iCfg = 0; iCfg < cConfigs; iCfg++) { unsigned iTest; BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) continue; /* unsupported config */ /* * Iterate the tests. */ for (iTest = 0; iTest < cTests; iTest++) { BS3CPUINSTR3_TEST2_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; unsigned const cValues = paTests[iTest].cValues; bool const fGprDst = paTests[iTest].fGprDst == true; bool const fMmBoth = paTests[iTest].fGprDst == 2; bool const fMmxInstr = paTests[iTest].enmType < T_SSE; bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm); uint8_t const cbAlign = RT_MIN(cbOperand, 16); PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf); PRTUINT256U puMemOpAlias = (PRTUINT256U)&g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf]; uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] || paTests[iTest].fInvalidEncoding ? X86_XCPT_UD : fMmxInstr ? paConfigs[iCfg].bXcptMmx : fSseInstr ? paConfigs[iCfg].bXcptSse : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; uint64_t const fGprValMask = paTests[iTest].cBitsGprValMask == 64 ? UINT64_MAX : RT_BIT_64(paTests[iTest].cBitsGprValMask) - 1; uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; unsigned cRecompRuns = 0; unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues; unsigned iVal; /* If testing unaligned memory accesses (or #PFs), skip register-only tests. This allows setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ if ((paTests[iTest].enmRm == RM_REG || paTests[iTest].enmRm == RM_MEM8) && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf)) continue; /* #AC is only raised in ring-3.: */ if (bXcptExpect == X86_XCPT_AC) { if (bRing != 3) bXcptExpect = X86_XCPT_DB; else if (fAvxInstr) bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ } if (fPf && bXcptExpect == X86_XCPT_DB) bXcptExpect = X86_XCPT_PF; Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); /* * Iterate the test values and do the actual testing. */ while (cRecompRuns < cMaxRecompRuns) for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++) { uint16_t cErrors; uint16_t uSavedFtw = 0xff; RTUINT256U uMemOpExpect; if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0)) continue; /* * Set up the context and some expectations. */ if (fMmBoth) { if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iGprReg, paValues[iVal].uMedia.QWords.qw0, BS3EXTCTXTOPMM_ZERO); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iGprReg, &paValues[iVal].uMedia.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iGprReg, &paValues[iVal].uMedia, 32); } else if (fGprDst) { /* dest - gpr/mem */ if (paTests[iTest].iGprReg == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); Bs3MemSet(puMemOpAlias, 0xcc, cbMemOp); if (bXcptExpect != X86_XCPT_DB) Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); else { Bs3MemSet(&uMemOpExpect, 0xaa, sizeof(uMemOpExpect)); switch (paTests[iTest].cbGpr) { case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break; case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break; case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break; case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break; default: BS3_ASSERT(0); } } } else Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, UINT64_C(0xcccccccccccccccc), BS3_MODE_IS_64BIT_CODE(bMode) ? 8 : 4); /* we only restore 63:32 when bMode==LM64 */ /* source - media/mem */ if (paTests[iTest].iMediaReg == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); BS3_ASSERT(paTests[iTest].iGprReg != UINT8_MAX); Bs3MemCpy(puMemOpAlias, &paValues[iVal].uMedia, cbMemOp); uMemOpExpect = paValues[iVal].uMedia; } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaReg, paValues[iVal].uMedia.QWords.qw0, BS3EXTCTXTOPMM_ZERO); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia, 32); } else { /* dest - media */ if (paTests[iTest].iMediaReg == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); Bs3MemSet(puMemOpAlias, 0xcc, cbMemOp); if (bXcptExpect == X86_XCPT_DB) uMemOpExpect = paValues[iVal].uMedia; else Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); } /* source - gpr/mem */ if (paTests[iTest].iGprReg == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); if (bXcptExpect == X86_XCPT_DB) switch (paTests[iTest].cbGpr) { case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break; case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break; case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break; case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break; default: BS3_ASSERT(0); } Bs3MemCpy(puMemOpAlias, &uMemOpExpect, cbMemOp); } else Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask, paTests[iTest].cbGpr); } /* Memory pointer. */ if (paTests[iTest].enmRm >= RM_MEM) { BS3_ASSERT(paTests[iTest].iGprReg == UINT8_MAX || paTests[iTest].iMediaReg == UINT8_MAX); Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); } /* * Execute. */ g_uBs3TrapEipHint = Ctx.rip.u32 + (bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0); Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); /* * Check the result: */ cErrors = Bs3TestSubErrorCount(); if (fMmxInstr && bXcptExpect == X86_XCPT_DB) { uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); } if (fMmBoth && bXcptExpect == X86_XCPT_DB) { RTUINT256U uDstVal = RTUINT256_INIT_C(0, 0, 0, 0); uDstVal.au64[0] = paValues[iVal].uGpr; if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaReg, paValues[iVal].uGpr, BS3EXTCTXTOPMM_SET); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaReg, &uDstVal.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaReg, &uDstVal, 32); } else if (!fGprDst && bXcptExpect == X86_XCPT_DB && paTests[iTest].iMediaReg != UINT8_MAX) { if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaReg, paValues[iVal].uMedia.QWords.qw0, BS3EXTCTXTOPMM_SET); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia, 32); } Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); if (TrapFrame.bXcpt != bXcptExpect) Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); if (fGprDst && bXcptExpect == X86_XCPT_DB && paTests[iTest].iGprReg != UINT8_MAX) Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask, paTests[iTest].cbGpr >= 4 ? 8 : paTests[iTest].cbGpr); /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) { if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; } if (bXcptExpect == X86_XCPT_PF) Ctx.cr2.u = (uintptr_t)puMemOp; Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, pszMode, idTestStep); Ctx.cr2.u = 0; if ( paTests[iTest].enmRm >= RM_MEM && Bs3MemCmp(puMemOpAlias, &uMemOpExpect, cbMemOp) != 0) Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOpAlias); if (cErrors != Bs3TestSubErrorCount()) { if (paConfigs[iCfg].fAligned) Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", bRing, iCfg, iTest, iVal, bXcptExpect); else Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); Bs3TestPrintf("\n"); } if (uSavedFtw != 0xff) Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); } } bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); } } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode)); /* * Next ring. */ bRing++; if (bRing > 3 || bMode == BS3_MODE_RM) break; Bs3RegCtxConvertToRingX(&Ctx, bRing); } /* * Cleanup. */ bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); return 0; } /* * PMOVMSKB, VPMOVMSKB. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmovmskb(uint8_t bMode) { static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffff) }, { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x00000000) }, { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x03000003) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x255193ab) }, }; static BS3CPUINSTR3_TEST2_T const s_aTests16[] = { { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 4, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 4, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST2_T const s_aTests32[] = { { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 4, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 4, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST2_T const s_aTests64[] = { { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 8, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 8, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 8, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 8, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 8, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpmovmskb_RAX_YMM9_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, true, 0, 9, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]MOVD / [V]MOVQ - Move doubleword / Move quadword. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movd_movq(uint8_t bMode) { static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesRm[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffffffffffff) }, { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) }, { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080808080808080) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x5555666677778888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesMediaD[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) }, { RTUINT256_INIT_C(0, 0, 0, 0x00000000ffffffff), UINT64_C(0xffffffffffffffff) }, { RTUINT256_INIT_C(0, 0, 0, 0x000000007f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) }, { RTUINT256_INIT_C(0, 0, 0, 0x0000000080808080), UINT64_C(0x8080808080808080) }, { RTUINT256_INIT_C(0, 0, 0, 0x0000000077778888), UINT64_C(0x5555666677778888) }, { RTUINT256_INIT_C(0, 0, 0, 0x00000000930996bb), UINT64_C(0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesMediaQ[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) }, { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff), UINT64_C(0xffffffffffffffff) }, { RTUINT256_INIT_C(0, 0, 0, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) }, { RTUINT256_INIT_C(0, 0, 0, 0x8080808080808080), UINT64_C(0x8080808080808080) }, { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888), UINT64_C(0x5555666677778888) }, { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb), UINT64_C(0x9c5ce073930996bb) }, }; /* Note! Seems the 256-bit variants doesn't generate \#ACs on a 10980XE. WEIRD! */ /* Note: 'VEX.W!' entries: 'vmovq' in non-long modes ignores VEX.W1, acts as VEX.W0 'vmovd' */ /* Note: 'MMx2' entries: test type #2 worker now supports Media, Media operands (fGprDst == 2) */ static BS3CPUINSTR3_TEST2_T const s_aTests16[] = { { bs3CpuInstr3_movd_MM1_EDX_icebp_c16, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c16, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_EAX_MM1_icebp_c16, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c16, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_XMM1_EAX_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c16, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_EAX_XMM1_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c16, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c16, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c16, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 8, 64, false, 2, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, /* MMx2 */ { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c16, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c16, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 8, 64, false, 2, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, /* MMx2 */ { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_06e_vmovq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, /* VEX.W! */ { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_07e_vmovq_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, /* VEX.W! */ { bs3CpuInstr3_vmovq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 8, 64, false, 2, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, /* MMx2 */ }; static BS3CPUINSTR3_TEST2_T const s_aTests32[] = { { bs3CpuInstr3_movd_MM1_EDX_icebp_c32, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c32, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_EAX_MM1_icebp_c32, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c32, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_XMM1_EAX_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c32, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_EAX_XMM1_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c32, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c32, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c32, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 8, 64, false, 2, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, /* MMx2 */ { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c32, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c32, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 8, 64, false, 2, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, /* MMx2 */ { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_06e_vmovq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, /* VEX.W! */ { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_07e_vmovq_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, /* VEX.W! */ { bs3CpuInstr3_vmovq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 8, 64, false, 2, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, /* MMx2 */ }; static BS3CPUINSTR3_TEST2_T const s_aTests64[] = { { bs3CpuInstr3_movd_MM1_EDX_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_MM1_R9D_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, false, 9, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c64, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_EAX_MM1_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_R10D_MM0_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, true, 10, 0, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c64, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_XMM1_EAX_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_XMM9_R8D_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_XMM9_FSxBX_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_movd_EAX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_R8D_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movd_FSxBX_XMM9_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_vmovd_XMM9_R9D_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, false, 9, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_vmovd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_vmovd_R8D_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_vmovd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_MM1_R9_icebp_c64, 255, RM_REG, T_MMX, 8, 64, false, false, 9, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_06e_movq_MM1_FSxBX_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_movq_R9_MM1_icebp_c64, 255, RM_REG, T_MMX, 8, 64, false, true, 9, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_07e_movq_FSxBX_MM1_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 8, 64, false, 2, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, /* MMx2 */ { bs3CpuInstr3_movq_XMM9_R8_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_06e_movq_XMM1_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_movq_XMM9_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_06e_movq_XMM9_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_movq_R8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_07e_movq_FSxBX_XMM1_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_FSxBX_XMM9_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_07e_movq_FSxBX_XMM9_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_movq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, 2, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, /* MMx2 */ { bs3CpuInstr3_vmovq_XMM9_R8_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_06e_vmovq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_vmovq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_06e_vmovq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, { bs3CpuInstr3_vmovq_R8_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_07e_vmovq_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_vmovq_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_07e_vmovq_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, { bs3CpuInstr3_vmovq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, 2, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, /* MMx2 */ }; static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * [V]PEXTRB / [V]PEXTRW / [V]PEXTRD / [V]PEXTRQ. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pextrb_pextrw_pextrd_pextrq(uint8_t bMode) { static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues00_b[] = { { RTUINT256_INIT_C(0, 0, 0, 0x1234), /*->*/ UINT64_C(0x34) }, { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xff) }, { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f) }, { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x80) }, { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x88) }, { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xbb) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesFF_b[] = { { RTUINT256_INIT_C(0, 0, 0x1234000000000000, 0), UINT64_C(0x12) }, { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xff) }, { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f) }, { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x80) }, { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x11) }, { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xb4) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues00_w[] = { { RTUINT256_INIT_C(0, 0, 0, 0x1234), /*->*/ UINT64_C(0x1234) }, { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffff) }, { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f) }, { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080) }, { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x8888) }, { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x96bb) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesFF_w[] = { { RTUINT256_INIT_C(0, 0, 0x1234000000000000, 0), UINT64_C(0x1234) }, { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffff) }, { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f) }, { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080) }, { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x1111) }, { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xb421) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesFF_w_64[] = { { RTUINT256_INIT_C(0, 0, 0, 0x1234000000000000), UINT64_C(0x1234) }, { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffff) }, { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f) }, { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080) }, { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x5555) }, { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x9c5c) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues00_d[] = { { RTUINT256_INIT_C(0, 0, 0, 0x1234), /*->*/ UINT64_C(0x00001234) }, { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffff) }, { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f) }, { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x80808080) }, { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x77778888) }, { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x930996bb) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesFF_d[] = { { RTUINT256_INIT_C(0, 0, 0x1234000000000000, 0), UINT64_C(0x12340000) }, { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffff) }, { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f) }, { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x80808080) }, { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x11112222) }, { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xb4212fa8) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues00_q[] = { { RTUINT256_INIT_C(0, 0, 0, 0x1234), /*->*/ UINT64_C(0x0000000000001234) }, { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffffffffffff) }, { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) }, { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080808080808080) }, { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x5555666677778888) }, { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesFF_q[] = { { RTUINT256_INIT_C(0, 0, 0x1234000000000000, 0), UINT64_C(0x1234000000000000) }, { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffffffffffff) }, { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) }, { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080808080808080) }, { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x1111222233334444) }, { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xb4212fa8564c9ba2) }, }; static BS3CPUINSTR3_TEST2_T const s_aTests16[] = { { bs3CpuInstr3_pextrb_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pextrb_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pextrb_FSxBX_XMM1_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM8, T_SSE4_1, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pextrb_FSxBX_XMM1_000h_icebp_c16, X86_XCPT_DB, RM_MEM8, T_SSE4_1, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpextrb_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpextrb_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpextrb_FSxBX_XMM1_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM8, T_AVX_128, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpextrb_FSxBX_XMM1_000h_icebp_c16, X86_XCPT_DB, RM_MEM8, T_AVX_128, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpextrb_w1b_edx_xmm1_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpextrb_l1_edx_xmm1_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, true, true, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c16, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_alt_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_FSxBX_XMM1_000h_icebp_c16, 255, RM_MEM16, T_SSE4_1, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_alt_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_FSxBX_XMM1_000h_icebp_c16, X86_XCPT_AC, RM_MEM16, T_AVX_128, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_EDX_MM1_0FFh_icebp_c16, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, { bs3CpuInstr3_pextrw_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_alt_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_FSxBX_XMM1_0FFh_icebp_c16, 255, RM_MEM16, T_SSE4_1, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_alt_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_FSxBX_XMM1_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM16, T_AVX_128, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrd_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pextrd_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pextrd_FSxBX_XMM1_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pextrd_FSxBX_XMM1_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpextrd_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpextrd_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpextrd_FSxBX_XMM1_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpextrd_FSxBX_XMM1_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, }; static BS3CPUINSTR3_TEST2_T const s_aTests32[] = { { bs3CpuInstr3_pextrb_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pextrb_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pextrb_FSxBX_XMM1_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM8, T_SSE4_1, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pextrb_FSxBX_XMM1_000h_icebp_c32, X86_XCPT_DB, RM_MEM8, T_SSE4_1, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpextrb_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpextrb_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpextrb_FSxBX_XMM1_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM8, T_AVX_128, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpextrb_FSxBX_XMM1_000h_icebp_c32, X86_XCPT_DB, RM_MEM8, T_AVX_128, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpextrb_w1b_edx_xmm1_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpextrb_l1_edx_xmm1_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, true, true, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c32, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_alt_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_FSxBX_XMM1_000h_icebp_c32, 255, RM_MEM16, T_SSE4_1, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_alt_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_FSxBX_XMM1_000h_icebp_c32, X86_XCPT_AC, RM_MEM16, T_AVX_128, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_EDX_MM1_0FFh_icebp_c32, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, { bs3CpuInstr3_pextrw_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_alt_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_FSxBX_XMM1_0FFh_icebp_c32, 255, RM_MEM16, T_SSE4_1, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_alt_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_FSxBX_XMM1_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM16, T_AVX_128, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrd_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pextrd_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pextrd_FSxBX_XMM1_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pextrd_FSxBX_XMM1_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpextrd_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpextrd_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpextrd_FSxBX_XMM1_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpextrd_FSxBX_XMM1_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, }; static BS3CPUINSTR3_TEST2_T const s_aTests64[] = { { bs3CpuInstr3_pextrb_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pextrb_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pextrb_FSxBX_XMM1_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM8, T_SSE4_1, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pextrb_FSxBX_XMM1_000h_icebp_c64, X86_XCPT_DB, RM_MEM8, T_SSE4_1, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pextrb_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pextrb_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pextrb_FSxBX_XMM8_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM8, T_SSE4_1, 1, 8, false, true, 255, 8, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pextrb_FSxBX_XMM8_000h_icebp_c64, X86_XCPT_DB, RM_MEM8, T_SSE4_1, 1, 8, false, true, 255, 8, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpextrb_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpextrb_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpextrb_FSxBX_XMM1_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM8, T_AVX_128, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpextrb_FSxBX_XMM1_000h_icebp_c64, X86_XCPT_DB, RM_MEM8, T_AVX_128, 1, 8, false, true, 255, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpextrb_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpextrb_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpextrb_FSxBX_XMM8_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM8, T_AVX_128, 1, 8, false, true, 255, 8, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpextrb_FSxBX_XMM8_000h_icebp_c64, X86_XCPT_DB, RM_MEM8, T_AVX_128, 1, 8, false, true, 255, 8, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpextrb_w1b_edx_xmm1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 10, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, /* manually setting VEX.B=1 */ { bs3CpuInstr3_vpextrb_l1_edx_xmm1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, true, true, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_alt_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_FSxBX_XMM1_000h_icebp_c64, 255, RM_MEM16, T_SSE4_1, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_alt_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_FSxBX_XMM1_000h_icebp_c64, X86_XCPT_AC, RM_MEM16, T_AVX_128, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_EDX_MM1_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, { bs3CpuInstr3_pextrw_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_alt_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_FSxBX_XMM1_0FFh_icebp_c64, 255, RM_MEM16, T_SSE4_1, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_alt_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_FSxBX_XMM1_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM16, T_AVX_128, 2, 16, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_R9D_MM1_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 9, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_alt_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_FSxBX_XMM8_000h_icebp_c64, 255, RM_MEM16, T_SSE4_1, 2, 16, false, true, 255, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_FSxBX_XMM8_000h_icebp_c64, X86_XCPT_AC, RM_MEM16, T_AVX_128, 2, 16, false, true, 255, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_R9D_MM1_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 9, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, { bs3CpuInstr3_pextrw_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_alt_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_FSxBX_XMM8_0FFh_icebp_c64, 255, RM_MEM16, T_SSE4_1, 2, 16, false, true, 255, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_FSxBX_XMM8_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM16, T_AVX_128, 2, 16, false, true, 255, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_R9_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, true, 9, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_alt_RDX_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_alt_R9_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, false, true, 9, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpextrw_RDX_XMM1_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pextrw_R9_XMM8_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_alt_RDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrw_alt_R9_XMM8_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpextrw_RDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pextrd_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pextrd_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pextrd_FSxBX_XMM1_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pextrd_FSxBX_XMM1_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pextrd_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pextrd_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pextrd_FSxBX_XMM8_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pextrd_FSxBX_XMM8_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpextrd_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpextrd_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpextrd_FSxBX_XMM1_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpextrd_FSxBX_XMM1_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpextrd_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpextrd_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpextrd_FSxBX_XMM8_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpextrd_FSxBX_XMM8_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pextrq_RDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_pextrq_RDX_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_pextrq_R9_XMM8_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_pextrq_R9_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, false, true, 9, 8, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_pextrq_FSxBX_XMM8_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE4_1, 8, 64, false, true, 255, 8, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_pextrq_FSxBX_XMM8_000h_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE4_1, 8, 64, false, true, 255, 8, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_vpextrq_RDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_vpextrq_RDX_XMM1_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_vpextrq_R9_XMM8_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_vpextrq_R9_XMM8_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 9, 8, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_vpextrq_FSxBX_XMM8_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 8, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_vpextrq_FSxBX_XMM8_000h_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 8, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, }; static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * [V]MOVMSKPS / [V]MOVMSKPD. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movmskps_movmskpd(uint8_t bMode) { static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR32_128[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0x0) }, { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xf) }, { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x0) }, { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xf) }, { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x0) }, { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xb) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR32_256[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0x00) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xff) }, { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x00) }, { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff0000, 0x1111222233334444, 0x5555666677778888), UINT64_C(0xf0) }, { RTUINT256_INIT_C(0x9c5ce073930996bb, 0xb4212fa8564c9ba2, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xeb) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR64_128[] = { { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x0) }, { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0x3) }, { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x0) }, { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x3) }, { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x0) }, { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x3) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR64_256[] = { { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xf) }, { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x0) }, { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xf) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff0000, 0x1111222233334444, 0x5555666677778888), UINT64_C(0xc) }, { RTUINT256_INIT_C(0x9c5ce073930996bb, 0xb4212fa8564c9ba2, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xf) }, }; static BS3CPUINSTR3_TEST2_T const s_aTests16[] = { { bs3CpuInstr3_movmskps_EDX_XMM1_icebp_c16, 255, RM_REG, T_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, { bs3CpuInstr3_vmovmskps_EDX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, { bs3CpuInstr3_vmovmskps_EDX_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, { bs3CpuInstr3_movmskpd_EDX_XMM1_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, { bs3CpuInstr3_vmovmskpd_EDX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, { bs3CpuInstr3_vmovmskpd_EDX_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, }; static BS3CPUINSTR3_TEST2_T const s_aTests32[] = { { bs3CpuInstr3_movmskps_EDX_XMM1_icebp_c32, 255, RM_REG, T_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, { bs3CpuInstr3_vmovmskps_EDX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, { bs3CpuInstr3_vmovmskps_EDX_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, { bs3CpuInstr3_movmskpd_EDX_XMM1_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, { bs3CpuInstr3_vmovmskpd_EDX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, { bs3CpuInstr3_vmovmskpd_EDX_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, }; static BS3CPUINSTR3_TEST2_T const s_aTests64[] = { { bs3CpuInstr3_movmskps_EDX_XMM1_icebp_c64, 255, RM_REG, T_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, { bs3CpuInstr3_movmskps_R9D_XMM8_icebp_c64, 255, RM_REG, T_SSE, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, { bs3CpuInstr3_movmskps_RDX_XMM1_icebp_c64, 255, RM_REG, T_SSE, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, { bs3CpuInstr3_vmovmskps_EDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, { bs3CpuInstr3_vmovmskps_RDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, { bs3CpuInstr3_vmovmskps_R9D_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, { bs3CpuInstr3_vmovmskps_EDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, { bs3CpuInstr3_vmovmskps_RDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, { bs3CpuInstr3_vmovmskps_R9D_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, { bs3CpuInstr3_movmskpd_EDX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, { bs3CpuInstr3_movmskpd_R9D_XMM8_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, { bs3CpuInstr3_movmskpd_RDX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, { bs3CpuInstr3_vmovmskpd_EDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, { bs3CpuInstr3_vmovmskpd_RDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, { bs3CpuInstr3_vmovmskpd_R9D_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, { bs3CpuInstr3_vmovmskpd_EDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, { bs3CpuInstr3_vmovmskpd_RDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, { bs3CpuInstr3_vmovmskpd_R9D_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, }; static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * [V]EXTRACTPS. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_extractps(uint8_t bMode) { static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues00[] = { { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), UINT64_C(0xbad7ab1e) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), UINT64_C(0xdecea5ed) }, { RTUINT256_INIT_C(0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff, 0x00000000a7a5a7a5), UINT64_C(0xa7a5a7a5) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues01[] = { { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), UINT64_C(0x5e1ec7ed) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), UINT64_C(0xdeadface) }, { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xffffffff00000000, 0xf0f1f2f3a7a5a7a5), UINT64_C(0xf0f1f2f3) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues02[] = { { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), UINT64_C(0xda7aba5e) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), UINT64_C(0xc01dce11) }, { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x00000000ffffffff, 0x0000000000000000), UINT64_C(0xffffffff) }, }; static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues03[] = { { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), UINT64_C(0xacce55ed) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), UINT64_C(0xa110ca7e) }, { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xffffffff00000000, 0x0000000000000000), UINT64_C(0xffffffff) }, }; static BS3CPUINSTR3_TEST2_T const s_aTests16[] = { { bs3CpuInstr3_extractps_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_extractps_EDX_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_extractps_EDX_XMM1_002h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_EDX_XMM1_003h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_EDX_XMM1_032h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_000h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_001h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_002h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_003h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_032h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_0FFh_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractps_EDX_XMM1_001h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vextractps_EDX_XMM1_002h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_EDX_XMM1_003h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_EDX_XMM1_032h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_001h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_002h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_003h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_032h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, }; static BS3CPUINSTR3_TEST2_T const s_aTests32[] = { { bs3CpuInstr3_extractps_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_extractps_EDX_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_extractps_EDX_XMM1_002h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_EDX_XMM1_003h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_EDX_XMM1_032h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_000h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_001h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_002h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_003h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_032h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_0FFh_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractps_EDX_XMM1_001h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vextractps_EDX_XMM1_002h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_EDX_XMM1_003h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_EDX_XMM1_032h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_001h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_002h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_003h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_032h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, }; static BS3CPUINSTR3_TEST2_T const s_aTests64[] = { { bs3CpuInstr3_extractps_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_extractps_EDX_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_extractps_EDX_XMM1_002h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_EDX_XMM1_003h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_EDX_XMM1_032h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_001h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_002h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_003h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_032h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_FSxBX_XMM1_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractps_EDX_XMM1_001h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vextractps_EDX_XMM1_002h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_EDX_XMM1_003h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_EDX_XMM1_032h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_001h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_002h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_003h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_032h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_FSxBX_XMM1_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_extractps_R9D_XMM8_001h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_extractps_R9D_XMM8_002h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_R9D_XMM8_003h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_R9D_XMM8_032h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_FSxBX_XMM8_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_extractps_FSxBX_XMM8_001h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_extractps_FSxBX_XMM8_002h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_FSxBX_XMM8_003h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_extractps_FSxBX_XMM8_032h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_extractps_FSxBX_XMM8_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractps_R9D_XMM8_001h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vextractps_R9D_XMM8_002h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_R9D_XMM8_003h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_R9D_XMM8_032h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_FSxBX_XMM8_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractps_FSxBX_XMM8_001h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues01), s_aValues01 }, { bs3CpuInstr3_vextractps_FSxBX_XMM8_002h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_FSxBX_XMM8_003h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, { bs3CpuInstr3_vextractps_FSxBX_XMM8_032h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, { bs3CpuInstr3_vextractps_FSxBX_XMM8_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, }; static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * Test type #3 - two MM/XMM/YMM operands, no flags. */ typedef struct BS3CPUINSTR3_TEST3_VALUES_T { RTUINT256U uSrc; RTUINT256U uDstOut; } BS3CPUINSTR3_TEST3_VALUES_T; typedef struct BS3CPUINSTR3_TEST3_T { FPFNBS3FAR pfnWorker; uint8_t bAvxMisalignXcpt; uint8_t enmRm; uint8_t enmType; uint8_t iRegDst; uint8_t iRegSrc; uint8_t cValues; BS3CPUINSTR3_TEST3_VALUES_T const BS3_FAR *paValues; } BS3CPUINSTR3_TEST3_T; typedef struct BS3CPUINSTR3_TEST3_MODE_T { BS3CPUINSTR3_TEST3_T const BS3_FAR *paTests; unsigned cTests; } BS3CPUINSTR3_TEST3_MODE_T; /** Initializer for a BS3CPUINSTR3_TEST3_MODE_T array (three entries). */ #define BS3CPUINSTR3_TEST3_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } /** * Test type #1 worker. */ static uint8_t bs3CpuInstr3_WorkerTestType3(uint8_t bMode, BS3CPUINSTR3_TEST3_T const BS3_FAR *paTests, unsigned cTests, PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs, uint8_t cbMaxAlign) { BS3REGCTX Ctx; BS3TRAPFRAME TrapFrame; const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); uint8_t BS3_FAR *pbBuf = g_pbBuf; uint32_t cbBuf = g_cbBuf; uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; PBS3EXTCTX pExtCtxOut; PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); if (!pExtCtx) return 0; /* Ensure the structures are allocated before we sample the stack pointer. */ Bs3MemSet(&Ctx, 0, sizeof(Ctx)); Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); /* * Create test context. */ Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); /* * Run the tests in all rings since alignment issues may behave * differently in ring-3 compared to ring-0. */ for (;;) { unsigned fPf = 0; do { unsigned iCfg; for (iCfg = 0; iCfg < cConfigs; iCfg++) { unsigned iTest; BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) continue; /* unsupported config */ /* * Iterate the tests. */ for (iTest = 0; iTest < cTests; iTest++) { BS3CPUINSTR3_TEST3_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; unsigned const cValues = paTests[iTest].cValues; bool const fMmxInstr = paTests[iTest].enmType < T_SSE; bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; uint8_t const cbMemOp = cbOperand; uint8_t const cbAlign = RT_MIN(cbOperand, !cbMaxAlign ? 16 : cbMaxAlign); PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf); PRTUINT256U puMemOpAlias = (PRTUINT256U)&g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf]; uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD : fMmxInstr ? paConfigs[iCfg].bXcptMmx : fSseInstr ? paConfigs[iCfg].bXcptSse : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; unsigned cRecompRuns = 0; unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues; unsigned iVal; /* If testing unaligned memory accesses (or #PF), skip register-only tests. This allows setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ if ((paTests[iTest].enmRm == RM_REG || paTests[iTest].enmRm == RM_MEM8) && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf)) continue; /* #AC is only raised in ring-3.: */ if (bXcptExpect == X86_XCPT_AC) { if (bRing != 3) bXcptExpect = X86_XCPT_DB; else if (fAvxInstr) bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ } if (fPf && bXcptExpect == X86_XCPT_DB) bXcptExpect = X86_XCPT_PF; Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); /* * Iterate the test values and do the actual testing. */ while (cRecompRuns < cMaxRecompRuns) for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++) { uint16_t cErrors; uint16_t uSavedFtw = 0xff; RTUINT256U uMemOpExpect; if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0)) continue; /* * Set up the context and some expectations. */ /* dest */ if (paTests[iTest].iRegDst == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); Bs3MemSet(puMemOpAlias, 0xcc, cbMemOp); if (bXcptExpect == X86_XCPT_DB) uMemOpExpect = paValues[iVal].uDstOut; else Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO); /* source */ if (paTests[iTest].iRegSrc == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX); Bs3MemCpy(puMemOpAlias, &paValues[iVal].uSrc, cbMemOp); uMemOpExpect = paValues[iVal].uSrc; } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, paValues[iVal].uSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc, 32); /* Memory pointer. */ if (paTests[iTest].enmRm >= RM_MEM) { BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX || paTests[iTest].iRegSrc == UINT8_MAX); Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); } /* * Execute. */ g_uBs3TrapEipHint = Ctx.rip.u32 + (bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0); Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); /* * Check the result: */ cErrors = Bs3TestSubErrorCount(); if (bXcptExpect == X86_XCPT_DB && fMmxInstr) { uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); } if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX) { if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand); } Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); if (TrapFrame.bXcpt != bXcptExpect) Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) { if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; } if (bXcptExpect == X86_XCPT_PF) Ctx.cr2.u = (uintptr_t)puMemOp; Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, pszMode, idTestStep); Ctx.cr2.u = 0; if ( paTests[iTest].enmRm >= RM_MEM && Bs3MemCmp(puMemOpAlias, &uMemOpExpect, cbMemOp) != 0) Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOpAlias); if (cErrors != Bs3TestSubErrorCount()) { if (paConfigs[iCfg].fAligned) Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", bRing, iCfg, iTest, iVal, bXcptExpect); else Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); Bs3TestPrintf("\n"); } if (uSavedFtw != 0xff) Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); } } bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); } } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode)); /* * Next ring. */ bRing++; if (bRing > 3 || bMode == BS3_MODE_RM) break; Bs3RegCtxConvertToRingX(&Ctx, bRing); } /* * Cleanup. */ bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); return 0; } /* * PSHUFW */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_pshufw(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0, 0, 0, 0x5555555555555555) }, { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0, 0, 0, 0x9c5c9c5c9c5c9c5c) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0, 0, 0, 0x8888777766665555) }, { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0, 0, 0, 0x96bb9309e0739c5c) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); } /* * [V]PSHUFHW */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshufhw(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x5555555555555555, 0x1111222233334444, 0x1111111111111111, 0x5555666677778888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x4d094d094d094d09, 0x3ef417c8666b3fe6, 0xb421b421b421b421, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x8888777766665555, 0x1111222233334444, 0x4444333322221111, 0x5555666677778888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x73d56cdcf02a4d09, 0x3ef417c8666b3fe6, 0x9ba2564c2fa8b421, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufhw_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufhw_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); } /* * [V]PSHUFLW */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshuflw(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x5555666677778888, 0x1111111111111111, 0x1111222233334444, 0x5555555555555555) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef43ef43ef43ef4, 0xb4212fa8564c9ba2, 0x9c5c9c5c9c5c9c5c) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x5555666677778888, 0x4444333322221111, 0x1111222233334444, 0x8888777766665555) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3fe6666b17c83ef4, 0xb4212fa8564c9ba2, 0x96bb9309e0739c5c) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshuflw_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshuflw_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); } /* * [V]PSHUFD */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshufd(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x5555666655556666, 0x5555666655556666, 0x1111222211112222, 0x1111222211112222) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x4d09f02a4d09f02a, 0x4d09f02a4d09f02a, 0xb4212fa8b4212fa8, 0xb4212fa8b4212fa8) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x3333444411112222, 0x7777888855556666, 0x7777888855556666, 0x3333444411112222) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x666b3fe63ef417c8, 0x6cdc73d54d09f02a, 0x930996bb9c5ce073, 0x564c9ba2b4212fa8) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, { bs3CpuInstr3_vpshufd_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vpshufd_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); } /** * Values shared by the move functions (same input as output). */ static BS3CPUINSTR3_TEST3_VALUES_T const g_aMoveValues3[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, }; /* * MOVNTDQA - load double qword, strictly aligned, with non-temporal hint. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movntdqa(uint8_t bMode) { static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movntdqa_XMM10_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE4_1, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdqa_XMM11_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdqa_YMM12_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/); } /* * MOVNTDQ - store double qword, strictly aligned, with non-temporal hint. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movntdq(uint8_t bMode) { static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_movntdq_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdq_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdq_FSxBX_YMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_movntdq_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdq_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdq_FSxBX_YMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_movntdq_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movntdq_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdq_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdq_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdq_FSxBX_YMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntdq_FSxBX_YMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/); } /* * [V]MOVNPS / [V]MOVNTPD - load single/double precision floating-point, aligned, * with non-temporal hint. Only difference is the unit. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movntps_movntpd(uint8_t bMode) { static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_movntps_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntps_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntps_FSxBX_YMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movntpd_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntpd_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntpd_FSxBX_YMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_movntps_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntps_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntps_FSxBX_YMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movntpd_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntpd_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntpd_FSxBX_YMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_movntps_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movntps_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntps_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntps_FSxBX_XMM11_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntps_FSxBX_YMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntps_FSxBX_YMM12_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movntpd_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movntpd_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntpd_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntpd_FSxBX_XMM11_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntpd_FSxBX_YMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovntpd_FSxBX_YMM12_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/); } /* * MOVUPS - packed single-precision floating point, unaligned. * * Note! We only cover one of the two register<->register variants here * thanks to the assembler (probably the one with the smaller opcode). */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movups(uint8_t bMode) { static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movups_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movups_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movups_FSxBX_XMM10_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovups_FSxBX_YMM12_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/); } /* * MOVUPD - packed double-precision floating point, unaligned. * * Note! We only cover one of the two register<->register variants here * thanks to the assembler (probably the one with the smaller opcode). */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movupd(uint8_t bMode) { static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movupd_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movupd_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movupd_FSxBX_XMM10_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovupd_FSxBX_YMM12_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/); } /* * [V]MOVSLDUP - Duplicate even single precision floating-point values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movsldup(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0xbbbbccccbbbbcccc, 0xffff2121ffff2121, 0x3333444433334444, 0x7777888877778888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x6cdc73d56cdc73d5, 0x666b3fe6666b3fe6, 0x564c9ba2564c9ba2, 0x930996bb930996bb) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movsldup_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE3, 8, 12, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movsldup_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovsldup_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); } /* * [V]MOVSHDUP - Duplicate even single precision floating-point values. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movshdup(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x9999aaaa9999aaaa, 0xddddeeeeddddeeee, 0x1111222211112222, 0x5555666655556666) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x4d09f02a4d09f02a, 0x3ef417c83ef417c8, 0xb4212fa8b4212fa8, 0x9c5ce0739c5ce073) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_movshdup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movshdup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_movshdup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movshdup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_movshdup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movshdup_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE3, 8, 12, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movshdup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movshdup_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovshdup_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); } /* * [V]MOVDDUP - Duplicate even single precision floating-point values. * * Similar to MOVSLDUP, but different exception class and unit size. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movddup(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0xddddeeeeffff2121, 0xddddeeeeffff2121, 0x5555666677778888, 0x5555666677778888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0x3ef417c8666b3fe6, 0x9c5ce073930996bb, 0x9c5ce073930996bb) }, }; /* Note! Seems the 256-bit variants doesn't generate \#ACs on a 10980XE. WEIRD! */ static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movddup_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE3, 8, 12, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_movddup_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_XMM11_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vmovddup_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5), 0 /*cbMaxAlign*/); } /* * [V]MOVAPS / [V]MOVAPD */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movaps_movapd(uint8_t bMode) { /* Note! Seems the 256-bit variants doesn't generate \#ACs on a 10980XE. WEIRD! */ static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_movaps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movaps_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movapd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movapd_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_YMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_YMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_movaps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movaps_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movapd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movapd_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_YMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_YMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_movaps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movaps_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movaps_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movaps_XMM10_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movapd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movapd_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movapd_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movapd_XMM10_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_XMM11_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_XMM11_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_YMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovaps_YMM12_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_YMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovapd_YMM12_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/); } /* * [V]MOVDQU - move unaligned packed qwords. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movdqu(uint8_t bMode) { static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_movdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_movdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqu_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqu_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqu_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_FSxBX_YMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_movdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_movdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqu_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqu_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqu_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_FSxBX_YMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_movdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_movdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqu_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_movdqu_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqu_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqu_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqu_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqu_FSxBX_XMM10_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqu_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_FSxBX_YMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqu_FSxBX_YMM12_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/); } /* * [V]MOVDQA - move aligned packed qwords. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movdqa(uint8_t bMode) { static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_movdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_movdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqa_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqa_FSxBX_XMM1_icebp_c16, 255, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqa_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_FSxBX_YMM1_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_movdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_movdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqa_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqa_FSxBX_XMM1_icebp_c32, 255, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqa_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_FSxBX_YMM1_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_movdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_movdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqa_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_movdqa_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqa_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqa_XMM10_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqa_FSxBX_XMM1_icebp_c64, 255, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_movdqa_FSxBX_XMM10_icebp_c64, 255, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_XMM8_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 8, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqa_XMM8_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 8, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_XMM11_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqa_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_07f_vmovdqa_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_YMM12_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_FSxBX_YMM1_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vmovdqa_FSxBX_YMM12_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/); } /* * [V]PABSB / [V]PABSW / [V]PABSD */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pabsb_pabsw_pabsd(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesB[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0x0101010101010101, 0x0101010101010101, 0x0101010101010101, 0x0101010101010101) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x6767565645453434, 0x2323121201012121, 0x1111222233334444, 0x5555666677777878) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x4d09102a6c24732b, 0x3e0c1738666b3f1a, 0x4c212f58564c655e, 0x645c20736d096a45) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesW[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0x0001000100010001, 0x0001000100010001, 0x0001000100010001, 0x0001000100010001) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x6667555644453334, 0x2223111200012121, 0x1111222233334444, 0x5555666677777778) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x4d090fd66cdc73d5, 0x3ef417c8666b3fe6, 0x4bdf2fa8564c645e, 0x63a41f8d6cf76945) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesD[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0x0000000100000001, 0x0000000100000001, 0x0000000100000001, 0x0000000100000001) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x6666555644443334, 0x222211120000dedf, 0x1111222233334444, 0x5555666677778888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0x4bded058564c9ba2, 0x63a31f8d6cf66945) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_pabsb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_pabsb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_pabsb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsb_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSSE3, 9, 8, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsb_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_vpabsb_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, { bs3CpuInstr3_pabsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSSE3, 9, 8, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsw_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_vpabsw_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, { bs3CpuInstr3_pabsd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pabsd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSSE3, 9, 8, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_pabsd_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesD), s_aValuesD }, { bs3CpuInstr3_vpabsd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); } /* * [V]PMOVSXBW / [V]PMOVSXBD / [V]PMOVSXBQ / [V]PMOVSXWD / [V]PMOVSXWQ / [V]PMOVSXDQ */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmovsxbw_pmovsxbd_pmovsxbq_pmovsxwd_pmovsxwq_pmovsxdq(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBW[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0011001100220022, 0x0033003300440044, 0x0055005500660066, 0x00770077ff88ff88) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0xffb40021002fffa8, 0x0056004cff9bffa2, 0xff9c005cffe00073, 0xff930009ff96ffbb) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBD[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0000005500000055, 0x0000006600000066, 0x0000007700000077, 0xffffff88ffffff88) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0xffffff9c0000005c, 0xffffffe000000073, 0xffffff9300000009, 0xffffff96ffffffbb) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBQ[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0000000000000077, 0x0000000000000077, 0xffffffffffffff88, 0xffffffffffffff88) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0xffffffffffffff93, 0x0000000000000009, 0xffffffffffffff96, 0xffffffffffffffbb) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesWD[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0000111100002222, 0x0000333300004444, 0x0000555500006666, 0x00007777ffff8888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0xffffb42100002fa8, 0x0000564cffff9ba2, 0xffff9c5cffffe073, 0xffff9309ffff96bb) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesWQ[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0000000000005555, 0x0000000000006666, 0x0000000000007777, 0xffffffffffff8888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0xffffffffffff9c5c, 0xffffffffffffe073, 0xffffffffffff9309, 0xffffffffffff96bb) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesDQ[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0000000011112222, 0x0000000033334444, 0x0000000055556666, 0x0000000077778888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0xffffffffb4212fa8, 0x00000000564c9ba2, 0xffffffff9c5ce073, 0xffffffff930996bb) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_pmovsxbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovsxbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovsxbd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovsxbd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovsxbq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovsxbq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovsxwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovsxwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovsxwq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovsxwq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovsxdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_pmovsxdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_pmovsxbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovsxbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovsxbd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovsxbd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovsxbq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovsxbq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovsxwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovsxwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovsxwq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovsxwq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovsxdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_pmovsxdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_pmovsxbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovsxbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovsxbw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovsxbw_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovsxbw_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovsxbd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovsxbd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovsxbd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovsxbd_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovsxbd_YMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovsxbq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovsxbq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovsxbq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovsxbq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovsxbq_YMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovsxwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovsxwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovsxwd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovsxwd_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovsxwd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovsxwq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovsxwq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovsxwq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovsxwq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovsxwq_YMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovsxdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_pmovsxdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_pmovsxdq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_pmovsxdq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovsxdq_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5), X86_EFL_STATUS_BITS); } /* * [V]PMOVZXBW / [V]PMOVZXBD / [V]PMOVZXBQ / [V]PMOVZXWD / [V]PMOVZXWQ / [V]PMOVZXDQ */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmovzxbw_pmovzxbd_pmovzxbq_pmovzxwd_pmovzxwq_pmovzxdq(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBW[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0x00ff00ff00ff00ff, 0x00ff00ff00ff00ff, 0x00ff00ff00ff00ff, 0x00ff00ff00ff00ff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0011001100220022, 0x0033003300440044, 0x0055005500660066, 0x0077007700880088) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x00b40021002f00a8, 0x0056004c009b00a2, 0x009c005c00e00073, 0x00930009009600bb) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBD[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0x000000ff000000ff, 0x000000ff000000ff, 0x000000ff000000ff, 0x000000ff000000ff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0000005500000055, 0x0000006600000066, 0x0000007700000077, 0x0000008800000088) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x0000009c0000005c, 0x000000e000000073, 0x0000009300000009, 0x00000096000000bb) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBQ[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0x00000000000000ff, 0x00000000000000ff, 0x00000000000000ff, 0x00000000000000ff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0000000000000077, 0x0000000000000077, 0x0000000000000088, 0x0000000000000088) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x0000000000000093, 0x0000000000000009, 0x0000000000000096, 0x00000000000000bb) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesWD[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0x0000ffff0000ffff, 0x0000ffff0000ffff, 0x0000ffff0000ffff, 0x0000ffff0000ffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0000111100002222, 0x0000333300004444, 0x0000555500006666, 0x0000777700008888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x0000b42100002fa8, 0x0000564c00009ba2, 0x00009c5c0000e073, 0x00009309000096bb) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesWQ[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0x000000000000ffff, 0x000000000000ffff, 0x000000000000ffff, 0x000000000000ffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0000000000005555, 0x0000000000006666, 0x0000000000007777, 0x0000000000008888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x0000000000009c5c, 0x000000000000e073, 0x0000000000009309, 0x00000000000096bb) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesDQ[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0x00000000ffffffff, 0x00000000ffffffff, 0x00000000ffffffff, 0x00000000ffffffff) }, { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(0x0000000011112222, 0x0000000033334444, 0x0000000055556666, 0x0000000077778888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(0x00000000b4212fa8, 0x00000000564c9ba2, 0x000000009c5ce073, 0x00000000930996bb) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_pmovzxbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovzxbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovzxbd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovzxbd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovzxbq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovzxbq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovzxwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovzxwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovzxwq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovzxwq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovzxdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_pmovzxdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_pmovzxbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovzxbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovzxbd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovzxbd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovzxbq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovzxbq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovzxwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovzxwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovzxwq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovzxwq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovzxdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_pmovzxdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_pmovzxbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovzxbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovzxbw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovzxbw_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_vpmovzxbw_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, { bs3CpuInstr3_pmovzxbd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovzxbd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovzxbd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovzxbd_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_vpmovzxbd_YMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, { bs3CpuInstr3_pmovzxbq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovzxbq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovzxbq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovzxbq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_vpmovzxbq_YMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, { bs3CpuInstr3_pmovzxwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovzxwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovzxwd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovzxwd_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_vpmovzxwd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, { bs3CpuInstr3_pmovzxwq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovzxwq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovzxwq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovzxwq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_vpmovzxwq_YMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, { bs3CpuInstr3_pmovzxdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_pmovzxdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_pmovzxdq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_pmovzxdq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, { bs3CpuInstr3_vpmovzxdq_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5), X86_EFL_STATUS_BITS); } /* * [V]LDDQU - Load unaligned integer from memory. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_lddqu(uint8_t bMode) { static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_lddqu_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vlddqu_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vlddqu_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_lddqu_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vlddqu_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vlddqu_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_lddqu_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_lddqu_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vlddqu_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vlddqu_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vlddqu_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, { bs3CpuInstr3_vlddqu_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/); } /* * [V]PHMINPOSUW */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phminposuw(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(1, 2, 0x0000000000000000, 0x000000000000ffff) }, /* No 256-bit variant */ { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C(5, 6, 0x0000000000000000, 0x0000000000071111) }, /* No 256-bit variant */ { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C(9, 10, 0x0000000000000000, 0x0000000000062fa8) }, /* No 256-bit variant */ }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_phminposuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_phminposuw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vphminposuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vphminposuw_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_phminposuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_phminposuw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vphminposuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vphminposuw_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_phminposuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_phminposuw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_phminposuw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_phminposuw_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vphminposuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vphminposuw_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vphminposuw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vphminposuw_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); } /* * VBROADCASTSS/VBROADCASTSD */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vbroadcastss_vbroadcastsd_vbroadcastf128(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues32[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x8888888877777777, 0x6666666655555555, 0x4444444433333333, 0x2222222211111111), /* => */ RTUINT256_INIT_C(0x1111111111111111, 0x1111111111111111, 0x1111111111111111, 0x1111111111111111) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues64[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x4444444444444444, 0x3333333333333333, 0x2222222222222222, 0x1111111111111111), /* => */ RTUINT256_INIT_C(0x1111111111111111, 0x1111111111111111, 0x1111111111111111, 0x1111111111111111) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues128[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x4444444444444444, 0x3333333333333333, 0x2222222222222222, 0x1111111111111111), /* => */ RTUINT256_INIT_C(0x2222222222222222, 0x1111111111111111, 0x2222222222222222, 0x1111111111111111) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_vbroadcastss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastsd_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vbroadcastsd_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vbroadcastf128_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues128), s_aValues128 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_vbroadcastss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastsd_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vbroadcastsd_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vbroadcastf128_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues128), s_aValues128 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_vbroadcastss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX2_128, 9, 8, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 8, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastss_YMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vbroadcastsd_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vbroadcastsd_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vbroadcastsd_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 8, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vbroadcastsd_YMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vbroadcastf128_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues128), s_aValues128 }, { bs3CpuInstr3_vbroadcastf128_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues128), s_aValues128 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); } /* * VPBROADCASTB/VPBROADCASTW/VPBROADCASTD/VPBROADCASTQ/VPBROADCASTI128 */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vpbroadcastb_vpbroadcastw_vpbroadcastd_vpbroadcastq_vbroadcasti128(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues8[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x99aabbccddeeff00, 0x8877665544332200, 0x00ffeeddccbbaa99, 0x8877665544332211), /* => */ RTUINT256_INIT_C(0x1111111111111111, 0x1111111111111111, 0x1111111111111111, 0x1111111111111111) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues16[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x0000ffffeeeedddd, 0xccccbbbbaaaa9999, 0x8888777766665555, 0x4444333322221111), /* => */ RTUINT256_INIT_C(0x1111111111111111, 0x1111111111111111, 0x1111111111111111, 0x1111111111111111) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues32[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x8888888877777777, 0x6666666655555555, 0x4444444433333333, 0x2222222211111111), /* => */ RTUINT256_INIT_C(0x1111111111111111, 0x1111111111111111, 0x1111111111111111, 0x1111111111111111) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues64[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x4444444444444444, 0x3333333333333333, 0x2222222222222222, 0x1111111111111111), /* => */ RTUINT256_INIT_C(0x1111111111111111, 0x1111111111111111, 0x1111111111111111, 0x1111111111111111) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues128[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0x4444444444444444, 0x3333333333333333, 0x2222222222222222, 0x1111111111111111), /* => */ RTUINT256_INIT_C(0x2222222222222222, 0x1111111111111111, 0x2222222222222222, 0x1111111111111111) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_vpbroadcastb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vbroadcasti128_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues128), s_aValues128 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_vpbroadcastb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vbroadcasti128_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues128), s_aValues128 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_vpbroadcastb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX2_128, 9, 8, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_128, 9, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 8, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastb_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 9, 255, RT_ELEMENTS(s_aValues8), s_aValues8 }, { bs3CpuInstr3_vpbroadcastw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX2_128, 9, 8, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_128, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 8, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastw_YMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_256, 9, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, { bs3CpuInstr3_vpbroadcastd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX2_128, 9, 8, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_128, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 8, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastd_YMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_256, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, { bs3CpuInstr3_vpbroadcastq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_128, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX2_128, 9, 8, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_128, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 8, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vpbroadcastq_YMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX2_256, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, { bs3CpuInstr3_vbroadcasti128_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues128), s_aValues128 }, { bs3CpuInstr3_vbroadcasti128_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 9, 255, RT_ELEMENTS(s_aValues128), s_aValues128 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); } /* * VEXTRACTI128/VEXTRACTF128 */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vextracti128_vextractf128(uint8_t bMode) { static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C( 0, 1, 0x5555666677778888, 0x1111222233334444) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C( 2, 3, 0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6) }, }; static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues00[] = { { RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /* => */ RTUINT256_INIT_C( 4, 5, 0x1111222233334444, 0x5555666677778888) }, { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /* => */ RTUINT256_INIT_C( 6, 7, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, }; static BS3CPUINSTR3_TEST3_T const s_aTests16[] = { { bs3CpuInstr3_vextracti128_XMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextracti128_FSxBX_YMM2_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextracti128_XMM1_YMM2_000h_icebp_c16, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextracti128_FSxBX_YMM2_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractf128_XMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextractf128_FSxBX_YMM2_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextractf128_XMM1_YMM2_000h_icebp_c16, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractf128_FSxBX_YMM2_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests32[] = { { bs3CpuInstr3_vextracti128_XMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextracti128_FSxBX_YMM2_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextracti128_XMM1_YMM2_000h_icebp_c32, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextracti128_FSxBX_YMM2_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractf128_XMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextractf128_FSxBX_YMM2_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextractf128_XMM1_YMM2_000h_icebp_c32, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractf128_FSxBX_YMM2_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST3_T const s_aTests64[] = { { bs3CpuInstr3_vextracti128_XMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextracti128_FSxBX_YMM2_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextracti128_XMM1_YMM2_000h_icebp_c64, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextracti128_FSxBX_YMM2_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextracti128_XMM8_YMM9_0FFh_icebp_c64, 255, RM_REG, T_AVX2_128, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextracti128_FSxBX_YMM9_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextracti128_XMM8_YMM9_000h_icebp_c64, 255, RM_REG, T_AVX2_128, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextracti128_FSxBX_YMM9_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractf128_XMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextractf128_FSxBX_YMM2_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextractf128_XMM1_YMM2_000h_icebp_c64, 255, RM_REG, T_AVX2_128, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractf128_FSxBX_YMM2_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractf128_XMM8_YMM9_0FFh_icebp_c64, 255, RM_REG, T_AVX2_128, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextractf128_FSxBX_YMM9_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, { bs3CpuInstr3_vextractf128_XMM8_YMM9_000h_icebp_c64, 255, RM_REG, T_AVX2_128, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, { bs3CpuInstr3_vextractf128_FSxBX_YMM9_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_128, 255, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, }; static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig6, RT_ELEMENTS(g_aXcptConfig6), 0 /*cbMaxAlign*/); } /* * Test type #4 - two source MM/XMM/YMM operands, outputs only eflags. * * Probably only used by the PTEST instruction. */ typedef struct BS3CPUINSTR3_TEST4_VALUES_T { RTUINT256U uSrc2; RTUINT256U uSrc1; uint16_t afEflOut[3]; /* [0]=MM result, [1]=XMM result, [2]=YMM result */ } BS3CPUINSTR3_TEST4_VALUES_T; typedef struct BS3CPUINSTR3_TEST4_T { FPFNBS3FAR pfnWorker; uint8_t bAvxMisalignXcpt; uint8_t enmRm; uint8_t enmType; uint8_t iRegSrc1; uint8_t iRegSrc2; uint8_t cValues; BS3CPUINSTR3_TEST4_VALUES_T const BS3_FAR *paValues; } BS3CPUINSTR3_TEST4_T; typedef struct BS3CPUINSTR3_TEST4_MODE_T { BS3CPUINSTR3_TEST4_T const BS3_FAR *paTests; unsigned cTests; } BS3CPUINSTR3_TEST4_MODE_T; /** Initializer for a BS3CPUINSTR3_TEST4_MODE_T array (three entries). */ #define BS3CPUINSTR3_TEST4_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } /** * Test type #4 worker. */ static uint8_t bs3CpuInstr3_WorkerTestType4(uint8_t bMode, BS3CPUINSTR3_TEST4_T const BS3_FAR *paTests, unsigned cTests, PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs, uint32_t fEflCheck) { BS3REGCTX Ctx; BS3TRAPFRAME TrapFrame; const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); uint8_t BS3_FAR *pbBuf = g_pbBuf; uint32_t cbBuf = g_cbBuf; uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; PBS3EXTCTX pExtCtxOut; PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); if (!pExtCtx) return 0; /* Ensure the structures are allocated before we sample the stack pointer. */ Bs3MemSet(&Ctx, 0, sizeof(Ctx)); Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); /* * Create test context. */ Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); /* * Run the tests in all rings since alignment issues may behave * differently in ring-3 compared to ring-0. */ for (;;) { unsigned fPf = 0; do { unsigned iCfg; for (iCfg = 0; iCfg < cConfigs; iCfg++) { unsigned iTest; BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) continue; /* unsupported config */ /* * Iterate the tests. */ for (iTest = 0; iTest < cTests; iTest++) { BS3CPUINSTR3_TEST4_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; unsigned const cValues = paTests[iTest].cValues; bool const fMmxInstr = paTests[iTest].enmType < T_SSE; bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; uint8_t const cbMemOp = cbOperand; uint8_t const cbAlign = RT_MIN(cbOperand, 16); PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf); PRTUINT256U puMemOpAlias = (PRTUINT256U)&g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf]; uint8_t const idxEflOut = cbOperand == 32 ? 2 : cbOperand == 16 ? 1 : 0; uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD : fMmxInstr ? paConfigs[iCfg].bXcptMmx : fSseInstr ? paConfigs[iCfg].bXcptSse : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; unsigned cRecompRuns = 0; unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues * 2; unsigned iVal; /* If testing unaligned memory accesses (or #PF), skip register-only tests. This allows setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ if ((paTests[iTest].enmRm == RM_REG || paTests[iTest].enmRm == RM_MEM8) && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf)) continue; /* #AC is only raised in ring-3.: */ if (bXcptExpect == X86_XCPT_AC) { if (bRing != 3) bXcptExpect = X86_XCPT_DB; else if (fAvxInstr) bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ } if (fPf && bXcptExpect == X86_XCPT_DB) bXcptExpect = X86_XCPT_PF; Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); /* * Iterate the test values and do the actual testing. */ while (cRecompRuns < cMaxRecompRuns) for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++) { unsigned iEflVariation; uint32_t const fSavedEfl = Ctx.rflags.u32; for (iEflVariation = 0; iEflVariation < 2; iEflVariation++) { uint16_t cErrors; uint16_t uSavedFtw = 0xff; RTUINT256U uMemOpExpect; if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, iEflVariation)) continue; /* * Set up the context and some expectations. */ /* eflags */ if (iEflVariation) Ctx.rflags.u32 = fSavedEfl | X86_EFL_STATUS_BITS; else Ctx.rflags.u32 = fSavedEfl & ~X86_EFL_STATUS_BITS; /* source1 */ if (paTests[iTest].iRegSrc1 == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); BS3_ASSERT(paTests[iTest].iRegSrc2 != UINT8_MAX); Bs3MemCpy(puMemOpAlias, &paValues[iVal].uSrc1, cbMemOp); uMemOpExpect = paValues[iVal].uSrc1; } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32); /* source2 */ if (paTests[iTest].iRegSrc2 == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); BS3_ASSERT(paTests[iTest].iRegSrc1 != UINT8_MAX); Bs3MemCpy(puMemOpAlias, &paValues[iVal].uSrc2, cbMemOp); uMemOpExpect = paValues[iVal].uSrc2; } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32); /* Memory pointer. */ if (paTests[iTest].enmRm >= RM_MEM) { BS3_ASSERT( paTests[iTest].iRegSrc1 == UINT8_MAX || paTests[iTest].iRegSrc2 == UINT8_MAX); Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); } /* * Execute. */ g_uBs3TrapEipHint = Ctx.rip.u32 + (bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0); Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); /* * Check the result: */ cErrors = Bs3TestSubErrorCount(); if (bXcptExpect == X86_XCPT_DB && fMmxInstr) { uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); } Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); if (TrapFrame.bXcpt != bXcptExpect) Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) { if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; } if (bXcptExpect == X86_XCPT_DB) Ctx.rflags.u32 = (Ctx.rflags.u32 & ~fEflCheck) | paValues[iVal].afEflOut[idxEflOut]; if (bXcptExpect == X86_XCPT_PF) Ctx.cr2.u = (uintptr_t)puMemOp; Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, pszMode, idTestStep); Ctx.cr2.u = 0; if ( paTests[iTest].enmRm >= RM_MEM && Bs3MemCmp(puMemOpAlias, &uMemOpExpect, cbMemOp) != 0) Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOpAlias); if (cErrors != Bs3TestSubErrorCount()) { if (paConfigs[iCfg].fAligned) Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u/efl#%u failed (bXcptExpect=%#x)", bRing, iCfg, iTest, iVal, iEflVariation, bXcptExpect); else Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u/efl#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", bRing, iCfg, iTest, iVal, iEflVariation, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); Bs3TestPrintf("\n"); } if (uSavedFtw != 0xff) Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); } Ctx.rflags.u32 = fSavedEfl; } } bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); } } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode)); /* * Next ring. */ bRing++; if (bRing > 3 || bMode == BS3_MODE_RM) break; Bs3RegCtxConvertToRingX(&Ctx, bRing); } /* * Cleanup. */ bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); return 0; } /* * PTEST */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_ptest(uint8_t bMode) { static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ { 0, X86_EFL_CF, X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ { 0, 0, 0 } }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ { 0, 0, 0 } }, { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ { 0, 0, 0 } }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ { 0, 0, 0 } }, }; static BS3CPUINSTR3_TEST4_T const s_aTests16[] = { { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST4_T const s_aTests32[] = { { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST4_T const s_aTests64[] = { { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_ptest_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_ptest_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); } /* * VTESTPS */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vtestps(uint8_t bMode) { static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ { 0, X86_EFL_CF, X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0, 0x7fffffff, 0, 0x7fffffff), /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*src1*/ RTUINT256_INIT_C(0x7fffffff7fffffff, 0x4000000070000000, 0, 0x7fffff070000000), /* => */ { 0, X86_EFL_ZF, X86_EFL_ZF } }, { /*src2*/ RTUINT256_INIT_C(0xfacade00ffffffff, 0xf00dcafef1234567, 0, 0), /*src1*/ RTUINT256_INIT_C(0xffffffff81234567, 0xfa7edeadfadec0de, 0, 0), /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0xf007ba11fa15efad, 0x8ffffffffe1afe15), /*src1*/ RTUINT256_INIT_C(0x70bacc00707a11ed, 0, 0x8f00eefffeedc001, 0xfeeb1e00ffffffff), /* => */ { 0, X86_EFL_CF, X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0xfa7edeadfadec0de, 0xfffffffff1234567, 0xfacade00ffffffff, 0xf00dcafef1234567), /*src1*/ RTUINT256_INIT_C(0, 0, 0xfffffffff1234567, 0xfa7edeadfadec0de), /* => */ { 0, X86_EFL_CF, 0 } }, { /*src2*/ RTUINT256_INIT_C(0xfeeb1ebe8f1edbed, 0xfeeb1ebe8f1edbed, 0, 0x80ee8eee800080ee), /*src1*/ RTUINT256_INIT_C(0, 0x8feab0108f0f0f0f, 0x80dd000081234567, 0x70bacc00707a11ed), /* => */ { 0, X86_EFL_ZF, 0 } }, { /*src2*/ RTUINT256_INIT_C(0xf01dc01dba5eba11, 0xacce55ed9defec75, 0, 0x70bacc00707a11ed), /*src1*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0x70bacc00707a11ed, 0), /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF } }, { /*src2*/ RTUINT256_INIT_C(0xcafec01dea7e5ef, 0x8f6f6ff080608fff, 0xefdb0f5fe793f600, 0x99fb1c399ff0cce), /*src1*/ RTUINT256_INIT_C(0, 0x8ff7123497dcaeb4, 0, 0xd0d0c01dea7eeedf), /* => */ { 0, 0, 0 } }, }; static BS3CPUINSTR3_TEST4_T const s_aTests16[] = { { bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST4_T const s_aTests32[] = { { bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST4_T const s_aTests64[] = { { bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestps_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); } /* * VTESTPD */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vtestpd(uint8_t bMode) { static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0x8000000000000000, 0x8fffffff00000000, 0x80000000ffffffff, 0xffffffffffffffff), /*src1*/ RTUINT256_INIT_C(0x8000000000000000, 0x80000000ffffffff, 0x80000000f000f000, 0xffffffffffffffff), /* => */ { 0, X86_EFL_CF, X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000), /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ { 0, X86_EFL_ZF, X86_EFL_ZF } }, { /*src2*/ RTUINT256_INIT_C(0xfacade007fffffff, 0xf00dcafe71234567, 0x7ab1ebadbad7ab1e, 0), /*src1*/ RTUINT256_INIT_C(0xffffffff81234567, 0xfa7edeadfadec0de, 0x7fffffffffffffff, 0x7ab1ebadbad7ab1e), /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0xf007ba11fa15efad, 0x8ffffffffe1afe15), /*src1*/ RTUINT256_INIT_C(0x70bacc00707a11ed, 0, 0x8f00eefffeedc001, 0xfeeb1e00ffffffff), /* => */ { 0, X86_EFL_CF, X86_EFL_CF } }, { /*src2*/ RTUINT256_INIT_C(0xfa7edeadfadec0de, 0xfffffffff1234567, 0xfacade00f00e0000, 0xf00dcafef1234567), /*src1*/ RTUINT256_INIT_C(0x7fffffffffffffff, 0, 0xe1234567f1234567, 0x8a7edead0adec0de), /* => */ { 0, X86_EFL_CF, 0 } }, { /*src2*/ RTUINT256_INIT_C(0xfeeb1ebe7f1edbed, 0xfeeb1ebe8f1edbed, 0x7fffffffffffffff, 0x80ee8eee800080ee), /*src1*/ RTUINT256_INIT_C(0, 0x8feab0108f0f0f0f, 0x80dd000081234567, 0x70bacc00707a11ed), /* => */ { 0, X86_EFL_ZF, 0 } }, { /*src2*/ RTUINT256_INIT_C(0xf01dc01dba5eba11, 0xacce55ed9defec75, 0x1fa7ca751abcdef0, 0x70bacc00f07a11ed), /*src1*/ RTUINT256_INIT_C(0x7000f000f000f000, 0x70bacc00707a11ed, 0x70bacc00f07a11ed, 0x7fffffff0fff0fff), /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF } }, { /*src2*/ RTUINT256_INIT_C(0xcafec01dea7e5ef, 0xdf6f6ff080608fff, 0xefdb0f5f6793f600, 0x99fb1c3300f0cced), /*src1*/ RTUINT256_INIT_C(0, 0x9ff7123477dcaeb4, 0, 0xb0d0c01d7a7eeedf), /* => */ { 0, 0, 0 } }, }; static BS3CPUINSTR3_TEST4_T const s_aTests16[] = { { bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST4_T const s_aTests32[] = { { bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST4_T const s_aTests64[] = { { bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vtestpd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); } /* * Test type #5 - three source MM/XMM/YMM operands. * * Used by [P]BLENDV, SHA256RNDS2, V[P]MASKMOV instructions. */ typedef struct BS3CPUINSTR3_TEST5_VALUES_T { RTUINT256U uSrc3; RTUINT256U uSrc2; RTUINT256U uSrc1; RTUINT256U uDstOut; uint8_t fFlags; } BS3CPUINSTR3_TEST5_VALUES_T; /** this test cannot trigger a page fault despite general behavior of the instruction */ #define BS3_TEST_F_NO_PF RT_BIT(0) typedef struct BS3CPUINSTR3_TEST5_T { FPFNBS3FAR pfnWorker; uint8_t bAvxMisalignXcpt; uint8_t enmRm; uint8_t enmType; uint8_t iRegDst; uint8_t iRegSrc1; uint8_t iRegSrc2; uint8_t iRegSrc3; uint8_t cValues; BS3CPUINSTR3_TEST5_VALUES_T const BS3_FAR *paValues; } BS3CPUINSTR3_TEST5_T; typedef struct BS3CPUINSTR3_TEST5_MODE_T { BS3CPUINSTR3_TEST5_T const BS3_FAR *paTests; unsigned cTests; } BS3CPUINSTR3_TEST5_MODE_T; /** Initializer for a BS3CPUINSTR3_TEST5_MODE_T array (three entries). */ #define BS3CPUINSTR3_TEST5_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } /** * Test type #5 worker. */ static uint8_t bs3CpuInstr3_WorkerTestType5(uint8_t bMode, BS3CPUINSTR3_TEST5_T const BS3_FAR *paTests, unsigned cTests, PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) { BS3REGCTX Ctx; BS3TRAPFRAME TrapFrame; const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; uint8_t BS3_FAR *pbBuf = g_pbBuf; uint32_t cbBuf = g_cbBuf; PBS3EXTCTX pExtCtxOut; PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); if (!pExtCtx) return 0; /* Ensure the structures are allocated before we sample the stack pointer. */ Bs3MemSet(&Ctx, 0, sizeof(Ctx)); Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); /* * Create test context. */ pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]); /* * Run the tests in all rings since alignment issues may behave * differently in ring-3 compared to ring-0. */ for (;;) { unsigned fPf = 0; do { unsigned iCfg; for (iCfg = 0; iCfg < cConfigs; iCfg++) { unsigned iTest; BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) continue; /* unsupported config */ /* * Iterate the tests. */ for (iTest = 0; iTest < cTests; iTest++) { BS3CPUINSTR3_TEST5_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; unsigned const cValues = paTests[iTest].cValues; bool const fMmxInstr = paTests[iTest].enmType < T_SSE; bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm); uint8_t const cbAlign = cbMemOp; PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf); PRTUINT256U puMemOpAlias = (PRTUINT256U)&g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf]; uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD : fMmxInstr ? paConfigs[iCfg].bXcptMmx : fSseInstr ? paConfigs[iCfg].bXcptSse : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; unsigned cRecompRuns = 0; unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues; unsigned iVal; /* If testing unaligned memory accesses (or #PF), skip register-only tests. This allows setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ if ((paTests[iTest].enmRm == RM_REG || paTests[iTest].enmRm == RM_MEM8) && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf)) continue; /* #AC is only raised in ring-3: */ if (bXcptExpect == X86_XCPT_AC) { if (bRing != 3) bXcptExpect = X86_XCPT_DB; else if (fAvxInstr) bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ } if (fPf && bXcptExpect == X86_XCPT_DB) bXcptExpect = X86_XCPT_PF; Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); /* * Iterate the test values and do the actual testing. */ while (cRecompRuns < cMaxRecompRuns) for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++) { uint16_t cErrors; uint16_t uSavedFtw = 0xff; RTUINT256U uMemOpExpect; if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0)) continue; /* Do not expect PF from instructions which are flagged as never faulting */ if (fPf && bXcptExpect == X86_XCPT_PF && paValues[iVal].fFlags & BS3_TEST_F_NO_PF) bXcptExpect = X86_XCPT_DB; /* * Set up the context and some expectations. */ /* dest */ if (paTests[iTest].iRegDst == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); Bs3MemSet(puMemOpAlias, 0xcc, cbMemOp); if (bXcptExpect == X86_XCPT_DB) uMemOpExpect = paValues[iVal].uDstOut; else Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO); /* source #1 (/ destination for MMX and SSE) */ if (paTests[iTest].iRegSrc1 == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); Bs3MemCpy(puMemOpAlias, &paValues[iVal].uSrc1, cbMemOp); if (paTests[iTest].iRegDst == UINT8_MAX) BS3_ASSERT(fSseInstr || fAvxInstr); if (bXcptExpect != X86_XCPT_DB) uMemOpExpect = paValues[iVal].uSrc1; } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32); /* source #2 */ if (paTests[iTest].iRegSrc2 == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX && paTests[iTest].iRegSrc1 != UINT8_MAX); Bs3MemCpy(puMemOpAlias, &paValues[iVal].uSrc2, cbMemOp); uMemOpExpect = paValues[iVal].uSrc2; } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32); /* source #3 */ if (paTests[iTest].iRegSrc3 == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX && paTests[iTest].iRegSrc1 != UINT8_MAX); Bs3MemCpy(puMemOpAlias, &paValues[iVal].uSrc3, cbMemOp); uMemOpExpect = paValues[iVal].uSrc3; } else if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc3, paValues[iVal].uSrc3.QWords.qw0, BS3EXTCTXTOPMM_ZERO); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc3, &paValues[iVal].uSrc3.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc3, &paValues[iVal].uSrc3, 32); /* Memory pointer. */ if (paTests[iTest].enmRm >= RM_MEM) { BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX || paTests[iTest].iRegSrc1 == UINT8_MAX || paTests[iTest].iRegSrc2 == UINT8_MAX || paTests[iTest].iRegSrc3 == UINT8_MAX); Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); } /* * Execute. */ g_uBs3TrapEipHint = Ctx.rip.u32 + (bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0); Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); /* * Check the result: */ cErrors = Bs3TestSubErrorCount(); /* Instructions which access memory haphazardly may PF haphazardly */ if (fPf && paTests[iTest].enmRm == RM_RANGE && TrapFrame.bXcpt == X86_XCPT_PF) bXcptExpect = X86_XCPT_PF; if (fMmxInstr && bXcptExpect == X86_XCPT_DB) { uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); /* Observed on 10980xe after pxor mm1, mm2. */ } if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX) { if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand); } #if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */ if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE && pExtCtx->Ctx.x.Hdr.bmXState == 0x7 && pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3) pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7; #endif Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); if (TrapFrame.bXcpt != bXcptExpect) Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) { if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; } if (bXcptExpect == X86_XCPT_PF) Ctx.cr2.u = (uintptr_t)puMemOp; Ctx.cr2Range = (paTests[iTest].enmRm == RM_MEM_DI || paTests[iTest].enmRm == RM_RANGE) ? cbMemOp - 1 : 0; Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, pszMode, idTestStep); Ctx.cr2.u = 0; Ctx.cr2Range = 0; if ( paTests[iTest].enmRm >= RM_MEM && Bs3MemCmp(puMemOpAlias, &uMemOpExpect, cbMemOp) != 0) /* Instructions which access memory haphazardly may or may not complete their work */ if (paTests[iTest].enmRm != RM_RANGE || TrapFrame.bXcpt != X86_XCPT_PF) Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOpAlias); if (cErrors != Bs3TestSubErrorCount()) { if (paConfigs[iCfg].fAligned) Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", bRing, iCfg, iTest, iVal, bXcptExpect); else Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); Bs3TestPrintf("\n"); } if (uSavedFtw != 0xff) Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); } } bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); } } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode)); /* * Next ring. */ bRing++; if (bRing > 3 || bMode == BS3_MODE_RM) break; Bs3RegCtxConvertToRingX(&Ctx, bRing); } /* * Cleanup. */ bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); return 0; } /* * PBLENDVB */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pblendvb(uint8_t bMode) { static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues[] = { { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x0000008000000000, 0x0000091000007f00, 0, 0x8080808080808080), /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3f4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x1234567890abcdef, 0xfedcba0987654321, 0xfedcba0987654321, 0x1234567890abcdef), /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0xddddeeee77778888, 0x111122aa33bbcccc, 0x111122aa33bbcccc, 0xddddeeee77778888), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST5_T const s_aTests16[] = { { bs3CpuInstr3_pblendvb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pblendvb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_XMM1_XMM2_XMM3_XMM4_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_XMM1_XMM2_FSxBX_XMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_YMM1_YMM2_YMM3_YMM4_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_YMM1_YMM2_FSxBX_YMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_T const s_aTests32[] = { { bs3CpuInstr3_pblendvb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pblendvb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_XMM1_XMM2_XMM3_XMM4_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_XMM1_XMM2_FSxBX_XMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_YMM1_YMM2_YMM3_YMM4_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_YMM1_YMM2_FSxBX_YMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_T const s_aTests64[] = { { bs3CpuInstr3_pblendvb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pblendvb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pblendvb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_pblendvb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_XMM1_XMM2_XMM3_XMM4_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_XMM1_XMM2_FSxBX_XMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_XMM8_XMM9_XMM10_XMM11_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_XMM8_XMM9_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_YMM1_YMM2_YMM3_YMM4_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_YMM1_YMM2_FSxBX_YMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_YMM8_YMM9_YMM10_YMM11_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vpblendvb_YMM8_YMM9_FSxBX_YMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * BLENDPS */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_blendvps(uint8_t bMode) { static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues[] = { { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x0000008000000000, 0x0000091000007f00, 0, 0x8080808080808080), /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x1234567890abcdef, 0xfedcba0987654321, 0xfedcba0987654321, 0x1234567890abcdef), /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0xddddeeee77778888, 0x1111222233334444, 0x1111222233334444, 0xddddeeee77778888), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST5_T const s_aTests16[] = { { bs3CpuInstr3_blendvps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_blendvps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_XMM1_XMM2_XMM3_XMM4_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_XMM1_XMM2_FSxBX_XMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_YMM1_YMM2_YMM3_YMM4_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_YMM1_YMM2_FSxBX_YMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_T const s_aTests32[] = { { bs3CpuInstr3_blendvps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_blendvps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_XMM1_XMM2_XMM3_XMM4_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_XMM1_XMM2_FSxBX_XMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_YMM1_YMM2_YMM3_YMM4_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_YMM1_YMM2_FSxBX_YMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_T const s_aTests64[] = { { bs3CpuInstr3_blendvps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_blendvps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_blendvps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_blendvps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_XMM1_XMM2_XMM3_XMM4_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_XMM1_XMM2_FSxBX_XMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_XMM8_XMM9_XMM10_XMM11_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_XMM8_XMM9_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_YMM1_YMM2_YMM3_YMM4_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_YMM1_YMM2_FSxBX_YMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_YMM8_YMM9_YMM10_YMM11_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvps_YMM8_YMM9_FSxBX_YMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * BLENDPD */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_blendvpd(uint8_t bMode) { static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues[] = { { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x0000008000000000, 0x0000091000007f00, 0, 0x8080808080808080), /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x1234567890abcdef, 0xfedcba0987654321, 0xfedcba0987654321, 0x1234567890abcdef), /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x1111222233334444, 0x1111222233334444, 0xddddeeeeffff0000), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST5_T const s_aTests16[] = { { bs3CpuInstr3_blendvpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_blendvpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_XMM1_XMM2_XMM3_XMM4_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_XMM1_XMM2_FSxBX_XMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_YMM1_YMM2_YMM3_YMM4_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_YMM1_YMM2_FSxBX_YMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_T const s_aTests32[] = { { bs3CpuInstr3_blendvpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_blendvpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_XMM1_XMM2_XMM3_XMM4_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_XMM1_XMM2_FSxBX_XMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_YMM1_YMM2_YMM3_YMM4_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_YMM1_YMM2_FSxBX_YMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_T const s_aTests64[] = { { bs3CpuInstr3_blendvpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_blendvpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_blendvpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_blendvpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_XMM1_XMM2_XMM3_XMM4_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_XMM1_XMM2_FSxBX_XMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_XMM8_XMM9_XMM10_XMM11_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_XMM8_XMM9_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_YMM1_YMM2_YMM3_YMM4_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_YMM1_YMM2_FSxBX_YMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_YMM8_YMM9_YMM10_YMM11_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_vblendvpd_YMM8_YMM9_FSxBX_YMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * SHA256RNDS2 */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_sha256rnds2(uint8_t bMode) { static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues[] = { { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(1, 2, 0, 0), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), /* => */ RTUINT256_INIT_C( 5, 6, 0xf79feefafffffffb, 0xf7bffefdfffffffd), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x0000008000000000, 0x0000091000007f00, 0, 0x8080808080808080), /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 9, 10, 0x6db0b4070638d9f7, 0x3c1e9824e85f3497), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 13, 14, 0x6db0b4070638d9f7, 0x3c1e9824e85f3497), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0x1234567890abcdef, 0xfedcba0987654321, 0xfedcba0987654321, 0x1234567890abcdef), /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), /* => */ RTUINT256_INIT_C( 17, 18, 0xef25e0d150a28cfd, 0xbd9ab3ae2970ef62), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST5_T const s_aTests16[] = { { bs3CpuInstr3_sha256rnds2_XMM1_XMM2_XMM0_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_sha256rnds2_XMM1_FSxBX_XMM0_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_T const s_aTests32[] = { { bs3CpuInstr3_sha256rnds2_XMM1_XMM2_XMM0_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_sha256rnds2_XMM1_FSxBX_XMM0_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_T const s_aTests64[] = { { bs3CpuInstr3_sha256rnds2_XMM1_XMM2_XMM0_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_sha256rnds2_XMM1_FSxBX_XMM0_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_sha256rnds2_XMM8_XMM9_XMM0_icebp_c64, 255, RM_REG, T_SHA, 8, 8, 9, 0, RT_ELEMENTS(s_aValues), s_aValues }, { bs3CpuInstr3_sha256rnds2_XMM8_FSxBX_XMM0_icebp_c64, 255, RM_MEM, T_SHA, 8, 8, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, }; static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * VMASKMOVP[SD], VPMASKMOV[DQ] - move selected dwords / qwords */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vmaskmovps_d_vpmaskmovd_q(uint8_t bMode) { static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues_LD_dw_128[] = { { // Copy all /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), // SRC (before instruction) uSrc3 (in worker) /*mask*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xfedcba9889abcdef), // MSK (before instruction) uSrc2 (in worker) /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), // INIT DST value (before) uSrc1 (in worker) /* => */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), // DST (after instruction) uDstO (in worker) /*flgs*/ 0 }, { // Copy only beginning of buffer /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9889abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000004000400), /*flgs*/ 0 }, { // Copy only end of buffer /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x9192939455969798, 0x6edcba9879abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0300030000000000, 0x0000000000000000), /*flgs*/ 0 }, { // Copy none: loads all-0s (memory not accessed) /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9879abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, }; static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues_ST_dw_128[] = { { // Copy all /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xfedcba9889abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*flgs*/ 0 }, { // Copy only beginning of buffer /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9889abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaa04000400), /*flgs*/ 0 }, { // Copy only end of buffer -- are these erroring because no copy happens on xmm? that must be it /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x9192939455969798, 0x6edcba9879abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0x03000300aaaaaaaa, 0xaaaaaaaaaaaaaaaa), /*flgs*/ 0 }, { // Copy none: stores nothing (memory not overwritten or even accessed) /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9879abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /*flgs*/ BS3_TEST_F_NO_PF }, }; static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues_LD_dw_256[] = { { // Copy all /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xfedcba9889abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*flgs*/ 0 }, { // Copy only beginning of buffer /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9889abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000004000400), /*flgs*/ 0 }, { // Copy only end of buffer /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0xb1b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9879abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0100010000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ 0 }, { // Copy none: loads all-0s (memory not accessed) /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9879abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, }; static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues_ST_dw_256[] = { { // Copy all /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xfedcba9889abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*flgs*/ 0 }, { // Copy only beginning of buffer /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9889abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaa04000400), /*flgs*/ 0 }, { // Copy only end of buffer /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0xb1b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9879abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x01000100aaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /*flgs*/ 0 }, { // Copy none: stores nothing (memory not overwritten or even accessed) /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9879abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /*flgs*/ BS3_TEST_F_NO_PF }, }; static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues_LD_qw_all[] = { { // Copy all /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xfedcba9889abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*flgs*/ 0 }, { // Copy some /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b4b5b6b7b8, 0xa1a2a3a435a6a7a8, 0x4192939495969798, 0xfedcba9889abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0200020002000200, 0x0000000000000000, 0x0400040004000400), /*flgs*/ 0 }, { // Copy none: loads all-0s (memory not accessed) /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9879abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, }; static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues_ST_qw_all[] = { { // Copy all /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xfedcba9889abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*flgs*/ 0 }, { // Copy some /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b4b5b6b7b8, 0xa1a2a3a435a6a7a8, 0x4192939495969798, 0xfedcba9889abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0x0200020002000200, 0xaaaaaaaaaaaaaaaa, 0x0400040004000400), /*flgs*/ 0 }, { // Copy none: stores nothing (memory not overwritten or even accessed) /*src */ RTUINT256_INIT_C(0x0100010001000100, 0x0200020002000200, 0x0300030003000300, 0x0400040004000400), /*mask*/ RTUINT256_INIT_C(0x01b2b3b415b6b7b8, 0x21a2a3a435a6a7a8, 0x4192939455969798, 0x6edcba9879abcdef), /*init*/ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /* => */ RTUINT256_INIT_C(0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa), /*flgs*/ BS3_TEST_F_NO_PF }, }; static BS3CPUINSTR3_TEST5_T const s_aTests16[] = { // => src1 src2 src3 // DEST INIT MASK SOURCE { bs3CpuInstr3_vmaskmovps_XMM0_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_128), s_aValues_LD_dw_128 }, { bs3CpuInstr3_vmaskmovps_YMM0_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_256), s_aValues_LD_dw_256 }, { bs3CpuInstr3_vmaskmovps_FSxBX_XMM0_XMM1_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_128), s_aValues_ST_dw_128 }, { bs3CpuInstr3_vmaskmovps_FSxBX_YMM0_YMM1_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_256), s_aValues_ST_dw_256 }, { bs3CpuInstr3_vmaskmovpd_XMM0_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vmaskmovpd_YMM0_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vmaskmovpd_FSxBX_XMM0_XMM1_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vmaskmovpd_FSxBX_YMM0_YMM1_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vpmaskmovd_XMM0_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_128), s_aValues_LD_dw_128 }, { bs3CpuInstr3_vpmaskmovd_YMM0_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_256), s_aValues_LD_dw_256 }, { bs3CpuInstr3_vpmaskmovd_FSxBX_XMM0_XMM1_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_128), s_aValues_ST_dw_128 }, { bs3CpuInstr3_vpmaskmovd_FSxBX_YMM0_YMM1_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_256), s_aValues_ST_dw_256 }, { bs3CpuInstr3_vpmaskmovq_XMM0_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vpmaskmovq_YMM0_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vpmaskmovq_FSxBX_XMM0_XMM1_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vpmaskmovq_FSxBX_YMM0_YMM1_icebp_c16, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, }; static BS3CPUINSTR3_TEST5_T const s_aTests32[] = { { bs3CpuInstr3_vmaskmovps_XMM0_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_128), s_aValues_LD_dw_128 }, { bs3CpuInstr3_vmaskmovps_YMM0_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_256), s_aValues_LD_dw_256 }, { bs3CpuInstr3_vmaskmovps_FSxBX_XMM0_XMM1_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_128), s_aValues_ST_dw_128 }, { bs3CpuInstr3_vmaskmovps_FSxBX_YMM0_YMM1_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_256), s_aValues_ST_dw_256 }, { bs3CpuInstr3_vmaskmovpd_XMM0_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vmaskmovpd_YMM0_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vmaskmovpd_FSxBX_XMM0_XMM1_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vmaskmovpd_FSxBX_YMM0_YMM1_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vpmaskmovd_XMM0_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_128), s_aValues_LD_dw_128 }, { bs3CpuInstr3_vpmaskmovd_YMM0_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_256), s_aValues_LD_dw_256 }, { bs3CpuInstr3_vpmaskmovd_FSxBX_XMM0_XMM1_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_128), s_aValues_ST_dw_128 }, { bs3CpuInstr3_vpmaskmovd_FSxBX_YMM0_YMM1_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_256), s_aValues_ST_dw_256 }, { bs3CpuInstr3_vpmaskmovq_XMM0_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vpmaskmovq_YMM0_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vpmaskmovq_FSxBX_XMM0_XMM1_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vpmaskmovq_FSxBX_YMM0_YMM1_icebp_c32, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, }; static BS3CPUINSTR3_TEST5_T const s_aTests64[] = { { bs3CpuInstr3_vmaskmovps_XMM0_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_128), s_aValues_LD_dw_128 }, { bs3CpuInstr3_vmaskmovps_YMM0_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_256), s_aValues_LD_dw_256 }, { bs3CpuInstr3_vmaskmovps_FSxBX_XMM0_XMM1_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_128), s_aValues_ST_dw_128 }, { bs3CpuInstr3_vmaskmovps_FSxBX_YMM0_YMM1_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_256), s_aValues_ST_dw_256 }, { bs3CpuInstr3_vmaskmovpd_XMM0_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vmaskmovpd_YMM0_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vmaskmovpd_FSxBX_XMM0_XMM1_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vmaskmovpd_FSxBX_YMM0_YMM1_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vpmaskmovd_XMM0_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_128), s_aValues_LD_dw_128 }, { bs3CpuInstr3_vpmaskmovd_YMM0_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_dw_256), s_aValues_LD_dw_256 }, { bs3CpuInstr3_vpmaskmovd_FSxBX_XMM0_XMM1_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_128), s_aValues_ST_dw_128 }, { bs3CpuInstr3_vpmaskmovd_FSxBX_YMM0_YMM1_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_dw_256), s_aValues_ST_dw_256 }, { bs3CpuInstr3_vpmaskmovq_XMM0_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vpmaskmovq_YMM0_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 0, 0, 1, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vpmaskmovq_FSxBX_XMM0_XMM1_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vpmaskmovq_FSxBX_YMM0_YMM1_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 255, 255, 0, 1, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vmaskmovps_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_128, 8, 8, 9, 255, RT_ELEMENTS(s_aValues_LD_dw_128), s_aValues_LD_dw_128 }, { bs3CpuInstr3_vmaskmovps_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_256, 8, 8, 9, 255, RT_ELEMENTS(s_aValues_LD_dw_256), s_aValues_LD_dw_256 }, { bs3CpuInstr3_vmaskmovps_FSxBX_XMM8_XMM9_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_128, 255, 255, 8, 9, RT_ELEMENTS(s_aValues_ST_dw_128), s_aValues_ST_dw_128 }, { bs3CpuInstr3_vmaskmovps_FSxBX_YMM8_YMM9_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_256, 255, 255, 8, 9, RT_ELEMENTS(s_aValues_ST_dw_256), s_aValues_ST_dw_256 }, { bs3CpuInstr3_vmaskmovpd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_128, 8, 8, 9, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vmaskmovpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_256, 8, 8, 9, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vmaskmovpd_FSxBX_XMM8_XMM9_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_128, 255, 255, 8, 9, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vmaskmovpd_FSxBX_YMM8_YMM9_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX_256, 255, 255, 8, 9, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vpmaskmovd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 8, 8, 9, 255, RT_ELEMENTS(s_aValues_LD_dw_128), s_aValues_LD_dw_128 }, { bs3CpuInstr3_vpmaskmovd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 8, 8, 9, 255, RT_ELEMENTS(s_aValues_LD_dw_256), s_aValues_LD_dw_256 }, { bs3CpuInstr3_vpmaskmovd_FSxBX_XMM8_XMM9_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 255, 255, 8, 9, RT_ELEMENTS(s_aValues_ST_dw_128), s_aValues_ST_dw_128 }, { bs3CpuInstr3_vpmaskmovd_FSxBX_YMM8_YMM9_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 255, 255, 8, 9, RT_ELEMENTS(s_aValues_ST_dw_256), s_aValues_ST_dw_256 }, { bs3CpuInstr3_vpmaskmovq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 8, 8, 9, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vpmaskmovq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 8, 8, 9, 255, RT_ELEMENTS(s_aValues_LD_qw_all), s_aValues_LD_qw_all }, { bs3CpuInstr3_vpmaskmovq_FSxBX_XMM8_XMM9_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_128, 255, 255, 8, 9, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, { bs3CpuInstr3_vpmaskmovq_FSxBX_YMM8_YMM9_icebp_c64, X86_XCPT_DB, RM_RANGE, T_AVX2_256, 255, 255, 8, 9, RT_ELEMENTS(s_aValues_ST_qw_all), s_aValues_ST_qw_all }, }; static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * Test type #6 - MM/XMM/YMM <- GPR, no VVVV. * * Used probably only by the PINSRW testcases */ typedef struct BS3CPUINSTR3_TEST6_VALUES_T { RTUINT256U uMediaSrc; uint64_t uGpr; RTUINT256U uMediaDst; } BS3CPUINSTR3_TEST6_VALUES_T; typedef struct BS3CPUINSTR3_TEST6_T { FPFNBS3FAR pfnWorker; uint8_t bAvxMisalignXcpt; uint8_t enmRm; uint8_t enmType; uint8_t cbGpr; uint8_t cBitsGprValMask; uint8_t iGprReg; uint8_t iMediaRegSrc; uint8_t iMediaRegDst; uint8_t cValues; BS3CPUINSTR3_TEST6_VALUES_T const BS3_FAR *paValues; } BS3CPUINSTR3_TEST6_T; typedef struct BS3CPUINSTR3_TEST6_MODE_T { BS3CPUINSTR3_TEST6_T const BS3_FAR *paTests; unsigned cTests; } BS3CPUINSTR3_TEST6_MODE_T; /** Initializer for a BS3CPUINSTR3_TEST6_MODE_T array (three entries). */ #define BS3CPUINSTR3_TEST6_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } /** * Test type #6 worker. */ static uint8_t bs3CpuInstr3_WorkerTestType6(uint8_t bMode, BS3CPUINSTR3_TEST6_T const BS3_FAR *paTests, unsigned cTests, PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) { BS3REGCTX Ctx; BS3TRAPFRAME TrapFrame; const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); uint8_t BS3_FAR *pbBuf = g_pbBuf; uint32_t cbBuf = g_cbBuf; uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; PBS3EXTCTX pExtCtxOut; PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); if (!pExtCtx) return 0; /* Ensure the structures are allocated before we sample the stack pointer. */ Bs3MemSet(&Ctx, 0, sizeof(Ctx)); Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); /* * Create test context. */ pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); /* * Run the tests in all rings since alignment issues may behave * differently in ring-3 compared to ring-0. */ for (;;) { unsigned fPf = 0; do { unsigned iCfg; for (iCfg = 0; iCfg < cConfigs; iCfg++) { unsigned iTest; BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) continue; /* unsupported config */ /* * Iterate the tests. */ for (iTest = 0; iTest < cTests; iTest++) { BS3CPUINSTR3_TEST6_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; unsigned const cValues = paTests[iTest].cValues; bool const fMmxInstr = paTests[iTest].enmType < T_SSE; bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm); uint8_t const cbAlign = RT_MIN(cbOperand, 16); PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf); PRTUINT256U puMemOpAlias = (PRTUINT256U)&g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf]; uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD : fMmxInstr ? paConfigs[iCfg].bXcptMmx : fSseInstr ? paConfigs[iCfg].bXcptSse : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; uint64_t const fGprValMask = paTests[iTest].cBitsGprValMask == 64 ? UINT64_MAX : RT_BIT_64(paTests[iTest].cBitsGprValMask) - 1; uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; unsigned cRecompRuns = 0; unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues; unsigned iVal; /* If testing unaligned memory accesses, skip register-only tests. This allows setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ if ((paTests[iTest].enmRm == RM_REG || paTests[iTest].enmRm == RM_MEM8) && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck || fPf)) continue; /* #AC is only raised in ring-3.: */ if (bXcptExpect == X86_XCPT_AC) { if (bRing != 3) bXcptExpect = X86_XCPT_DB; else if (fAvxInstr) bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ } if (fPf && bXcptExpect == X86_XCPT_DB) bXcptExpect = X86_XCPT_PF; Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); /* * Iterate the test values and do the actual testing. */ while (cRecompRuns < cMaxRecompRuns) for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++) { uint16_t cErrors; uint16_t uSavedFtw = 0xff; RTUINT256U uMemOpExpect; if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0)) continue; /* * Set up the context and some expectations. */ /* source - media */ BS3_ASSERT(paTests[iTest].iMediaRegSrc != UINT8_MAX); if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaRegSrc, paValues[iVal].uMediaSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaRegSrc, &paValues[iVal].uMediaSrc.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaRegSrc, &paValues[iVal].uMediaSrc, 32); /* source - gpr/mem */ if (paTests[iTest].iGprReg == UINT8_MAX) { BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); if (bXcptExpect == X86_XCPT_DB) switch (paTests[iTest].cbGpr) { case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break; case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break; case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break; case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break; default: BS3_ASSERT(0); } Bs3MemCpy(puMemOpAlias, &uMemOpExpect, cbMemOp); } else Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask, paTests[iTest].cbGpr); /* Memory pointer. */ if (paTests[iTest].enmRm >= RM_MEM) { BS3_ASSERT(paTests[iTest].iGprReg == UINT8_MAX || paTests[iTest].iMediaRegSrc == UINT8_MAX); Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); } /* * Execute. */ g_uBs3TrapEipHint = Ctx.rip.u32 + (bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0); Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); /* * Check the result: */ cErrors = Bs3TestSubErrorCount(); if (fMmxInstr && bXcptExpect == X86_XCPT_DB) { uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); } if (bXcptExpect == X86_XCPT_DB) { if (fMmxInstr) Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaRegDst, paValues[iVal].uMediaDst.QWords.qw0, BS3EXTCTXTOPMM_SET); else if (fSseInstr) Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaRegDst, &paValues[iVal].uMediaDst.DQWords.dqw0); else Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaRegDst, &paValues[iVal].uMediaDst, 32); } Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); if (TrapFrame.bXcpt != bXcptExpect) Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) { if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; } if (bXcptExpect == X86_XCPT_PF) Ctx.cr2.u = (uintptr_t)puMemOp; Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, pszMode, idTestStep); Ctx.cr2.u = 0; if ( paTests[iTest].enmRm >= RM_MEM && Bs3MemCmp(puMemOpAlias, &uMemOpExpect, cbMemOp) != 0) Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOpAlias); if (cErrors != Bs3TestSubErrorCount()) { if (paConfigs[iCfg].fAligned) Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", bRing, iCfg, iTest, iVal, bXcptExpect); else Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); Bs3TestPrintf("\n"); } if (uSavedFtw != 0xff) Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); } } bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); } } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode)); /* * Next ring. */ bRing++; if (bRing > 3 || bMode == BS3_MODE_RM) break; Bs3RegCtxConvertToRingX(&Ctx, bRing); } /* * Cleanup. */ bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); return 0; } /* * [V]PINSRB / [V]PINSRW / [V]PINSRD / [V]PINSRQ. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pinsrb_pinsrw_pinsrd_pinsrq(uint8_t bMode) { static BS3CPUINSTR3_TEST6_VALUES_T const s_aValues00_b[] = { { /*medSrc*/ RTUINT256_INIT_C(0, 0, 0x807f6e5d4c3b2a19, 0xf0e1d2c3b4a59687), /*gprSrc*/ UINT64_C( 0xcdefba9845671234), /*medDst*/ RTUINT256_INIT_C(0, 0, 0x807f6e5d4c3b2a19, 0xf0e1d2c3b4a59634) }, }; static BS3CPUINSTR3_TEST6_VALUES_T const s_aValuesFF_b[] = { { /*medSrc*/ RTUINT256_INIT_C(0, 0, 0x0000000000000000, 0x0000000000000000), /*gprSrc*/ UINT64_C( 0x0000000000001234), /*medDst*/ RTUINT256_INIT_C(0, 0, 0x3400000000000000, 0x0000000000000000) }, }; static BS3CPUINSTR3_TEST6_VALUES_T const s_aValues00_w[] = { { /*medSrc*/ RTUINT256_INIT_C(0, 0, 0x807f6e5d4c3b2a19, 0xf0e1d2c3b4a59687), /*gprSrc*/ UINT64_C( 0xcdefba9845671234), /*medDst*/ RTUINT256_INIT_C(0, 0, 0x807f6e5d4c3b2a19, 0xf0e1d2c3b4a51234) }, }; static BS3CPUINSTR3_TEST6_VALUES_T const s_aValuesFF_w_64[] = { { /*medSrc*/ RTUINT256_INIT_C(0, 0, 0x0000000000000000, 0x0000000000000000), /*gprSrc*/ UINT64_C( 0x0000000000001234), /*medDst*/ RTUINT256_INIT_C(0, 0, 0x0000000000000000, 0x1234000000000000) }, }; static BS3CPUINSTR3_TEST6_VALUES_T const s_aValuesFF_w[] = { { /*medSrc*/ RTUINT256_INIT_C(0, 0, 0x0000000000000000, 0x0000000000000000), /*gprSrc*/ UINT64_C( 0x0000000000001234), /*medDst*/ RTUINT256_INIT_C(0, 0, 0x1234000000000000, 0x0000000000000000) }, }; static BS3CPUINSTR3_TEST6_VALUES_T const s_aValues00_d[] = { { /*medSrc*/ RTUINT256_INIT_C(0, 0, 0x807f6e5d4c3b2a19, 0xf0e1d2c3b4a59687), /*gprSrc*/ UINT64_C( 0xcdefba9845671234), /*medDst*/ RTUINT256_INIT_C(0, 0, 0x807f6e5d4c3b2a19, 0xf0e1d2c345671234) }, }; static BS3CPUINSTR3_TEST6_VALUES_T const s_aValuesFF_d[] = { { /*medSrc*/ RTUINT256_INIT_C(0, 0, 0x0000000000000000, 0x0000000000000000), /*gprSrc*/ UINT64_C( 0x0000000000001234), /*medDst*/ RTUINT256_INIT_C(0, 0, 0x0000123400000000, 0x0000000000000000) }, }; static BS3CPUINSTR3_TEST6_VALUES_T const s_aValues00_q[] = { { /*medSrc*/ RTUINT256_INIT_C(0, 0, 0x807f6e5d4c3b2a19, 0xf0e1d2c3b4a59687), /*gprSrc*/ UINT64_C( 0xcdefba9845671234), /*medDst*/ RTUINT256_INIT_C(0, 0, 0x807f6e5d4c3b2a19, 0xcdefba9845671234) }, }; static BS3CPUINSTR3_TEST6_VALUES_T const s_aValuesFF_q[] = { { /*medSrc*/ RTUINT256_INIT_C(0, 0, 0x0000000000000000, 0x0000000000000000), /*gprSrc*/ UINT64_C( 0x0000000000001234), /*medDst*/ RTUINT256_INIT_C(0, 0, 0x0000000000001234, 0x0000000000000000) }, }; static BS3CPUINSTR3_TEST6_T const s_aTests16[] = { { bs3CpuInstr3_pinsrb_XMM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pinsrb_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pinsrb_XMM1_EDX_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pinsrb_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c16, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c16, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c16, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pinsrd_XMM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pinsrd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pinsrd_XMM1_EDX_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pinsrd_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, }; static BS3CPUINSTR3_TEST6_T const s_aTests32[] = { { bs3CpuInstr3_pinsrb_XMM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pinsrb_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pinsrb_XMM1_EDX_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pinsrb_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c32, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c32, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c32, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pinsrd_XMM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pinsrd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pinsrd_XMM1_EDX_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pinsrd_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, }; static BS3CPUINSTR3_TEST6_T const s_aTests64[] = { { bs3CpuInstr3_pinsrb_XMM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pinsrb_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pinsrb_XMM1_EDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 8, 2, 1, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pinsrb_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 1, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pinsrb_XMM8_R9D_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 8, 9, 8, 8, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pinsrb_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 8, 8, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_pinsrb_XMM8_R9D_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 8, 9, 8, 8, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pinsrb_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM8, T_SSE4_1, 1, 8, 255, 8, 8, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_EDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 8, 2, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpinsrb_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 2, 1, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpinsrb_XMM8_XMM9_R9D_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 8, 9, 9, 8, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpinsrb_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 9, 8, RT_ELEMENTS(s_aValuesFF_b), s_aValuesFF_b }, { bs3CpuInstr3_vpinsrb_XMM8_XMM9_R9D_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 8, 9, 9, 8, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_vpinsrb_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM8, T_AVX_128, 1, 8, 255, 9, 8, RT_ELEMENTS(s_aValues00_b), s_aValues00_b }, { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_MM1_R9D_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, 16, 9, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, { bs3CpuInstr3_pinsrw_MM1_R9D_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 2, 16, 9, 1, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_MMX_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w_64), s_aValuesFF_w_64 }, { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c64, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_SSE, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE, 2, 16, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pinsrw_XMM8_R9D_000h_icebp_c64, 255, RM_REG, T_SSE, 2, 16, 9, 8, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE, 2, 16, 255, 8, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_XMM8_R9D_0FFh_icebp_c64, 255, RM_REG, T_SSE, 2, 16, 9, 8, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pinsrw_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE, 2, 16, 255, 8, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pinsrw_XMM1_RDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pinsrw_XMM8_R9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 2, 16, 9, 8, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pinsrw_XMM1_RDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 2, 16, 2, 1, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_pinsrw_XMM8_R9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 2, 16, 9, 8, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 2, 16, 2, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_000h_icebp_c64, 255, RM_REG, T_AVX_128, 2, 16, 9, 9, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 9, 8, RT_ELEMENTS(s_aValues00_w), s_aValues00_w }, { bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 2, 16, 9, 9, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 2, 16, 255, 9, 8, RT_ELEMENTS(s_aValuesFF_w), s_aValuesFF_w }, { bs3CpuInstr3_pinsrd_XMM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pinsrd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pinsrd_XMM1_EDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pinsrd_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pinsrd_XMM8_R9D_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, 9, 8, 8, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pinsrd_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 8, 8, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_pinsrd_XMM8_R9D_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, 9, 8, 8, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pinsrd_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, 255, 8, 8, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_EDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpinsrd_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpinsrd_XMM8_XMM9_R9D_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 9, 9, 8, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpinsrd_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 9, 8, RT_ELEMENTS(s_aValuesFF_d), s_aValuesFF_d }, { bs3CpuInstr3_vpinsrd_XMM8_XMM9_R9D_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 9, 9, 8, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_vpinsrd_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 9, 8, RT_ELEMENTS(s_aValues00_d), s_aValues00_d }, { bs3CpuInstr3_pinsrq_XMM1_RDX_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_pinsrq_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, 64, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_pinsrq_XMM1_RDX_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, 2, 1, 1, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_pinsrq_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, 64, 255, 1, 1, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_pinsrq_XMM8_R9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, 9, 8, 8, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_pinsrq_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, 64, 255, 8, 8, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_pinsrq_XMM8_R9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 64, 9, 8, 8, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_pinsrq_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM64, T_SSE4_1, 8, 64, 255, 8, 8, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_vpinsrq_XMM1_XMM2_RDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, 2, 2, 1, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_vpinsrq_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, 255, 2, 1, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_vpinsrq_XMM1_XMM2_RDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, 2, 2, 1, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_vpinsrq_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, 255, 2, 1, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_vpinsrq_XMM8_XMM9_R9_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, 9, 9, 8, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_vpinsrq_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, 255, 9, 8, RT_ELEMENTS(s_aValuesFF_q), s_aValuesFF_q }, { bs3CpuInstr3_vpinsrq_XMM8_XMM9_R9_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, 9, 9, 8, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, { bs3CpuInstr3_vpinsrq_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, 255, 9, 8, RT_ELEMENTS(s_aValues00_q), s_aValues00_q }, }; static BS3CPUINSTR3_TEST6_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST6_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType6(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * [V]PMADDWD - Multiply and add packed signed word integers. */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaddwd(uint8_t bMode) { static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x3c0b6394364ffde4) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 5, 6, 7, 0xebcf52b41ad4c573) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C( 9, 10, 0x26a0ce5421e769a4, 0x3c0b6394364ffde4) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C( 13, 14, 0x1f5960b8c391d7d2, 0xebcf52b41ad4c573) }, }; static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = { { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), /* => */ RTUINT256_INIT_C(0x07e3afd4052e4d24, 0x153e3d141186d964, 0x26a0ce5421e769a4, 0x3c0b6394364ffde4) }, { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c880008000, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec80008000, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* => */ RTUINT256_INIT_C(0x0b692cfd1ae06638, 0xf3dcd01080000000, 0x1f5960b8c391d7d2, 0xebcf52b41ad4c573) }, }; static BS3CPUINSTR3_TEST1_T const s_aTests16[] = { { bs3CpuInstr3_pmaddwd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddwd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_pmaddwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddwd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddwd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddwd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vpmaddwd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_T const s_aTests32[] = { { bs3CpuInstr3_pmaddwd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddwd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_pmaddwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddwd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddwd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddwd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vpmaddwd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_T const s_aTests64[] = { { bs3CpuInstr3_pmaddwd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddwd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, { bs3CpuInstr3_pmaddwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_pmaddwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_pmaddwd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_pmaddwd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddwd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddwd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddwd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddwd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, { bs3CpuInstr3_vpmaddwd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vpmaddwd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vpmaddwd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, { bs3CpuInstr3_vpmaddwd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, }; static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); } /* * Initialize the global buffer for 'gather' instruction tests. * * pbBuf is a buffer of 2x 4K pages which are accessible to the * instruction under test. The pointer we receive actually points to * to the midpoint, one page into this buffer; the instruction is * passed this same pointer to the middle of the buffer. * * Initialize this memory to a specific pattern so that reads will produce * deterministic, identifiable patterns. * * The buffer is initialized with 16-bit integers giving the offset in * bytes away from that center pointer; i.e. negative values in the page * below the pointer, positive in the page above. */ BS3_DECL_FAR(void) bs3CpuInstr3GatherBufSetup(uint8_t BS3_FAR *pbBuf) { uint16_t BS3_FAR *pBufEntry = (uint16_t BS3_FAR *)pbBuf; uint32_t iEntry; for (iEntry = 0; iEntry < X86_PAGE_SIZE; ++iEntry) pBufEntry[iEntry] = iEntry * 2 - X86_PAGE_SIZE; } /* * Test type #7 - three source XMM/YMM operands, * two of which are written, * and test-table-driven control over the memory pointer. * * Probably only used by the V[P]GATHER instruction family. * * Derived from 'type #5' (at r163284). */ typedef struct BS3CPUINSTR3_TEST7_VALUES_T { RTUINT256U uMask; RTUINT256U uMaskPf; RTUINT256U uOffsets; RTUINT256U uDstInit; RTUINT256U uDstOut; uint8_t fFlags; } BS3CPUINSTR3_TEST7_VALUES_T; typedef struct BS3CPUINSTR3_TEST7_T { FPFNBS3FAR pfnWorker; uint8_t bXcpt; int32_t cMemOpOffset; uint8_t enmType; uint8_t iMmDst; uint8_t iGpMem; uint8_t iMmOff; uint8_t iMmMsk; uint8_t cValues; BS3CPUINSTR3_TEST7_VALUES_T const BS3_FAR *paValues; } BS3CPUINSTR3_TEST7_T; typedef struct BS3CPUINSTR3_TEST7_MODE_T { BS3CPUINSTR3_TEST7_T const BS3_FAR *paTests; unsigned cTests; } BS3CPUINSTR3_TEST7_MODE_T; /** Initializer for a BS3CPUINSTR3_TEST7_MODE_T array (three entries). */ #define BS3CPUINSTR3_TEST7_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } /** * Test type #7 worker. */ static uint8_t bs3CpuInstr3_WorkerTestType7(uint8_t bMode, BS3CPUINSTR3_TEST7_T const BS3_FAR *paTests, unsigned cTests, PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) { BS3REGCTX Ctx; BS3TRAPFRAME TrapFrame; const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; uint8_t BS3_FAR *pbBuf = g_pbBuf; uint32_t cbBuf = g_cbBuf; PBS3EXTCTX pExtCtxOut; PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); if (!pExtCtx) return 0; /* Ensure the structures are allocated before we sample the stack pointer. */ Bs3MemSet(&Ctx, 0, sizeof(Ctx)); Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); /* * Create test context. */ pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); bs3CpuInstr3GatherBufSetup(g_pbBufAlias); Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]); /* * Run the tests in all rings since alignment issues may behave * differently in ring-3 compared to ring-0. */ for (;;) { unsigned fPf = 0; do { unsigned iCfg; for (iCfg = 0; iCfg < cConfigs; iCfg++) { unsigned iTest; BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) continue; /* unsupported config */ /* * Iterate the tests. */ for (iTest = 0; iTest < cTests; iTest++) { BS3CPUINSTR3_TEST7_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; unsigned const cValues = paTests[iTest].cValues; uint8_t const cbOperand = paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; PRTUINT256U puMemOp = fPf ? (PRTUINT256U)&pbBuf[X86_PAGE_SIZE * 2 + 256] : (PRTUINT256U)&pbBuf[X86_PAGE_SIZE]; uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; unsigned cRecompRuns = 0; unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler + cValues; unsigned iVal; Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); /* * Iterate the test values and do the actual testing. */ while (cRecompRuns < cMaxRecompRuns) for (iVal = 0; iVal < cValues; iVal++, idTestStep++, cRecompRuns++) { uint16_t cErrors; uint16_t uSavedFtw = 0xff; uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; if (BS3_SKIPIT(bRing, iCfg, iTest, iVal, 0)) continue; /* These instructions do not raise #AC */ if (bXcptExpect == X86_XCPT_AC) bXcptExpect = paTests[iTest].bXcpt; if (paTests[iTest].bXcpt && bXcptExpect == X86_XCPT_DB) bXcptExpect = paTests[iTest].bXcpt; if (fPf && bXcptExpect == X86_XCPT_DB && !(paValues[iVal].fFlags & BS3_TEST_F_NO_PF)) bXcptExpect = X86_XCPT_PF; /* * Set up the context and some expectations. */ /* initial value of destination register */ Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmDst, &paValues[iVal].uDstInit, 32); /* offsets register */ Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmOff, &paValues[iVal].uOffsets, 32); /* initial value of mask register */ Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmMsk, &paValues[iVal].uMask, 32); /* Memory pointer. */ puMemOp = fPf ? (PRTUINT256U)&pbBuf[X86_PAGE_SIZE * 2 + 256] : (PRTUINT256U)&pbBuf[X86_PAGE_SIZE]; puMemOp = (PRTUINT256U)(((uint8_t BS3_FAR *)puMemOp) - paTests[iTest].cMemOpOffset); BS3_ASSERT(paTests[iTest].iGpMem == X86_GREG_xBX || paTests[iTest].iGpMem == X86_GREG_x8); if (paTests[iTest].iGpMem == X86_GREG_xBX) Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); else if (paTests[iTest].iGpMem == X86_GREG_x8) Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.r8, &Ctx.fs, puMemOp); /* * Execute. */ g_uBs3TrapEipHint = Ctx.rip.u32 + (bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0); Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); /* CPUs are inconsistent about FTW modification during these exceptions */ if (bXcptExpect == X86_XCPT_PF || bXcptExpect == X86_XCPT_AC) Bs3ExtCtxSetAbridgedFtw(pExtCtx, Bs3ExtCtxGetAbridgedFtw(pExtCtxOut)); /* * Check the result: */ cErrors = Bs3TestSubErrorCount(); if (bXcptExpect == X86_XCPT_DB) { RTUINT256U zip = RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000); Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmDst, &paValues[iVal].uDstOut, cbOperand); Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmMsk, &zip, cbOperand); } if (bXcptExpect == X86_XCPT_PF) Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMmMsk, &paValues[iVal].uMaskPf, cbOperand); #if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */ if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE && pExtCtx->Ctx.x.Hdr.bmXState == 0x7 && pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3) pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7; #endif Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); if (TrapFrame.bXcpt != bXcptExpect) Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) { if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; } /* * These instructions can access far wider memory. The cr2Range value reflects * that the *test scenarios* reside within a +/- 1 page range of puMemOp. */ if (bXcptExpect == X86_XCPT_PF) { Ctx.cr2.u = ((uintptr_t)puMemOp) - X86_PAGE_SIZE; Ctx.cr2Range = X86_PAGE_SIZE * 2; } Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, pszMode, idTestStep); if (bXcptExpect == X86_XCPT_PF) { Ctx.cr2.u = 0; Ctx.cr2Range = 0; } if (cErrors != Bs3TestSubErrorCount()) { Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)\n", bRing, iCfg, iTest, iVal, bXcptExpect); } if (uSavedFtw != 0xff) Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); } } bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); } } while (fPf++ == 0 && BS3_MODE_IS_PAGED(bMode)); /* * Next ring. */ bRing++; if (bRing > 3 || bMode == BS3_MODE_RM) break; Bs3RegCtxConvertToRingX(&Ctx, bRing); } /* * Cleanup. */ bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); return 0; } /* * VGATHERDPS - Gather Packed Single Precision FP Values Using Signed Dword Indices * VPGATHERDD - Gather Packed Dword Values Using Signed Dword Indices */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vgatherdps_vpgatherdd(uint8_t bMode) { static BS3CPUINSTR3_TEST7_VALUES_T const s_aValuesUD[] = { // Values don't matter, instruction is supposed to #UD! { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), /*pmsk*/ RTUINT256_INIT_C(0, 0, 0, 0), /*offs*/ RTUINT256_INIT_C(0, 0, 0, 0), /*init*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_32x1[] = { // 32-bit data slices and 32-bit indices times 1 { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0002000000020000, 0x0002000000020000, 0x0002000000020000, 0x0002000000020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), /*offs*/ RTUINT256_INIT_C(0x00000001ffffff99, 0x0000003300000044, 0xfffffefb00000076, 0x0000007c0000007b), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0x0400020078787878, 0x7878787800460044, 0xfefefcfe78787878, 0x787878787e007c00), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_32x2[] = { // 32-bit data slices and 32-bit indices times 2 { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0002000000020000, 0x0002000000020000, 0x0002000000020000, 0x0002000000020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), /*offs*/ RTUINT256_INIT_C(0x00000001ffffff99, 0x0000003300000044, 0xfffffefb00000076, 0x0000007c0000007b), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0x0004000278787878, 0x78787878008a0088, 0xfdf8fdf678787878, 0x7878787800f800f6), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_T const s_aTests16[] = { { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, }; static BS3CPUINSTR3_TEST7_T const s_aTests32[] = { { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, }; static BS3CPUINSTR3_TEST7_T const s_aTests64[] = { { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm0_rbx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vgatherdps_ymm8_r8d_plus_0_plus_ymm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x2), s_aValues32_32x2 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm0_rbx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, { bs3CpuInstr3_vpgatherdd_ymm8_r8d_plus_0_plus_ymm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_32x1), s_aValues32_32x1 }, }; static BS3CPUINSTR3_TEST7_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST7_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType7(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * VGATHERQPS - Gather Packed Single Precision FP Values Using Signed Qword Indices * VPGATHERQD - Gather Packed Dword Values Using Signed Qword Indices */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vgatherqps_vpgatherqd(uint8_t bMode) { static BS3CPUINSTR3_TEST7_VALUES_T const s_aValuesUD[] = { // Values don't matter, instruction is supposed to #UD! { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), /*pmsk*/ RTUINT256_INIT_C(0, 0, 0, 0), /*offs*/ RTUINT256_INIT_C(0, 0, 0, 0), /*init*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_64x1X[] = { // 32-bit data slices and 64-bit indices times 1; only 2 indices (XMM's worth) { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0002000000020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000002, 0x0000000000000004, 0xfffffffffffffefb, 0x0000000000000345), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x7878787848034603), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_64x1Y[] = { // 32-bit data slices and 64-bit indices times 1; 4 indices (YMM's worth) { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0002000000020000, 0x0002000000020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000002, 0x0000000000000004, 0xfffffffffffffefb, 0x0000000000000345), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0004000278787878, 0x7878787848034603), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_64x2X[] = { // 32-bit data slices and 64-bit indices times 2; only 2 indices (XMM's worth) { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0002000000020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000002, 0x0000000000000004, 0xfffffffffffffefb, 0x0000000000000345), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x78787878068c068a), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues32_64x2Y[] = { // 32-bit data slices and 64-bit indices times 2; 4 indices (YMM's worth) { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0002000000020000, 0x0002000000020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000002, 0x0000000000000004, 0xfffffffffffffefb, 0x0000000000000345), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0006000478787878, 0x78787878068c068a), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_T const s_aTests16[] = { { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, }; static BS3CPUINSTR3_TEST7_T const s_aTests32[] = { { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, }; static BS3CPUINSTR3_TEST7_T const s_aTests64[] = { { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm0_rbx_plus_0_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vgatherqps_xmm8_r8d_plus_0_plus_ymm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2X), s_aValues32_64x2X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_64x1X), s_aValues32_64x1X }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_0_plus_ymm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x2Y), s_aValues32_64x2Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_2_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_2_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_plus_153_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_ebx_less_153_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm0_rbx_plus_0_plus_ymm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, { bs3CpuInstr3_vpgatherqd_xmm8_r8d_plus_0_plus_ymm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues32_64x1Y), s_aValues32_64x1Y }, }; static BS3CPUINSTR3_TEST7_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST7_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType7(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * VGATHERDPD - Gather Packed Double Precision FP Values Using Signed Dword Indices * VPGATHERDQ - Gather Packed Qword Values Using Signed Dword Indices */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vgatherdpd_vpgatherdq(uint8_t bMode) { static BS3CPUINSTR3_TEST7_VALUES_T const s_aValuesUD[] = { // Values don't matter, instruction is supposed to #UD! { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), /*pmsk*/ RTUINT256_INIT_C(0, 0, 0, 0), /*offs*/ RTUINT256_INIT_C(0, 0, 0, 0), /*init*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_32x1[] = { // 64-bit data slices and 32-bit indices times 1 { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0006000400020000, 0x0006000400020000, 0x0006000400020000, 0x0006000400020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000900000999, 0x123456789abcdef0, 0xfffff68900000006, 0x0000000700000008), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0x90f68ef68cf68af6, 0x7878787878787878, 0x0e000c000a000800, 0x7878787878787878), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_32x2[] = { // 64-bit data slices and 32-bit indices times 2 { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0006000400020000, 0x0006000400020000, 0x0006000400020000, 0x0006000400020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000900000999, 0x123456789abcdef0, 0xfffff88900000006, 0x0000000700000008), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0xf118f116f114f112, 0x7878787878787878, 0x001400120010000e, 0x7878787878787878), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_T const s_aTests16[] = { { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, }; static BS3CPUINSTR3_TEST7_T const s_aTests32[] = { { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, }; static BS3CPUINSTR3_TEST7_T const s_aTests64[] = { { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm0_rbx_plus_0_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vgatherdpd_ymm8_r8d_plus_0_plus_xmm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm0_x_1_ymm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_0_plus_xmm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x2), s_aValues64_32x2 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_2_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_2_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_plus_153_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_ebx_less_153_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm0_rbx_plus_0_plus_xmm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, { bs3CpuInstr3_vpgatherdq_ymm8_r8d_plus_0_plus_xmm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_32x1), s_aValues64_32x1 }, }; static BS3CPUINSTR3_TEST7_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST7_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType7(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /* * VGATHERQPD - Gather Packed Double Precision FP Values Using Signed Qword Indices * VPGATHERQQ - Gather Packed Qword Values Using Signed Qword Indices */ BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vgatherqpd_vpgatherqq(uint8_t bMode) { static BS3CPUINSTR3_TEST7_VALUES_T const s_aValuesUD[] = { // Values don't matter, instruction is supposed to #UD! { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), /*pmsk*/ RTUINT256_INIT_C(0, 0, 0, 0), /*offs*/ RTUINT256_INIT_C(0, 0, 0, 0), /*init*/ RTUINT256_INIT_C(0, 0, 0, 0), /* => */ RTUINT256_INIT_C(0, 0, 0, 0), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_64x1X[] = { // 64-bit data slices and 64-bit indices times 1; only 2 indices (XMM's worth) { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0006000400020000, 0x0006000400020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000399, 0x123456789abcdef0, 0xffffffffffffff77, 0x00000000000003ed), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x7eff7cff7aff78ff, 0x7878787878787878), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_64x1Y[] = { // 64-bit data slices and 64-bit indices times 1; 4 indices (YMM's worth) { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0006000400020000, 0x0006000400020000, 0x0006000400020000, 0x0006000400020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000399, 0x123456789abcdef0, 0xffffffffffffff77, 0x00000000000003ed), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0xa0039e039c039a03, 0x7878787878787878, 0x7eff7cff7aff78ff, 0x7878787878787878), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_64x2X[] = { // 64-bit data slices and 64-bit indices times 2; only 2 indices (XMM's worth) { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0006000400020000, 0x0006000400020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000199, 0x123456789abcdef0, 0xffffffffffffffc7, 0x00000000000000cd), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xff94ff92ff90ff8e, 0x7878787878787878), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_VALUES_T const s_aValues64_64x2Y[] = { // 64-bit data slices and 64-bit indices times 2; 4 indices (YMM's worth) { /*mask*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*pmsk*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*flgs*/ BS3_TEST_F_NO_PF }, { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), /*offs*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /*init*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000), /* => */ RTUINT256_INIT_C(0x0006000400020000, 0x0006000400020000, 0x0006000400020000, 0x0006000400020000), /*flgs*/ 0 }, { /*mask*/ RTUINT256_INIT_C(0xffffffff00000000, 0x11111111eeeeeeee, 0xdddddddd22222222, 0x33333333cccccccc), /*pmsk*/ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000), /*offs*/ RTUINT256_INIT_C(0x0000000000000199, 0x123456789abcdef0, 0xffffffffffffffc7, 0x00000000000000cd), /*init*/ RTUINT256_INIT_C(0x7878787878787878, 0x7878787878787878, 0x7878787878787878, 0x7878787878787878), /* => */ RTUINT256_INIT_C(0x0338033603340332, 0x7878787878787878, 0xff94ff92ff90ff8e, 0x7878787878787878), /*flgs*/ 0 }, }; static BS3CPUINSTR3_TEST7_T const s_aTests16[] = { { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c16, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c16, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c16, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, }; static BS3CPUINSTR3_TEST7_T const s_aTests32[] = { { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c32, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c32, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c32, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, }; static BS3CPUINSTR3_TEST7_T const s_aTests64[] = { { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm0_rbx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vgatherqpd_ymm8_r8d_plus_0_plus_ymm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm0_x_1_xmm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_128, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_0_plus_xmm1_x_2_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2X), s_aValues64_64x2X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_2_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_plus_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_ebx_less_153_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm0_rbx_plus_0_plus_xmm1_x_1_xmm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_xmm8_r8d_plus_0_plus_xmm9_x_1_xmm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_128, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_64x1X), s_aValues64_64x1X }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm0_x_1_ymm2_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 0, 2, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm0_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 0, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm1_icebp_c64, X86_XCPT_UD, 0, T_AVX2_256, 0, 3, 1, 1, RT_ELEMENTS(s_aValuesUD), s_aValuesUD }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_0_plus_ymm1_x_2_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x2Y), s_aValues64_64x2Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_2_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -2, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_plus_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_ebx_less_153_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, -153, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm0_rbx_plus_0_plus_ymm1_x_1_ymm2_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 0, 3, 1, 2, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, { bs3CpuInstr3_vpgatherqq_ymm8_r8d_plus_0_plus_ymm9_x_1_ymm10_icebp_c64, X86_XCPT_DB, 0, T_AVX2_256, 8, 8, 9, 10, RT_ELEMENTS(s_aValues64_64x1Y), s_aValues64_64x1Y }, }; static BS3CPUINSTR3_TEST7_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST7_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); return bs3CpuInstr3_WorkerTestType7(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); } /** * The 32-bit protected mode main function. * * The tests a driven by 32-bit test drivers, even for real-mode tests (though * we'll switch between PE32 and RM for each test step we perform). Given that * we test MMX, SSE and AVX here, we don't need to worry about 286 or 8086. * * Some extra steps needs to be taken to properly handle extended state in LM64 * (Bs3ExtCtxRestoreEx & Bs3ExtCtxSaveEx) and when testing real mode * (Bs3RegCtxSaveForMode & Bs3TrapSetJmpAndRestoreWithExtCtxAndRm). */ BS3_DECL(void) Main_pe32() { static const BS3TESTMODEBYONEENTRY g_aTests[] = { #if 1 /*ndef DEBUG_bird*/ # define ALL_TESTS #endif #if defined(ALL_TESTS) { "[v]andps/[v]andpd/[v]pand", bs3CpuInstr3_v_andps_andpd_pand, 0 }, { "[v]andnps/[v]andnpd/[v]pandn", bs3CpuInstr3_v_andnps_andnpd_pandn, 0 }, { "[v]orps/[v]orpd/[v]or", bs3CpuInstr3_v_orps_orpd_por, 0 }, { "[v]xorps/[v]xorpd/[v]pxor", bs3CpuInstr3_v_xorps_xorpd_pxor, 0 }, #endif #if defined(ALL_TESTS) { "[v]pcmpgtb/[v]pcmpgtw/[v]pcmpgtd/[v]pcmpgtq", bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd_pcmpgtq, 0 }, { "[v]pcmpeqb/[v]pcmpeqw/[v]pcmpeqd/[v]pcmpeqq", bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd_pcmpeqq, 0 }, #endif #if defined(ALL_TESTS) { "[v]paddb/[v]paddw/[v]paddd/[v]paddq", bs3CpuInstr3_v_paddb_paddw_paddd_paddq, 0 }, { "[v]psubb/[v]psubw/[v]psubd/[v]psubq", bs3CpuInstr3_v_psubb_psubw_psubd_psubq, 0 }, #endif #if defined(ALL_TESTS) { "[v]pmullw/[v]pmulld", bs3CpuInstr3_v_pmullw_pmulld, 0 }, { "[v]pmulhw", bs3CpuInstr3_v_pmulhw, 0 }, { "[v]pmulhuw", bs3CpuInstr3_v_pmulhuw, 0 }, #endif #if defined(ALL_TESTS) { "[v]pmovmskb", bs3CpuInstr3_v_pmovmskb, 0 }, { "pshufb", bs3CpuInstr3_pshufb, 0 }, { "pshufw", bs3CpuInstr3_pshufw, 0 }, { "[v]pshufhw", bs3CpuInstr3_v_pshufhw, 0 }, { "[v]pshuflw", bs3CpuInstr3_v_pshuflw, 0 }, { "[v]pshufd", bs3CpuInstr3_v_pshufd, 0 }, #endif #if defined(ALL_TESTS) { "[v]punpckhbw", bs3CpuInstr3_v_punpckhbw, 0 }, { "[v]punpckhwd", bs3CpuInstr3_v_punpckhwd, 0 }, { "[v]punpckhdq", bs3CpuInstr3_v_punpckhdq, 0 }, { "[v]punpckhqdq", bs3CpuInstr3_v_punpckhqdq, 0 }, #endif #if defined(ALL_TESTS) { "[v]punpcklbw", bs3CpuInstr3_v_punpcklbw, 0 }, { "[v]punpcklwd", bs3CpuInstr3_v_punpcklwd, 0 }, { "[v]punpckldq", bs3CpuInstr3_v_punpckldq, 0 }, { "[v]punpcklqdq", bs3CpuInstr3_v_punpcklqdq, 0 }, #endif #if defined(ALL_TESTS) { "[v]packsswb", bs3CpuInstr3_v_packsswb, 0 }, { "[v]packssdw", bs3CpuInstr3_v_packssdw, 0 }, { "[v]packuswb", bs3CpuInstr3_v_packuswb, 0 }, { "[v]packusdw", bs3CpuInstr3_v_packusdw, 0 }, #endif #if defined(ALL_TESTS) { "[v]pmaxub/[v]pmaxuw/[v]pmaxud", bs3CpuInstr3_v_pmaxub_pmaxuw_pmaxud, 0 }, { "[v]pmaxsb/[v]pmaxsw/[v]pmaxsd", bs3CpuInstr3_v_pmaxsb_pmaxsw_pmaxsd, 0 }, { "[v]pminub/[v]pminuw/[v]pminud", bs3CpuInstr3_v_pminub_pminuw_pminud, 0 }, { "[v]pminsb/[v]pminsw/[v]pminsd", bs3CpuInstr3_v_pminsb_pminsw_pminsd, 0 }, #endif #if defined(ALL_TESTS) { "[v]movntdqa", bs3CpuInstr3_v_movntdqa, 0 }, { "[v]movntdq", bs3CpuInstr3_v_movntdq, 0 }, { "[v]movntps_movntpd", bs3CpuInstr3_v_movntps_movntpd, 0 }, { "[v]movups", bs3CpuInstr3_v_movups, 0 }, { "[v]movupd", bs3CpuInstr3_v_movupd, 0 }, { "[v]movss", bs3CpuInstr3_v_movss, 0 }, { "[v]movsd", bs3CpuInstr3_v_movsd, 0 }, { "[v]movhlps", bs3CpuInstr3_v_movhlps, 0 }, { "[v]movlps/[v]movlpd", bs3CpuInstr3_v_movlps_movlpd, 0 }, { "[v]movhps/[v]movhpd", bs3CpuInstr3_v_movhps_movhpd, 0 }, { "[v]movsldup", bs3CpuInstr3_v_movsldup, 0 }, { "[v]movshdup", bs3CpuInstr3_v_movshdup, 0 }, { "[v]movddup", bs3CpuInstr3_v_movddup, 0 }, { "[v]movaps_movapd", bs3CpuInstr3_v_movaps_movapd, 0 }, { "[v]movd_movq", bs3CpuInstr3_v_movd_movq, 0 }, { "[v]movdqu", bs3CpuInstr3_v_movdqu, 0 }, { "[v]movdqa", bs3CpuInstr3_v_movdqa, 0 }, #endif #if defined(ALL_TESTS) { "[v]ptest", bs3CpuInstr3_v_ptest, 0 }, #endif #if defined(ALL_TESTS) { "vtestps", bs3CpuInstr3_vtestps, 0 }, #endif #if defined(ALL_TESTS) { "vtestpd", bs3CpuInstr3_vtestpd, 0 }, #endif #if defined(ALL_TESTS) { "[v]pavgb/[v]pavgw", bs3CpuInstr3_v_pavgb_pavgw, 0 }, #endif #if defined(ALL_TESTS) { "[v]pabsb/[v]pabsw/[v]pabsd", bs3CpuInstr3_v_pabsb_pabsw_pabsd, 0 }, { "[v]psignb/[v]psignw/[v]psignd", bs3CpuInstr3_v_psignb_psignw_psignd, 0 }, #endif #if defined(ALL_TESTS) { "[v]phaddw/[v]phaddd", bs3CpuInstr3_v_phaddw_phaddd, 0 }, { "[v]phsubw/[v]phsubd", bs3CpuInstr3_v_phsubw_phsubd, 0 }, { "[v]phaddsw", bs3CpuInstr3_v_phaddsw, 0 }, { "[v]phsubsw", bs3CpuInstr3_v_phsubsw, 0 }, { "[v]pmaddubsw", bs3CpuInstr3_v_pmaddubsw, 0 }, #endif #if defined(ALL_TESTS) { "[v]pmulhrsw", bs3CpuInstr3_v_pmulhrsw, 0 }, { "[v]psadbw", bs3CpuInstr3_v_psadbw, 0 }, { "[v]pmuldq", bs3CpuInstr3_v_pmuldq, 0 }, { "[v]pmuludq", bs3CpuInstr3_v_pmuludq, 0 }, { "[v]punpcklps/[v]punpcklpd", bs3CpuInstr3_v_punpcklps_punpcklpd, 0 }, { "[v]punpckhps/[v]punpckhpd", bs3CpuInstr3_v_punpckhps_punpckhpd, 0 }, #endif #if defined(ALL_TESTS) { "[v]pmovsxbw/[v]pmovsxbd/[v]pmovsxbq/[v]pmovsxwd/[v]pmovsxwq/[v]pmovsxdq", bs3CpuInstr3_v_pmovsxbw_pmovsxbd_pmovsxbq_pmovsxwd_pmovsxwq_pmovsxdq, 0 }, { "[v]pmovzxbw/[v]pmovzxbd/[v]pmovzxbq/[v]pmovzxwd/[v]pmovzxwq/[v]pmovzxdq", bs3CpuInstr3_v_pmovzxbw_pmovzxbd_pmovzxbq_pmovzxwd_pmovzxwq_pmovzxdq, 0 }, #endif #if defined(ALL_TESTS) { "[v]shufps", bs3CpuInstr3_v_shufps, 0 }, { "[v]shufpd", bs3CpuInstr3_v_shufpd, 0 }, #endif #if defined(ALL_TESTS) { "[v]lddqu", bs3CpuInstr3_v_lddqu, 0 }, #endif #if defined(ALL_TESTS) { "[v]phminposuw", bs3CpuInstr3_v_phminposuw, 0 }, #endif #if defined(ALL_TESTS) { "[v]pblendvb", bs3CpuInstr3_v_pblendvb, 0 }, { "[v]blendvps", bs3CpuInstr3_v_blendvps, 0 }, { "[v]blendvpd", bs3CpuInstr3_v_blendvpd, 0 }, #endif #if defined(ALL_TESTS) { "[v]palignr", bs3CpuInstr3_v_palignr, 0 }, #endif #if defined(ALL_TESTS) { "[v]pblendw", bs3CpuInstr3_v_pblendw, 0 }, { "vpblendd", bs3CpuInstr3_vpblendd, 0 }, { "[v]blendps", bs3CpuInstr3_v_blendps, 0 }, { "[v]blendpd", bs3CpuInstr3_v_blendpd, 0 }, #endif #if defined(ALL_TESTS) { "[v]pclmulqdq", bs3CpuInstr3_v_pclmulqdq, 0 }, { "[v]pinsrb/[v]pinsrw/[v]pinsrd/[v]pinsrq", bs3CpuInstr3_v_pinsrb_pinsrw_pinsrd_pinsrq, 0 }, { "[v]pextrb/[v]pextrw/[v]pextrd/[v]pextrq", bs3CpuInstr3_v_pextrb_pextrw_pextrd_pextrq, 0 }, { "[v]movmskps/[v]movmskpd", bs3CpuInstr3_v_movmskps_movmskpd, 0 }, #endif #if defined(ALL_TESTS) { "sha1nexte/sha1msg1/sha1msg2/sha256msg1/sha256msg2/sha1rnds4", bs3CpuInstr3_v_sha1nexte_sha1msg1_sha1msg2_sha256msg1_sha256msg2_sha1rnds4, 0 }, { "sha256rnds2", bs3CpuInstr3_v_sha256rnds2, 0 }, #endif #if defined(ALL_TESTS) { "[v]mpsadbw", bs3CpuInstr3_v_mpsadbw, 0 }, #endif #if defined(ALL_TESTS) { "vbroadcastss/vbroadcastsd/vbroadcastf128", bs3CpuInstr3_vbroadcastss_vbroadcastsd_vbroadcastf128, 0 }, { "vpbroadcastb/vpbroadcastw/vpbroadcastd/vpbroadcastq/vbroadcasti128", bs3CpuInstr3_vpbroadcastb_vpbroadcastw_vpbroadcastd_vpbroadcastq_vbroadcasti128, 0 }, #endif #if defined(ALL_TESTS) { "vinserti128/vinsertf128", bs3CpuInstr3_vinserti128_vinsertf128, 0 }, { "vextracti128/vextractf128", bs3CpuInstr3_vextracti128_vextractf128, 0 }, #endif #if defined(ALL_TESTS) { "[v]insertps", bs3CpuInstr3_v_insertps, 0 }, { "[v]extractps", bs3CpuInstr3_v_extractps, 0 }, #endif #if defined(ALL_TESTS) { "[v]psubsb/[v]psubsw", bs3CpuInstr3_v_psubsb_psubsw, 0 }, { "[v]psubusb/[v]psubusw", bs3CpuInstr3_v_psubusb_psubusw, 0 }, { "[v]paddusb/[v]paddusw", bs3CpuInstr3_v_paddusb_paddusw, 0 }, { "[v]paddsb/[v]paddsw", bs3CpuInstr3_v_paddsb_paddsw, 0 }, #endif #if defined(ALL_TESTS) { "[v]psllw/[v]pslld/[v]psllq", bs3CpuInstr3_v_psllw_pslld_psllq, 0 }, { "[v]psraw/[v]psrad", bs3CpuInstr3_v_psraw_psrad, 0 }, { "[v]psrlw/[v]psrld/[v]psrlq", bs3CpuInstr3_v_psrlw_psrld_psrlq, 0 }, #endif #if defined(ALL_TESTS) { "vpsllvd/vpsllvq", bs3CpuInstr3_vpsllvd_vpsllvq, 0 }, { "vpsravd", bs3CpuInstr3_vpsravd, 0 }, { "vpsrlvd/vpsrlvq", bs3CpuInstr3_vpsrlvd_vpsrlvq, 0 }, { "[v]pslldq/[v]psrldq", bs3CpuInstr3_v_pslldq_v_psrldq, 0 }, #endif #if defined(ALL_TESTS) { "vperm2i128/vperm2f128", bs3CpuInstr3_vperm2i128_vperm2f128, 0 }, #endif #if defined(ALL_TESTS) { "vpermilps", bs3CpuInstr3_vpermilps, 0 }, { "vpermilpd", bs3CpuInstr3_vpermilpd, 0 }, #endif #if defined(ALL_TESTS) { "[v]pmaddwd", bs3CpuInstr3_v_pmaddwd, 0 }, #endif #if defined(ALL_TESTS) { "maskmovq/[v]maskmovdqu", bs3CpuInstr3_maskmovq_v_maskmovdqu, 0 }, { "vmaskmovps/vmaskmovpd/vpmaskmovd/vpmaskmovq", bs3CpuInstr3_vmaskmovps_d_vpmaskmovd_q, 0 }, #endif #if defined(ALL_TESTS) { "vgatherdps/vpgatherdd", bs3CpuInstr3_vgatherdps_vpgatherdd, 0 }, { "vgatherqps/vpgatherqd", bs3CpuInstr3_vgatherqps_vpgatherqd, 0 }, { "vgatherdpd/vpgatherdq", bs3CpuInstr3_vgatherdpd_vpgatherdq, 0 }, { "vgatherqpd/vpgatherqq", bs3CpuInstr3_vgatherqpd_vpgatherqq, 0 }, #endif }; Bs3TestInit("bs3-cpu-instr-3"); /* * Initialize globals. */ if (g_uBs3CpuDetected & BS3CPU_F_CPUID) { uint32_t fEbx, fEcx, fEdx; ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx); g_afTypeSupports[T_MMX] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_MMX); g_afTypeSupports[T_MMX_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE); g_afTypeSupports[T_MMX_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2); g_afTypeSupports[T_MMX_SSSE3] = RT_BOOL(fEdx & X86_CPUID_FEATURE_ECX_SSSE3); g_afTypeSupports[T_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE); g_afTypeSupports[T_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2); g_afTypeSupports[T_SSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE3); g_afTypeSupports[T_SSSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSSE3); g_afTypeSupports[T_SSE4_1] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_1); g_afTypeSupports[T_SSE4_2] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_2); g_afTypeSupports[T_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL); g_afTypeSupports[T_AVX_128] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); g_afTypeSupports[T_AVX_256] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); g_afTypeSupports[T_AVX_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL) && RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); if (ASMCpuId_EAX(0) >= 7) { ASMCpuIdExSlow(7, 0, 0, 0, NULL, &fEbx, NULL, NULL); g_afTypeSupports[T_AVX2_128] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2); g_afTypeSupports[T_AVX2_256] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2); g_afTypeSupports[T_SHA] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_SHA); } if (g_uBs3CpuDetected & BS3CPU_F_CPUID_EXT_LEAVES) { ASMCpuIdExSlow(UINT32_C(0x80000001), 0, 0, 0, NULL, NULL, &fEcx, &fEdx); g_afTypeSupports[T_AXMMX] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_EDX_AXMMX); g_afTypeSupports[T_SSE4A] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_SSE4A); g_fAmdMisalignedSse = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_MISALNSSE); } g_afTypeSupports[T_AXMMX_OR_SSE] = g_afTypeSupports[T_AXMMX] || g_afTypeSupports[T_SSE]; } /* * Allocate a buffer for testing. */ g_cbBuf = X86_PAGE_SIZE * 4; g_pbBuf = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_REAL, g_cbBuf); if (g_pbBuf) { g_pbBufAliasAlloc = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_TILED, g_cbBuf); if (g_pbBufAliasAlloc) { /* * Do the tests. */ Bs3TestDoModesByOne_pe32(g_aTests, RT_ELEMENTS(g_aTests), BS3TESTMODEBYONEENTRY_F_REAL_MODE_READY); bs3CpuInstrX_ShowTallies(true); } else Bs3TestFailed("Failed to allocate 16K alias buffer (tiled addressable)"); } else Bs3TestFailed("Failed to allocate 16K buffer (real mode addressable)"); Bs3TestTerm(); }