|
|
|
@55106
|
10 years |
vboxsync |
VMM: host+guest xsave/xrstor state handling - not enabled.
|
|
|
|
@55054
|
10 years |
vboxsync |
Removed support for host CPUs without FXSAVE/FXRSTOR support.
|
|
|
|
@55048
|
10 years |
vboxsync |
VMM,REM: Allocate the FPU/SSE/AVX/FUTURE state stuff. We need to use …
|
|
|
|
@54898
|
10 years |
vboxsync |
CPUMCTX,CPUMHOST: Replaced the fpu (X86FXSAVE) member with an XState …
|
|
|
|
@54707
|
10 years |
vboxsync |
re-enable EILVT handling by backing out r98856
|
|
|
|
@54698
|
10 years |
vboxsync |
VMMSwitcher: disable EILVT handing again to check if it makes any …
|
|
|
|
@54546
|
10 years |
vboxsync |
VMMSwitcher: no write completion required
|
|
|
|
@54537
|
10 years |
vboxsync |
VMMSwitcher: fixed code for disabling the Extended LVT APIC registers
|
|
|
|
@54496
|
10 years |
vboxsync |
VMMSwitcher: test code for disabling the Extended LVT APIC registers …
|
|
|
|
@54474
|
10 years |
vboxsync |
VMMSwitcher: fixed two typos which prevented proper handling of the …
|
|
|
|
@53835
|
10 years |
vboxsync |
VMMSwitcher: also mask NMI in APIC_REG_LVT_CMCI
|
|
|
|
@52410
|
10 years |
vboxsync |
traling spaces
|
|
|
|
@52296
|
10 years |
vboxsync |
VMM: Missed copyright header update in r95407.
|
|
|
|
@52295
|
10 years |
vboxsync |
VMM: Fix mixing 64-bit/32-bit FPU state in raw-mode.
|
|
|
|
@50661
|
11 years |
vboxsync |
GCC:/MSC: => gcc:/msc: like everywhere
|
|
|
|
@47844
|
11 years |
vboxsync |
VMM: X2APIC + NMI. Only tested on AMD64.
|
|
|
|
@47689
|
11 years |
vboxsync |
tstVMM: DRx fixes.
|
|
|
|
@47686
|
11 years |
vboxsync |
VMMSwitcher: typo
|
|
|
|
@47660
|
11 years |
vboxsync |
VMM: Debug register handling redo. (only partly tested on AMD-V so far.)
|
|
|
|
@41985
|
12 years |
vboxsync |
VMM: Fixed tstVMM (single stepping ++ in raw-mode code).
|
|
|
|
@41976
|
12 years |
vboxsync |
VMM: Switcher and TRPM fixes wrt hypervisor traps and tstVMM.
|
|
|
|
@41933
|
12 years |
vboxsync |
VMMSwitcher: Drop the unused assembly switcher functions taking guest …
|
|
|
|
@41906
|
12 years |
vboxsync |
CPUM: Combined the visible and hidden selector register data into one …
|
|
|
|
@41905
|
12 years |
vboxsync |
CPUMCTX++: Rearranging the CPUMCTX structure in preparation of some …
|
|
|
|
@37969
|
13 years |
vboxsync |
AMD64andLegacy.mac: Avoid #GPing in world switcher code when restoring …
|
|
|
|
@37955
|
13 years |
vboxsync |
Moved VBox/x86.h/mac to iprt/x86.h/mac.
|
|
|
|
@35418
|
14 years |
vboxsync |
VMMSwitcher/AMD64andLegacy.mac: superfluous instruction
|
|
|
|
@35346
|
14 years |
vboxsync |
VMM reorg: Moving the public include files from include/VBox to …
|
|
|
|
@35333
|
14 years |
vboxsync |
VMM source reorg.
|
|
|
|
@34986
|
14 years |
vboxsync |
VMMSwitcher/AMD64andLegacy: restore the Local APIC NMI vectors _after_ …
|
|
|
|
@33935
|
14 years |
vboxsync |
VMM: mask all Local APIC interrupt vectors which are set up to NMI …
|
|
|
|
@33540
|
14 years |
vboxsync |
*: spelling fixes, thanks Timeless!
|
|
|
|
@30164
|
14 years |
vboxsync |
CPUM: Added /CPUM/PortableCpuIdLevel={0..3} for automatically …
|
|
|
|
@28800
|
15 years |
vboxsync |
Automated rebranding to Oracle copyright/license strings via filemuncher
|
|
|
|
@21946
|
15 years |
vboxsync |
AMD64andLegacy.mac: CPUM.ulOffCPUMCPU is 32-bit.
|
|
|
|
@21944
|
15 years |
vboxsync |
AMD64AndLegacy.mac: fixed wrong save/restore of EDX in …
|
|
|
|
@21937
|
15 years |
vboxsync |
Fixed wrong check for sysenter.
|
|
|
|
@18927
|
16 years |
vboxsync |
Big step to separate VMM data structures for guest SMP. (pgm, em)
|
|
|
|
@16859
|
16 years |
vboxsync |
Load hypervisor CR3 from CPUM (instead of hardcoded fixups in the …
|
|
|
|
@15414
|
16 years |
vboxsync |
Corrected VBOX_WITH_HYBIRD_32BIT_KERNEL to …
|
|
|
|
@14979
|
16 years |
vboxsync |
Switcher fixes
|
|
|
|
@14254
|
16 years |
vboxsync |
Safety precautions.
|
|
|
|
@14167
|
16 years |
vboxsync |
VMM: AMD64 -> 32bit switcher (for testing only).
|
|
copied from trunk/src/VBox/VMM/VMMSwitcher/AMD64ToPAE.asm
|
|
|
|
@13960
|
16 years |
vboxsync |
Moved guest and host CPU contexts into per-VCPU array.
|
