|
|
@10633
|
16 years |
vboxsync |
No return
|
|
|
@10630
|
16 years |
vboxsync |
Newer functions for handling fpu save/restore in ring 0.
|
|
|
@10609
|
16 years |
vboxsync |
Check for unexpected rescheduling.
|
|
|
@10607
|
16 years |
vboxsync |
Guest state loading and host state saving *must* be done after TPR …
|
|
|
@10602
|
16 years |
vboxsync |
Backed out previous changeset; no harm done there.
|
|
|
@10601
|
16 years |
vboxsync |
Fixed bogus return code check (string callback can fail if there's no …
|
|
|
@10600
|
16 years |
vboxsync |
Logging update
|
|
|
@10586
|
16 years |
vboxsync |
Moved the VT-x checks to the non-64 bit case.
|
|
|
@10572
|
16 years |
vboxsync |
Use NIL_RTR0MEMOBJ and ASMMemZeroPage.
|
|
|
@10571
|
16 years |
vboxsync |
Forgot to make the addition cpuid leafs available.
|
|
|
@10570
|
16 years |
vboxsync |
Extra check for the monitor/mwait data
|
|
|
@10569
|
16 years |
vboxsync |
Expose cpuid 2-5 minus dangerous bits.
|
|
|
@10567
|
16 years |
vboxsync |
Expose cpuid 0x80000007 (AMD - Advanced Power Management (TSC …
|
|
|
@10566
|
16 years |
vboxsync |
Comment
|
|
|
@10542
|
16 years |
vboxsync |
Go directly to the halted state when encountering a hlt instruction …
|
|
|
@10538
|
16 years |
vboxsync |
Fixed ring 3 mmio handling (unused previously).
|
|
|
@10537
|
16 years |
vboxsync |
Updated HWACCMDumpRegs
|
|
|
@10523
|
16 years |
vboxsync |
Backed out CPL change; fixes ACP2 installation regression for VT-x.
|
|
|
@10520
|
16 years |
vboxsync |
return docs.
|
|
|
@10513
|
16 years |
vboxsync |
Dropped the padding.
|
|
|
@10510
|
16 years |
vboxsync |
Release build fix
|
|
|
@10509
|
16 years |
vboxsync |
And again
|
|
|
@10508
|
16 years |
vboxsync |
Stupid compiler
|
|
|
@10507
|
16 years |
vboxsync |
Fixed release build problem
|
|
|
@10506
|
16 years |
vboxsync |
Assertion
|
|
|
@10505
|
16 years |
vboxsync |
Easier to grep for
|
|
|
@10504
|
16 years |
vboxsync |
Don't violate my own rules…
|
|
|
@10503
|
16 years |
vboxsync |
More logging
|
|
|
@10502
|
16 years |
vboxsync |
Take precautions for being rescheduled to a different cpu due to long …
|
|
|
@10500
|
16 years |
vboxsync |
Clarified comment
|
|
|
@10499
|
16 years |
vboxsync |
Another paranoid assertion.
|
|
|
@10498
|
16 years |
vboxsync |
Added warning
|
|
|
@10497
|
16 years |
vboxsync |
Another edge case where we need to flush the TLB.
|
|
|
@10496
|
16 years |
vboxsync |
Attempt 2
|
|
|
@10495
|
16 years |
vboxsync |
AssertCR3 fix for AMD64 paging
|
|
|
@10494
|
16 years |
vboxsync |
Fixed ring 3 AssertCR3 handler init.
|
|
|
@10493
|
16 years |
vboxsync |
Added .pgmassertcr3 debugger command.
|
|
|
@10492
|
16 years |
vboxsync |
Added PDMApicHasPendingIrq.
|
|
|
@10491
|
16 years |
vboxsync |
Logging
|
|
|
@10489
|
16 years |
vboxsync |
AMD-V: Always flush the TLB the first time a cpu is used.
|
|
|
@10480
|
16 years |
vboxsync |
Must monitor CR8 writes. (for now)
|
|
|
@10473
|
16 years |
vboxsync |
MMIO instruction emulation for OR, BT and XOR added.
|
|
|
@10471
|
16 years |
vboxsync |
warning
|
|
|
@10466
|
16 years |
vboxsync |
Write back cached TPR
|
|
|
@10465
|
16 years |
vboxsync |
Cleaned up
|
|
|
@10464
|
16 years |
vboxsync |
More assertions
|
|
|
@10463
|
16 years |
vboxsync |
Use the TPR threshold feature.
|
|
|
@10458
|
16 years |
vboxsync |
TPR & interrupt dispatch updates.
|
|
|
@10450
|
16 years |
vboxsync |
Added VMMGetSvnRev() (exported) and changed VMMR0Init and VMMGCInit …
|
|
|
@10436
|
16 years |
vboxsync |
Restore pVM->pgm.s.GCPhysCR3.
|
|
|
@10411
|
16 years |
vboxsync |
Missing change
|
|
|
@10410
|
16 years |
vboxsync |
Introduced VM_FF_REM_HANDLER_NOTIFY action flag to replay the handler …
|
|
|
@10409
|
16 years |
vboxsync |
Backed out part of the previous changeset: breaks the saved state.
|
|
|
@10408
|
16 years |
vboxsync |
Increase number of queued rem handler notifications. Flush them on …
|
|
|
@10405
|
16 years |
vboxsync |
Treat pages as reused when changing at least 0x40 qwords with rep …
|
|
|
@10404
|
16 years |
vboxsync |
Compile fix
|
|
|
@10403
|
16 years |
vboxsync |
REX implies 64 bits mode.
|
|
|
@10402
|
16 years |
vboxsync |
REX and REP prefixes must be set for movsq/stosq check.
|
|
|
@10401
|
16 years |
vboxsync |
Detect page reuse by rep movsq.
|
|
|
@10398
|
16 years |
vboxsync |
Exit the guest paging mode before the pgm pool gets reset.
|
|
|
@10397
|
16 years |
vboxsync |
Wrong assertions and order.
|
|
|
@10382
|
16 years |
vboxsync |
Refuse huge (>= _4G) REP prefixed transfers.
|
|
|
@10381
|
16 years |
vboxsync |
Updates for 64 bits mmio.
|
|
|
@10379
|
16 years |
vboxsync |
MMIO: missing changes for 64 bits mode.
|
|
|
@10368
|
16 years |
vboxsync |
Check presence of 2nd shadow pt entry too of course.
|
|
|
@10365
|
16 years |
vboxsync |
pCpu can be NULL.
|
|
|
@10364
|
16 years |
vboxsync |
Cleaned up
|
|
|
@10363
|
16 years |
vboxsync |
Correction
|
|
|
@10362
|
16 years |
vboxsync |
More verbose assertion
|
|
|
@10360
|
16 years |
vboxsync |
Removed the same assertion as before in the AMD-V code.
|
|
|
@10359
|
16 years |
vboxsync |
Removed obsolete HWACCM_CHANGED_GUEST_CR8
|
|
|
@10358
|
16 years |
vboxsync |
Implemented cr8 reading (PDMApicGetTPR).
|
|
|
@10357
|
16 years |
vboxsync |
Flush the recompiler's TLB when our invlpg replay array overflows.
|
|
|
@10356
|
16 years |
vboxsync |
Safety precaution
|
|
|
@10355
|
16 years |
vboxsync |
TPR updates
|
|
|
@10354
|
16 years |
vboxsync |
Extra assertion
|
|
|
@10353
|
16 years |
vboxsync |
TPR caching for VT-x. Removed the CR8 register from CPUMCTX.
|
|
|
@10343
|
16 years |
vboxsync |
Logging update
|
|
|
@10342
|
16 years |
vboxsync |
Clear old cr3 values before attempting to allocate a new page from our …
|
|
|
@10340
|
16 years |
vboxsync |
Pool flush handling updates
|
|
|
@10336
|
16 years |
vboxsync |
Corrections for rc handling.
|
|
|
@10334
|
16 years |
vboxsync |
Stosq case for clearing pages.
|
|
|
@10331
|
16 years |
vboxsync |
Removed the assertion completely.
|
|
|
@10330
|
16 years |
vboxsync |
Wrong assertion. Due to ring 3 far jumps the assertion condition can …
|
|
|
@10326
|
16 years |
vboxsync |
Handle the VERR_PGM_POOL_FLUSHED return code properly.
|
|
|
@10324
|
16 years |
vboxsync |
Too strict
|
|
|
@10323
|
16 years |
vboxsync |
Clear the shadow page table entries whenever the guest modifies its …
|
|
|
@10321
|
16 years |
vboxsync |
Deal with pool flushes directly when possible.
|
|
|
@10320
|
16 years |
vboxsync |
Rearranged code to deal with pgm pool tasks during SyncCR3.
|
|
|
@10319
|
16 years |
vboxsync |
pgmPoolClearAll can be executed in ring 0.
|
|
|
@10318
|
16 years |
vboxsync |
There are no virtual handlers in nested paging mode.
|
|
|
@10317
|
16 years |
vboxsync |
SyncCR3 change for nested paging to deal with pool flushes.
|
|
|
@10315
|
16 years |
vboxsync |
Don't dump the guru meditation to stderr for me
|
|
|
@10314
|
16 years |
vboxsync |
More logging
|
|
|
@10301
|
16 years |
vboxsync |
Wrong place for the assertion
|
|
|
@10300
|
16 years |
vboxsync |
Allow PGMMODE_PAE_NX with VT-x and AMD-V.
|
|
|
@10299
|
16 years |
vboxsync |
Force a TLB flush on a mode switch too.
|
|
|
@10297
|
16 years |
vboxsync |
More assertions.
|
|
|
@10290
|
16 years |
vboxsync |
Enable 64 bits guest support.
|
|
|
@10289
|
16 years |
vboxsync |
Expose X86_CPUID_AMD_FEATURE_EDX_MCA & X86_CPUID_AMD_FEATURE_EDX_MTRR …
|
|
|