Changes between Version 4 and Version 5 of Ticket #10532, comment 6
- Timestamp:
- May 10, 2012 12:30:12 PM (13 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
Ticket #10532, comment 6
v4 v5 30 30 12. The TSS state is loaded into the processor. This includes the LDTR register, the PDBR (control register CR3), the EFLAGS register, the EIP register, the generalpurpose registers, and the segment selectors. A fault during the load of this state may corrupt architectural state. 31 31 32 So, same [https://bugs.launchpad.net/qemu/+bug/996798 bug] is finded in [https://raw.github.com/qemu/QEMU/v1.0/target-i386/op_helper.c QEMU code].32 So, same [https://bugs.launchpad.net/qemu/+bug/996798 bug] was found in [https://raw.github.com/qemu/QEMU/v1.0/target-i386/op_helper.c QEMU code].
