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Last change
on this file since 54924 was 54496, checked in by vboxsync, 10 years ago |
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VMMSwitcher: test code for disabling the Extended LVT APIC registers on newer AMD boxes
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Author Date Id Revision
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File size:
1.3 KB
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| 1 | %ifndef ___VBox_apic_h
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| 2 | %define ___VBox_apic_h
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| 3 | %define APIC_REG_VERSION 0x0030
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| 4 | %define APIC_REG_VERSION_GET_VER(u32) (u32 & 0xff)
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| 5 | %define APIC_REG_VERSION_GET_MAX_LVT(u32) ((u32 & 0xff0000) >> 16)
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| 6 | %define APIC_REG_LVT_LINT0 0x0350
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| 7 | %define APIC_REG_LVT_LINT1 0x0360
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| 8 | %define APIC_REG_LVT_ERR 0x0370
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| 9 | %define APIC_REG_LVT_PC 0x0340
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| 10 | %define APIC_REG_LVT_THMR 0x0330
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| 11 | %define APIC_REG_LVT_CMCI 0x02F0
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| 12 | %define APIC_REG_EILVT0 0x0500
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| 13 | %define APIC_REG_EILVT1 0x0510
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| 14 | %define APIC_REG_EILVT2 0x0520
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| 15 | %define APIC_REG_EILVT3 0x0530
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| 16 | %define APIC_REG_LVT_MODE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
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| 17 | %define APIC_REG_LVT_MODE_FIXED 0
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| 18 | %define APIC_REG_LVT_MODE_NMI RT_BIT(10)
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| 19 | %define APIC_REG_LVT_MODE_EXTINT (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
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| 20 | %define APIC_REG_LVT_PIN_POLARIY RT_BIT(13)
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| 21 | %define APIC_REG_LVT_REMOTE_IRR RT_BIT(14)
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| 22 | %define APIC_REG_LVT_LEVEL_TRIGGER RT_BIT(15)
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| 23 | %define APIC_REG_LVT_MASKED RT_BIT(16)
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| 24 | %ifdef ___iprt_asm_amd64_x86_h
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| 25 | %endif
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| 26 | %endif
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