VirtualBox

source: vbox/trunk/include/VBox/cpum.h@ 7695

Last change on this file since 7695 was 7695, checked in by vboxsync, 17 years ago

Added system MSRs to the CPUMCTX structure.
Sync them in REM as well.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 27.4 KB
Line 
1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_cpum_h
27#define ___VBox_cpum_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/x86.h>
32
33
34__BEGIN_DECLS
35
36/** @defgroup grp_cpum The CPU Monitor(/Manager) API
37 * @{
38 */
39
40/**
41 * Selector hidden registers.
42 */
43typedef struct CPUMSELREGHID
44{
45 /** Base register. */
46 uint32_t u32Base;
47 /** Limit (expanded). */
48 uint32_t u32Limit;
49 /** Flags.
50 * This is the high 32-bit word of the descriptor entry.
51 * Only the flags, dpl and type are used. */
52 X86DESCATTR Attr;
53} CPUMSELREGHID;
54
55
56/**
57 * The sysenter register set.
58 */
59typedef struct CPUMSYSENTER
60{
61 /** Ring 0 cs.
62 * This value + 8 is the Ring 0 ss.
63 * This value + 16 is the Ring 3 cs.
64 * This value + 24 is the Ring 3 ss.
65 */
66 uint64_t cs;
67 /** Ring 0 eip. */
68 uint64_t eip;
69 /** Ring 0 esp. */
70 uint64_t esp;
71} CPUMSYSENTER;
72
73
74/**
75 * CPU context core.
76 */
77#pragma pack(1)
78typedef struct CPUMCTXCORE
79{
80 union
81 {
82 uint32_t edi;
83 uint64_t rdi;
84 };
85 union
86 {
87 uint32_t esi;
88 uint64_t rsi;
89 };
90 union
91 {
92 uint32_t ebp;
93 uint64_t rbp;
94 };
95 union
96 {
97 uint32_t eax;
98 uint64_t rax;
99 };
100 union
101 {
102 uint32_t ebx;
103 uint64_t rbx;
104 };
105 union
106 {
107 uint32_t edx;
108 uint64_t rdx;
109 };
110 union
111 {
112 uint32_t ecx;
113 uint64_t rcx;
114 };
115 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
116 uint32_t esp;
117 RTSEL ss;
118 RTSEL ssPadding;
119 /* Note: no overlap with esp here. */
120 uint64_t rsp;
121
122 RTSEL gs;
123 RTSEL gsPadding;
124 RTSEL fs;
125 RTSEL fsPadding;
126 RTSEL es;
127 RTSEL esPadding;
128 RTSEL ds;
129 RTSEL dsPadding;
130 RTSEL cs;
131 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
132
133 union
134 {
135 X86EFLAGS eflags;
136 X86RFLAGS rflags;
137 };
138 union
139 {
140 uint32_t eip;
141 uint64_t rip;
142 };
143
144 uint64_t r8;
145 uint64_t r9;
146 uint64_t r10;
147 uint64_t r11;
148 uint64_t r12;
149 uint64_t r13;
150 uint64_t r14;
151 uint64_t r15;
152
153 /** Hidden selector registers.
154 * @{ */
155 CPUMSELREGHID esHid;
156 CPUMSELREGHID csHid;
157 CPUMSELREGHID ssHid;
158 CPUMSELREGHID dsHid;
159 CPUMSELREGHID fsHid;
160 CPUMSELREGHID gsHid;
161 /** @} */
162
163} CPUMCTXCORE;
164#pragma pack()
165
166
167/**
168 * CPU context.
169 */
170#pragma pack(1)
171typedef struct CPUMCTX
172{
173 /** FPU state. (16-byte alignment)
174 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
175 * actual format or convert it (waste of time). */
176 X86FXSTATE fpu;
177
178 /** CPUMCTXCORE Part.
179 * @{ */
180 union
181 {
182 uint32_t edi;
183 uint64_t rdi;
184 };
185 union
186 {
187 uint32_t esi;
188 uint64_t rsi;
189 };
190 union
191 {
192 uint32_t ebp;
193 uint64_t rbp;
194 };
195 union
196 {
197 uint32_t eax;
198 uint64_t rax;
199 };
200 union
201 {
202 uint32_t ebx;
203 uint64_t rbx;
204 };
205 union
206 {
207 uint32_t edx;
208 uint64_t rdx;
209 };
210 union
211 {
212 uint32_t ecx;
213 uint64_t rcx;
214 };
215 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
216 uint32_t esp;
217 RTSEL ss;
218 RTSEL ssPadding;
219 /* Note: no overlap with esp here. */
220 uint64_t rsp;
221
222 RTSEL gs;
223 RTSEL gsPadding;
224 RTSEL fs;
225 RTSEL fsPadding;
226 RTSEL es;
227 RTSEL esPadding;
228 RTSEL ds;
229 RTSEL dsPadding;
230 RTSEL cs;
231 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
232
233 union
234 {
235 X86EFLAGS eflags;
236 X86RFLAGS rflags;
237 };
238 union
239 {
240 uint32_t eip;
241 uint64_t rip;
242 };
243
244 uint64_t r8;
245 uint64_t r9;
246 uint64_t r10;
247 uint64_t r11;
248 uint64_t r12;
249 uint64_t r13;
250 uint64_t r14;
251 uint64_t r15;
252
253 /** Hidden selector registers.
254 * @{ */
255 CPUMSELREGHID esHid;
256 CPUMSELREGHID csHid;
257 CPUMSELREGHID ssHid;
258 CPUMSELREGHID dsHid;
259 CPUMSELREGHID fsHid;
260 CPUMSELREGHID gsHid;
261 /** @} */
262
263 /** @} */
264
265 /** Control registers.
266 * @{ */
267 uint64_t cr0;
268 uint64_t cr2;
269 uint64_t cr3;
270 uint64_t cr4;
271 uint64_t cr8;
272 /** @} */
273
274 /** Debug registers.
275 * @{ */
276 uint64_t dr0;
277 uint64_t dr1;
278 uint64_t dr2;
279 uint64_t dr3;
280 uint64_t dr4; /**< @todo remove dr4 and dr5. */
281 uint64_t dr5;
282 uint64_t dr6;
283 uint64_t dr7;
284 /* DR8-15 are currently not supported */
285 /** @} */
286
287 /** Global Descriptor Table register. */
288 VBOXGDTR gdtr;
289 uint16_t gdtrPadding;
290 uint32_t gdtrPadding64;/** @todo fix this hack */
291 /** Interrupt Descriptor Table register. */
292 VBOXIDTR idtr;
293 uint16_t idtrPadding;
294 uint32_t idtrPadding64;/** @todo fix this hack */
295 /** The task register.
296 * Only the guest context uses all the members. */
297 RTSEL ldtr;
298 RTSEL ldtrPadding;
299 /** The task register.
300 * Only the guest context uses all the members. */
301 RTSEL tr;
302 RTSEL trPadding;
303
304 /** The sysenter msr registers.
305 * This member is not used by the hypervisor context. */
306 CPUMSYSENTER SysEnter;
307
308 /** System MSRs.
309 * @{ */
310 uint64_t msrEFER;
311 uint64_t msrSTAR;
312 uint64_t msrPAT;
313 uint64_t msrLSTAR;
314 uint64_t msrCSTAR;
315 uint64_t msrSFMASK;
316 uint64_t msrFSBASE;
317 uint64_t msrGSBASE;
318 uint64_t msrKERNELGSBASE;
319 /** @} */
320
321 /** Hidden selector registers.
322 * @{ */
323 CPUMSELREGHID ldtrHid;
324 CPUMSELREGHID trHid;
325 /** @} */
326
327 /* padding to get 32byte aligned size */
328 uint32_t padding[2];
329} CPUMCTX;
330#pragma pack()
331
332/**
333 * Gets the CPUMCTXCORE part of a CPUMCTX.
334 */
335#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
336
337/**
338 * The register set returned by a CPUID operation.
339 */
340typedef struct CPUMCPUID
341{
342 uint32_t eax;
343 uint32_t ebx;
344 uint32_t ecx;
345 uint32_t edx;
346} CPUMCPUID;
347/** Pointer to a CPUID leaf. */
348typedef CPUMCPUID *PCPUMCPUID;
349/** Pointer to a const CPUID leaf. */
350typedef const CPUMCPUID *PCCPUMCPUID;
351
352/**
353 * CPUID feature to set or clear.
354 */
355typedef enum CPUMCPUIDFEATURE
356{
357 CPUMCPUIDFEATURE_INVALID = 0,
358 /** The APIC feature bit. (Std+Ext) */
359 CPUMCPUIDFEATURE_APIC,
360 /** The sysenter/sysexit feature bit. (Std+Ext) */
361 CPUMCPUIDFEATURE_SEP,
362 /** The PAE feature bit. (Std+Ext) */
363 CPUMCPUIDFEATURE_PAE,
364 /** The LONG MODE feature bit. (Ext) */
365 CPUMCPUIDFEATURE_LONG_MODE
366} CPUMCPUIDFEATURE;
367
368
369/** @name Guest Register Getters.
370 * @{ */
371CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
372CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
373CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
374CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
375CPUMDECL(uint32_t) CPUMGetGuestCR0(PVM pVM);
376CPUMDECL(uint32_t) CPUMGetGuestCR2(PVM pVM);
377CPUMDECL(uint32_t) CPUMGetGuestCR3(PVM pVM);
378CPUMDECL(uint32_t) CPUMGetGuestCR4(PVM pVM);
379CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
380CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
381CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
382CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
383CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
384CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
385CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
386CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
387CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
388CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
389CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
390CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
391CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
392CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
393CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
394CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
395CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
396CPUMDECL(RTUINTREG) CPUMGetGuestDR0(PVM pVM);
397CPUMDECL(RTUINTREG) CPUMGetGuestDR1(PVM pVM);
398CPUMDECL(RTUINTREG) CPUMGetGuestDR2(PVM pVM);
399CPUMDECL(RTUINTREG) CPUMGetGuestDR3(PVM pVM);
400CPUMDECL(RTUINTREG) CPUMGetGuestDR6(PVM pVM);
401CPUMDECL(RTUINTREG) CPUMGetGuestDR7(PVM pVM);
402CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
403CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
404CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
405CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
406CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM);
407CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
408CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
409CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
410CPUMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
411CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
412/** @} */
413
414/** @name Guest Register Setters.
415 * @{ */
416CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
417CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
418CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
419CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
420CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint32_t cr0);
421CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint32_t cr2);
422CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint32_t cr3);
423CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint32_t cr4);
424CPUMDECL(int) CPUMSetGuestCRx(PVM pVM, uint32_t iReg, uint32_t Value);
425CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, RTGCUINTREG uDr0);
426CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, RTGCUINTREG uDr1);
427CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, RTGCUINTREG uDr2);
428CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, RTGCUINTREG uDr3);
429CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, RTGCUINTREG uDr6);
430CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, RTGCUINTREG uDr7);
431CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint32_t Value);
432CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
433CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
434CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
435CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
436CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
437CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
438CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
439CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
440CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
441CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
442CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
443CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
444CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
445CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
446CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
447CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
448CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
449CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
450CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
451/** @} */
452
453/** @name Misc Guest Predicate Functions.
454 * @{ */
455
456/**
457 * Tests if the guest is running in real mode or not.
458 *
459 * @returns true if in real mode, otherwise false.
460 * @param pVM The VM handle.
461 */
462DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
463{
464 return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
465}
466
467/**
468 * Tests if the guest is running in protected or not.
469 *
470 * @returns true if in protected mode, otherwise false.
471 * @param pVM The VM handle.
472 */
473DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
474{
475 return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
476}
477
478/**
479 * Tests if the guest is running in paged protected or not.
480 *
481 * @returns true if in paged protected mode, otherwise false.
482 * @param pVM The VM handle.
483 */
484DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
485{
486 return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
487}
488
489/**
490 * Tests if the guest is running in paged protected or not.
491 *
492 * @returns true if in paged protected mode, otherwise false.
493 * @param pVM The VM handle.
494 */
495CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
496
497/**
498 * Tests if the guest is running in paged protected or not.
499 *
500 * @returns true if in paged protected mode, otherwise false.
501 * @param pVM The VM handle.
502 */
503CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
504
505/**
506 * Tests if the guest is running in paged protected or not.
507 *
508 * @returns true if in paged protected mode, otherwise false.
509 * @param pVM The VM handle.
510 */
511CPUMDECL(bool) CPUMIsGuestIn64BitCode(PVM pVM);
512
513/** @} */
514
515
516
517/** @name Hypervisor Register Getters.
518 * @{ */
519CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
520CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
521CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
522CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
523CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
524CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
525#if 0 /* these are not correct. */
526CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
527CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
528CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
529CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
530#endif
531/** This register is only saved on fatal traps. */
532CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
533CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
534/** This register is only saved on fatal traps. */
535CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
536/** This register is only saved on fatal traps. */
537CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
538CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
539CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
540CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
541CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
542CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
543CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
544CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
545CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
546CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
547CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
548CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
549CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
550CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
551CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
552CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
553CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
554/** @} */
555
556/** @name Hypervisor Register Setters.
557 * @{ */
558CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
559CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
560CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
561CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
562CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
563CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
564CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
565CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
566CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
567CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
568CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
569CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
570CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
571CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
572CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
573CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
574CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
575CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
576CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
577CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
578CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
579CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
580/** @} */
581
582CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
583
584/**
585 * Sets or resets an alternative hypervisor context core.
586 *
587 * This is called when we get a hypervisor trap set switch the context
588 * core with the trap frame on the stack. It is called again to reset
589 * back to the default context core when resuming hypervisor execution.
590 *
591 * @param pVM The VM handle.
592 * @param pCtxCore Pointer to the alternative context core or NULL
593 * to go back to the default context core.
594 */
595CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
596
597
598/**
599 * Queries the pointer to the internal CPUMCTX structure
600 *
601 * @returns VBox status code.
602 * @param pVM Handle to the virtual machine.
603 * @param ppCtx Receives the CPUMCTX pointer when successful.
604 */
605CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
606
607/**
608 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
609 *
610 * @returns VBox status code.
611 * @param pVM Handle to the virtual machine.
612 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
613 */
614CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
615
616
617/**
618 * Gets the pointer to the internal CPUMCTXCORE structure.
619 * This is only for reading in order to save a few calls.
620 *
621 * @param pVM Handle to the virtual machine.
622 */
623CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
624
625/**
626 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
627 * This is only for reading in order to save a few calls.
628 *
629 * @param pVM Handle to the virtual machine.
630 */
631CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
632
633/**
634 * Sets the guest context core registers.
635 *
636 * @param pVM Handle to the virtual machine.
637 * @param pCtxCore The new context core values.
638 */
639CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
640
641
642/**
643 * Transforms the guest CPU state to raw-ring mode.
644 *
645 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
646 *
647 * @returns VBox status. (recompiler failure)
648 * @param pVM VM handle.
649 * @param pCtxCore The context core (for trap usage).
650 * @see @ref pg_raw
651 */
652CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
653
654/**
655 * Transforms the guest CPU state from raw-ring mode to correct values.
656 *
657 * This function will change any selector registers with DPL=1 to DPL=0.
658 *
659 * @returns Adjusted rc.
660 * @param pVM VM handle.
661 * @param rc Raw mode return code
662 * @param pCtxCore The context core (for trap usage).
663 * @see @ref pg_raw
664 */
665CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
666
667/**
668 * Gets the EFLAGS while we're in raw-mode.
669 *
670 * @returns The eflags.
671 * @param pVM The VM handle.
672 * @param pCtxCore The context core.
673 */
674CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
675
676/**
677 * Updates the EFLAGS while we're in raw-mode.
678 *
679 * @param pVM The VM handle.
680 * @param pCtxCore The context core.
681 * @param eflags The new EFLAGS value.
682 */
683CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
684
685/**
686 * Lazily sync in the FPU/XMM state
687 *
688 * This function will change any selector registers with DPL=1 to DPL=0.
689 *
690 * @returns VBox status code.
691 * @param pVM VM handle.
692 */
693CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
694
695
696/**
697 * Restore host FPU/XMM state
698 *
699 * @returns VBox status code.
700 * @param pVM VM handle.
701 */
702CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
703
704/** @name Changed flags
705 * These flags are used to keep track of which important register that
706 * have been changed since last they were reset. The only one allowed
707 * to clear them is REM!
708 * @{
709 */
710#define CPUM_CHANGED_FPU_REM RT_BIT(0)
711#define CPUM_CHANGED_CR0 RT_BIT(1)
712#define CPUM_CHANGED_CR4 RT_BIT(2)
713#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
714#define CPUM_CHANGED_CR3 RT_BIT(4)
715#define CPUM_CHANGED_GDTR RT_BIT(5)
716#define CPUM_CHANGED_IDTR RT_BIT(6)
717#define CPUM_CHANGED_LDTR RT_BIT(7)
718#define CPUM_CHANGED_TR RT_BIT(8)
719#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
720#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
721/** @} */
722
723/**
724 * Gets and resets the changed flags (CPUM_CHANGED_*).
725 *
726 * @returns The changed flags.
727 * @param pVM VM handle.
728 */
729CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
730
731/**
732 * Sets the specified changed flags (CPUM_CHANGED_*).
733 *
734 * @param pVM The VM handle.
735 */
736CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
737
738/**
739 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
740 * @returns true if supported.
741 * @returns false if not supported.
742 * @param pVM The VM handle.
743 */
744CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
745
746/**
747 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
748 * @returns true if used.
749 * @returns false if not used.
750 * @param pVM The VM handle.
751 */
752CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
753
754/**
755 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
756 * @returns true if used.
757 * @returns false if not used.
758 * @param pVM The VM handle.
759 */
760CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
761
762/**
763 * Checks if we activated the FPU/XMM state of the guest OS
764 * @returns true if we did.
765 * @returns false if not.
766 * @param pVM The VM handle.
767 */
768CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
769
770/**
771 * Deactivate the FPU/XMM state of the guest OS
772 * @param pVM The VM handle.
773 */
774CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
775
776
777/**
778 * Checks if the hidden selector registers are valid
779 * @returns true if they are.
780 * @returns false if not.
781 * @param pVM The VM handle.
782 */
783CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
784
785/**
786 * Checks if the hidden selector registers are valid
787 * @param pVM The VM handle.
788 * @param fValid Valid or not
789 */
790CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
791
792/**
793 * Get the current privilege level of the guest.
794 *
795 * @returns cpl
796 * @param pVM VM Handle.
797 * @param pRegFrame Trap register frame.
798 */
799CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
800
801/**
802 * CPU modes.
803 */
804typedef enum CPUMMODE
805{
806 /** The usual invalid zero entry. */
807 CPUMMODE_INVALID = 0,
808 /** Real mode. */
809 CPUMMODE_REAL,
810 /** Protected mode (32-bit). */
811 CPUMMODE_PROTECTED,
812 /** Long mode (64-bit). */
813 CPUMMODE_LONG
814} CPUMMODE;
815
816/**
817 * Gets the current guest CPU mode.
818 *
819 * If paging mode is what you need, check out PGMGetGuestMode().
820 *
821 * @returns The CPU mode.
822 * @param pVM The VM handle.
823 */
824CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
825
826
827#ifdef IN_RING3
828/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
829 * @ingroup grp_cpum
830 * @{
831 */
832
833/**
834 * Initializes the CPUM.
835 *
836 * @returns VBox status code.
837 * @param pVM The VM to operate on.
838 */
839CPUMR3DECL(int) CPUMR3Init(PVM pVM);
840
841/**
842 * Applies relocations to data and code managed by this
843 * component. This function will be called at init and
844 * whenever the VMM need to relocate it self inside the GC.
845 *
846 * The CPUM will update the addresses used by the switcher.
847 *
848 * @param pVM The VM.
849 */
850CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
851
852/**
853 * Terminates the CPUM.
854 *
855 * Termination means cleaning up and freeing all resources,
856 * the VM it self is at this point powered off or suspended.
857 *
858 * @returns VBox status code.
859 * @param pVM The VM to operate on.
860 */
861CPUMR3DECL(int) CPUMR3Term(PVM pVM);
862
863/**
864 * Resets the CPU.
865 *
866 * @param pVM The VM handle.
867 */
868CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
869
870/**
871 * Queries the pointer to the internal CPUMCTX structure
872 *
873 * @returns VBox status code.
874 * @param pVM Handle to the virtual machine.
875 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
876 */
877CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx);
878
879
880#ifdef DEBUG
881/**
882 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
883 *
884 * @internal
885 */
886CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
887#endif
888
889/**
890 * API for controlling a few of the CPU features found in CR4.
891 *
892 * Currently only X86_CR4_TSD is accepted as input.
893 *
894 * @returns VBox status code.
895 *
896 * @param pVM The VM handle.
897 * @param fOr The CR4 OR mask.
898 * @param fAnd The CR4 AND mask.
899 */
900CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
901
902/** @} */
903#endif
904
905#ifdef IN_GC
906/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
907 * @ingroup grp_cpum
908 * @{
909 */
910
911/**
912 * Calls a guest trap/interrupt handler directly
913 * Assumes a trap stack frame has already been setup on the guest's stack!
914 *
915 * @param pRegFrame Original trap/interrupt context
916 * @param selCS Code selector of handler
917 * @param pHandler GC virtual address of handler
918 * @param eflags Callee's EFLAGS
919 * @param selSS Stack selector for handler
920 * @param pEsp Stack address for handler
921 *
922 * This function does not return!
923 *
924 */
925CPUMGCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
926
927/**
928 * Performs an iret to V86 code
929 * Assumes a trap stack frame has already been setup on the guest's stack!
930 *
931 * @param pRegFrame Original trap/interrupt context
932 *
933 * This function does not return!
934 */
935CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
936
937/** @} */
938#endif
939
940#ifdef IN_RING0
941/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
942 * @ingroup grp_cpum
943 * @{
944 */
945
946/**
947 * Does Ring-0 CPUM initialization.
948 *
949 * This is mainly to check that the Host CPU mode is compatible
950 * with VBox.
951 *
952 * @returns VBox status code.
953 * @param pVM The VM to operate on.
954 */
955CPUMR0DECL(int) CPUMR0Init(PVM pVM);
956
957/** @} */
958#endif
959
960/** @} */
961__END_DECLS
962
963
964#endif
965
966
967
968
969
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