Changeset 7695 in vbox

Timestamp:

Apr 2, 2008 12:17:19 PM (17 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

29222

Message:

Added system MSRs to the CPUMCTX structure.
Sync them in REM as well.

Location:

trunk

Files:

• include/VBox/cpum.h (modified) (2 diffs)
• include/VBox/cpum.mac (modified) (2 diffs)
• include/VBox/vm.h (modified) (1 diff)
• include/VBox/vm.mac (modified) (1 diff)
• include/VBox/x86.h (modified) (1 diff)
• src/VBox/VMM/CPUMInternal.mac (modified) (5 diffs)
• src/recompiler/VBoxRecompiler.c (modified) (2 diffs)

trunk/include/VBox/cpum.h

@@ -306 +306 @@
     CPUMSYSENTER    SysEnter;
 
+    /** System MSRs.
+     * @{ */
+    uint64_t        msrEFER;
+    uint64_t        msrSTAR;
+    uint64_t        msrPAT;
+    uint64_t        msrLSTAR;
+    uint64_t        msrCSTAR;
+    uint64_t        msrSFMASK;
+    uint64_t        msrFSBASE;
+    uint64_t        msrGSBASE;
+    uint64_t        msrKERNELGSBASE;
+    /** @} */
+
     /** Hidden selector registers.
      * @{ */
@@ -313 +326 @@
 
     /* padding to get 32byte aligned size */
-    uint32_t        padding[4];
+    uint32_t        padding[2];
 } CPUMCTX;
 #pragma pack()

trunk/include/VBox/cpum.mac

@@ -185 +185 @@
     .SysEnter.esp       resb    8
 
+    .msrEFER            resb    8
+    .msrSTAR            resb    8
+    .msrPAT             resb    8
+    .msrLSTAR           resb    8
+    .msrCSTAR           resb    8
+    .msrSFMASK          resb    8
+    .msrFSBASE          resb    8
+    .msrGSBASE          resb    8
+    .msrKERNELGSBASE    resb    8
+
     .ldtrHid.u32Base    resd    1
     .ldtrHid.u32Limit   resd    1
@@ -194 +204 @@
 
     ; padding
-    .padding            resd    4
+    .padding            resd    2
 endstruc
 

trunk/include/VBox/vm.h

@@ -392 +392 @@
         struct CPUM s;
 #endif
-        char        padding[4128];      /* multiple of 32 */
+        char        padding[4384];      /* multiple of 32 */
     } cpum;
 

trunk/include/VBox/vm.mac

@@ -88 +88 @@
 
     alignb 32
-    .cpum                 resb 4128
+    .cpum                 resb 4384
     .vmm                  resb 1024
 

trunk/include/VBox/x86.h

@@ -713 +713 @@
 #endif
 
+/* Page Attribute Table. */
+#define IA32_CR_PAT                         0x277
+
 /** Basic VMX information. */
 #define MSR_IA32_VMX_BASIC_INFO             0x480

trunk/src/VBox/VMM/CPUMInternal.mac

@@ -256 +256 @@
     .Hyper.SysEnter.esp       resb    8
 
+    .Hyper.msrEFER            resb    8
+    .Hyper.msrSTAR            resb    8
+    .Hyper.msrPAT             resb    8
+    .Hyper.msrLSTAR           resb    8
+    .Hyper.msrCSTAR           resb    8
+    .Hyper.msrSFMASK          resb    8
+    .Hyper.msrFSBASE          resb    8
+    .Hyper.msrGSBASE          resb    8
+    .Hyper.msrKERNELGSBASE    resb    8
+
     .Hyper.ldtrHid.u32Base    resd    1
     .Hyper.ldtrHid.u32Limit   resd    1
@@ -265 +275 @@
 
     ; padding
-    .Hyper.padding            resd    4
+    .Hyper.padding            resd    2
 
 
@@ -362 +372 @@
     .Guest.SysEnter.esp       resb    8
 
+    .Guest.msrEFER            resb    8
+    .Guest.msrSTAR            resb    8
+    .Guest.msrPAT             resb    8
+    .Guest.msrLSTAR           resb    8
+    .Guest.msrCSTAR           resb    8
+    .Guest.msrSFMASK          resb    8
+    .Guest.msrFSBASE          resb    8
+    .Guest.msrGSBASE          resb    8
+    .Guest.msrKERNELGSBASE    resb    8
+
     .Guest.ldtrHid.u32Base    resd    1
     .Guest.ldtrHid.u32Limit   resd    1
@@ -371 +391 @@
 
     ; padding
-    .Guest.padding            resd    4
+    .Guest.padding            resd    2
 
 
@@ -408 +428 @@
     .GuestCpuIdDef        resb    16
 
-    ; debug stuff...
-    .GuestEntry           resb    960
+    ; CPUMCTX debug stuff...
+    .GuestEntry           resb   1024
 
 endstruc

trunk/src/recompiler/VBoxRecompiler.c

@@ -1859 +1859 @@
     }
 
+    /* Update MSRs. */
+    pVM->rem.s.Env.efer         = pCtx->msrEFER;
+    pVM->rem.s.Env.star         = pCtx->msrSTAR;
+    pVM->rem.s.Env.pat          = pCtx->msrPAT;
+#ifdef TARGET_X86_64
+    pVM->rem.s.Env.lstar        = pCtx->msrLSTAR;
+    pVM->rem.s.Env.cstar        = pCtx->msrCSTAR;
+    pVM->rem.s.Env.fmask        = pCtx->msrSFMASK;
+    pVM->rem.s.Env.kernelgsbase = pCtx->msrKERNELGSBASE;
+#endif
+    /* Note that FS_BASE & GS_BASE are already synced; QEmu keeps them in the hidden selector registers. 
+     * So we basically assume the hidden registers are in sync with these MSRs (vt-x & amd-v). Correct??
+     */
+
     /*
      * Check for traps.
@@ -2113 +2127 @@
     pCtx->SysEnter.eip     = pVM->rem.s.Env.sysenter_eip;
     pCtx->SysEnter.esp     = pVM->rem.s.Env.sysenter_esp;
+
+    /* System MSRs. */
+    pCtx->msrEFER          = pVM->rem.s.Env.efer;
+    pCtx->msrSTAR          = pVM->rem.s.Env.star;
+    pCtx->msrPAT           = pVM->rem.s.Env.pat;
+#ifdef TARGET_X86_64
+    pCtx->msrLSTAR         = pVM->rem.s.Env.lstar;
+    pCtx->msrCSTAR         = pVM->rem.s.Env.cstar;
+    pCtx->msrSFMASK        = pVM->rem.s.Env.fmask;
+    pCtx->msrFSBASE        = pVM->rem.s.Env.segs[R_FS].base;
+    pCtx->msrGSBASE        = pVM->rem.s.Env.segs[R_GS].base;
+    pCtx->msrKERNELGSBASE  = pVM->rem.s.Env.kernelgsbase;
+#endif
 
     remR3TrapClear(pVM);