VirtualBox

source: vbox/trunk/include/VBox/pgm.h@ 9569

Last change on this file since 9569 was 9212, checked in by vboxsync, 17 years ago

Major changes for sizeof(RTGCPTR) == uint64_t.
Introduced RCPTRTYPE for pointers valid in raw mode only (RTGCPTR32).

Disabled by default. Enable by adding VBOX_WITH_64_BITS_GUESTS to your LocalConfig.kmk.
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File size: 26.0 KB
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1/** @file
2 * PGM - Page Monitor/Monitor.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_pgm_h
31#define ___VBox_pgm_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/sup.h>
36#include <VBox/vmapi.h>
37#include <VBox/x86.h>
38
39__BEGIN_DECLS
40
41/** @defgroup grp_pgm The Page Monitor/Manager API
42 * @{
43 */
44
45/** Chunk size for dynamically allocated physical memory. */
46#define PGM_DYNAMIC_CHUNK_SIZE (1*1024*1024)
47/** Shift GC physical address by 20 bits to get the offset into the pvHCChunkHC array. */
48#define PGM_DYNAMIC_CHUNK_SHIFT 20
49/** Dynamic chunk offset mask. */
50#define PGM_DYNAMIC_CHUNK_OFFSET_MASK 0xfffff
51/** Dynamic chunk base mask. */
52#define PGM_DYNAMIC_CHUNK_BASE_MASK (~(RTGCPHYS)PGM_DYNAMIC_CHUNK_OFFSET_MASK)
53
54
55/** Page flags used for PGMHyperSetPageFlags
56 * @deprecated
57 * @{ */
58#define PGMPAGE_READ 1
59#define PGMPAGE_WRITE 2
60#define PGMPAGE_USER 4
61#define PGMPAGE_SYSTEM 8
62#define PGMPAGE_NOTPRESENT 16
63/** @} */
64
65
66/**
67 * FNPGMRELOCATE callback mode.
68 */
69typedef enum PGMRELOCATECALL
70{
71 /** The callback is for checking if the suggested address is suitable. */
72 PGMRELOCATECALL_SUGGEST = 1,
73 /** The callback is for executing the relocation. */
74 PGMRELOCATECALL_RELOCATE
75} PGMRELOCATECALL;
76
77
78/**
79 * Callback function which will be called when PGM is trying to find
80 * a new location for the mapping.
81 *
82 * The callback is called in two modes, 1) the check mode and 2) the relocate mode.
83 * In 1) the callback should say if it objects to a suggested new location. If it
84 * accepts the new location, it is called again for doing it's relocation.
85 *
86 *
87 * @returns true if the location is ok.
88 * @returns false if another location should be found.
89 * @param GCPtrOld The old virtual address.
90 * @param GCPtrNew The new virtual address.
91 * @param enmMode Used to indicate the callback mode.
92 * @param pvUser User argument.
93 * @remark The return value is no a failure indicator, it's an acceptance
94 * indicator. Relocation can not fail!
95 */
96typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
97/** Pointer to a relocation callback function. */
98typedef FNPGMRELOCATE *PFNPGMRELOCATE;
99
100
101/**
102 * Physical page access handler type.
103 */
104typedef enum PGMPHYSHANDLERTYPE
105{
106 /** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
107 PGMPHYSHANDLERTYPE_MMIO = 1,
108 /** Handler all write access to a physical page range. */
109 PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
110 /** Handler all access to a physical page range. */
111 PGMPHYSHANDLERTYPE_PHYSICAL_ALL
112
113} PGMPHYSHANDLERTYPE;
114
115/**
116 * \#PF Handler callback for physical access handler ranges (MMIO among others) in GC.
117 *
118 * @returns VBox status code (appropriate for GC return).
119 * @param pVM VM Handle.
120 * @param uErrorCode CPU Error code.
121 * @param pRegFrame Trap register frame.
122 * NULL on DMA and other non CPU access.
123 * @param pvFault The fault address (cr2).
124 * @param GCPhysFault The GC physical address corresponding to pvFault.
125 * @param pvUser User argument.
126 */
127typedef DECLCALLBACK(int) FNPGMGCPHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
128/** Pointer to PGM access callback. */
129typedef FNPGMGCPHYSHANDLER *PFNPGMGCPHYSHANDLER;
130
131/**
132 * \#PF Handler callback for physical access handler ranges (MMIO among others) in R0.
133 *
134 * @returns VBox status code (appropriate for GC return).
135 * @param pVM VM Handle.
136 * @param uErrorCode CPU Error code.
137 * @param pRegFrame Trap register frame.
138 * NULL on DMA and other non CPU access.
139 * @param pvFault The fault address (cr2).
140 * @param GCPhysFault The GC physical address corresponding to pvFault.
141 * @param pvUser User argument.
142 */
143typedef DECLCALLBACK(int) FNPGMR0PHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
144/** Pointer to PGM access callback. */
145typedef FNPGMR0PHYSHANDLER *PFNPGMR0PHYSHANDLER;
146
147/**
148 * Guest Access type
149 */
150typedef enum PGMACCESSTYPE
151{
152 /** Read access. */
153 PGMACCESSTYPE_READ = 1,
154 /** Write access. */
155 PGMACCESSTYPE_WRITE
156} PGMACCESSTYPE;
157
158/**
159 * \#PF Handler callback for physical access handler ranges (MMIO among others) in HC.
160 *
161 * The handler can not raise any faults, it's mainly for monitoring write access
162 * to certain pages.
163 *
164 * @returns VINF_SUCCESS if the handler have carried out the operation.
165 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
166 * @param pVM VM Handle.
167 * @param GCPhys The physical address the guest is writing to.
168 * @param pvPhys The HC mapping of that address.
169 * @param pvBuf What the guest is reading/writing.
170 * @param cbBuf How much it's reading/writing.
171 * @param enmAccessType The access type.
172 * @param pvUser User argument.
173 */
174typedef DECLCALLBACK(int) FNPGMR3PHYSHANDLER(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
175/** Pointer to PGM access callback. */
176typedef FNPGMR3PHYSHANDLER *PFNPGMR3PHYSHANDLER;
177
178
179/**
180 * Virtual access handler type.
181 */
182typedef enum PGMVIRTHANDLERTYPE
183{
184 /** Write access handled. */
185 PGMVIRTHANDLERTYPE_WRITE = 1,
186 /** All access handled. */
187 PGMVIRTHANDLERTYPE_ALL,
188 /** Hypervisor write access handled.
189 * This is used to catch the guest trying to write to LDT, TSS and any other
190 * system structure which the brain dead intel guys let unprivilegde code find. */
191 PGMVIRTHANDLERTYPE_HYPERVISOR
192} PGMVIRTHANDLERTYPE;
193
194/**
195 * \#PF Handler callback for virtual access handler ranges.
196 *
197 * Important to realize that a physical page in a range can have aliases, and
198 * for ALL and WRITE handlers these will also trigger.
199 *
200 * @returns VBox status code (appropriate for GC return).
201 * @param pVM VM Handle.
202 * @param uErrorCode CPU Error code.
203 * @param pRegFrame Trap register frame.
204 * @param pvFault The fault address (cr2).
205 * @param pvRange The base address of the handled virtual range.
206 * @param offRange The offset of the access into this range.
207 * (If it's a EIP range this's the EIP, if not it's pvFault.)
208 */
209typedef DECLCALLBACK(int) FNPGMGCVIRTHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
210/** Pointer to PGM access callback. */
211typedef FNPGMGCVIRTHANDLER *PFNPGMGCVIRTHANDLER;
212
213/**
214 * \#PF Handler callback for virtual access handler ranges.
215 *
216 * Important to realize that a physical page in a range can have aliases, and
217 * for ALL and WRITE handlers these will also trigger.
218 *
219 * @returns VINF_SUCCESS if the handler have carried out the operation.
220 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
221 * @param pVM VM Handle.
222 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
223 * @param pvPtr The HC mapping of that address.
224 * @param pvBuf What the guest is reading/writing.
225 * @param cbBuf How much it's reading/writing.
226 * @param enmAccessType The access type.
227 * @param pvUser User argument.
228 */
229typedef DECLCALLBACK(int) FNPGMHCVIRTHANDLER(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
230/** Pointer to PGM access callback. */
231typedef FNPGMHCVIRTHANDLER *PFNPGMHCVIRTHANDLER;
232
233
234/**
235 * \#PF Handler callback for invalidation of virtual access handler ranges.
236 *
237 * @param pVM VM Handle.
238 * @param GCPtr The virtual address the guest has changed.
239 */
240typedef DECLCALLBACK(int) FNPGMHCVIRTINVALIDATE(PVM pVM, RTGCPTR GCPtr);
241/** Pointer to PGM invalidation callback. */
242typedef FNPGMHCVIRTINVALIDATE *PFNPGMHCVIRTINVALIDATE;
243
244/**
245 * Paging mode.
246 */
247typedef enum PGMMODE
248{
249 /** The usual invalid value. */
250 PGMMODE_INVALID = 0,
251 /** Real mode. */
252 PGMMODE_REAL,
253 /** Protected mode, no paging. */
254 PGMMODE_PROTECTED,
255 /** 32-bit paging. */
256 PGMMODE_32_BIT,
257 /** PAE paging. */
258 PGMMODE_PAE,
259 /** PAE paging with NX enabled. */
260 PGMMODE_PAE_NX,
261 /** 64-bit AMD paging (long mode). */
262 PGMMODE_AMD64,
263 /** 64-bit AMD paging (long mode) with NX enabled. */
264 PGMMODE_AMD64_NX,
265 /** Nested paging mode (shadow only; guest physical to host physical). */
266 PGMMODE_NESTED,
267 /** The max number of modes */
268 PGMMODE_MAX,
269 /** 32bit hackishness. */
270 PGMMODE_32BIT_HACK = 0x7fffffff
271} PGMMODE;
272
273/**
274 * The current ROM page protection.
275 */
276typedef enum PGMROMPROT
277{
278 /** The customary invalid value. */
279 PGMROMPROT_INVALID = 0,
280 /** Read from the virgin ROM page, ignore writes.
281 * Map the virgin page, use write access handler to ignore writes. */
282 PGMROMPROT_READ_ROM_WRITE_IGNORE,
283 /** Read from the virgin ROM page, write to the shadow RAM.
284 * Map the virgin page, use write access handler change the RAM. */
285 PGMROMPROT_READ_ROM_WRITE_RAM,
286 /** Read from the shadow ROM page, ignore writes.
287 * Map the shadow page read-only, use write access handler to ignore writes. */
288 PGMROMPROT_READ_RAM_WRITE_IGNORE,
289 /** Read from the shadow ROM page, ignore writes.
290 * Map the shadow page read-write, disabled write access handler. */
291 PGMROMPROT_READ_RAM_WRITE_RAM,
292 /** The end of valid values. */
293 PGMROMPROT_END,
294 /** The usual 32-bit type size hack. */
295 PGMROMPROT_32BIT_HACK = 0x7fffffff
296} PGMROMPROT;
297
298/**
299 * Is the ROM mapped (true) or is the shadow RAM mapped (false).
300 *
301 * @returns boolean.
302 * @param enmProt The PGMROMPROT value, must be valid.
303 */
304#define PGMROMPROT_IS_ROM(enmProt) \
305 ( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
306 || (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
307
308
309PGMDECL(uint32_t) PGMGetHyperCR3(PVM pVM);
310PGMDECL(uint32_t) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode);
311PGMDECL(uint32_t) PGMGetHyper32BitCR3(PVM pVM);
312PGMDECL(uint32_t) PGMGetHyperPaeCR3(PVM pVM);
313PGMDECL(uint32_t) PGMGetHyperAmd64CR3(PVM pVM);
314PGMDECL(uint32_t) PGMGetInterHCCR3(PVM pVM);
315PGMDECL(uint32_t) PGMGetInterGCCR3(PVM pVM);
316PGMDECL(uint32_t) PGMGetInter32BitCR3(PVM pVM);
317PGMDECL(uint32_t) PGMGetInterPaeCR3(PVM pVM);
318PGMDECL(uint32_t) PGMGetInterAmd64CR3(PVM pVM);
319PGMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
320PGMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage);
321PGMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess);
322PGMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess);
323PGMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
324PGMDECL(int) PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
325PGMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
326PGMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
327PGMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
328PGMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
329PGMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
330PGMDECL(int) PGMShwGetLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PDPAE *ppPD);
331PGMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
332PGMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr);
333PGMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
334PGMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
335PGMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal);
336PGMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3);
337PGMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
338PGMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer);
339PGMDECL(PGMMODE) PGMGetGuestMode(PVM pVM);
340PGMDECL(PGMMODE) PGMGetShadowMode(PVM pVM);
341PGMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
342PGMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
343PGMDECL(int) PGMHandlerPhysicalRegisterEx(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
344 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
345 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
346 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC, RCPTRTYPE(void *) pvUserGC,
347 R3PTRTYPE(const char *) pszDesc);
348PGMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
349PGMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
350PGMDECL(int) PGMHandlerPhysicalChangeCallbacks(PVM pVM, RTGCPHYS GCPhys,
351 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
352 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
353 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC, RCPTRTYPE(void *) pvUserGC,
354 R3PTRTYPE(const char *) pszDesc);
355PGMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
356PGMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
357PGMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
358PGMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
359PGMDECL(int) PGMHandlerPhysicalPageReset(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
360PGMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
361PGMDECL(bool) PGMPhysIsA20Enabled(PVM pVM);
362PGMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
363PGMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
364PGMDECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
365PGMDECL(int) PGMPhysGCPtr2GCPhys(PVM pVM, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
366PGMDECL(int) PGMPhysGCPtr2HCPhys(PVM pVM, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
367PDMDECL(void) PGMPhysInvalidatePageGCMapTLB(PVM pVM);
368PDMDECL(void) PGMPhysInvalidatePageR0MapTLB(PVM pVM);
369PDMDECL(void) PGMPhysInvalidatePageR3MapTLB(PVM pVM);
370
371/**
372 * Page mapping lock.
373 *
374 * @remarks This doesn't work in structures shared between
375 * ring-3, ring-0 and/or GC.
376 */
377typedef struct PGMPAGEMAPLOCK
378{
379 /** @todo see PGMPhysIsPageMappingLockValid for possibly incorrect assumptions */
380#ifdef IN_GC
381 /** Just a dummy for the time being. */
382 uint32_t u32Dummy;
383#else
384 /** Pointer to the PGMPAGE. */
385 void *pvPage;
386 /** Pointer to the PGMCHUNKR3MAP. */
387 void *pvMap;
388#endif
389} PGMPAGEMAPLOCK;
390/** Pointer to a page mapping lock. */
391typedef PGMPAGEMAPLOCK *PPGMPAGEMAPLOCK;
392
393PGMDECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
394PGMDECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
395PGMDECL(int) PGMPhysGCPtr2CCPtr(PVM pVM, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
396PGMDECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVM pVM, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
397PGMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
398
399/**
400 * Checks if the lock structure is valid
401 *
402 * @param pVM The VM handle.
403 * @param pLock The lock structure initialized by the mapping function.
404 */
405DECLINLINE(bool) PGMPhysIsPageMappingLockValid(PVM pVM, PPGMPAGEMAPLOCK pLock)
406{
407 /** @todo -> complete/change this */
408#ifdef IN_GC
409 return !!(pLock->u32Dummy);
410#else
411 return !!(pLock->pvPage);
412#endif
413}
414
415PGMDECL(int) PGMPhysGCPhys2HCPtr(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange, PRTHCPTR pHCPtr);
416PGMDECL(int) PGMPhysGCPtr2HCPtr(PVM pVM, RTGCPTR GCPtr, PRTHCPTR pHCPtr);
417PGMDECL(int) PGMPhysGCPtr2HCPtrByGstCR3(PVM pVM, RTGCPTR GCPtr, uint64_t cr3, unsigned fFlags, PRTHCPTR pHCPtr);
418PGMDECL(void) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
419PGMDECL(void) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
420#ifndef IN_GC /* Only ring 0 & 3. */
421PGMDECL(int) PGMPhysReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
422PGMDECL(int) PGMPhysWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
423PGMDECL(int) PGMPhysReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
424PGMDECL(int) PGMPhysWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
425PGMDECL(int) PGMPhysReadGCPtrSafe(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
426PGMDECL(int) PGMPhysWriteGCPtrSafe(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
427PGMDECL(int) PGMPhysWriteGCPtrDirty(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
428PGMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage);
429#endif /* !IN_GC */
430PGMDECL(int) PGMPhysInterpretedRead(PVM pVM, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb);
431#ifdef VBOX_STRICT
432PGMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
433PGMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
434PGMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4);
435#endif /* VBOX_STRICT */
436
437
438#ifdef IN_GC
439/** @defgroup grp_pgm_gc The PGM Guest Context API
440 * @ingroup grp_pgm
441 * @{
442 */
443PGMGCDECL(int) PGMGCDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv);
444PGMGCDECL(int) PGMGCDynMapGCPageEx(PVM pVM, RTGCPHYS GCPhys, void **ppv);
445PGMGCDECL(int) PGMGCDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv);
446PGMGCDECL(int) PGMGCInvalidatePage(PVM pVM, RTGCPTR GCPtrPage);
447/** @} */
448#endif /* IN_GC */
449
450
451#ifdef IN_RING0
452/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
453 * @ingroup grp_pgm
454 * @{
455 */
456PGMR0DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM);
457PGMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
458/** @} */
459#endif /* IN_RING0 */
460
461
462
463#ifdef IN_RING3
464/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
465 * @ingroup grp_pgm
466 * @{
467 */
468PGMR3DECL(int) PGMR3Init(PVM pVM);
469PGMR3DECL(int) PGMR3InitDynMap(PVM pVM);
470PGMR3DECL(int) PGMR3InitFinalize(PVM pVM);
471PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
472PGMR3DECL(void) PGMR3Reset(PVM pVM);
473PGMR3DECL(int) PGMR3Term(PVM pVM);
474PDMR3DECL(int) PGMR3LockCall(PVM pVM);
475PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable);
476PGMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
477
478#ifndef VBOX_WITH_NEW_PHYS_CODE
479PGMR3DECL(int) PGM3PhysGrowRange(PVM pVM, PCRTGCPHYS GCPhys);
480#endif /* !VBOX_WITH_NEW_PHYS_CODE */
481PGMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
482PDMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
483 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
484 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
485 RCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC, RTGCPTR pvUserGC,
486 R3PTRTYPE(const char *) pszDesc);
487PDMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
488PDMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc);
489PDMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
490PDMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
491PDMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
492PDMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
493PDMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
494
495/** @group PGMR3PhysRegisterRom flags.
496 * @{ */
497/** Inidicates that ROM shadowing should be enabled. */
498#define PGMPHYS_ROM_FLAG_SHADOWED RT_BIT_32(0)
499/** Indicates that what pvBinary points to won't go away
500 * and can be used for strictness checks. */
501#define PGMPHYS_ROM_FLAG_PERMANENT_BINARY RT_BIT_32(1)
502/** @} */
503
504PGMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
505 const void *pvBinary, uint32_t fFlags, const char *pszDesc);
506PGMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
507PGMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
508#ifndef VBOX_WITH_NEW_PHYS_CODE
509PGMR3DECL(int) PGMR3PhysRegisterChunk(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
510#endif /* !VBOX_WITH_NEW_PHYS_CODE */
511PGMR3DECL(int) PGMR3PhysSetFlags(PVM pVM, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, unsigned fMask);
512PGMDECL(void) PGMR3PhysSetA20(PVM pVM, bool fEnable);
513PGMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, PFNPGMRELOCATE pfnRelocate, void *pvUser, const char *pszDesc);
514PGMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
515PGMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
516PGMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
517PGMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
518PGMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
519PGMR3DECL(bool) PGMR3MapHasConflicts(PVM pVM, uint64_t cr3, bool fRawR0);
520PGMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
521PGMR3DECL(int) PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
522 PFNPGMR3PHYSHANDLER pfnHandlerR3, void *pvUserR3,
523 const char *pszModR0, const char *pszHandlerR0, RTR0PTR pvUserR0,
524 const char *pszModGC, const char *pszHandlerGC, RTGCPTR pvUserGC, const char *pszDesc);
525PGMDECL(int) PGMHandlerVirtualRegisterEx(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
526 PFNPGMHCVIRTINVALIDATE pfnInvalidateHC,
527 PFNPGMHCVIRTHANDLER pfnHandlerHC, RTGCPTR pfnHandlerGC,
528 R3PTRTYPE(const char *) pszDesc);
529PGMR3DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
530 PFNPGMHCVIRTINVALIDATE pfnInvalidateHC,
531 PFNPGMHCVIRTHANDLER pfnHandlerHC,
532 const char *pszHandlerGC, const char *pszModGC, const char *pszDesc);
533PGMDECL(int) PGMHandlerVirtualChangeInvalidateCallback(PVM pVM, RTGCPTR GCPtr, PFNPGMHCVIRTINVALIDATE pfnInvalidateHC);
534PGMDECL(int) PGMHandlerVirtualDeregister(PVM pVM, RTGCPTR GCPtr);
535PDMR3DECL(int) PGMR3PoolGrow(PVM pVM);
536#ifdef ___VBox_dbgf_h /** @todo fix this! */
537PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
538#endif
539PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch);
540
541PGMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys);
542PGMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys);
543PGMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys);
544PGMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys);
545PGMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value);
546PGMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value);
547PGMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value);
548PGMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value);
549PDMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
550PGMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
551PDMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
552
553PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
554
555PGMR3DECL(int) PGMR3DbgHCPtr2GCPhys(PVM pVM, RTHCPTR HCPtr, PRTGCPHYS pGCPhys);
556PGMR3DECL(int) PGMR3DbgHCPtr2HCPhys(PVM pVM, RTHCPTR HCPtr, PRTHCPHYS pHCPhys);
557PGMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PVM pVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
558PDMR3DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
559PDMR3DECL(int) PGMR3DbgScanVirtual(PVM pVM, RTGCUINTPTR GCPtr, RTGCUINTPTR cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
560/** @} */
561#endif /* IN_RING3 */
562
563__END_DECLS
564
565/** @} */
566#endif
567
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