VirtualBox

source: vbox/trunk/include/VBox/vmm/apic.h@ 61067

Last change on this file since 61067 was 61044, checked in by vboxsync, 9 years ago

apic.h: See r=bird in code.
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Line 
1/** @file
2 * APIC - Advanced Programmable Interrupt Controller.
3 */
4
5/*
6 * Copyright (C) 2006-2016 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_apic_h
27#define ___VBox_vmm_apic_h
28
29#include <VBox/vmm/pdmins.h>
30#include <VBox/vmm/pdmdev.h>
31
32/** @defgroup grp_apic The local APIC VMM API
33 * @ingroup grp_vmm
34 * @{
35 */
36
37/** Gets the APIC base physical address. */
38#define MSR_APICBASE_GET_PHYSADDR(a) ((a) & PAGE_BASE_GC_MASK)
39/** Gets the APIC mode. */
40#define MSR_APICBASE_GET_MODE(a) (((a) >> 10) & UINT64_C(3))
41/** The APIC global enable bit. */
42/** @todo r=bird: Please do N O T use _BIT for what clearly are masks!
43 * See x86.h and vm.h for examples of how we use _BIT elsewhere!
44 * Besides, you are duplicating existing x86.h defines here
45 * (MSR_IA32_APICBASE_XXX). */
46#define MSR_APICBASE_XAPIC_ENABLE_BIT RT_BIT_64(11)
47/** The x2APIC global enable bit. */
48#define MSR_APICBASE_X2APIC_ENABLE_BIT RT_BIT_64(10)
49/** The APIC bootstrap processor bit. */
50#define MSR_APICBASE_BOOTSTRAP_CPU_BIT RT_BIT_64(8)
51/** The default APIC base address. */
52#define XAPIC_APICBASE_PHYSADDR UINT64_C(0xfee00000)
53/** The APIC base MSR - Is the APIC enabled? */
54#define MSR_APICBASE_IS_ENABLED(a_Msr) RT_BOOL((a_Msr) & MSR_APICBASE_XAPIC_ENABLE_BIT)
55
56/** Offset of APIC ID Register. */
57#define XAPIC_OFF_ID 0x020
58/** Offset of APIC Version Register. */
59#define XAPIC_OFF_VERSION 0x030
60/** Offset of Task Priority Register. */
61#define XAPIC_OFF_TPR 0x080
62/** Offset of Arbitrartion Priority register. */
63#define XAPIC_OFF_APR 0x090
64/** Offset of Processor Priority register. */
65#define XAPIC_OFF_PPR 0x0A0
66/** Offset of End Of Interrupt register. */
67#define XAPIC_OFF_EOI 0x0B0
68/** Offset of Remote Read Register. */
69#define XAPIC_OFF_RRD 0x0C0
70/** Offset of Logical Destination Register. */
71#define XAPIC_OFF_LDR 0x0D0
72/** Offset of Destination Format Register. */
73#define XAPIC_OFF_DFR 0x0E0
74/** Offset of Spurious Interrupt Vector Register. */
75#define XAPIC_OFF_SVR 0x0F0
76/** Offset of In-service Register (bits 31:0). */
77#define XAPIC_OFF_ISR0 0x100
78/** Offset of In-service Register (bits 63:32). */
79#define XAPIC_OFF_ISR1 0x110
80/** Offset of In-service Register (bits 95:64). */
81#define XAPIC_OFF_ISR2 0x120
82/** Offset of In-service Register (bits 127:96). */
83#define XAPIC_OFF_ISR3 0x130
84/** Offset of In-service Register (bits 159:128). */
85#define XAPIC_OFF_ISR4 0x140
86/** Offset of In-service Register (bits 191:160). */
87#define XAPIC_OFF_ISR5 0x150
88/** Offset of In-service Register (bits 223:192). */
89#define XAPIC_OFF_ISR6 0x160
90/** Offset of In-service Register (bits 255:224). */
91#define XAPIC_OFF_ISR7 0x170
92/** Offset of Trigger Mode Register (bits 31:0). */
93#define XAPIC_OFF_TMR0 0x180
94/** Offset of Trigger Mode Register (bits 63:32). */
95#define XAPIC_OFF_TMR1 0x190
96/** Offset of Trigger Mode Register (bits 95:64). */
97#define XAPIC_OFF_TMR2 0x1A0
98/** Offset of Trigger Mode Register (bits 127:96). */
99#define XAPIC_OFF_TMR3 0x1B0
100/** Offset of Trigger Mode Register (bits 159:128). */
101#define XAPIC_OFF_TMR4 0x1C0
102/** Offset of Trigger Mode Register (bits 191:160). */
103#define XAPIC_OFF_TMR5 0x1D0
104/** Offset of Trigger Mode Register (bits 223:192). */
105#define XAPIC_OFF_TMR6 0x1E0
106/** Offset of Trigger Mode Register (bits 255:224). */
107#define XAPIC_OFF_TMR7 0x1F0
108/** Offset of Interrupt Request Register (bits 31:0). */
109#define XAPIC_OFF_IRR0 0x200
110/** Offset of Interrupt Request Register (bits 63:32). */
111#define XAPIC_OFF_IRR1 0x210
112/** Offset of Interrupt Request Register (bits 95:64). */
113#define XAPIC_OFF_IRR2 0x220
114/** Offset of Interrupt Request Register (bits 127:96). */
115#define XAPIC_OFF_IRR3 0x230
116/** Offset of Interrupt Request Register (bits 159:128). */
117#define XAPIC_OFF_IRR4 0x240
118/** Offset of Interrupt Request Register (bits 191:160). */
119#define XAPIC_OFF_IRR5 0x250
120/** Offset of Interrupt Request Register (bits 223:192). */
121#define XAPIC_OFF_IRR6 0x260
122/** Offset of Interrupt Request Register (bits 255:224). */
123#define XAPIC_OFF_IRR7 0x270
124/** Offset of Error Status Register. */
125#define XAPIC_OFF_ESR 0x280
126/** Offset of LVT CMCI Register. */
127#define XAPIC_OFF_LVT_CMCI 0x2F0
128/** Offset of Interrupt Command Register - Lo. */
129#define XAPIC_OFF_ICR_LO 0x300
130/** Offset of Interrupt Command Register - Hi. */
131#define XAPIC_OFF_ICR_HI 0x310
132/** Offset of LVT Timer Register. */
133#define XAPIC_OFF_LVT_TIMER 0x320
134/** Offset of LVT Thermal Sensor Register. */
135#define XAPIC_OFF_LVT_THERMAL 0x330
136/** Offset of LVT Performance Counter Register. */
137#define XAPIC_OFF_LVT_PERF 0x340
138/** Offset of LVT LINT0 Register. */
139#define XAPIC_OFF_LVT_LINT0 0x350
140/** Offset of LVT LINT1 Register. */
141#define XAPIC_OFF_LVT_LINT1 0x360
142/** Offset of LVT Error Register . */
143#define XAPIC_OFF_LVT_ERROR 0x370
144/** Offset of Timer Initial Count Register. */
145#define XAPIC_OFF_TIMER_ICR 0x380
146/** Offset of Timer Current Count Register. */
147#define XAPIC_OFF_TIMER_CCR 0x390
148/** Offset of Timer Divide Configuration Register. */
149#define XAPIC_OFF_TIMER_DCR 0x3E0
150/** Offset of Self-IPI Register (x2APIC only). */
151#define X2APIC_OFF_SELF_IPI 0x3F0
152
153/** Offset of LVT range start. */
154#define XAPIC_OFF_LVT_START XAPIC_OFF_LVT_TIMER
155/** Offset of LVT range end (inclusive). */
156#define XAPIC_OFF_LVT_END XAPIC_OFF_LVT_ERROR
157/** Offset of LVT extended range start. */
158#define XAPIC_OFF_LVT_EXT_START XAPIC_OFF_LVT_CMCI
159/** Offset of LVT extended range end (inclusive). */
160#define XAPIC_OFF_LVT_EXT_END XAPIC_OFF_LVT_CMCI
161
162
163RT_C_DECLS_BEGIN
164
165#ifdef IN_RING3
166/** @defgroup grp_apic_r3 The APIC Host Context Ring-3 API
167 * @{
168 */
169VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu);
170VMMR3_INT_DECL(void) APICR3Reset(PVMCPU pVCpu, bool fResetApicBaseMsr);
171/** @} */
172#endif /* IN_RING3 */
173
174#ifdef IN_RING0
175/** @defgroup grp_apic_r0 The APIC Host Context Ring-0 API
176 * @{
177 */
178VMMR0_INT_DECL(int) APICR0InitVM(PVM pVM);
179VMMR0_INT_DECL(int) APICR0TermVM(PVM pVM);
180/** @} */
181#endif /* IN_RING0 */
182
183VMMDECL(bool) APICQueueInterruptToService(PVMCPU pVCpu, uint8_t u8PendingIntr);
184VMMDECL(void) APICDequeueInterruptFromService(PVMCPU pVCpu, uint8_t u8PendingIntr);
185VMMDECL(void) APICUpdatePendingInterrupts(PVMCPU pVCpu);
186VMMDECL(bool) APICGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr);
187
188RT_C_DECLS_END
189
190extern const PDMDEVREG g_DeviceAPIC;
191/** @} */
192
193#endif
194
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