cpum-x86-amd64.h@ 107558

Last change on this file since 107558 was 107389, checked in by vboxsync, 8 weeks ago
VMM/CPUM: The CPUMFEATURE structures can't be in target specific headers, since we need them for the host CPU as well. jiraref:VBP-1470
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Line
1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpum_x86_amd64_h
37	#define VBOX_INCLUDED_vmm_cpum_x86_amd64_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <iprt/x86.h>
43	#include <VBox/vmm/hm_svm.h>
44	#include <VBox/vmm/hm_vmx.h>
45
46	RT_C_DECLS_BEGIN
47
48	/** @defgroup grp_cpum The CPU Monitor / Manager API
49	* @ingroup grp_vmm
50	* @{
51	*/
52
53	/**
54	* CPUID feature to set or clear.
55	*/
56	typedef enum CPUMCPUIDFEATURE
57	{
58	CPUMCPUIDFEATURE_INVALID = 0,
59	/** The APIC feature bit. (Std+Ext)
60	* Note! There is a per-cpu flag for masking this CPUID feature bit when the
61	* APICBASE.ENABLED bit is zero. So, this feature is only set/cleared
62	* at VM construction time like all the others. This didn't used to be
63	* that way, this is new with 5.1. */
64	CPUMCPUIDFEATURE_APIC,
65	/** The sysenter/sysexit feature bit. (Std) */
66	CPUMCPUIDFEATURE_SEP,
67	/** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
68	CPUMCPUIDFEATURE_SYSCALL,
69	/** The PAE feature bit. (Std+Ext) */
70	CPUMCPUIDFEATURE_PAE,
71	/** The NX feature bit. (Ext) */
72	CPUMCPUIDFEATURE_NX,
73	/** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
74	CPUMCPUIDFEATURE_LAHF,
75	/** The LONG MODE feature bit. (Ext) */
76	CPUMCPUIDFEATURE_LONG_MODE,
77	/** The x2APIC feature bit. (Std) */
78	CPUMCPUIDFEATURE_X2APIC,
79	/** The RDTSCP feature bit. (Ext) */
80	CPUMCPUIDFEATURE_RDTSCP,
81	/** The Hypervisor Present bit. (Std) */
82	CPUMCPUIDFEATURE_HVP,
83	/** The speculation control feature bits. (StExt) */
84	CPUMCPUIDFEATURE_SPEC_CTRL,
85	/** 32bit hackishness. */
86	CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
87	} CPUMCPUIDFEATURE;
88
89
90	/**
91	* CPUID leaf.
92	*
93	* @remarks This structure is used by the patch manager and is therefore
94	* more or less set in stone.
95	*/
96	typedef struct CPUMCPUIDLEAF
97	{
98	/** The leaf number. */
99	uint32_t uLeaf;
100	/** The sub-leaf number. */
101	uint32_t uSubLeaf;
102	/** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
103	uint32_t fSubLeafMask;
104
105	/** The EAX value. */
106	uint32_t uEax;
107	/** The EBX value. */
108	uint32_t uEbx;
109	/** The ECX value. */
110	uint32_t uEcx;
111	/** The EDX value. */
112	uint32_t uEdx;
113
114	/** Flags. */
115	uint32_t fFlags;
116	} CPUMCPUIDLEAF;
117	#ifndef VBOX_FOR_DTRACE_LIB
118	AssertCompileSize(CPUMCPUIDLEAF, 32);
119	#endif
120	/** Pointer to a CPUID leaf. */
121	typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
122	/** Pointer to a const CPUID leaf. */
123	typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
124
125	/** @name CPUMCPUIDLEAF::fFlags
126	* @{ */
127	/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
128	* and EDX containing the extended APIC ID. */
129	#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
130	/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
131	#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
132	/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
133	#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
134	/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
135	#define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
136	/** Mask of the valid flags. */
137	#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0xf)
138	/** @} */
139
140	/**
141	* Method used to deal with unknown CPUID leaves.
142	* @remarks Used in patch code.
143	*/
144	typedef enum CPUMUNKNOWNCPUID
145	{
146	/** Invalid zero value. */
147	CPUMUNKNOWNCPUID_INVALID = 0,
148	/** Use given default values (DefCpuId). */
149	CPUMUNKNOWNCPUID_DEFAULTS,
150	/** Return the last standard leaf.
151	* Intel Sandy Bridge has been observed doing this. */
152	CPUMUNKNOWNCPUID_LAST_STD_LEAF,
153	/** Return the last standard leaf, with ecx observed.
154	* Intel Sandy Bridge has been observed doing this. */
155	CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
156	/** The register values are passed thru unmodified. */
157	CPUMUNKNOWNCPUID_PASSTHRU,
158	/** End of valid value. */
159	CPUMUNKNOWNCPUID_END,
160	/** Ensure 32-bit type. */
161	CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
162	} CPUMUNKNOWNCPUID;
163	/** Pointer to unknown CPUID leaf method. */
164	typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
165
166
167	/**
168	* The register set returned by a CPUID operation.
169	*/
170	typedef struct CPUMCPUID
171	{
172	uint32_t uEax;
173	uint32_t uEbx;
174	uint32_t uEcx;
175	uint32_t uEdx;
176	} CPUMCPUID;
177	/** Pointer to a CPUID leaf. */
178	typedef CPUMCPUID *PCPUMCPUID;
179	/** Pointer to a const CPUID leaf. */
180	typedef const CPUMCPUID *PCCPUMCPUID;
181
182
183	/**
184	* MSR read functions.
185	*/
186	typedef enum CPUMMSRRDFN
187	{
188	/** Invalid zero value. */
189	kCpumMsrRdFn_Invalid = 0,
190	/** Return the CPUMMSRRANGE::uValue. */
191	kCpumMsrRdFn_FixedValue,
192	/** Alias to the MSR range starting at the MSR given by
193	* CPUMMSRRANGE::uValue. Must be used in pair with
194	* kCpumMsrWrFn_MsrAlias. */
195	kCpumMsrRdFn_MsrAlias,
196	/** Write only register, GP all read attempts. */
197	kCpumMsrRdFn_WriteOnly,
198
199	kCpumMsrRdFn_Ia32P5McAddr,
200	kCpumMsrRdFn_Ia32P5McType,
201	kCpumMsrRdFn_Ia32TimestampCounter,
202	kCpumMsrRdFn_Ia32PlatformId, /*< Takes real CPU value for reference. /
203	kCpumMsrRdFn_Ia32ApicBase,
204	kCpumMsrRdFn_Ia32FeatureControl,
205	kCpumMsrRdFn_Ia32BiosSignId, /*< Range value returned. /
206	kCpumMsrRdFn_Ia32SmmMonitorCtl,
207	kCpumMsrRdFn_Ia32PmcN,
208	kCpumMsrRdFn_Ia32MonitorFilterLineSize,
209	kCpumMsrRdFn_Ia32MPerf,
210	kCpumMsrRdFn_Ia32APerf,
211	kCpumMsrRdFn_Ia32MtrrCap, /*< Takes real CPU value for reference. /
212	kCpumMsrRdFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
213	kCpumMsrRdFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
214	kCpumMsrRdFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
215	kCpumMsrRdFn_Ia32MtrrDefType,
216	kCpumMsrRdFn_Ia32Pat,
217	kCpumMsrRdFn_Ia32SysEnterCs,
218	kCpumMsrRdFn_Ia32SysEnterEsp,
219	kCpumMsrRdFn_Ia32SysEnterEip,
220	kCpumMsrRdFn_Ia32McgCap,
221	kCpumMsrRdFn_Ia32McgStatus,
222	kCpumMsrRdFn_Ia32McgCtl,
223	kCpumMsrRdFn_Ia32DebugCtl,
224	kCpumMsrRdFn_Ia32SmrrPhysBase,
225	kCpumMsrRdFn_Ia32SmrrPhysMask,
226	kCpumMsrRdFn_Ia32PlatformDcaCap,
227	kCpumMsrRdFn_Ia32CpuDcaCap,
228	kCpumMsrRdFn_Ia32Dca0Cap,
229	kCpumMsrRdFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
230	kCpumMsrRdFn_Ia32PerfStatus, /*< Range value returned. /
231	kCpumMsrRdFn_Ia32PerfCtl, /*< Range value returned. /
232	kCpumMsrRdFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
233	kCpumMsrRdFn_Ia32PerfCapabilities, /*< Takes reference value. /
234	kCpumMsrRdFn_Ia32FixedCtrCtrl,
235	kCpumMsrRdFn_Ia32PerfGlobalStatus, /*< Takes reference value. /
236	kCpumMsrRdFn_Ia32PerfGlobalCtrl,
237	kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
238	kCpumMsrRdFn_Ia32PebsEnable,
239	kCpumMsrRdFn_Ia32ClockModulation, /*< Range value returned. /
240	kCpumMsrRdFn_Ia32ThermInterrupt, /*< Range value returned. /
241	kCpumMsrRdFn_Ia32ThermStatus, /*< Range value returned. /
242	kCpumMsrRdFn_Ia32Therm2Ctl, /*< Range value returned. /
243	kCpumMsrRdFn_Ia32MiscEnable, /*< Range value returned. /
244	kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
245	kCpumMsrRdFn_Ia32McNCtl2, /*< Takes register number of start of range. /
246	kCpumMsrRdFn_Ia32DsArea,
247	kCpumMsrRdFn_Ia32TscDeadline,
248	kCpumMsrRdFn_Ia32X2ApicN,
249	kCpumMsrRdFn_Ia32DebugInterface,
250	kCpumMsrRdFn_Ia32VmxBasic, /*< Takes real value as reference. /
251	kCpumMsrRdFn_Ia32VmxPinbasedCtls, /*< Takes real value as reference. /
252	kCpumMsrRdFn_Ia32VmxProcbasedCtls, /*< Takes real value as reference. /
253	kCpumMsrRdFn_Ia32VmxExitCtls, /*< Takes real value as reference. /
254	kCpumMsrRdFn_Ia32VmxEntryCtls, /*< Takes real value as reference. /
255	kCpumMsrRdFn_Ia32VmxMisc, /*< Takes real value as reference. /
256	kCpumMsrRdFn_Ia32VmxCr0Fixed0, /*< Takes real value as reference. /
257	kCpumMsrRdFn_Ia32VmxCr0Fixed1, /*< Takes real value as reference. /
258	kCpumMsrRdFn_Ia32VmxCr4Fixed0, /*< Takes real value as reference. /
259	kCpumMsrRdFn_Ia32VmxCr4Fixed1, /*< Takes real value as reference. /
260	kCpumMsrRdFn_Ia32VmxVmcsEnum, /*< Takes real value as reference. /
261	kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /*< Takes real value as reference. /
262	kCpumMsrRdFn_Ia32VmxEptVpidCap, /*< Takes real value as reference. /
263	kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /*< Takes real value as reference. /
264	kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /*< Takes real value as reference. /
265	kCpumMsrRdFn_Ia32VmxTrueExitCtls, /*< Takes real value as reference. /
266	kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /*< Takes real value as reference. /
267	kCpumMsrRdFn_Ia32VmxVmFunc, /*< Takes real value as reference. /
268	kCpumMsrRdFn_Ia32SpecCtrl,
269	kCpumMsrRdFn_Ia32ArchCapabilities,
270
271	kCpumMsrRdFn_Amd64Efer,
272	kCpumMsrRdFn_Amd64SyscallTarget,
273	kCpumMsrRdFn_Amd64LongSyscallTarget,
274	kCpumMsrRdFn_Amd64CompSyscallTarget,
275	kCpumMsrRdFn_Amd64SyscallFlagMask,
276	kCpumMsrRdFn_Amd64FsBase,
277	kCpumMsrRdFn_Amd64GsBase,
278	kCpumMsrRdFn_Amd64KernelGsBase,
279	kCpumMsrRdFn_Amd64TscAux,
280
281	kCpumMsrRdFn_IntelEblCrPowerOn,
282	kCpumMsrRdFn_IntelI7CoreThreadCount,
283	kCpumMsrRdFn_IntelP4EbcHardPowerOn,
284	kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
285	kCpumMsrRdFn_IntelP4EbcFrequencyId,
286	kCpumMsrRdFn_IntelP6FsbFrequency, /*< Takes real value as reference. /
287	kCpumMsrRdFn_IntelPlatformInfo,
288	kCpumMsrRdFn_IntelFlexRatio, /*< Takes real value as reference. /
289	kCpumMsrRdFn_IntelPkgCStConfigControl,
290	kCpumMsrRdFn_IntelPmgIoCaptureBase,
291	kCpumMsrRdFn_IntelLastBranchFromToN,
292	kCpumMsrRdFn_IntelLastBranchFromN,
293	kCpumMsrRdFn_IntelLastBranchToN,
294	kCpumMsrRdFn_IntelLastBranchTos,
295	kCpumMsrRdFn_IntelBblCrCtl,
296	kCpumMsrRdFn_IntelBblCrCtl3,
297	kCpumMsrRdFn_IntelI7TemperatureTarget, /*< Range value returned. /
298	kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/*< Takes register number. /
299	kCpumMsrRdFn_IntelI7MiscPwrMgmt,
300	kCpumMsrRdFn_IntelP6CrN,
301	kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
302	kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
303	kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
304	kCpumMsrRdFn_IntelI7SandyAesNiCtl,
305	kCpumMsrRdFn_IntelI7TurboRatioLimit, /*< Returns range value. /
306	kCpumMsrRdFn_IntelI7LbrSelect,
307	kCpumMsrRdFn_IntelI7SandyErrorControl,
308	kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/*< Returns range value. /
309	kCpumMsrRdFn_IntelI7PowerCtl,
310	kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
311	kCpumMsrRdFn_IntelI7PebsLdLat,
312	kCpumMsrRdFn_IntelI7PkgCnResidencyN, /*< Takes C-state number. /
313	kCpumMsrRdFn_IntelI7CoreCnResidencyN, /*< Takes C-state number. /
314	kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/*< Takes real value as reference. /
315	kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /*< Takes real value as reference. /
316	kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /*< Takes real value as reference. /
317	kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /*< Takes real value as reference. /
318	kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /*< Takes real value as reference. /
319	kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /*< Takes real value as reference. /
320	kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /*< Takes real value as reference. /
321	kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /*< Takes real value as reference. /
322	kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /*< Takes real value as reference. /
323	kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /*< Takes real value as reference. /
324	kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/*< Takes real value as reference. /
325	kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /*< Takes real value as reference. /
326	kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /*< Takes real value as reference. /
327	kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /*< Takes real value as reference. /
328	kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /*< Takes real value as reference. /
329	kCpumMsrRdFn_IntelI7RaplPp0Policy, /*< Takes real value as reference. /
330	kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /*< Takes real value as reference. /
331	kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /*< Takes real value as reference. /
332	kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /*< Takes real value as reference. /
333	kCpumMsrRdFn_IntelI7RaplPp1Policy, /*< Takes real value as reference. /
334	kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /*< Takes real value as reference. /
335	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /*< Takes real value as reference. /
336	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /*< Takes real value as reference. /
337	kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
338	kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
339	kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
340	kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
341	kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
342	kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
343	kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
344	kCpumMsrRdFn_IntelI7UncCBoxConfig,
345	kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
346	kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
347	kCpumMsrRdFn_IntelI7SmiCount,
348	kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /*< Range value returned. /
349	kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
350	kCpumMsrRdFn_IntelCore1ExtConfig,
351	kCpumMsrRdFn_IntelCore1DtsCalControl,
352	kCpumMsrRdFn_IntelCore2PeciControl,
353	kCpumMsrRdFn_IntelAtSilvCoreC1Recidency,
354
355	kCpumMsrRdFn_P6LastBranchFromIp,
356	kCpumMsrRdFn_P6LastBranchToIp,
357	kCpumMsrRdFn_P6LastIntFromIp,
358	kCpumMsrRdFn_P6LastIntToIp,
359
360	kCpumMsrRdFn_AmdFam15hTscRate,
361	kCpumMsrRdFn_AmdFam15hLwpCfg,
362	kCpumMsrRdFn_AmdFam15hLwpCbAddr,
363	kCpumMsrRdFn_AmdFam10hMc4MiscN,
364	kCpumMsrRdFn_AmdK8PerfCtlN,
365	kCpumMsrRdFn_AmdK8PerfCtrN,
366	kCpumMsrRdFn_AmdK8SysCfg, /*< Range value returned. /
367	kCpumMsrRdFn_AmdK8HwCr,
368	kCpumMsrRdFn_AmdK8IorrBaseN,
369	kCpumMsrRdFn_AmdK8IorrMaskN,
370	kCpumMsrRdFn_AmdK8TopOfMemN,
371	kCpumMsrRdFn_AmdK8NbCfg1,
372	kCpumMsrRdFn_AmdK8McXcptRedir,
373	kCpumMsrRdFn_AmdK8CpuNameN,
374	kCpumMsrRdFn_AmdK8HwThermalCtrl, /*< Range value returned. /
375	kCpumMsrRdFn_AmdK8SwThermalCtrl,
376	kCpumMsrRdFn_AmdK8FidVidControl, /*< Range value returned. /
377	kCpumMsrRdFn_AmdK8FidVidStatus, /*< Range value returned. /
378	kCpumMsrRdFn_AmdK8McCtlMaskN,
379	kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
380	kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
381	kCpumMsrRdFn_AmdK8IntPendingMessage,
382	kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
383	kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
384	kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
385	kCpumMsrRdFn_AmdFam10hPStateCurLimit, /*< Returns range value. /
386	kCpumMsrRdFn_AmdFam10hPStateControl, /*< Returns range value. /
387	kCpumMsrRdFn_AmdFam10hPStateStatus, /*< Returns range value. /
388	kCpumMsrRdFn_AmdFam10hPStateN, /*< Returns range value. This isn't an register index! /
389	kCpumMsrRdFn_AmdFam10hCofVidControl, /*< Returns range value. /
390	kCpumMsrRdFn_AmdFam10hCofVidStatus, /*< Returns range value. /
391	kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
392	kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
393	kCpumMsrRdFn_AmdK8SmmBase,
394	kCpumMsrRdFn_AmdK8SmmAddr,
395	kCpumMsrRdFn_AmdK8SmmMask,
396	kCpumMsrRdFn_AmdK8VmCr,
397	kCpumMsrRdFn_AmdK8IgnNe,
398	kCpumMsrRdFn_AmdK8SmmCtl,
399	kCpumMsrRdFn_AmdK8VmHSavePa,
400	kCpumMsrRdFn_AmdFam10hVmLockKey,
401	kCpumMsrRdFn_AmdFam10hSmmLockKey,
402	kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
403	kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
404	kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
405	kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
406	kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
407	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
408	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
409	kCpumMsrRdFn_AmdK7MicrocodeCtl, /*< Returns range value. /
410	kCpumMsrRdFn_AmdK7ClusterIdMaybe, /*< Returns range value. /
411	kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
412	kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
413	kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
414	kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
415	kCpumMsrRdFn_AmdK8PatchLevel, /*< Returns range value. /
416	kCpumMsrRdFn_AmdK7DebugStatusMaybe,
417	kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
418	kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
419	kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
420	kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
421	kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
422	kCpumMsrRdFn_AmdK7NodeId,
423	kCpumMsrRdFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
424	kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
425	kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
426	kCpumMsrRdFn_AmdK7LoadStoreCfg,
427	kCpumMsrRdFn_AmdK7InstrCacheCfg,
428	kCpumMsrRdFn_AmdK7DataCacheCfg,
429	kCpumMsrRdFn_AmdK7BusUnitCfg,
430	kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
431	kCpumMsrRdFn_AmdFam15hFpuCfg,
432	kCpumMsrRdFn_AmdFam15hDecoderCfg,
433	kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
434	kCpumMsrRdFn_AmdFam15hCombUnitCfg,
435	kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
436	kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
437	kCpumMsrRdFn_AmdFam15hExecUnitCfg,
438	kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
439	kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
440	kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
441	kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
442	kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
443	kCpumMsrRdFn_AmdFam10hIbsOpRip,
444	kCpumMsrRdFn_AmdFam10hIbsOpData,
445	kCpumMsrRdFn_AmdFam10hIbsOpData2,
446	kCpumMsrRdFn_AmdFam10hIbsOpData3,
447	kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
448	kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
449	kCpumMsrRdFn_AmdFam10hIbsCtl,
450	kCpumMsrRdFn_AmdFam14hIbsBrTarget,
451
452	kCpumMsrRdFn_Gim,
453
454	/** End of valid MSR read function indexes. */
455	kCpumMsrRdFn_End
456	} CPUMMSRRDFN;
457
458	/**
459	* MSR write functions.
460	*/
461	typedef enum CPUMMSRWRFN
462	{
463	/** Invalid zero value. */
464	kCpumMsrWrFn_Invalid = 0,
465	/** Writes are ignored, the fWrGpMask is observed though. */
466	kCpumMsrWrFn_IgnoreWrite,
467	/** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
468	kCpumMsrWrFn_ReadOnly,
469	/** Alias to the MSR range starting at the MSR given by
470	* CPUMMSRRANGE::uValue. Must be used in pair with
471	* kCpumMsrRdFn_MsrAlias. */
472	kCpumMsrWrFn_MsrAlias,
473
474	kCpumMsrWrFn_Ia32P5McAddr,
475	kCpumMsrWrFn_Ia32P5McType,
476	kCpumMsrWrFn_Ia32TimestampCounter,
477	kCpumMsrWrFn_Ia32ApicBase,
478	kCpumMsrWrFn_Ia32FeatureControl,
479	kCpumMsrWrFn_Ia32BiosSignId,
480	kCpumMsrWrFn_Ia32BiosUpdateTrigger,
481	kCpumMsrWrFn_Ia32SmmMonitorCtl,
482	kCpumMsrWrFn_Ia32PmcN,
483	kCpumMsrWrFn_Ia32MonitorFilterLineSize,
484	kCpumMsrWrFn_Ia32MPerf,
485	kCpumMsrWrFn_Ia32APerf,
486	kCpumMsrWrFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
487	kCpumMsrWrFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
488	kCpumMsrWrFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
489	kCpumMsrWrFn_Ia32MtrrDefType,
490	kCpumMsrWrFn_Ia32Pat,
491	kCpumMsrWrFn_Ia32SysEnterCs,
492	kCpumMsrWrFn_Ia32SysEnterEsp,
493	kCpumMsrWrFn_Ia32SysEnterEip,
494	kCpumMsrWrFn_Ia32McgStatus,
495	kCpumMsrWrFn_Ia32McgCtl,
496	kCpumMsrWrFn_Ia32DebugCtl,
497	kCpumMsrWrFn_Ia32SmrrPhysBase,
498	kCpumMsrWrFn_Ia32SmrrPhysMask,
499	kCpumMsrWrFn_Ia32PlatformDcaCap,
500	kCpumMsrWrFn_Ia32Dca0Cap,
501	kCpumMsrWrFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
502	kCpumMsrWrFn_Ia32PerfStatus,
503	kCpumMsrWrFn_Ia32PerfCtl,
504	kCpumMsrWrFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
505	kCpumMsrWrFn_Ia32PerfCapabilities,
506	kCpumMsrWrFn_Ia32FixedCtrCtrl,
507	kCpumMsrWrFn_Ia32PerfGlobalStatus,
508	kCpumMsrWrFn_Ia32PerfGlobalCtrl,
509	kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
510	kCpumMsrWrFn_Ia32PebsEnable,
511	kCpumMsrWrFn_Ia32ClockModulation,
512	kCpumMsrWrFn_Ia32ThermInterrupt,
513	kCpumMsrWrFn_Ia32ThermStatus,
514	kCpumMsrWrFn_Ia32Therm2Ctl,
515	kCpumMsrWrFn_Ia32MiscEnable,
516	kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
517	kCpumMsrWrFn_Ia32McNCtl2, /*< Takes register number of start of range. /
518	kCpumMsrWrFn_Ia32DsArea,
519	kCpumMsrWrFn_Ia32TscDeadline,
520	kCpumMsrWrFn_Ia32X2ApicN,
521	kCpumMsrWrFn_Ia32DebugInterface,
522	kCpumMsrWrFn_Ia32SpecCtrl,
523	kCpumMsrWrFn_Ia32PredCmd,
524	kCpumMsrWrFn_Ia32FlushCmd,
525
526	kCpumMsrWrFn_Amd64Efer,
527	kCpumMsrWrFn_Amd64SyscallTarget,
528	kCpumMsrWrFn_Amd64LongSyscallTarget,
529	kCpumMsrWrFn_Amd64CompSyscallTarget,
530	kCpumMsrWrFn_Amd64SyscallFlagMask,
531	kCpumMsrWrFn_Amd64FsBase,
532	kCpumMsrWrFn_Amd64GsBase,
533	kCpumMsrWrFn_Amd64KernelGsBase,
534	kCpumMsrWrFn_Amd64TscAux,
535	kCpumMsrWrFn_IntelEblCrPowerOn,
536	kCpumMsrWrFn_IntelP4EbcHardPowerOn,
537	kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
538	kCpumMsrWrFn_IntelP4EbcFrequencyId,
539	kCpumMsrWrFn_IntelFlexRatio,
540	kCpumMsrWrFn_IntelPkgCStConfigControl,
541	kCpumMsrWrFn_IntelPmgIoCaptureBase,
542	kCpumMsrWrFn_IntelLastBranchFromToN,
543	kCpumMsrWrFn_IntelLastBranchFromN,
544	kCpumMsrWrFn_IntelLastBranchToN,
545	kCpumMsrWrFn_IntelLastBranchTos,
546	kCpumMsrWrFn_IntelBblCrCtl,
547	kCpumMsrWrFn_IntelBblCrCtl3,
548	kCpumMsrWrFn_IntelI7TemperatureTarget,
549	kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /*< Takes register number. /
550	kCpumMsrWrFn_IntelI7MiscPwrMgmt,
551	kCpumMsrWrFn_IntelP6CrN,
552	kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
553	kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
554	kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
555	kCpumMsrWrFn_IntelI7SandyAesNiCtl,
556	kCpumMsrWrFn_IntelI7TurboRatioLimit,
557	kCpumMsrWrFn_IntelI7LbrSelect,
558	kCpumMsrWrFn_IntelI7SandyErrorControl,
559	kCpumMsrWrFn_IntelI7PowerCtl,
560	kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
561	kCpumMsrWrFn_IntelI7PebsLdLat,
562	kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
563	kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
564	kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /*< R/O but found writable bits on a Silvermont CPU here. /
565	kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
566	kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /*< R/O but found writable bits on a Silvermont CPU here. /
567	kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
568	kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
569	kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
570	kCpumMsrWrFn_IntelI7RaplPp0Policy,
571	kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
572	kCpumMsrWrFn_IntelI7RaplPp1Policy,
573	kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
574	kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
575	kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
576	kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
577	kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
578	kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
579	kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
580	kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
581	kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
582	kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
583	kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
584	kCpumMsrWrFn_IntelCore1ExtConfig,
585	kCpumMsrWrFn_IntelCore1DtsCalControl,
586	kCpumMsrWrFn_IntelCore2PeciControl,
587
588	kCpumMsrWrFn_P6LastIntFromIp,
589	kCpumMsrWrFn_P6LastIntToIp,
590
591	kCpumMsrWrFn_AmdFam15hTscRate,
592	kCpumMsrWrFn_AmdFam15hLwpCfg,
593	kCpumMsrWrFn_AmdFam15hLwpCbAddr,
594	kCpumMsrWrFn_AmdFam10hMc4MiscN,
595	kCpumMsrWrFn_AmdK8PerfCtlN,
596	kCpumMsrWrFn_AmdK8PerfCtrN,
597	kCpumMsrWrFn_AmdK8SysCfg,
598	kCpumMsrWrFn_AmdK8HwCr,
599	kCpumMsrWrFn_AmdK8IorrBaseN,
600	kCpumMsrWrFn_AmdK8IorrMaskN,
601	kCpumMsrWrFn_AmdK8TopOfMemN,
602	kCpumMsrWrFn_AmdK8NbCfg1,
603	kCpumMsrWrFn_AmdK8McXcptRedir,
604	kCpumMsrWrFn_AmdK8CpuNameN,
605	kCpumMsrWrFn_AmdK8HwThermalCtrl,
606	kCpumMsrWrFn_AmdK8SwThermalCtrl,
607	kCpumMsrWrFn_AmdK8FidVidControl,
608	kCpumMsrWrFn_AmdK8McCtlMaskN,
609	kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
610	kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
611	kCpumMsrWrFn_AmdK8IntPendingMessage,
612	kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
613	kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
614	kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
615	kCpumMsrWrFn_AmdFam10hPStateControl,
616	kCpumMsrWrFn_AmdFam10hPStateStatus,
617	kCpumMsrWrFn_AmdFam10hPStateN,
618	kCpumMsrWrFn_AmdFam10hCofVidControl,
619	kCpumMsrWrFn_AmdFam10hCofVidStatus,
620	kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
621	kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
622	kCpumMsrWrFn_AmdK8SmmBase,
623	kCpumMsrWrFn_AmdK8SmmAddr,
624	kCpumMsrWrFn_AmdK8SmmMask,
625	kCpumMsrWrFn_AmdK8VmCr,
626	kCpumMsrWrFn_AmdK8IgnNe,
627	kCpumMsrWrFn_AmdK8SmmCtl,
628	kCpumMsrWrFn_AmdK8VmHSavePa,
629	kCpumMsrWrFn_AmdFam10hVmLockKey,
630	kCpumMsrWrFn_AmdFam10hSmmLockKey,
631	kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
632	kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
633	kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
634	kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
635	kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
636	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
637	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
638	kCpumMsrWrFn_AmdK7MicrocodeCtl,
639	kCpumMsrWrFn_AmdK7ClusterIdMaybe,
640	kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
641	kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
642	kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
643	kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
644	kCpumMsrWrFn_AmdK8PatchLoader,
645	kCpumMsrWrFn_AmdK7DebugStatusMaybe,
646	kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
647	kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
648	kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
649	kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
650	kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
651	kCpumMsrWrFn_AmdK7NodeId,
652	kCpumMsrWrFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
653	kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
654	kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
655	kCpumMsrWrFn_AmdK7LoadStoreCfg,
656	kCpumMsrWrFn_AmdK7InstrCacheCfg,
657	kCpumMsrWrFn_AmdK7DataCacheCfg,
658	kCpumMsrWrFn_AmdK7BusUnitCfg,
659	kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
660	kCpumMsrWrFn_AmdFam15hFpuCfg,
661	kCpumMsrWrFn_AmdFam15hDecoderCfg,
662	kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
663	kCpumMsrWrFn_AmdFam15hCombUnitCfg,
664	kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
665	kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
666	kCpumMsrWrFn_AmdFam15hExecUnitCfg,
667	kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
668	kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
669	kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
670	kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
671	kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
672	kCpumMsrWrFn_AmdFam10hIbsOpRip,
673	kCpumMsrWrFn_AmdFam10hIbsOpData,
674	kCpumMsrWrFn_AmdFam10hIbsOpData2,
675	kCpumMsrWrFn_AmdFam10hIbsOpData3,
676	kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
677	kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
678	kCpumMsrWrFn_AmdFam10hIbsCtl,
679	kCpumMsrWrFn_AmdFam14hIbsBrTarget,
680
681	kCpumMsrWrFn_Gim,
682
683	/** End of valid MSR write function indexes. */
684	kCpumMsrWrFn_End
685	} CPUMMSRWRFN;
686
687	/**
688	* MSR range.
689	*/
690	typedef struct CPUMMSRRANGE
691	{
692	/** The first MSR. [0] */
693	uint32_t uFirst;
694	/** The last MSR. [4] */
695	uint32_t uLast;
696	/** The read function (CPUMMSRRDFN). [8] */
697	uint16_t enmRdFn;
698	/** The write function (CPUMMSRWRFN). [10] */
699	uint16_t enmWrFn;
700	/** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
701	* UINT16_MAX if not used by the read and write functions. [12] */
702	uint32_t offCpumCpu : 24;
703	/** Reserved for future hacks. [15] */
704	uint32_t fReserved : 8;
705	/** The init/read value. [16]
706	* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
707	* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
708	* offset into CPUM. */
709	uint64_t uValue;
710	/** The bits to ignore when writing. [24] */
711	uint64_t fWrIgnMask;
712	/** The bits that will cause a GP(0) when writing. [32]
713	* This is always checked prior to calling the write function. Using
714	* UINT64_MAX effectively marks the MSR as read-only. */
715	uint64_t fWrGpMask;
716	/** The register name, if applicable. [40] */
717	char szName[56];
718
719	/** The number of reads. */
720	STAMCOUNTER cReads;
721	/** The number of writes. */
722	STAMCOUNTER cWrites;
723	/** The number of times ignored bits were written. */
724	STAMCOUNTER cIgnoredBits;
725	/** The number of GPs generated. */
726	STAMCOUNTER cGps;
727	} CPUMMSRRANGE;
728	#ifndef VBOX_FOR_DTRACE_LIB
729	AssertCompileSize(CPUMMSRRANGE, 128);
730	#endif
731	/** Pointer to an MSR range. */
732	typedef CPUMMSRRANGE *PCPUMMSRRANGE;
733	/** Pointer to a const MSR range. */
734	typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
735
736
737	/**
738	* MSRs which are required while exploding features.
739	*/
740	typedef struct CPUMMSRS
741	{
742	union
743	{
744	VMXMSRS vmx;
745	SVMMSRS svm;
746	} hwvirt;
747	} CPUMMSRS;
748	/** Pointer to an CPUMMSRS struct. */
749	typedef CPUMMSRS *PCPUMMSRS;
750	/** Pointer to a const CPUMMSRS struct. */
751	typedef CPUMMSRS const *PCCPUMMSRS;
752
753
754	/**
755	* CPU database entry.
756	*/
757	typedef struct CPUMDBENTRY
758	{
759	/** The CPU name. */
760	const char *pszName;
761	/** The full CPU name. */
762	const char *pszFullName;
763	/** The CPU vendor (CPUMCPUVENDOR). */
764	uint8_t enmVendor;
765	/** The CPU family. */
766	uint8_t uFamily;
767	/** The CPU model. */
768	uint8_t uModel;
769	/** The CPU stepping. */
770	uint8_t uStepping;
771	/** The microarchitecture. */
772	CPUMMICROARCH enmMicroarch;
773	/** Scalable bus frequency used for reporting other frequencies. */
774	uint64_t uScalableBusFreq;
775	/** Flags - CPUMDB_F_XXX. */
776	uint32_t fFlags;
777	/** The maximum physical address with of the CPU. This should correspond to
778	* the value in CPUID leaf 0x80000008 when present. */
779	uint8_t cMaxPhysAddrWidth;
780	/** The MXCSR mask. */
781	uint32_t fMxCsrMask;
782	/** Pointer to an array of CPUID leaves. */
783	PCCPUMCPUIDLEAF paCpuIdLeaves;
784	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
785	uint32_t cCpuIdLeaves;
786	/** The method used to deal with unknown CPUID leaves. */
787	CPUMUNKNOWNCPUID enmUnknownCpuId;
788	/** The default unknown CPUID value. */
789	CPUMCPUID DefUnknownCpuId;
790
791	/** MSR mask. Several microarchitectures ignore the higher bits of ECX in
792	* the RDMSR and WRMSR instructions. */
793	uint32_t fMsrMask;
794
795	/** The number of ranges in the table pointed to b paMsrRanges. */
796	uint32_t cMsrRanges;
797	/** MSR ranges for this CPU. */
798	PCCPUMMSRRANGE paMsrRanges;
799	} CPUMDBENTRY;
800	/** Pointer to a const CPU database entry. */
801	typedef CPUMDBENTRY const *PCCPUMDBENTRY;
802
803	/** @name CPUMDB_F_XXX - CPUDBENTRY::fFlags
804	* @{ */
805	/** Should execute all in IEM.
806	* @todo Implement this - currently done in Main... */
807	#define CPUMDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
808	/** @} */
809
810
811
812	#ifndef VBOX_FOR_DTRACE_LIB
813
814	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
815	VMMDECL(int) CPUMCpuIdCollectLeavesX86(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves);
816	VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
817	#endif
818
819	VMM_INT_DECL(bool) CPUMAssertGuestRFlagsCookie(PVM pVM, PVMCPU pVCpu);
820
821
822	/** @name Guest Register Getters.
823	* @{ */
824	VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR);
825	VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit);
826	VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden);
827	VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu);
828	VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t pGCPtrBase, uint32_t pcbLimit);
829	VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu);
830	VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu);
831	VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu);
832	VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu);
833	VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu);
834	VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue);
835	VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu);
836	VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu);
837	VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu);
838	VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu);
839	VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu);
840	VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu);
841	VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu);
842	VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu);
843	VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu);
844	VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu);
845	VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu);
846	VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu);
847	VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu);
848	VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu);
849	VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu);
850	VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu);
851	VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu);
852	VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu);
853	VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu);
854	VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu);
855	VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu);
856	VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu);
857	VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu);
858	VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
859	VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t iLeaf, uint32_t iSubLeaf, int f64BitMode,
860	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx);
861	VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu);
862	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatCtrl(PCVMCPUCC pVCpu);
863	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PCVMCPUCC pVCpu);
864	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPUCC pVCpu);
865	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxEptVpidCap(PCVMCPUCC pVCpu);
866	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *puValue);
867	VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t uValue);
868	/** @} */
869
870	/** @name Guest Register Setters.
871	* @{ */
872	VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
873	VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
874	VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
875	VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
876	VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0);
877	VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
878	VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
879	VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
880	VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0);
881	VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1);
882	VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2);
883	VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3);
884	VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
885	VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7);
886	VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value);
887	VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue);
888	VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
889	VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
890	VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
891	VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
892	VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
893	VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
894	VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
895	VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
896	VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
897	VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
898	VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
899	VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
900	VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
901	VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
902	VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
903	VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
904	VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
905	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
906	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
907	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
908	VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible);
909	VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
910	VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPUCC pVCpu, uint64_t uValue);
911	VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPUCC pVCpu);
912	VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPUCC pVCpu, uint64_t uValue);
913	VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPUCC pVCpu);
914	VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM);
915	VMM_INT_DECL(void) CPUMSetGuestPaePdpes(PVMCPU pVCpu, PCX86PDPE paPaePdpes);
916	VMM_INT_DECL(void) CPUMGetGuestPaePdpes(PVMCPU pVCpu, PX86PDPE paPaePdpes);
917	/** @} */
918
919
920	/** @name Misc Guest Predicate Functions.
921	* @{ */
922	VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu);
923	VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu);
924	VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu);
925	VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu);
926	VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu);
927	VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu);
928	VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu);
929	VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu);
930	VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu);
931	VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu);
932	/** @} */
933
934	/** @name Nested Hardware-Virtualization Helpers.
935	* @{ */
936	VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu);
937	VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu);
938	VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
939	VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
940
941	/* SVM helpers. */
942	VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
943	VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
944	VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx);
945	VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx);
946	VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr);
947	VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
948	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
949	PSVMIOIOEXITINFO pIoExitInfo);
950	VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t pbOffMsrpm, uint8_t puMsrpmBit);
951
952	/* VMX helpers. */
953	VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField);
954	VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess);
955	VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3);
956	VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc);
957	VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick);
958	VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu);
959	VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr);
960	VMM_INT_DECL(bool) CPUMIsGuestVmxEptPagingEnabled(PCVMCPUCC pVCpu);
961	VMM_INT_DECL(bool) CPUMIsGuestVmxEptPaePagingEnabled(PCVMCPUCC pVCpu);
962	VMM_INT_DECL(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PCVMCPUCC pVCpu);
963	/** @} */
964
965	#if !defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS) \|\| defined(DOXYGEN_RUNNING)
966	/** @name Inlined Guest Getters and predicates Functions.
967	* @{ */
968
969	/**
970	* Gets valid CR0 bits for the guest.
971	*
972	* @returns Valid CR0 bits.
973	*/
974	DECLINLINE(uint64_t) CPUMGetGuestCR0ValidMask(void)
975	{
976	return ( X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS
977	\| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_WP \| X86_CR0_AM
978	\| X86_CR0_NW \| X86_CR0_CD \| X86_CR0_PG);
979	}
980
981	/**
982	* Tests if the guest is running in real mode or not.
983	*
984	* @returns true if in real mode, otherwise false.
985	* @param pCtx Current CPU context.
986	*/
987	DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCCPUMCTX pCtx)
988	{
989	return !(pCtx->cr0 & X86_CR0_PE);
990	}
991
992	/**
993	* Tests if the guest is running in real or virtual 8086 mode.
994	*
995	* @returns @c true if it is, @c false if not.
996	* @param pCtx Current CPU context.
997	*/
998	DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCCPUMCTX pCtx)
999	{
1000	return !(pCtx->cr0 & X86_CR0_PE)
1001	\|\| pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1002	}
1003
1004	/**
1005	* Tests if the guest is running in virtual 8086 mode.
1006	*
1007	* @returns @c true if it is, @c false if not.
1008	* @param pCtx Current CPU context.
1009	*/
1010	DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCCPUMCTX pCtx)
1011	{
1012	return (pCtx->eflags.Bits.u1VM == 1);
1013	}
1014
1015	/**
1016	* Tests if the guest is running in paged protected or not.
1017	*
1018	* @returns true if in paged protected mode, otherwise false.
1019	* @param pCtx Current CPU context.
1020	*/
1021	DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1022	{
1023	return (pCtx->cr0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG);
1024	}
1025
1026	/**
1027	* Tests if the guest is running in long mode or not.
1028	*
1029	* @returns true if in long mode, otherwise false.
1030	* @param pCtx Current CPU context.
1031	*/
1032	DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCCPUMCTX pCtx)
1033	{
1034	return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1035	}
1036
1037	VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCCPUMCTX pCtx);
1038
1039	/**
1040	* Tests if the guest is running in 64 bits mode or not.
1041	*
1042	* @returns true if in 64 bits protected mode, otherwise false.
1043	* @param pCtx Current CPU context.
1044	*/
1045	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCCPUMCTX pCtx)
1046	{
1047	if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1048	return false;
1049	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1050	return CPUMIsGuestIn64BitCodeSlow(pCtx);
1051	return pCtx->cs.Attr.n.u1Long;
1052	}
1053
1054	/**
1055	* Tests if the guest has paging enabled or not.
1056	*
1057	* @returns true if paging is enabled, otherwise false.
1058	* @param pCtx Current CPU context.
1059	*/
1060	DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCCPUMCTX pCtx)
1061	{
1062	return !!(pCtx->cr0 & X86_CR0_PG);
1063	}
1064
1065	/**
1066	* Tests if PAE paging is enabled given the relevant control registers.
1067	*
1068	* @returns @c true if in PAE mode, @c false otherwise.
1069	* @param uCr0 The CR0 value.
1070	* @param uCr4 The CR4 value.
1071	* @param uEferMsr The EFER value.
1072	*/
1073	DECLINLINE(bool) CPUMIsPaePagingEnabled(uint64_t uCr0, uint64_t uCr4, uint64_t uEferMsr)
1074	{
1075	/* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1076	than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1077	return ( (uCr4 & X86_CR4_PAE)
1078	&& (uCr0 & X86_CR0_PG)
1079	&& !(uEferMsr & MSR_K6_EFER_LMA));
1080	}
1081
1082	/**
1083	* Tests if the guest is running in PAE mode or not.
1084	*
1085	* @returns @c true if in PAE mode, @c false otherwise.
1086	* @param pCtx Current CPU context.
1087	*/
1088	DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCCPUMCTX pCtx)
1089	{
1090	return CPUMIsPaePagingEnabled(pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
1091	}
1092
1093	/**
1094	* Tests if the guest has AMD SVM enabled or not.
1095	*
1096	* @returns true if SMV is enabled, otherwise false.
1097	* @param pCtx Current CPU context.
1098	*/
1099	DECLINLINE(bool) CPUMIsGuestSvmEnabled(PCCPUMCTX pCtx)
1100	{
1101	return RT_BOOL(pCtx->msrEFER & MSR_K6_EFER_SVME);
1102	}
1103
1104	/**
1105	* Tests if the guest has Intel VT-x enabled or not.
1106	*
1107	* @returns true if VMX is enabled, otherwise false.
1108	* @param pCtx Current CPU context.
1109	*/
1110	DECLINLINE(bool) CPUMIsGuestVmxEnabled(PCCPUMCTX pCtx)
1111	{
1112	return RT_BOOL(pCtx->cr4 & X86_CR4_VMXE);
1113	}
1114
1115	/**
1116	* Returns the guest's global-interrupt (GIF) flag.
1117	*
1118	* @returns true when global-interrupts are enabled, otherwise false.
1119	* @param pCtx Current CPU context.
1120	*/
1121	DECLINLINE(bool) CPUMGetGuestGif(PCCPUMCTX pCtx)
1122	{
1123	return pCtx->hwvirt.fGif;
1124	}
1125
1126	/**
1127	* Sets the guest's global-interrupt flag (GIF).
1128	*
1129	* @param pCtx Current CPU context.
1130	* @param fGif The value to set.
1131	*/
1132	DECLINLINE(void) CPUMSetGuestGif(PCPUMCTX pCtx, bool fGif)
1133	{
1134	pCtx->hwvirt.fGif = fGif;
1135	}
1136
1137	/**
1138	* Checks if we're in an "interrupt shadow", i.e. after a STI, POP SS or MOV SS.
1139	*
1140	* This also inhibit NMIs, except perhaps for nested guests.
1141	*
1142	* @returns true if interrupts are inhibited by interrupt shadow, false if not.
1143	* @param pCtx Current guest CPU context.
1144	* @note Requires pCtx->rip to be up to date.
1145	* @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
1146	* differs from CPUMCTX::rip.
1147	*/
1148	DECLINLINE(bool) CPUMIsInInterruptShadow(PCCPUMCTX pCtx)
1149	{
1150	if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW))
1151	return false;
1152
1153	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1154	return pCtx->uRipInhibitInt == pCtx->rip;
1155	}
1156
1157	/**
1158	* Checks if we're in an "interrupt shadow", i.e. after a STI, POP SS or MOV SS,
1159	* updating the state if stale.
1160	*
1161	* This also inhibit NMIs, except perhaps for nested guests.
1162	*
1163	* @retval true if interrupts are inhibited by interrupt shadow.
1164	* @retval false if not.
1165	* @param pCtx Current guest CPU context.
1166	* @note Requires pCtx->rip to be up to date.
1167	*/
1168	DECLINLINE(bool) CPUMIsInInterruptShadowWithUpdate(PCPUMCTX pCtx)
1169	{
1170	if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW))
1171	return false;
1172
1173	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1174	if (pCtx->uRipInhibitInt == pCtx->rip)
1175	return true;
1176
1177	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1178	return false;
1179	}
1180
1181	/**
1182	* Checks if we're in an "interrupt shadow", i.e. after a STI, POP SS or MOV SS,
1183	* updating the state if stale while also returning the reason for the interrupt
1184	* inhibition.
1185	*
1186	* This also inhibit NMIs, except perhaps for nested guests.
1187	*
1188	* @retval true if interrupts are inhibited by interrupt shadow.
1189	* @retval false if not.
1190	* @param pCtx Current guest CPU context.
1191	* @param pfInhibitShw Where to store which type of interrupt inhibition was
1192	* active (see CPUMCTX_INHIBIT_XXX).
1193	* @note Requires pCtx->rip to be up to date.
1194	*/
1195	DECLINLINE(bool) CPUMIsInInterruptShadowWithUpdateEx(PCPUMCTX pCtx, uint32_t *pfInhibitShw)
1196	{
1197	Assert(pfInhibitShw);
1198	*pfInhibitShw = pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW;
1199	return CPUMIsInInterruptShadowWithUpdate(pCtx);
1200	}
1201
1202	/**
1203	* Checks if we're in an "interrupt shadow" due to a POP SS or MOV SS
1204	* instruction.
1205	*
1206	* This also inhibit NMIs, except perhaps for nested guests.
1207	*
1208	* @retval true if interrupts are inhibited due to POP/MOV SS.
1209	* @retval false if not.
1210	* @param pCtx Current guest CPU context.
1211	* @note Requires pCtx->rip to be up to date.
1212	* @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
1213	* differs from CPUMCTX::rip.
1214	* @note Both CPUMIsInInterruptShadowAfterSti() and this function may return
1215	* true depending on the execution engine being used.
1216	*/
1217	DECLINLINE(bool) CPUMIsInInterruptShadowAfterSs(PCCPUMCTX pCtx)
1218	{
1219	if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW_SS))
1220	return false;
1221
1222	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1223	return pCtx->uRipInhibitInt == pCtx->rip;
1224	}
1225
1226	/**
1227	* Checks if we're in an "interrupt shadow" due to an STI instruction.
1228	*
1229	* This also inhibit NMIs, except perhaps for nested guests.
1230	*
1231	* @retval true if interrupts are inhibited due to STI.
1232	* @retval false if not.
1233	* @param pCtx Current guest CPU context.
1234	* @note Requires pCtx->rip to be up to date.
1235	* @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
1236	* differs from CPUMCTX::rip.
1237	* @note Both CPUMIsInInterruptShadowAfterSs() and this function may return
1238	* true depending on the execution engine being used.
1239	*/
1240	DECLINLINE(bool) CPUMIsInInterruptShadowAfterSti(PCCPUMCTX pCtx)
1241	{
1242	if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW_STI))
1243	return false;
1244
1245	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1246	return pCtx->uRipInhibitInt == pCtx->rip;
1247	}
1248
1249	/**
1250	* Sets the "interrupt shadow" flag, after a STI, POP SS or MOV SS instruction.
1251	*
1252	* @param pCtx Current guest CPU context.
1253	* @note Requires pCtx->rip to be up to date.
1254	*/
1255	DECLINLINE(void) CPUMSetInInterruptShadow(PCPUMCTX pCtx)
1256	{
1257	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1258	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW;
1259	pCtx->uRipInhibitInt = pCtx->rip;
1260	}
1261
1262	/**
1263	* Sets the "interrupt shadow" flag, after a STI, POP SS or MOV SS instruction,
1264	* extended version.
1265	*
1266	* @param pCtx Current guest CPU context.
1267	* @param rip The RIP for which it is inhibited.
1268	*/
1269	DECLINLINE(void) CPUMSetInInterruptShadowEx(PCPUMCTX pCtx, uint64_t rip)
1270	{
1271	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW;
1272	pCtx->uRipInhibitInt = rip;
1273	}
1274
1275	/**
1276	* Sets the "interrupt shadow" flag after a POP SS or MOV SS instruction.
1277	*
1278	* @param pCtx Current guest CPU context.
1279	* @note Requires pCtx->rip to be up to date.
1280	*/
1281	DECLINLINE(void) CPUMSetInInterruptShadowSs(PCPUMCTX pCtx)
1282	{
1283	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1284	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW_SS;
1285	pCtx->uRipInhibitInt = pCtx->rip;
1286	}
1287
1288	/**
1289	* Sets the "interrupt shadow" flag after an STI instruction.
1290	*
1291	* @param pCtx Current guest CPU context.
1292	* @note Requires pCtx->rip to be up to date.
1293	*/
1294	DECLINLINE(void) CPUMSetInInterruptShadowSti(PCPUMCTX pCtx)
1295	{
1296	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1297	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW_STI;
1298	pCtx->uRipInhibitInt = pCtx->rip;
1299	}
1300
1301	/**
1302	* Clears the "interrupt shadow" flag.
1303	*
1304	* @param pCtx Current guest CPU context.
1305	*/
1306	DECLINLINE(void) CPUMClearInterruptShadow(PCPUMCTX pCtx)
1307	{
1308	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1309	}
1310
1311	/**
1312	* Update the "interrupt shadow" flag.
1313	*
1314	* @param pCtx Current guest CPU context.
1315	* @param fInhibited The new state.
1316	* @note Requires pCtx->rip to be up to date.
1317	*/
1318	DECLINLINE(void) CPUMUpdateInterruptShadow(PCPUMCTX pCtx, bool fInhibited)
1319	{
1320	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1321	if (!fInhibited)
1322	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1323	else
1324	{
1325	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW;
1326	pCtx->uRipInhibitInt = pCtx->rip;
1327	}
1328	}
1329
1330	/**
1331	* Update the "interrupt shadow" flag, extended version.
1332	*
1333	* @returns fInhibited.
1334	* @param pCtx Current guest CPU context.
1335	* @param fInhibited The new state.
1336	* @param rip The RIP for which it is inhibited.
1337	*/
1338	DECLINLINE(bool) CPUMUpdateInterruptShadowEx(PCPUMCTX pCtx, bool fInhibited, uint64_t rip)
1339	{
1340	if (!fInhibited)
1341	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1342	else
1343	{
1344	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW;
1345	pCtx->uRipInhibitInt = rip;
1346	}
1347	return fInhibited;
1348	}
1349
1350	/**
1351	* Update the two "interrupt shadow" flags separately, extended version.
1352	*
1353	* @param pCtx Current guest CPU context.
1354	* @param fInhibitedBySs The new state for the MOV SS & POP SS aspect.
1355	* @param fInhibitedBySti The new state for the STI aspect.
1356	* @param rip The RIP for which it is inhibited.
1357	*/
1358	DECLINLINE(void) CPUMUpdateInterruptShadowSsStiEx(PCPUMCTX pCtx, bool fInhibitedBySs, bool fInhibitedBySti, uint64_t rip)
1359	{
1360	if (!(fInhibitedBySs \| fInhibitedBySti))
1361	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1362	else
1363	{
1364	pCtx->eflags.uBoth \|= (fInhibitedBySs ? CPUMCTX_INHIBIT_SHADOW_SS : UINT32_C(0))
1365	\| (fInhibitedBySti ? CPUMCTX_INHIBIT_SHADOW_STI : UINT32_C(0));
1366	pCtx->uRipInhibitInt = rip;
1367	}
1368	}
1369
1370	/* VMX forward declarations used by extended function versions: */
1371	DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx);
1372	DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PCCPUMCTX pCtx, uint32_t uPinCtls);
1373	DECLINLINE(bool) CPUMIsGuestVmxVirtNmiBlocking(PCCPUMCTX pCtx);
1374	DECLINLINE(void) CPUMSetGuestVmxVirtNmiBlocking(PCPUMCTX pCtx, bool fBlocking);
1375
1376	/**
1377	* Checks whether interrupts, include NMIs, are inhibited by pending NMI
1378	* delivery.
1379	*
1380	* This only checks the inhibit mask.
1381	*
1382	* @retval true if interrupts are inhibited by NMI handling.
1383	* @retval false if interrupts are not inhibited by NMI handling.
1384	* @param pCtx Current guest CPU context.
1385	*/
1386	DECLINLINE(bool) CPUMAreInterruptsInhibitedByNmi(PCCPUMCTX pCtx)
1387	{
1388	return (pCtx->eflags.uBoth & CPUMCTX_INHIBIT_NMI) != 0;
1389	}
1390
1391	/**
1392	* Extended version of CPUMAreInterruptsInhibitedByNmi() that takes VMX non-root
1393	* mode into account when check whether interrupts are inhibited by NMI.
1394	*
1395	* @retval true if interrupts are inhibited by NMI handling.
1396	* @retval false if interrupts are not inhibited by NMI handling.
1397	* @param pCtx Current guest CPU context.
1398	*/
1399	DECLINLINE(bool) CPUMAreInterruptsInhibitedByNmiEx(PCCPUMCTX pCtx)
1400	{
1401	/* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
1402	if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1403	\|\| !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1404	return CPUMAreInterruptsInhibitedByNmi(pCtx);
1405	return CPUMIsGuestVmxVirtNmiBlocking(pCtx);
1406	}
1407
1408	/**
1409	* Marks interrupts, include NMIs, as inhibited by pending NMI delivery.
1410	*
1411	* @param pCtx Current guest CPU context.
1412	*/
1413	DECLINLINE(void) CPUMSetInterruptInhibitingByNmi(PCPUMCTX pCtx)
1414	{
1415	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_NMI;
1416	}
1417
1418	/**
1419	* Extended version of CPUMSetInterruptInhibitingByNmi() that takes VMX non-root
1420	* mode into account when marking interrupts as inhibited by NMI.
1421	*
1422	* @param pCtx Current guest CPU context.
1423	*/
1424	DECLINLINE(void) CPUMSetInterruptInhibitingByNmiEx(PCPUMCTX pCtx)
1425	{
1426	/* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
1427	if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1428	\|\| !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1429	CPUMSetInterruptInhibitingByNmi(pCtx);
1430	else
1431	CPUMSetGuestVmxVirtNmiBlocking(pCtx, true);
1432	}
1433
1434	/**
1435	* Marks interrupts, include NMIs, as no longer inhibited by pending NMI
1436	* delivery.
1437	*
1438	* @param pCtx Current guest CPU context.
1439	*/
1440	DECLINLINE(void) CPUMClearInterruptInhibitingByNmi(PCPUMCTX pCtx)
1441	{
1442	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_NMI;
1443	}
1444
1445	/**
1446	* Extended version of CPUMClearInterruptInhibitingByNmi() that takes VMX
1447	* non-root mode into account when doing the updating.
1448	*
1449	* @param pCtx Current guest CPU context.
1450	*/
1451	DECLINLINE(void) CPUMClearInterruptInhibitingByNmiEx(PCPUMCTX pCtx)
1452	{
1453	/* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
1454	if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1455	\|\| !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1456	CPUMClearInterruptInhibitingByNmi(pCtx);
1457	else
1458	CPUMSetGuestVmxVirtNmiBlocking(pCtx, false);
1459	}
1460
1461	/**
1462	* Update whether interrupts, include NMIs, are inhibited by pending NMI
1463	* delivery.
1464	*
1465	* @param pCtx Current guest CPU context.
1466	* @param fInhibited The new state.
1467	*/
1468	DECLINLINE(void) CPUMUpdateInterruptInhibitingByNmi(PCPUMCTX pCtx, bool fInhibited)
1469	{
1470	if (!fInhibited)
1471	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_NMI;
1472	else
1473	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_NMI;
1474	}
1475
1476	/**
1477	* Extended version of CPUMUpdateInterruptInhibitingByNmi() that takes VMX
1478	* non-root mode into account when doing the updating.
1479	*
1480	* @param pCtx Current guest CPU context.
1481	* @param fInhibited The new state.
1482	*/
1483	DECLINLINE(void) CPUMUpdateInterruptInhibitingByNmiEx(PCPUMCTX pCtx, bool fInhibited)
1484	{
1485	/*
1486	* Set the state of guest-NMI blocking in any of the following cases:
1487	* - We're not executing a nested-guest.
1488	* - We're executing an SVM nested-guest[1].
1489	* - We're executing a VMX nested-guest without virtual-NMIs enabled.
1490	*
1491	* [1] -- SVM does not support virtual-NMIs or virtual-NMI blocking.
1492	* SVM hypervisors must track NMI blocking themselves by intercepting
1493	* the IRET instruction after injection of an NMI.
1494	*/
1495	if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1496	\|\| !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1497	CPUMUpdateInterruptInhibitingByNmi(pCtx, fInhibited);
1498	/*
1499	* Set the state of virtual-NMI blocking, if we are executing a
1500	* VMX nested-guest with virtual-NMIs enabled.
1501	*/
1502	else
1503	CPUMSetGuestVmxVirtNmiBlocking(pCtx, fInhibited);
1504	}
1505
1506
1507	/**
1508	* Checks if we are executing inside an SVM nested hardware-virtualized guest.
1509	*
1510	* @returns @c true if in SVM nested-guest mode, @c false otherwise.
1511	* @param pCtx Current CPU context.
1512	*/
1513	DECLINLINE(bool) CPUMIsGuestInSvmNestedHwVirtMode(PCCPUMCTX pCtx)
1514	{
1515	/*
1516	* With AMD-V, the VMRUN intercept is a pre-requisite to entering SVM guest-mode.
1517	* See AMD spec. 15.5 "VMRUN instruction" subsection "Canonicalization and Consistency Checks".
1518	*/
1519	#ifndef IN_RC
1520	if ( pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM
1521	\|\| !(pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN))
1522	return false;
1523	return true;
1524	#else
1525	NOREF(pCtx);
1526	return false;
1527	#endif
1528	}
1529
1530	/**
1531	* Checks if the guest is in VMX non-root operation.
1532	*
1533	* @returns @c true if in VMX non-root operation, @c false otherwise.
1534	* @param pCtx Current CPU context.
1535	*/
1536	DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx)
1537	{
1538	#ifndef IN_RC
1539	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
1540	return false;
1541	Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode \|\| pCtx->hwvirt.vmx.fInVmxRootMode);
1542	return pCtx->hwvirt.vmx.fInVmxNonRootMode;
1543	#else
1544	NOREF(pCtx);
1545	return false;
1546	#endif
1547	}
1548
1549	/**
1550	* Checks if we are executing inside an SVM or VMX nested hardware-virtualized
1551	* guest.
1552	*
1553	* @returns @c true if in nested-guest mode, @c false otherwise.
1554	* @param pCtx Current CPU context.
1555	*/
1556	DECLINLINE(bool) CPUMIsGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
1557	{
1558	#if 0
1559	return CPUMIsGuestInVmxNonRootMode(pCtx) \|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
1560	#else
1561	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_NONE)
1562	return false;
1563	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX)
1564	{
1565	Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode \|\| pCtx->hwvirt.vmx.fInVmxRootMode);
1566	return pCtx->hwvirt.vmx.fInVmxNonRootMode;
1567	}
1568	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1569	return RT_BOOL(pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN);
1570	#endif
1571	}
1572
1573	/**
1574	* Checks if we are executing inside an SVM or VMX nested hardware-virtualized
1575	* guest.
1576	*
1577	* @retval CPUMHWVIRT_NONE if not in SVM or VMX non-root mode.
1578	* @retval CPUMHWVIRT_VMX if in VMX non-root mode.
1579	* @retval CPUMHWVIRT_SVM if in SVM non-root mode.
1580	* @param pCtx Current CPU context.
1581	*/
1582	DECLINLINE(CPUMHWVIRT) CPUMGetGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
1583	{
1584	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_NONE)
1585	return CPUMHWVIRT_NONE;
1586	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX)
1587	{
1588	Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode \|\| pCtx->hwvirt.vmx.fInVmxRootMode);
1589	return pCtx->hwvirt.vmx.fInVmxNonRootMode ? CPUMHWVIRT_VMX : CPUMHWVIRT_NONE;
1590	}
1591	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1592	return pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN ? CPUMHWVIRT_SVM : CPUMHWVIRT_NONE;
1593	}
1594
1595	/**
1596	* Checks if the guest is in VMX root operation.
1597	*
1598	* @returns @c true if in VMX root operation, @c false otherwise.
1599	* @param pCtx Current CPU context.
1600	*/
1601	DECLINLINE(bool) CPUMIsGuestInVmxRootMode(PCCPUMCTX pCtx)
1602	{
1603	#ifndef IN_RC
1604	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
1605	return false;
1606	return pCtx->hwvirt.vmx.fInVmxRootMode;
1607	#else
1608	NOREF(pCtx);
1609	return false;
1610	#endif
1611	}
1612
1613	# ifndef IN_RC
1614
1615	/**
1616	* Checks if the nested-guest VMCB has the specified ctrl/instruction intercept
1617	* active.
1618	*
1619	* @returns @c true if in intercept is set, @c false otherwise.
1620	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1621	* @param pCtx Current CPU context.
1622	* @param fIntercept The SVM control/instruction intercept, see
1623	* SVM_CTRL_INTERCEPT_*.
1624	*/
1625	DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint64_t fIntercept)
1626	{
1627	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1628	return false;
1629	uint64_t u64Intercepts;
1630	if (!HMGetGuestSvmCtrlIntercepts(pVCpu, &u64Intercepts))
1631	u64Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl;
1632	return RT_BOOL(u64Intercepts & fIntercept);
1633	}
1634
1635	/**
1636	* Checks if the nested-guest VMCB has the specified CR read intercept active.
1637	*
1638	* @returns @c true if in intercept is set, @c false otherwise.
1639	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1640	* @param pCtx Current CPU context.
1641	* @param uCr The CR register number (0 to 15).
1642	*/
1643	DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1644	{
1645	Assert(uCr < 16);
1646	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1647	return false;
1648	uint16_t u16Intercepts;
1649	if (!HMGetGuestSvmReadCRxIntercepts(pVCpu, &u16Intercepts))
1650	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptRdCRx;
1651	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
1652	}
1653
1654	/**
1655	* Checks if the nested-guest VMCB has the specified CR write intercept active.
1656	*
1657	* @returns @c true if in intercept is set, @c false otherwise.
1658	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1659	* @param pCtx Current CPU context.
1660	* @param uCr The CR register number (0 to 15).
1661	*/
1662	DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1663	{
1664	Assert(uCr < 16);
1665	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1666	return false;
1667	uint16_t u16Intercepts;
1668	if (!HMGetGuestSvmWriteCRxIntercepts(pVCpu, &u16Intercepts))
1669	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptWrCRx;
1670	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
1671	}
1672
1673	/**
1674	* Checks if the nested-guest VMCB has the specified DR read intercept active.
1675	*
1676	* @returns @c true if in intercept is set, @c false otherwise.
1677	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1678	* @param pCtx Current CPU context.
1679	* @param uDr The DR register number (0 to 15).
1680	*/
1681	DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1682	{
1683	Assert(uDr < 16);
1684	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1685	return false;
1686	uint16_t u16Intercepts;
1687	if (!HMGetGuestSvmReadDRxIntercepts(pVCpu, &u16Intercepts))
1688	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptRdDRx;
1689	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
1690	}
1691
1692	/**
1693	* Checks if the nested-guest VMCB has the specified DR write intercept active.
1694	*
1695	* @returns @c true if in intercept is set, @c false otherwise.
1696	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1697	* @param pCtx Current CPU context.
1698	* @param uDr The DR register number (0 to 15).
1699	*/
1700	DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1701	{
1702	Assert(uDr < 16);
1703	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1704	return false;
1705	uint16_t u16Intercepts;
1706	if (!HMGetGuestSvmWriteDRxIntercepts(pVCpu, &u16Intercepts))
1707	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptWrDRx;
1708	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
1709	}
1710
1711	/**
1712	* Checks if the nested-guest VMCB has the specified exception intercept active.
1713	*
1714	* @returns @c true if in intercept is active, @c false otherwise.
1715	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1716	* @param pCtx Current CPU context.
1717	* @param uVector The exception / interrupt vector.
1718	*/
1719	DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
1720	{
1721	Assert(uVector <= X86_XCPT_LAST);
1722	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1723	return false;
1724	uint32_t u32Intercepts;
1725	if (!HMGetGuestSvmXcptIntercepts(pVCpu, &u32Intercepts))
1726	u32Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u32InterceptXcpt;
1727	return RT_BOOL(u32Intercepts & RT_BIT(uVector));
1728	}
1729
1730	/**
1731	* Checks if the nested-guest VMCB has virtual-interrupt masking enabled.
1732	*
1733	* @returns @c true if virtual-interrupts are masked, @c false otherwise.
1734	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1735	* @param pCtx Current CPU context.
1736	*
1737	* @remarks Should only be called when SVM feature is exposed to the guest.
1738	*/
1739	DECLINLINE(bool) CPUMIsGuestSvmVirtIntrMasking(PCVMCPU pVCpu, PCCPUMCTX pCtx)
1740	{
1741	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1742	return false;
1743	bool fVIntrMasking;
1744	if (!HMGetGuestSvmVirtIntrMasking(pVCpu, &fVIntrMasking))
1745	fVIntrMasking = pCtx->hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u1VIntrMasking;
1746	return fVIntrMasking;
1747	}
1748
1749	/**
1750	* Checks if the nested-guest VMCB has nested-paging enabled.
1751	*
1752	* @returns @c true if nested-paging is enabled, @c false otherwise.
1753	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1754	* @param pCtx Current CPU context.
1755	*
1756	* @remarks Should only be called when SVM feature is exposed to the guest.
1757	*/
1758	DECLINLINE(bool) CPUMIsGuestSvmNestedPagingEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
1759	{
1760	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1761	return false;
1762	bool fNestedPaging;
1763	if (!HMGetGuestSvmNestedPaging(pVCpu, &fNestedPaging))
1764	fNestedPaging = pCtx->hwvirt.svm.Vmcb.ctrl.NestedPagingCtrl.n.u1NestedPaging;
1765	return fNestedPaging;
1766	}
1767
1768	/**
1769	* Gets the nested-guest VMCB pause-filter count.
1770	*
1771	* @returns The pause-filter count.
1772	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1773	* @param pCtx Current CPU context.
1774	*
1775	* @remarks Should only be called when SVM feature is exposed to the guest.
1776	*/
1777	DECLINLINE(uint16_t) CPUMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, PCCPUMCTX pCtx)
1778	{
1779	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1780	return false;
1781	uint16_t u16PauseFilterCount;
1782	if (!HMGetGuestSvmPauseFilterCount(pVCpu, &u16PauseFilterCount))
1783	u16PauseFilterCount = pCtx->hwvirt.svm.Vmcb.ctrl.u16PauseFilterCount;
1784	return u16PauseFilterCount;
1785	}
1786
1787	/**
1788	* Updates the NextRIP (NRIP) field in the nested-guest VMCB.
1789	*
1790	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1791	* @param pCtx Current CPU context.
1792	* @param cbInstr The length of the current instruction in bytes.
1793	*
1794	* @remarks Should only be called when SVM feature is exposed to the guest.
1795	*/
1796	DECLINLINE(void) CPUMGuestSvmUpdateNRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbInstr)
1797	{
1798	RT_NOREF(pVCpu);
1799	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1800	pCtx->hwvirt.svm.Vmcb.ctrl.u64NextRIP = pCtx->rip + cbInstr;
1801	}
1802
1803	/**
1804	* Checks whether one of the given Pin-based VM-execution controls are set when
1805	* executing a nested-guest.
1806	*
1807	* @returns @c true if set, @c false otherwise.
1808	* @param pCtx Current CPU context.
1809	* @param uPinCtls The Pin-based VM-execution controls to check.
1810	*
1811	* @remarks This does not check if all given controls are set if more than one
1812	* control is passed in @a uPinCtl.
1813	*/
1814	DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PCCPUMCTX pCtx, uint32_t uPinCtls)
1815	{
1816	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
1817	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32PinCtls & uPinCtls);
1818	}
1819
1820	/**
1821	* Checks whether one of the given Processor-based VM-execution controls are set
1822	* when executing a nested-guest.
1823	*
1824	* @returns @c true if set, @c false otherwise.
1825	* @param pCtx Current CPU context.
1826	* @param uProcCtls The Processor-based VM-execution controls to check.
1827	*
1828	* @remarks This does not check if all given controls are set if more than one
1829	* control is passed in @a uProcCtls.
1830	*/
1831	DECLINLINE(bool) CPUMIsGuestVmxProcCtlsSet(PCCPUMCTX pCtx, uint32_t uProcCtls)
1832	{
1833	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
1834	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ProcCtls & uProcCtls);
1835	}
1836
1837	/**
1838	* Checks whether one of the given Secondary Processor-based VM-execution controls
1839	* are set when executing a nested-guest.
1840	*
1841	* @returns @c true if set, @c false otherwise.
1842	* @param pCtx Current CPU context.
1843	* @param uProcCtls2 The Secondary Processor-based VM-execution controls to
1844	* check.
1845	*
1846	* @remarks This does not check if all given controls are set if more than one
1847	* control is passed in @a uProcCtls2.
1848	*/
1849	DECLINLINE(bool) CPUMIsGuestVmxProcCtls2Set(PCCPUMCTX pCtx, uint32_t uProcCtls2)
1850	{
1851	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
1852	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ProcCtls2 & uProcCtls2);
1853	}
1854
1855	/**
1856	* Checks whether one of the given Tertiary Processor-based VM-execution controls
1857	* are set when executing a nested-guest.
1858	*
1859	* @returns @c true if set, @c false otherwise.
1860	* @param pCtx Current CPU context.
1861	* @param uProcCtls3 The Tertiary Processor-based VM-execution controls to
1862	* check.
1863	*
1864	* @remarks This does not check if all given controls are set if more than one
1865	* control is passed in @a uProcCtls3.
1866	*/
1867	DECLINLINE(bool) CPUMIsGuestVmxProcCtls3Set(PCCPUMCTX pCtx, uint64_t uProcCtls3)
1868	{
1869	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
1870	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u64ProcCtls3.u & uProcCtls3);
1871	}
1872
1873	/**
1874	* Checks whether one of the given VM-exit controls are set when executing a
1875	* nested-guest.
1876	*
1877	* @returns @c true if set, @c false otherwise.
1878	* @param pCtx Current CPU context.
1879	* @param uExitCtls The VM-exit controls to check.
1880	*
1881	* @remarks This does not check if all given controls are set if more than one
1882	* control is passed in @a uExitCtls.
1883	*/
1884	DECLINLINE(bool) CPUMIsGuestVmxExitCtlsSet(PCCPUMCTX pCtx, uint32_t uExitCtls)
1885	{
1886	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
1887	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ExitCtls & uExitCtls);
1888	}
1889
1890	/**
1891	* Checks whether one of the given VM-entry controls are set when executing a
1892	* nested-guest.
1893	*
1894	* @returns @c true if set, @c false otherwise.
1895	* @param pCtx Current CPU context.
1896	* @param uEntryCtls The VM-entry controls to check.
1897	*
1898	* @remarks This does not check if all given controls are set if more than one
1899	* control is passed in @a uEntryCtls.
1900	*/
1901	DECLINLINE(bool) CPUMIsGuestVmxEntryCtlsSet(PCCPUMCTX pCtx, uint32_t uEntryCtls)
1902	{
1903	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
1904	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32EntryCtls & uEntryCtls);
1905	}
1906
1907	/**
1908	* Checks whether events injected in the nested-guest are subject to VM-exit checks.
1909	*
1910	* @returns @c true if set, @c false otherwise.
1911	* @param pCtx Current CPU context.
1912	*/
1913	DECLINLINE(bool) CPUMIsGuestVmxInterceptEvents(PCCPUMCTX pCtx)
1914	{
1915	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
1916	return pCtx->hwvirt.vmx.fInterceptEvents;
1917	}
1918
1919	/**
1920	* Sets whether events injected in the nested-guest are subject to VM-exit checks.
1921	*
1922	* @param pCtx Current CPU context.
1923	* @param fIntercept Whether to subject injected events to VM-exits or not.
1924	*/
1925	DECLINLINE(void) CPUMSetGuestVmxInterceptEvents(PCPUMCTX pCtx, bool fInterceptEvents)
1926	{
1927	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
1928	pCtx->hwvirt.vmx.fInterceptEvents = fInterceptEvents;
1929	}
1930
1931	/**
1932	* Checks whether the given exception causes a VM-exit.
1933	*
1934	* The exception type include hardware exceptions, software exceptions (#BP, #OF)
1935	* and privileged software exceptions (#DB generated by INT1/ICEBP).
1936	*
1937	* Software interrupts do -not- cause VM-exits and hence must not be used with this
1938	* function.
1939	*
1940	* @returns @c true if the exception causes a VM-exit, @c false otherwise.
1941	* @param pCtx Current CPU context.
1942	* @param uVector The exception vector.
1943	* @param uErrCode The error code associated with the exception. Pass 0 if not
1944	* applicable.
1945	*/
1946	DECLINLINE(bool) CPUMIsGuestVmxXcptInterceptSet(PCCPUMCTX pCtx, uint8_t uVector, uint32_t uErrCode)
1947	{
1948	Assert(uVector <= X86_XCPT_LAST);
1949
1950	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
1951
1952	/* NMIs have a dedicated VM-execution control for causing VM-exits. */
1953	if (uVector == X86_XCPT_NMI)
1954	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
1955
1956	/* Page-faults are subject to masking using its error code. */
1957	uint32_t fXcptBitmap = pCtx->hwvirt.vmx.Vmcs.u32XcptBitmap;
1958	if (uVector == X86_XCPT_PF)
1959	{
1960	uint32_t const fXcptPFMask = pCtx->hwvirt.vmx.Vmcs.u32XcptPFMask;
1961	uint32_t const fXcptPFMatch = pCtx->hwvirt.vmx.Vmcs.u32XcptPFMatch;
1962	if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
1963	fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
1964	}
1965
1966	/* Consult the exception bitmap for all other exceptions. */
1967	if (fXcptBitmap & RT_BIT(uVector))
1968	return true;
1969	return false;
1970	}
1971
1972
1973	/**
1974	* Checks whether the guest is in VMX non-root mode and using EPT paging.
1975	*
1976	* @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
1977	* @param pCtx Current CPU context.
1978	*/
1979	DECLINLINE(bool) CPUMIsGuestVmxEptPagingEnabledEx(PCCPUMCTX pCtx)
1980	{
1981	return CPUMIsGuestInVmxNonRootMode(pCtx)
1982	&& CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_EPT);
1983	}
1984
1985
1986	/**
1987	* Implements VMSucceed for VMX instruction success.
1988	*
1989	* @param pCtx Current CPU context.
1990	*/
1991	DECLINLINE(void) CPUMSetGuestVmxVmSucceed(PCPUMCTX pCtx)
1992	{
1993	pCtx->eflags.uBoth &= ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF);
1994	}
1995
1996	/**
1997	* Implements VMFailInvalid for VMX instruction failure.
1998	*
1999	* @param pCtx Current CPU context.
2000	*/
2001	DECLINLINE(void) CPUMSetGuestVmxVmFailInvalid(PCPUMCTX pCtx)
2002	{
2003	pCtx->eflags.uBoth &= ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF);
2004	pCtx->eflags.uBoth \|= X86_EFL_CF;
2005	}
2006
2007	/**
2008	* Implements VMFailValid for VMX instruction failure.
2009	*
2010	* @param pCtx Current CPU context.
2011	* @param enmInsErr The VM instruction error.
2012	*/
2013	DECLINLINE(void) CPUMSetGuestVmxVmFailValid(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2014	{
2015	pCtx->eflags.uBoth &= ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF);
2016	pCtx->eflags.uBoth \|= X86_EFL_ZF;
2017	pCtx->hwvirt.vmx.Vmcs.u32RoVmInstrError = enmInsErr;
2018	}
2019
2020	/**
2021	* Implements VMFail for VMX instruction failure.
2022	*
2023	* @param pCtx Current CPU context.
2024	* @param enmInsErr The VM instruction error.
2025	*/
2026	DECLINLINE(void) CPUMSetGuestVmxVmFail(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2027	{
2028	if (pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS)
2029	CPUMSetGuestVmxVmFailValid(pCtx, enmInsErr);
2030	else
2031	CPUMSetGuestVmxVmFailInvalid(pCtx);
2032	}
2033
2034	/**
2035	* Returns the guest-physical address of the APIC-access page when executing a
2036	* nested-guest.
2037	*
2038	* @returns The APIC-access page guest-physical address.
2039	* @param pCtx Current CPU context.
2040	*/
2041	DECLINLINE(uint64_t) CPUMGetGuestVmxApicAccessPageAddrEx(PCCPUMCTX pCtx)
2042	{
2043	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2044	return pCtx->hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
2045	}
2046
2047	/**
2048	* Gets the nested-guest CR0 subject to the guest/host mask and the read-shadow.
2049	*
2050	* @returns The nested-guest CR0.
2051	* @param pCtx Current CPU context.
2052	* @param fGstHostMask The CR0 guest/host mask to use.
2053	*/
2054	DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr0(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2055	{
2056	/*
2057	* For each CR0 bit owned by the host, the corresponding bit from the
2058	* CR0 read shadow is loaded. For each CR0 bit that is not owned by the host,
2059	* the corresponding bit from the guest CR0 is loaded.
2060	*
2061	* See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2062	*/
2063	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2064	uint64_t const uGstCr0 = pCtx->cr0;
2065	uint64_t const fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2066	return (fReadShadow & fGstHostMask) \| (uGstCr0 & ~fGstHostMask);
2067	}
2068
2069	/**
2070	* Gets the nested-guest CR4 subject to the guest/host mask and the read-shadow.
2071	*
2072	* @returns The nested-guest CR4.
2073	* @param pCtx Current CPU context.
2074	* @param fGstHostMask The CR4 guest/host mask to use.
2075	*/
2076	DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr4(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2077	{
2078	/*
2079	* For each CR4 bit owned by the host, the corresponding bit from the
2080	* CR4 read shadow is loaded. For each CR4 bit that is not owned by the host,
2081	* the corresponding bit from the guest CR4 is loaded.
2082	*
2083	* See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2084	*/
2085	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2086	uint64_t const uGstCr4 = pCtx->cr4;
2087	uint64_t const fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr4ReadShadow.u;
2088	return (fReadShadow & fGstHostMask) \| (uGstCr4 & ~fGstHostMask);
2089	}
2090
2091	/**
2092	* Checks whether the LMSW access causes a VM-exit or not.
2093	*
2094	* @returns @c true if the LMSW access causes a VM-exit, @c false otherwise.
2095	* @param pCtx Current CPU context.
2096	* @param uNewMsw The LMSW source operand (the Machine Status Word).
2097	*/
2098	DECLINLINE(bool) CPUMIsGuestVmxLmswInterceptSet(PCCPUMCTX pCtx, uint16_t uNewMsw)
2099	{
2100	/*
2101	* LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
2102	*
2103	* See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
2104	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2105	*/
2106	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2107
2108	uint32_t const fGstHostMask = (uint32_t)pCtx->hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2109	uint32_t const fReadShadow = (uint32_t)pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2110
2111	/*
2112	* LMSW can never clear CR0.PE but it may set it. Hence, we handle the
2113	* CR0.PE case first, before the rest of the bits in the MSW.
2114	*
2115	* If CR0.PE is owned by the host and CR0.PE differs between the
2116	* MSW (source operand) and the read-shadow, we must cause a VM-exit.
2117	*/
2118	if ( (fGstHostMask & X86_CR0_PE)
2119	&& (uNewMsw & X86_CR0_PE)
2120	&& !(fReadShadow & X86_CR0_PE))
2121	return true;
2122
2123	/*
2124	* If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
2125	* bits differ between the MSW (source operand) and the read-shadow, we must
2126	* cause a VM-exit.
2127	*/
2128	uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS);
2129	if ((fReadShadow & fGstHostLmswMask) != (uNewMsw & fGstHostLmswMask))
2130	return true;
2131
2132	return false;
2133	}
2134
2135	/**
2136	* Checks whether the Mov-to-CR0/CR4 access causes a VM-exit or not.
2137	*
2138	* @returns @c true if the Mov CRX access causes a VM-exit, @c false otherwise.
2139	* @param pCtx Current CPU context.
2140	* @param iCrReg The control register number (must be 0 or 4).
2141	* @param uNewCrX The CR0/CR4 value being written.
2142	*/
2143	DECLINLINE(bool) CPUMIsGuestVmxMovToCr0Cr4InterceptSet(PCCPUMCTX pCtx, uint8_t iCrReg, uint64_t uNewCrX)
2144	{
2145	/*
2146	* For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
2147	* corresponding bits differ between the source operand and the read-shadow,
2148	* we must cause a VM-exit.
2149	*
2150	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2151	*/
2152	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2153	Assert(iCrReg == 0 \|\| iCrReg == 4);
2154
2155	uint64_t fGstHostMask;
2156	uint64_t fReadShadow;
2157	if (iCrReg == 0)
2158	{
2159	fGstHostMask = pCtx->hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2160	fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2161	}
2162	else
2163	{
2164	fGstHostMask = pCtx->hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2165	fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr4ReadShadow.u;
2166	}
2167
2168	if ((fReadShadow & fGstHostMask) != (uNewCrX & fGstHostMask))
2169	{
2170	Assert(fGstHostMask != 0);
2171	return true;
2172	}
2173
2174	return false;
2175	}
2176
2177	/**
2178	* Returns whether the guest has an active, current VMCS.
2179	*
2180	* @returns @c true if the guest has an active, current VMCS, @c false otherwise.
2181	* @param pCtx Current CPU context.
2182	*/
2183	DECLINLINE(bool) CPUMIsGuestVmxCurrentVmcsValid(PCCPUMCTX pCtx)
2184	{
2185	return pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS;
2186	}
2187
2188	# endif /* !IN_RC */
2189
2190	/**
2191	* Checks whether the VMX nested-guest is in a state to receive physical (APIC)
2192	* interrupts.
2193	*
2194	* @returns @c true if it's ready, @c false otherwise.
2195	* @param pCtx The guest-CPU context.
2196	*/
2197	DECLINLINE(bool) CPUMIsGuestVmxPhysIntrEnabled(PCCPUMCTX pCtx)
2198	{
2199	#ifdef IN_RC
2200	AssertReleaseFailedReturn(false);
2201	#else
2202	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2203	if (CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_EXT_INT_EXIT))
2204	return true;
2205	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RFLAGS);
2206	return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2207	#endif
2208	}
2209
2210	/**
2211	* Checks whether the VMX nested-guest is blocking virtual-NMIs.
2212	*
2213	* @returns @c true if it's blocked, @c false otherwise.
2214	* @param pCtx The guest-CPU context.
2215	*/
2216	DECLINLINE(bool) CPUMIsGuestVmxVirtNmiBlocking(PCCPUMCTX pCtx)
2217	{
2218	#ifdef IN_RC
2219	RT_NOREF(pCtx);
2220	AssertReleaseFailedReturn(false);
2221	#else
2222	/*
2223	* Return the state of virtual-NMI blocking, if we are executing a
2224	* VMX nested-guest with virtual-NMIs enabled.
2225	*/
2226	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2227	Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2228	return pCtx->hwvirt.vmx.fVirtNmiBlocking;
2229	#endif
2230	}
2231
2232	/**
2233	* Sets or clears VMX nested-guest virtual-NMI blocking.
2234	*
2235	* @param pCtx The guest-CPU context.
2236	* @param fBlocking Whether virtual-NMI blocking is in effect or not.
2237	*/
2238	DECLINLINE(void) CPUMSetGuestVmxVirtNmiBlocking(PCPUMCTX pCtx, bool fBlocking)
2239	{
2240	#ifdef IN_RC
2241	RT_NOREF2(pCtx, fBlocking);
2242	AssertReleaseFailedReturnVoid();
2243	#else
2244	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2245	Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2246	pCtx->hwvirt.vmx.fVirtNmiBlocking = fBlocking;
2247	#endif
2248	}
2249
2250	/**
2251	* Checks whether the VMX nested-guest is in a state to receive virtual interrupts
2252	* (those injected with the "virtual-interrupt delivery" feature).
2253	*
2254	* @returns @c true if it's ready, @c false otherwise.
2255	* @param pCtx The guest-CPU context.
2256	*/
2257	DECLINLINE(bool) CPUMIsGuestVmxVirtIntrEnabled(PCCPUMCTX pCtx)
2258	{
2259	#ifdef IN_RC
2260	RT_NOREF2(pCtx);
2261	AssertReleaseFailedReturn(false);
2262	#else
2263	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2264	return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2265	#endif
2266	}
2267
2268	/** @} */
2269	#endif /* !IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS \|\| DOXYGEN_RUNNING */
2270
2271
2272
2273	/** @name Hypervisor Register Getters.
2274	* @{ */
2275	VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
2276	VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
2277	VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
2278	VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
2279	VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
2280	VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
2281	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
2282	/** @} */
2283
2284	/** @name Hypervisor Register Setters.
2285	* @{ */
2286	VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
2287	VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
2288	VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
2289	VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg);
2290	/** @} */
2291
2292	#ifdef VBOX_INCLUDED_vmm_cpumctx_h
2293	VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu);
2294	#endif
2295
2296	/** @name Changed flags.
2297	* These flags are used to keep track of which important register that
2298	* have been changed since last they were reset. The only one allowed
2299	* to clear them is REM!
2300	*
2301	* @todo This is obsolete, but remains as it will be refactored for coordinating
2302	* IEM and NEM/HM later. Probably.
2303	* @{
2304	*/
2305	#define CPUM_CHANGED_FPU_REM RT_BIT(0)
2306	#define CPUM_CHANGED_CR0 RT_BIT(1)
2307	#define CPUM_CHANGED_CR4 RT_BIT(2)
2308	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
2309	#define CPUM_CHANGED_CR3 RT_BIT(4)
2310	#define CPUM_CHANGED_GDTR RT_BIT(5)
2311	#define CPUM_CHANGED_IDTR RT_BIT(6)
2312	#define CPUM_CHANGED_LDTR RT_BIT(7)
2313	#define CPUM_CHANGED_TR RT_BIT(8) /*@< Currently unused. /
2314	#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
2315	#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /*@< Currently unused. /
2316	#define CPUM_CHANGED_CPUID RT_BIT(11)
2317	#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
2318	\| CPUM_CHANGED_CR0 \
2319	\| CPUM_CHANGED_CR4 \
2320	\| CPUM_CHANGED_GLOBAL_TLB_FLUSH \
2321	\| CPUM_CHANGED_CR3 \
2322	\| CPUM_CHANGED_GDTR \
2323	\| CPUM_CHANGED_IDTR \
2324	\| CPUM_CHANGED_LDTR \
2325	\| CPUM_CHANGED_TR \
2326	\| CPUM_CHANGED_SYSENTER_MSR \
2327	\| CPUM_CHANGED_HIDDEN_SEL_REGS \
2328	\| CPUM_CHANGED_CPUID )
2329	/** @} */
2330
2331	VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
2332	VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
2333	VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
2334	VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
2335	VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu);
2336	VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu);
2337	VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
2338	VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
2339	VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
2340	VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
2341	VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM);
2342	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
2343	VMMDECL(uint64_t) CPUMGetGuestEferMsrValidMask(PVM pVM);
2344	VMMDECL(int) CPUMIsGuestEferMsrWriteValid(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
2345	uint64_t *puValidEfer);
2346	VMMDECL(void) CPUMSetGuestEferMsrNoChecks(PVMCPUCC pVCpu, uint64_t uOldEfer, uint64_t uValidEfer);
2347	VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue);
2348
2349
2350	/** Guest CPU interruptibility level, see CPUMGetGuestInterruptibility(). */
2351	typedef enum CPUMINTERRUPTIBILITY
2352	{
2353	CPUMINTERRUPTIBILITY_INVALID = 0,
2354	CPUMINTERRUPTIBILITY_UNRESTRAINED,
2355	CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED,
2356	CPUMINTERRUPTIBILITY_INT_DISABLED,
2357	CPUMINTERRUPTIBILITY_INT_INHIBITED, /*< @todo rename as it inhibits NMIs too. /
2358	CPUMINTERRUPTIBILITY_NMI_INHIBIT,
2359	CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT,
2360	CPUMINTERRUPTIBILITY_END,
2361	CPUMINTERRUPTIBILITY_32BIT_HACK = 0x7fffffff
2362	} CPUMINTERRUPTIBILITY;
2363
2364	VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu);
2365
2366	/** @name Typical scalable bus frequency values.
2367	* @{ */
2368	/** Special internal value indicating that we don't know the frequency.
2369	* @internal */
2370	#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
2371	#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
2372	#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
2373	#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
2374	#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
2375	#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
2376	#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
2377	#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
2378	/** @} */
2379
2380
2381	#ifdef IN_RING3
2382	/** @defgroup grp_cpum_r3 The CPUM ring-3 API
2383	* @{
2384	*/
2385	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
2386	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
2387	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves);
2388	VMMDECL(CPUMMICROARCH) CPUMCpuIdDetermineX86MicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
2389	uint8_t bModel, uint8_t bStepping);
2390	VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch);
2391	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
2392	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
2393	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2394	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void);
2395	#endif
2396
2397	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
2398
2399	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu);
2400	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu);
2401	/** @} */
2402	#endif /* IN_RING3 */
2403
2404	#ifdef IN_RING0
2405	/** @defgroup grp_cpum_r0 The CPUM ring-0 API
2406	* @{
2407	*/
2408	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
2409	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
2410	VMMR0_INT_DECL(void) CPUMR0InitPerVMData(PGVM pGVM);
2411	VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM);
2412	DECLASM(void) CPUMR0RegisterVCpuThread(PVMCPUCC pVCpu);
2413	DECLASM(void) CPUMR0TouchHostFpu(void);
2414	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu);
2415	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu);
2416	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu);
2417	VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVMCC pVM, PVMCPUCC pVCpu);
2418	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6);
2419	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6);
2420
2421	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6);
2422	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6);
2423	/** @} */
2424	#endif /* IN_RING0 */
2425
2426	/** @defgroup grp_cpum_rz The CPUM raw-mode and ring-0 context API
2427	* @{
2428	*/
2429	VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPUCC pVCpu);
2430	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPUCC pVCpu);
2431	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForChange(PVMCPUCC pVCpu);
2432	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPUCC pVCpu);
2433	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeAvxForRead(PVMCPUCC pVCpu);
2434	/** @} */
2435
2436
2437	#endif /* !VBOX_FOR_DTRACE_LIB */
2438	/** @} */
2439	RT_C_DECLS_END
2440
2441
2442	#endif /* !VBOX_INCLUDED_vmm_cpum_x86_amd64_h */
2443

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source: vbox/trunk/include/VBox/vmm/cpum-x86-amd64.h@ 107558

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