VirtualBox

Ignore:
Timestamp:
Dec 19, 2024 3:55:08 PM (8 weeks ago)
Author:
vboxsync
Message:

VMM/CPUM: The CPUMFEATURE structures can't be in target specific headers, since we need them for the host CPU as well. jiraref:VBP-1470

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/cpum-x86-amd64.h

    r107220 r107389  
    753753
    754754/**
    755  * CPU features and quirks.
    756  * This is mostly exploded CPUID info.
    757  */
    758 typedef struct CPUMFEATURES
    759 {
    760     /** The CPU vendor (CPUMCPUVENDOR). */
    761     uint8_t         enmCpuVendor;
    762     /** The CPU family. */
    763     uint8_t         uFamily;
    764     /** The CPU model. */
    765     uint8_t         uModel;
    766     /** The CPU stepping. */
    767     uint8_t         uStepping;
    768     /** The microarchitecture. */
    769 #ifndef VBOX_FOR_DTRACE_LIB
    770     CPUMMICROARCH   enmMicroarch;
    771 #else
    772     uint32_t        enmMicroarch;
    773 #endif
    774     /** The maximum physical address width of the CPU. */
    775     uint8_t         cMaxPhysAddrWidth;
    776     /** The maximum linear address width of the CPU. */
    777     uint8_t         cMaxLinearAddrWidth;
    778     /** Max size of the extended state (or FPU state if no XSAVE). */
    779     uint16_t        cbMaxExtendedState;
    780 
    781     /** Supports MSRs. */
    782     uint32_t        fMsr : 1;
    783     /** Supports the page size extension (4/2 MB pages). */
    784     uint32_t        fPse : 1;
    785     /** Supports 36-bit page size extension (4 MB pages can map memory above
    786      *  4GB). */
    787     uint32_t        fPse36 : 1;
    788     /** Supports physical address extension (PAE). */
    789     uint32_t        fPae : 1;
    790     /** Supports page-global extension (PGE). */
    791     uint32_t        fPge : 1;
    792     /** Page attribute table (PAT) support (page level cache control). */
    793     uint32_t        fPat : 1;
    794     /** Supports the FXSAVE and FXRSTOR instructions. */
    795     uint32_t        fFxSaveRstor : 1;
    796     /** Supports the XSAVE and XRSTOR instructions. */
    797     uint32_t        fXSaveRstor : 1;
    798     /** Supports the XSAVEOPT instruction. */
    799     uint32_t        fXSaveOpt : 1;
    800     /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
    801     uint32_t        fOpSysXSaveRstor : 1;
    802     /** Supports MMX. */
    803     uint32_t        fMmx : 1;
    804     /** Supports AMD extensions to MMX instructions. */
    805     uint32_t        fAmdMmxExts : 1;
    806     /** Supports SSE. */
    807     uint32_t        fSse : 1;
    808     /** Supports SSE2. */
    809     uint32_t        fSse2 : 1;
    810     /** Supports SSE3. */
    811     uint32_t        fSse3 : 1;
    812     /** Supports SSSE3. */
    813     uint32_t        fSsse3 : 1;
    814     /** Supports SSE4.1. */
    815     uint32_t        fSse41 : 1;
    816     /** Supports SSE4.2. */
    817     uint32_t        fSse42 : 1;
    818     /** Supports AVX. */
    819     uint32_t        fAvx : 1;
    820     /** Supports AVX2. */
    821     uint32_t        fAvx2 : 1;
    822     /** Supports AVX512 foundation. */
    823     uint32_t        fAvx512Foundation : 1;
    824     /** Supports RDTSC. */
    825     uint32_t        fTsc : 1;
    826     /** Intel SYSENTER/SYSEXIT support */
    827     uint32_t        fSysEnter : 1;
    828     /** Supports MTRR. */
    829     uint32_t        fMtrr : 1;
    830     /** First generation APIC. */
    831     uint32_t        fApic : 1;
    832     /** Second generation APIC. */
    833     uint32_t        fX2Apic : 1;
    834     /** Hypervisor present. */
    835     uint32_t        fHypervisorPresent : 1;
    836     /** MWAIT & MONITOR instructions supported. */
    837     uint32_t        fMonitorMWait : 1;
    838     /** MWAIT Extensions present. */
    839     uint32_t        fMWaitExtensions : 1;
    840     /** Supports CMPXCHG8B. */
    841     uint32_t        fCmpXchg8b : 1;
    842     /** Supports CMPXCHG16B in 64-bit mode. */
    843     uint32_t        fCmpXchg16b : 1;
    844     /** Supports CLFLUSH. */
    845     uint32_t        fClFlush : 1;
    846     /** Supports CLFLUSHOPT. */
    847     uint32_t        fClFlushOpt : 1;
    848     /** Supports IA32_PRED_CMD.IBPB. */
    849     uint32_t        fIbpb : 1;
    850     /** Supports IA32_SPEC_CTRL.IBRS. */
    851     uint32_t        fIbrs : 1;
    852     /** Supports IA32_SPEC_CTRL.STIBP. */
    853     uint32_t        fStibp : 1;
    854     /** Supports IA32_FLUSH_CMD. */
    855     uint32_t        fFlushCmd : 1;
    856     /** Supports IA32_ARCH_CAP. */
    857     uint32_t        fArchCap : 1;
    858     /** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */
    859     uint32_t        fMdsClear : 1;
    860     /** Supports PCID. */
    861     uint32_t        fPcid : 1;
    862     /** Supports INVPCID. */
    863     uint32_t        fInvpcid : 1;
    864     /** Supports read/write FSGSBASE instructions. */
    865     uint32_t        fFsGsBase : 1;
    866     /** Supports BMI1 instructions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, and TZCNT). */
    867     uint32_t        fBmi1 : 1;
    868     /** Supports BMI2 instructions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX,
    869      * and SHLX). */
    870     uint32_t        fBmi2 : 1;
    871     /** Supports POPCNT instruction. */
    872     uint32_t        fPopCnt : 1;
    873     /** Supports RDRAND instruction. */
    874     uint32_t        fRdRand : 1;
    875     /** Supports RDSEED instruction. */
    876     uint32_t        fRdSeed : 1;
    877     /** Supports Hardware Lock Elision (HLE). */
    878     uint32_t        fHle : 1;
    879     /** Supports Restricted Transactional Memory (RTM - XBEGIN, XEND, XABORT). */
    880     uint32_t        fRtm : 1;
    881     /** Supports PCLMULQDQ instruction. */
    882     uint32_t        fPclMul : 1;
    883     /** Supports AES-NI (six AESxxx instructions). */
    884     uint32_t        fAesNi : 1;
    885     /** Support MOVBE instruction. */
    886     uint32_t        fMovBe : 1;
    887     /** Support SHA instructions. */
    888     uint32_t        fSha : 1;
    889     /** Support ADX instructions. */
    890     uint32_t        fAdx : 1;
    891     /** Supports FMA. */
    892     uint32_t        fFma : 1;
    893     /** Supports F16C. */
    894     uint32_t        fF16c : 1;
    895 
    896     /** Supports AMD 3DNow instructions. */
    897     uint32_t        f3DNow : 1;
    898     /** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
    899     uint32_t        f3DNowPrefetch : 1;
    900 
    901     /** AMD64: Supports long mode. */
    902     uint32_t        fLongMode : 1;
    903     /** AMD64: SYSCALL/SYSRET support. */
    904     uint32_t        fSysCall : 1;
    905     /** AMD64: No-execute page table bit. */
    906     uint32_t        fNoExecute : 1;
    907     /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
    908     uint32_t        fLahfSahf : 1;
    909     /** AMD64: Supports RDTSCP. */
    910     uint32_t        fRdTscP : 1;
    911     /** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
    912     uint32_t        fMovCr8In32Bit : 1;
    913     /** AMD64: Supports XOP (similar to VEX3/AVX). */
    914     uint32_t        fXop : 1;
    915     /** AMD64: Supports ABM, i.e. the LZCNT instruction. */
    916     uint32_t        fAbm : 1;
    917     /** AMD64: Supports TBM (BEXTR, BLCFILL, BLCI, BLCIC, BLCMSK, BLCS,
    918      *  BLSFILL, BLSIC, T1MSKC, and TZMSK). */
    919     uint32_t        fTbm : 1;
    920 
    921     /** Indicates that FPU instruction and data pointers may leak.
    922      * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
    923      * is only saved and restored if an exception is pending. */
    924     uint32_t        fLeakyFxSR : 1;
    925 
    926     /** Supports VEX instruction encoding (AVX, BMI, etc.). */
    927     uint32_t        fVex : 1;
    928 
    929     /** AMD64: Supports AMD SVM. */
    930     uint32_t        fSvm : 1;
    931 
    932     /** Support for Intel VMX. */
    933     uint32_t        fVmx : 1;
    934 
    935     /** Indicates that speculative execution control CPUID bits and MSRs are exposed.
    936      * The details are different for Intel and AMD but both have similar
    937      * functionality. */
    938     uint32_t        fSpeculationControl : 1;
    939 
    940     /** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0).
    941      * @remarks Only safe use after CPUM ring-0 init! */
    942     uint32_t        fArchRdclNo : 1;
    943     /** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1).
    944      * @remarks Only safe use after CPUM ring-0 init! */
    945     uint32_t        fArchIbrsAll : 1;
    946     /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2).
    947      * @remarks Only safe use after CPUM ring-0 init! */
    948     uint32_t        fArchRsbOverride : 1;
    949     /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3).
    950      * @remarks Only safe use after CPUM ring-0 init! */
    951     uint32_t        fArchVmmNeedNotFlushL1d : 1;
    952     /** MSR_IA32_ARCH_CAPABILITIES: MDS_NO (bit 4).
    953      * @remarks Only safe use after CPUM ring-0 init! */
    954     uint32_t        fArchMdsNo : 1;
    955 
    956     /** Alignment padding / reserved for future use (96 bits total, plus 12 bytes
    957      *  prior to the bit fields -> total of 24 bytes) */
    958     uint32_t        fPadding0 : 19;
    959 
    960 
    961     /** @name SVM
    962      * @{ */
    963     /** SVM: Supports Nested-paging. */
    964     uint32_t        fSvmNestedPaging : 1;
    965     /** SVM: Support LBR (Last Branch Record) virtualization. */
    966     uint32_t        fSvmLbrVirt : 1;
    967     /** SVM: Supports SVM lock. */
    968     uint32_t        fSvmSvmLock : 1;
    969     /** SVM: Supports Next RIP save. */
    970     uint32_t        fSvmNextRipSave : 1;
    971     /** SVM: Supports TSC rate MSR. */
    972     uint32_t        fSvmTscRateMsr : 1;
    973     /** SVM: Supports VMCB clean bits. */
    974     uint32_t        fSvmVmcbClean : 1;
    975     /** SVM: Supports Flush-by-ASID. */
    976     uint32_t        fSvmFlusbByAsid : 1;
    977     /** SVM: Supports decode assist. */
    978     uint32_t        fSvmDecodeAssists : 1;
    979     /** SVM: Supports Pause filter. */
    980     uint32_t        fSvmPauseFilter : 1;
    981     /** SVM: Supports Pause filter threshold. */
    982     uint32_t        fSvmPauseFilterThreshold : 1;
    983     /** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
    984     uint32_t        fSvmAvic : 1;
    985     /** SVM: Supports Virtualized VMSAVE/VMLOAD. */
    986     uint32_t        fSvmVirtVmsaveVmload : 1;
    987     /** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
    988     uint32_t        fSvmVGif : 1;
    989     /** SVM: Supports GMET (Guest Mode Execute Trap Extension). */
    990     uint32_t        fSvmGmet : 1;
    991     /** SVM: Supports AVIC in x2APIC mode. */
    992     uint32_t        fSvmX2Avic : 1;
    993     /** SVM: Supports SSSCheck (SVM Supervisor Shadow Stack). */
    994     uint32_t        fSvmSSSCheck : 1;
    995     /** SVM: Supports SPEC_CTRL virtualization. */
    996     uint32_t        fSvmSpecCtrl : 1;
    997     /** SVM: Supports Read-Only Guest Page Table feature. */
    998     uint32_t        fSvmRoGpt : 1;
    999     /** SVM: Supports HOST_MCE_OVERRIDE. */
    1000     uint32_t        fSvmHostMceOverride : 1;
    1001     /** SVM: Supports TlbiCtl (INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept). */
    1002     uint32_t        fSvmTlbiCtl : 1;
    1003      /** SVM: Supports NMI virtualization. */
    1004     uint32_t        fSvmVNmi : 1;
    1005     /** SVM: Supports IBS virtualizaiton. */
    1006     uint32_t        fSvmIbsVirt : 1;
    1007     /** SVM: Supports Extended LVT AVIC access changes. */
    1008     uint32_t        fSvmExtLvtAvicAccessChg : 1;
    1009     /** SVM: Supports Guest VMCB address check. */
    1010     uint32_t        fSvmNstVirtVmcbAddrChk : 1;
    1011     /** SVM: Supports Bus Lock Threshold. */
    1012     uint32_t        fSvmBusLockThreshold : 1;
    1013     /** SVM: Padding / reserved for future features (64 bits total w/ max ASID). */
    1014     uint32_t        fSvmPadding0 : 7;
    1015     /** SVM: Maximum supported ASID. */
    1016     uint32_t        uSvmMaxAsid;
    1017     /** @} */
    1018 
    1019 
    1020     /** VMX: Maximum physical address width. */
    1021     uint32_t        cVmxMaxPhysAddrWidth : 8;
    1022 
    1023     /** @name VMX basic controls.
    1024      * @{ */
    1025     /** VMX: Supports INS/OUTS VM-exit instruction info. */
    1026     uint32_t        fVmxInsOutInfo : 1;
    1027     /** @} */
    1028 
    1029     /** @name VMX Pin-based controls.
    1030      * @{ */
    1031     /** VMX: Supports external interrupt VM-exit. */
    1032     uint32_t        fVmxExtIntExit : 1;
    1033     /** VMX: Supports NMI VM-exit. */
    1034     uint32_t        fVmxNmiExit : 1;
    1035     /** VMX: Supports Virtual NMIs. */
    1036     uint32_t        fVmxVirtNmi : 1;
    1037     /** VMX: Supports preemption timer. */
    1038     uint32_t        fVmxPreemptTimer : 1;
    1039     /** VMX: Supports posted interrupts. */
    1040     uint32_t        fVmxPostedInt : 1;
    1041     /** @} */
    1042 
    1043     /** @name VMX Processor-based controls.
    1044      * @{ */
    1045     /** VMX: Supports Interrupt-window exiting. */
    1046     uint32_t        fVmxIntWindowExit : 1;
    1047     /** VMX: Supports TSC offsetting. */
    1048     uint32_t        fVmxTscOffsetting : 1;
    1049     /** VMX: Supports HLT exiting. */
    1050     uint32_t        fVmxHltExit : 1;
    1051     /** VMX: Supports INVLPG exiting. */
    1052     uint32_t        fVmxInvlpgExit : 1;
    1053     /** VMX: Supports MWAIT exiting. */
    1054     uint32_t        fVmxMwaitExit : 1;
    1055     /** VMX: Supports RDPMC exiting. */
    1056     uint32_t        fVmxRdpmcExit : 1;
    1057     /** VMX: Supports RDTSC exiting. */
    1058     uint32_t        fVmxRdtscExit : 1;
    1059     /** VMX: Supports CR3-load exiting. */
    1060     uint32_t        fVmxCr3LoadExit : 1;
    1061     /** VMX: Supports CR3-store exiting. */
    1062     uint32_t        fVmxCr3StoreExit : 1;
    1063     /** VMX: Supports tertiary processor-based VM-execution controls. */
    1064     uint32_t        fVmxTertiaryExecCtls : 1;
    1065     /** VMX: Supports CR8-load exiting. */
    1066     uint32_t        fVmxCr8LoadExit : 1;
    1067     /** VMX: Supports CR8-store exiting. */
    1068     uint32_t        fVmxCr8StoreExit : 1;
    1069     /** VMX: Supports TPR shadow. */
    1070     uint32_t        fVmxUseTprShadow : 1;
    1071     /** VMX: Supports NMI-window exiting. */
    1072     uint32_t        fVmxNmiWindowExit : 1;
    1073     /** VMX: Supports Mov-DRx exiting. */
    1074     uint32_t        fVmxMovDRxExit : 1;
    1075     /** VMX: Supports Unconditional I/O exiting. */
    1076     uint32_t        fVmxUncondIoExit : 1;
    1077     /** VMX: Supportgs I/O bitmaps. */
    1078     uint32_t        fVmxUseIoBitmaps : 1;
    1079     /** VMX: Supports Monitor Trap Flag. */
    1080     uint32_t        fVmxMonitorTrapFlag : 1;
    1081     /** VMX: Supports MSR bitmap. */
    1082     uint32_t        fVmxUseMsrBitmaps : 1;
    1083     /** VMX: Supports MONITOR exiting. */
    1084     uint32_t        fVmxMonitorExit : 1;
    1085     /** VMX: Supports PAUSE exiting. */
    1086     uint32_t        fVmxPauseExit : 1;
    1087     /** VMX: Supports secondary processor-based VM-execution controls. */
    1088     uint32_t        fVmxSecondaryExecCtls : 1;
    1089     /** @} */
    1090 
    1091     /** @name VMX Secondary processor-based controls.
    1092      * @{ */
    1093     /** VMX: Supports virtualize-APIC access. */
    1094     uint32_t        fVmxVirtApicAccess : 1;
    1095     /** VMX: Supports EPT (Extended Page Tables). */
    1096     uint32_t        fVmxEpt : 1;
    1097     /** VMX: Supports descriptor-table exiting. */
    1098     uint32_t        fVmxDescTableExit : 1;
    1099     /** VMX: Supports RDTSCP. */
    1100     uint32_t        fVmxRdtscp : 1;
    1101     /** VMX: Supports virtualize-x2APIC mode. */
    1102     uint32_t        fVmxVirtX2ApicMode : 1;
    1103     /** VMX: Supports VPID. */
    1104     uint32_t        fVmxVpid : 1;
    1105     /** VMX: Supports WBIND exiting. */
    1106     uint32_t        fVmxWbinvdExit : 1;
    1107     /** VMX: Supports Unrestricted guest. */
    1108     uint32_t        fVmxUnrestrictedGuest : 1;
    1109     /** VMX: Supports APIC-register virtualization. */
    1110     uint32_t        fVmxApicRegVirt : 1;
    1111     /** VMX: Supports virtual-interrupt delivery. */
    1112     uint32_t        fVmxVirtIntDelivery : 1;
    1113     /** VMX: Supports Pause-loop exiting. */
    1114     uint32_t        fVmxPauseLoopExit : 1;
    1115     /** VMX: Supports RDRAND exiting. */
    1116     uint32_t        fVmxRdrandExit : 1;
    1117     /** VMX: Supports INVPCID. */
    1118     uint32_t        fVmxInvpcid : 1;
    1119     /** VMX: Supports VM functions. */
    1120     uint32_t        fVmxVmFunc : 1;
    1121     /** VMX: Supports VMCS shadowing. */
    1122     uint32_t        fVmxVmcsShadowing : 1;
    1123     /** VMX: Supports RDSEED exiting. */
    1124     uint32_t        fVmxRdseedExit : 1;
    1125     /** VMX: Supports PML. */
    1126     uint32_t        fVmxPml : 1;
    1127     /** VMX: Supports EPT-violations \#VE. */
    1128     uint32_t        fVmxEptXcptVe : 1;
    1129     /** VMX: Supports conceal VMX from PT. */
    1130     uint32_t        fVmxConcealVmxFromPt : 1;
    1131     /** VMX: Supports XSAVES/XRSTORS. */
    1132     uint32_t        fVmxXsavesXrstors : 1;
    1133     /** VMX: Supports PASID translation. */
    1134     uint32_t        fVmxPasidTranslate : 1;
    1135     /** VMX: Supports mode-based execute control for EPT. */
    1136     uint32_t        fVmxModeBasedExecuteEpt : 1;
    1137     /** VMX: Supports sub-page write permissions for EPT. */
    1138     uint32_t        fVmxSppEpt : 1;
    1139     /** VMX: Supports Intel PT to output guest-physical addresses for EPT. */
    1140     uint32_t        fVmxPtEpt : 1;
    1141     /** VMX: Supports TSC scaling. */
    1142     uint32_t        fVmxUseTscScaling : 1;
    1143     /** VMX: Supports TPAUSE, UMONITOR, or UMWAIT. */
    1144     uint32_t        fVmxUserWaitPause : 1;
    1145     /** VMX: Supports PCONFIG. */
    1146     uint32_t        fVmxPconfig : 1;
    1147     /** VMX: Supports enclave (ENCLV) exiting. */
    1148     uint32_t        fVmxEnclvExit : 1;
    1149     /** VMX: Supports VMM bus-lock detection. */
    1150     uint32_t        fVmxBusLockDetect : 1;
    1151     /** VMX: Supports instruction timeout. */
    1152     uint32_t        fVmxInstrTimeout : 1;
    1153     /** @} */
    1154 
    1155     /** @name VMX Tertiary processor-based controls.
    1156      * @{ */
    1157     /** VMX: Supports LOADIWKEY exiting. */
    1158     uint32_t        fVmxLoadIwKeyExit : 1;
    1159     /** VMX: Supports hypervisor-managed linear address translation (HLAT). */
    1160     uint32_t        fVmxHlat : 1;
    1161     /** VMX: Supports EPT paging-write control. */
    1162     uint32_t        fVmxEptPagingWrite : 1;
    1163     /** VMX: Supports Guest-paging verification. */
    1164     uint32_t        fVmxGstPagingVerify : 1;
    1165     /** VMX: Supports IPI virtualization. */
    1166     uint32_t        fVmxIpiVirt : 1;
    1167     /** VMX: Supports virtualize IA32_SPEC_CTRL. */
    1168     uint32_t        fVmxVirtSpecCtrl : 1;
    1169     /** @} */
    1170 
    1171     /** @name VMX VM-entry controls.
    1172      * @{ */
    1173     /** VMX: Supports load-debug controls on VM-entry. */
    1174     uint32_t        fVmxEntryLoadDebugCtls : 1;
    1175     /** VMX: Supports IA32e mode guest. */
    1176     uint32_t        fVmxIa32eModeGuest : 1;
    1177     /** VMX: Supports load guest EFER MSR on VM-entry. */
    1178     uint32_t        fVmxEntryLoadEferMsr : 1;
    1179     /** VMX: Supports load guest PAT MSR on VM-entry. */
    1180     uint32_t        fVmxEntryLoadPatMsr : 1;
    1181     /** @} */
    1182 
    1183     /** @name VMX VM-exit controls.
    1184      * @{ */
    1185     /** VMX: Supports save debug controls on VM-exit. */
    1186     uint32_t        fVmxExitSaveDebugCtls : 1;
    1187     /** VMX: Supports host-address space size. */
    1188     uint32_t        fVmxHostAddrSpaceSize : 1;
    1189     /** VMX: Supports acknowledge external interrupt on VM-exit. */
    1190     uint32_t        fVmxExitAckExtInt : 1;
    1191     /** VMX: Supports save guest PAT MSR on VM-exit. */
    1192     uint32_t        fVmxExitSavePatMsr : 1;
    1193     /** VMX: Supports load hsot PAT MSR on VM-exit. */
    1194     uint32_t        fVmxExitLoadPatMsr : 1;
    1195     /** VMX: Supports save guest EFER MSR on VM-exit. */
    1196     uint32_t        fVmxExitSaveEferMsr : 1;
    1197     /** VMX: Supports load host EFER MSR on VM-exit. */
    1198     uint32_t        fVmxExitLoadEferMsr : 1;
    1199     /** VMX: Supports save VMX preemption timer on VM-exit. */
    1200     uint32_t        fVmxSavePreemptTimer : 1;
    1201     /** VMX: Supports secondary VM-exit controls. */
    1202     uint32_t        fVmxSecondaryExitCtls : 1;
    1203     /** @} */
    1204 
    1205     /** @name VMX Miscellaneous data.
    1206      * @{ */
    1207     /** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */
    1208     uint32_t        fVmxExitSaveEferLma : 1;
    1209     /** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */
    1210     uint32_t        fVmxPt : 1;
    1211     /** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
    1212      *  VMWRITE cannot modify read-only VM-exit information fields. */
    1213     uint32_t        fVmxVmwriteAll : 1;
    1214     /** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero
    1215      *  length instructions. */
    1216     uint32_t        fVmxEntryInjectSoftInt : 1;
    1217     /** @} */
    1218 
    1219     /** VMX: Padding / reserved for future features. */
    1220     uint32_t        fVmxPadding0 : 7;
    1221     /** VMX: Padding / reserved for future, making it a total of 128 bits.  */
    1222     uint32_t        fVmxPadding1;
    1223 } CPUMFEATURES;
    1224 #ifndef VBOX_FOR_DTRACE_LIB
    1225 AssertCompileSize(CPUMFEATURES, 48);
    1226 #endif
    1227 /** Pointer to a CPU feature structure. */
    1228 typedef CPUMFEATURES *PCPUMFEATURES;
    1229 /** Pointer to a const CPU feature structure. */
    1230 typedef CPUMFEATURES const *PCCPUMFEATURES;
    1231 
    1232 /**
    1233  * Chameleon wrapper structure for the host CPU features.
    1234  *
    1235  * This is used for the globally readable g_CpumHostFeatures variable, which is
    1236  * initialized once during VMMR0 load for ring-0 and during CPUMR3Init in
    1237  * ring-3.  To reflect this immutability after load/init, we use this wrapper
    1238  * structure to switch it between const and non-const depending on the context.
    1239  * Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp).
    1240  */
    1241 typedef struct CPUHOSTFEATURES
    1242 {
    1243     CPUMFEATURES
    1244 #ifndef CPUM_WITH_NONCONST_HOST_FEATURES
    1245     const
    1246 #endif
    1247                     s;
    1248 } CPUHOSTFEATURES;
    1249 /** Pointer to a const host CPU feature structure. */
    1250 typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;
    1251 
    1252 /** Host CPU features.
    1253  * @note In ring-3, only valid after CPUMR3Init.  In ring-0, valid after
    1254  *       module init. */
    1255 extern CPUHOSTFEATURES g_CpumHostFeatures;
    1256 
    1257 
    1258 /**
    1259755 * CPU database entry.
    1260756 */
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette