VirtualBox

source: vbox/trunk/include/VBox/vmm/cpum.h@ 83263

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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_cpum_h
27#define VBOX_INCLUDED_vmm_cpum_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/x86.h>
33#include <VBox/types.h>
34#ifdef RT_ARCH_AMD64
35# include <VBox/vmm/cpumctx.h>
36#endif
37#include <VBox/vmm/stam.h>
38#include <VBox/vmm/vmapi.h>
39#include <VBox/vmm/hm_svm.h>
40#include <VBox/vmm/hm_vmx.h>
41
42RT_C_DECLS_BEGIN
43
44/** @defgroup grp_cpum The CPU Monitor / Manager API
45 * @ingroup grp_vmm
46 * @{
47 */
48
49/**
50 * CPUID feature to set or clear.
51 */
52typedef enum CPUMCPUIDFEATURE
53{
54 CPUMCPUIDFEATURE_INVALID = 0,
55 /** The APIC feature bit. (Std+Ext)
56 * Note! There is a per-cpu flag for masking this CPUID feature bit when the
57 * APICBASE.ENABLED bit is zero. So, this feature is only set/cleared
58 * at VM construction time like all the others. This didn't used to be
59 * that way, this is new with 5.1. */
60 CPUMCPUIDFEATURE_APIC,
61 /** The sysenter/sysexit feature bit. (Std) */
62 CPUMCPUIDFEATURE_SEP,
63 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
64 CPUMCPUIDFEATURE_SYSCALL,
65 /** The PAE feature bit. (Std+Ext) */
66 CPUMCPUIDFEATURE_PAE,
67 /** The NX feature bit. (Ext) */
68 CPUMCPUIDFEATURE_NX,
69 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
70 CPUMCPUIDFEATURE_LAHF,
71 /** The LONG MODE feature bit. (Ext) */
72 CPUMCPUIDFEATURE_LONG_MODE,
73 /** The PAT feature bit. (Std+Ext) */
74 CPUMCPUIDFEATURE_PAT,
75 /** The x2APIC feature bit. (Std) */
76 CPUMCPUIDFEATURE_X2APIC,
77 /** The RDTSCP feature bit. (Ext) */
78 CPUMCPUIDFEATURE_RDTSCP,
79 /** The Hypervisor Present bit. (Std) */
80 CPUMCPUIDFEATURE_HVP,
81 /** The MWait Extensions bits (Std) */
82 CPUMCPUIDFEATURE_MWAIT_EXTS,
83 /** The speculation control feature bits. (StExt) */
84 CPUMCPUIDFEATURE_SPEC_CTRL,
85 /** 32bit hackishness. */
86 CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
87} CPUMCPUIDFEATURE;
88
89/**
90 * CPU Vendor.
91 */
92typedef enum CPUMCPUVENDOR
93{
94 CPUMCPUVENDOR_INVALID = 0,
95 CPUMCPUVENDOR_INTEL,
96 CPUMCPUVENDOR_AMD,
97 CPUMCPUVENDOR_VIA,
98 CPUMCPUVENDOR_CYRIX,
99 CPUMCPUVENDOR_SHANGHAI,
100 CPUMCPUVENDOR_HYGON,
101 CPUMCPUVENDOR_UNKNOWN,
102 /** 32bit hackishness. */
103 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
104} CPUMCPUVENDOR;
105
106
107/**
108 * X86 and AMD64 CPU microarchitectures and in processor generations.
109 *
110 * @remarks The separation here is sometimes a little bit too finely grained,
111 * and the differences is more like processor generation than micro
112 * arch. This can be useful, so we'll provide functions for getting at
113 * more coarse grained info.
114 */
115typedef enum CPUMMICROARCH
116{
117 kCpumMicroarch_Invalid = 0,
118
119 kCpumMicroarch_Intel_First,
120
121 kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
122 kCpumMicroarch_Intel_80186,
123 kCpumMicroarch_Intel_80286,
124 kCpumMicroarch_Intel_80386,
125 kCpumMicroarch_Intel_80486,
126 kCpumMicroarch_Intel_P5,
127
128 kCpumMicroarch_Intel_P6_Core_Atom_First,
129 kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
130 kCpumMicroarch_Intel_P6_II,
131 kCpumMicroarch_Intel_P6_III,
132
133 kCpumMicroarch_Intel_P6_M_Banias,
134 kCpumMicroarch_Intel_P6_M_Dothan,
135 kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */
136
137 kCpumMicroarch_Intel_Core2_First,
138 kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First, /**< 65nm, Merom/Conroe/Kentsfield/Tigerton */
139 kCpumMicroarch_Intel_Core2_Penryn, /**< 45nm, Penryn/Wolfdale/Yorkfield/Harpertown */
140 kCpumMicroarch_Intel_Core2_End,
141
142 kCpumMicroarch_Intel_Core7_First,
143 kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
144 kCpumMicroarch_Intel_Core7_Westmere,
145 kCpumMicroarch_Intel_Core7_SandyBridge,
146 kCpumMicroarch_Intel_Core7_IvyBridge,
147 kCpumMicroarch_Intel_Core7_Haswell,
148 kCpumMicroarch_Intel_Core7_Broadwell,
149 kCpumMicroarch_Intel_Core7_Skylake,
150 kCpumMicroarch_Intel_Core7_KabyLake,
151 kCpumMicroarch_Intel_Core7_CoffeeLake,
152 kCpumMicroarch_Intel_Core7_WhiskeyLake,
153 kCpumMicroarch_Intel_Core7_CascadeLake,
154 kCpumMicroarch_Intel_Core7_CannonLake,
155 kCpumMicroarch_Intel_Core7_IceLake,
156 kCpumMicroarch_Intel_Core7_TigerLake,
157 kCpumMicroarch_Intel_Core7_End,
158
159 kCpumMicroarch_Intel_Atom_First,
160 kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
161 kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */
162 kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */
163 kCpumMicroarch_Intel_Atom_Silvermont, /**< 22nm */
164 kCpumMicroarch_Intel_Atom_Airmount, /**< 14nm */
165 kCpumMicroarch_Intel_Atom_Goldmont, /**< 14nm */
166 kCpumMicroarch_Intel_Atom_GoldmontPlus, /**< 14nm */
167 kCpumMicroarch_Intel_Atom_Unknown,
168 kCpumMicroarch_Intel_Atom_End,
169
170
171 kCpumMicroarch_Intel_Phi_First,
172 kCpumMicroarch_Intel_Phi_KnightsFerry = kCpumMicroarch_Intel_Phi_First,
173 kCpumMicroarch_Intel_Phi_KnightsCorner,
174 kCpumMicroarch_Intel_Phi_KnightsLanding,
175 kCpumMicroarch_Intel_Phi_KnightsHill,
176 kCpumMicroarch_Intel_Phi_KnightsMill,
177 kCpumMicroarch_Intel_Phi_End,
178
179 kCpumMicroarch_Intel_P6_Core_Atom_End,
180
181 kCpumMicroarch_Intel_NB_First,
182 kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /**< 180nm */
183 kCpumMicroarch_Intel_NB_Northwood, /**< 130nm */
184 kCpumMicroarch_Intel_NB_Prescott, /**< 90nm */
185 kCpumMicroarch_Intel_NB_Prescott2M, /**< 90nm */
186 kCpumMicroarch_Intel_NB_CedarMill, /**< 65nm */
187 kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
188 kCpumMicroarch_Intel_NB_Unknown,
189 kCpumMicroarch_Intel_NB_End,
190
191 kCpumMicroarch_Intel_Unknown,
192 kCpumMicroarch_Intel_End,
193
194 kCpumMicroarch_AMD_First,
195 kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
196 kCpumMicroarch_AMD_Am386,
197 kCpumMicroarch_AMD_Am486,
198 kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */
199 kCpumMicroarch_AMD_K5,
200 kCpumMicroarch_AMD_K6,
201
202 kCpumMicroarch_AMD_K7_First,
203 kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
204 kCpumMicroarch_AMD_K7_Spitfire,
205 kCpumMicroarch_AMD_K7_Thunderbird,
206 kCpumMicroarch_AMD_K7_Morgan,
207 kCpumMicroarch_AMD_K7_Thoroughbred,
208 kCpumMicroarch_AMD_K7_Barton,
209 kCpumMicroarch_AMD_K7_Unknown,
210 kCpumMicroarch_AMD_K7_End,
211
212 kCpumMicroarch_AMD_K8_First,
213 kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
214 kCpumMicroarch_AMD_K8_90nm, /**< 90nm shrink */
215 kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */
216 kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */
217 kCpumMicroarch_AMD_K8_65nm, /**< 65nm shrink. */
218 kCpumMicroarch_AMD_K8_End,
219
220 kCpumMicroarch_AMD_K10,
221 kCpumMicroarch_AMD_K10_Lion,
222 kCpumMicroarch_AMD_K10_Llano,
223 kCpumMicroarch_AMD_Bobcat,
224 kCpumMicroarch_AMD_Jaguar,
225
226 kCpumMicroarch_AMD_15h_First,
227 kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
228 kCpumMicroarch_AMD_15h_Piledriver,
229 kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */
230 kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */
231 kCpumMicroarch_AMD_15h_Unknown,
232 kCpumMicroarch_AMD_15h_End,
233
234 kCpumMicroarch_AMD_16h_First,
235 kCpumMicroarch_AMD_16h_End,
236
237 kCpumMicroarch_AMD_Zen_First,
238 kCpumMicroarch_AMD_Zen_Ryzen = kCpumMicroarch_AMD_Zen_First,
239 kCpumMicroarch_AMD_Zen_End,
240
241 kCpumMicroarch_AMD_Unknown,
242 kCpumMicroarch_AMD_End,
243
244 kCpumMicroarch_Hygon_First,
245 kCpumMicroarch_Hygon_Dhyana = kCpumMicroarch_Hygon_First,
246 kCpumMicroarch_Hygon_Unknown,
247 kCpumMicroarch_Hygon_End,
248
249 kCpumMicroarch_VIA_First,
250 kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
251 kCpumMicroarch_Centaur_C2,
252 kCpumMicroarch_Centaur_C3,
253 kCpumMicroarch_VIA_C3_M2,
254 kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */
255 kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */
256 kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */
257 kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */
258 kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */
259 kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */
260 kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */
261 kCpumMicroarch_VIA_Isaiah,
262 kCpumMicroarch_VIA_Unknown,
263 kCpumMicroarch_VIA_End,
264
265 kCpumMicroarch_Shanghai_First,
266 kCpumMicroarch_Shanghai_Wudaokou = kCpumMicroarch_Shanghai_First,
267 kCpumMicroarch_Shanghai_Unknown,
268 kCpumMicroarch_Shanghai_End,
269
270 kCpumMicroarch_Cyrix_First,
271 kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
272 kCpumMicroarch_Cyrix_M1,
273 kCpumMicroarch_Cyrix_MediaGX,
274 kCpumMicroarch_Cyrix_MediaGXm,
275 kCpumMicroarch_Cyrix_M2,
276 kCpumMicroarch_Cyrix_Unknown,
277 kCpumMicroarch_Cyrix_End,
278
279 kCpumMicroarch_NEC_First,
280 kCpumMicroarch_NEC_V20 = kCpumMicroarch_NEC_First,
281 kCpumMicroarch_NEC_V30,
282 kCpumMicroarch_NEC_End,
283
284 kCpumMicroarch_Unknown,
285
286 kCpumMicroarch_32BitHack = 0x7fffffff
287} CPUMMICROARCH;
288
289
290/** Predicate macro for catching netburst CPUs. */
291#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
292 ((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
293
294/** Predicate macro for catching Core7 CPUs. */
295#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
296 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
297
298/** Predicate macro for catching Core 2 CPUs. */
299#define CPUMMICROARCH_IS_INTEL_CORE2(a_enmMicroarch) \
300 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core2_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core2_End)
301
302/** Predicate macro for catching Atom CPUs, Silvermont and upwards. */
303#define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \
304 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End)
305
306/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
307#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
308 ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
309
310/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
311#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
312
313/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
314#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
315
316/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
317#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
318
319/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
320#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
321
322/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
323 * decendants). */
324#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
325 ((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
326
327/** Predicate macro for catching AMD Family 16H CPUs. */
328#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
329 ((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
330
331
332
333/**
334 * CPUID leaf.
335 *
336 * @remarks This structure is used by the patch manager and is therefore
337 * more or less set in stone.
338 */
339typedef struct CPUMCPUIDLEAF
340{
341 /** The leaf number. */
342 uint32_t uLeaf;
343 /** The sub-leaf number. */
344 uint32_t uSubLeaf;
345 /** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
346 uint32_t fSubLeafMask;
347
348 /** The EAX value. */
349 uint32_t uEax;
350 /** The EBX value. */
351 uint32_t uEbx;
352 /** The ECX value. */
353 uint32_t uEcx;
354 /** The EDX value. */
355 uint32_t uEdx;
356
357 /** Flags. */
358 uint32_t fFlags;
359} CPUMCPUIDLEAF;
360#ifndef VBOX_FOR_DTRACE_LIB
361AssertCompileSize(CPUMCPUIDLEAF, 32);
362#endif
363/** Pointer to a CPUID leaf. */
364typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
365/** Pointer to a const CPUID leaf. */
366typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
367
368/** @name CPUMCPUIDLEAF::fFlags
369 * @{ */
370/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
371 * and EDX containing the extended APIC ID. */
372#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
373/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
374#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
375/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
376#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
377/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
378#define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
379/** Mask of the valid flags. */
380#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0xf)
381/** @} */
382
383/**
384 * Method used to deal with unknown CPUID leaves.
385 * @remarks Used in patch code.
386 */
387typedef enum CPUMUNKNOWNCPUID
388{
389 /** Invalid zero value. */
390 CPUMUNKNOWNCPUID_INVALID = 0,
391 /** Use given default values (DefCpuId). */
392 CPUMUNKNOWNCPUID_DEFAULTS,
393 /** Return the last standard leaf.
394 * Intel Sandy Bridge has been observed doing this. */
395 CPUMUNKNOWNCPUID_LAST_STD_LEAF,
396 /** Return the last standard leaf, with ecx observed.
397 * Intel Sandy Bridge has been observed doing this. */
398 CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
399 /** The register values are passed thru unmodified. */
400 CPUMUNKNOWNCPUID_PASSTHRU,
401 /** End of valid value. */
402 CPUMUNKNOWNCPUID_END,
403 /** Ensure 32-bit type. */
404 CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
405} CPUMUNKNOWNCPUID;
406/** Pointer to unknown CPUID leaf method. */
407typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
408
409
410/**
411 * The register set returned by a CPUID operation.
412 */
413typedef struct CPUMCPUID
414{
415 uint32_t uEax;
416 uint32_t uEbx;
417 uint32_t uEcx;
418 uint32_t uEdx;
419} CPUMCPUID;
420/** Pointer to a CPUID leaf. */
421typedef CPUMCPUID *PCPUMCPUID;
422/** Pointer to a const CPUID leaf. */
423typedef const CPUMCPUID *PCCPUMCPUID;
424
425
426/**
427 * MSR read functions.
428 */
429typedef enum CPUMMSRRDFN
430{
431 /** Invalid zero value. */
432 kCpumMsrRdFn_Invalid = 0,
433 /** Return the CPUMMSRRANGE::uValue. */
434 kCpumMsrRdFn_FixedValue,
435 /** Alias to the MSR range starting at the MSR given by
436 * CPUMMSRRANGE::uValue. Must be used in pair with
437 * kCpumMsrWrFn_MsrAlias. */
438 kCpumMsrRdFn_MsrAlias,
439 /** Write only register, GP all read attempts. */
440 kCpumMsrRdFn_WriteOnly,
441
442 kCpumMsrRdFn_Ia32P5McAddr,
443 kCpumMsrRdFn_Ia32P5McType,
444 kCpumMsrRdFn_Ia32TimestampCounter,
445 kCpumMsrRdFn_Ia32PlatformId, /**< Takes real CPU value for reference. */
446 kCpumMsrRdFn_Ia32ApicBase,
447 kCpumMsrRdFn_Ia32FeatureControl,
448 kCpumMsrRdFn_Ia32BiosSignId, /**< Range value returned. */
449 kCpumMsrRdFn_Ia32SmmMonitorCtl,
450 kCpumMsrRdFn_Ia32PmcN,
451 kCpumMsrRdFn_Ia32MonitorFilterLineSize,
452 kCpumMsrRdFn_Ia32MPerf,
453 kCpumMsrRdFn_Ia32APerf,
454 kCpumMsrRdFn_Ia32MtrrCap, /**< Takes real CPU value for reference. */
455 kCpumMsrRdFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
456 kCpumMsrRdFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
457 kCpumMsrRdFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
458 kCpumMsrRdFn_Ia32MtrrDefType,
459 kCpumMsrRdFn_Ia32Pat,
460 kCpumMsrRdFn_Ia32SysEnterCs,
461 kCpumMsrRdFn_Ia32SysEnterEsp,
462 kCpumMsrRdFn_Ia32SysEnterEip,
463 kCpumMsrRdFn_Ia32McgCap,
464 kCpumMsrRdFn_Ia32McgStatus,
465 kCpumMsrRdFn_Ia32McgCtl,
466 kCpumMsrRdFn_Ia32DebugCtl,
467 kCpumMsrRdFn_Ia32SmrrPhysBase,
468 kCpumMsrRdFn_Ia32SmrrPhysMask,
469 kCpumMsrRdFn_Ia32PlatformDcaCap,
470 kCpumMsrRdFn_Ia32CpuDcaCap,
471 kCpumMsrRdFn_Ia32Dca0Cap,
472 kCpumMsrRdFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
473 kCpumMsrRdFn_Ia32PerfStatus, /**< Range value returned. */
474 kCpumMsrRdFn_Ia32PerfCtl, /**< Range value returned. */
475 kCpumMsrRdFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
476 kCpumMsrRdFn_Ia32PerfCapabilities, /**< Takes reference value. */
477 kCpumMsrRdFn_Ia32FixedCtrCtrl,
478 kCpumMsrRdFn_Ia32PerfGlobalStatus, /**< Takes reference value. */
479 kCpumMsrRdFn_Ia32PerfGlobalCtrl,
480 kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
481 kCpumMsrRdFn_Ia32PebsEnable,
482 kCpumMsrRdFn_Ia32ClockModulation, /**< Range value returned. */
483 kCpumMsrRdFn_Ia32ThermInterrupt, /**< Range value returned. */
484 kCpumMsrRdFn_Ia32ThermStatus, /**< Range value returned. */
485 kCpumMsrRdFn_Ia32Therm2Ctl, /**< Range value returned. */
486 kCpumMsrRdFn_Ia32MiscEnable, /**< Range value returned. */
487 kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
488 kCpumMsrRdFn_Ia32McNCtl2, /**< Takes register number of start of range. */
489 kCpumMsrRdFn_Ia32DsArea,
490 kCpumMsrRdFn_Ia32TscDeadline,
491 kCpumMsrRdFn_Ia32X2ApicN,
492 kCpumMsrRdFn_Ia32DebugInterface,
493 kCpumMsrRdFn_Ia32VmxBasic, /**< Takes real value as reference. */
494 kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */
495 kCpumMsrRdFn_Ia32VmxProcbasedCtls, /**< Takes real value as reference. */
496 kCpumMsrRdFn_Ia32VmxExitCtls, /**< Takes real value as reference. */
497 kCpumMsrRdFn_Ia32VmxEntryCtls, /**< Takes real value as reference. */
498 kCpumMsrRdFn_Ia32VmxMisc, /**< Takes real value as reference. */
499 kCpumMsrRdFn_Ia32VmxCr0Fixed0, /**< Takes real value as reference. */
500 kCpumMsrRdFn_Ia32VmxCr0Fixed1, /**< Takes real value as reference. */
501 kCpumMsrRdFn_Ia32VmxCr4Fixed0, /**< Takes real value as reference. */
502 kCpumMsrRdFn_Ia32VmxCr4Fixed1, /**< Takes real value as reference. */
503 kCpumMsrRdFn_Ia32VmxVmcsEnum, /**< Takes real value as reference. */
504 kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /**< Takes real value as reference. */
505 kCpumMsrRdFn_Ia32VmxEptVpidCap, /**< Takes real value as reference. */
506 kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /**< Takes real value as reference. */
507 kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /**< Takes real value as reference. */
508 kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */
509 kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */
510 kCpumMsrRdFn_Ia32VmxVmFunc, /**< Takes real value as reference. */
511 kCpumMsrRdFn_Ia32SpecCtrl,
512 kCpumMsrRdFn_Ia32ArchCapabilities,
513
514 kCpumMsrRdFn_Amd64Efer,
515 kCpumMsrRdFn_Amd64SyscallTarget,
516 kCpumMsrRdFn_Amd64LongSyscallTarget,
517 kCpumMsrRdFn_Amd64CompSyscallTarget,
518 kCpumMsrRdFn_Amd64SyscallFlagMask,
519 kCpumMsrRdFn_Amd64FsBase,
520 kCpumMsrRdFn_Amd64GsBase,
521 kCpumMsrRdFn_Amd64KernelGsBase,
522 kCpumMsrRdFn_Amd64TscAux,
523
524 kCpumMsrRdFn_IntelEblCrPowerOn,
525 kCpumMsrRdFn_IntelI7CoreThreadCount,
526 kCpumMsrRdFn_IntelP4EbcHardPowerOn,
527 kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
528 kCpumMsrRdFn_IntelP4EbcFrequencyId,
529 kCpumMsrRdFn_IntelP6FsbFrequency, /**< Takes real value as reference. */
530 kCpumMsrRdFn_IntelPlatformInfo,
531 kCpumMsrRdFn_IntelFlexRatio, /**< Takes real value as reference. */
532 kCpumMsrRdFn_IntelPkgCStConfigControl,
533 kCpumMsrRdFn_IntelPmgIoCaptureBase,
534 kCpumMsrRdFn_IntelLastBranchFromToN,
535 kCpumMsrRdFn_IntelLastBranchFromN,
536 kCpumMsrRdFn_IntelLastBranchToN,
537 kCpumMsrRdFn_IntelLastBranchTos,
538 kCpumMsrRdFn_IntelBblCrCtl,
539 kCpumMsrRdFn_IntelBblCrCtl3,
540 kCpumMsrRdFn_IntelI7TemperatureTarget, /**< Range value returned. */
541 kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
542 kCpumMsrRdFn_IntelI7MiscPwrMgmt,
543 kCpumMsrRdFn_IntelP6CrN,
544 kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
545 kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
546 kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
547 kCpumMsrRdFn_IntelI7SandyAesNiCtl,
548 kCpumMsrRdFn_IntelI7TurboRatioLimit, /**< Returns range value. */
549 kCpumMsrRdFn_IntelI7LbrSelect,
550 kCpumMsrRdFn_IntelI7SandyErrorControl,
551 kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
552 kCpumMsrRdFn_IntelI7PowerCtl,
553 kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
554 kCpumMsrRdFn_IntelI7PebsLdLat,
555 kCpumMsrRdFn_IntelI7PkgCnResidencyN, /**< Takes C-state number. */
556 kCpumMsrRdFn_IntelI7CoreCnResidencyN, /**< Takes C-state number. */
557 kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
558 kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /**< Takes real value as reference. */
559 kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /**< Takes real value as reference. */
560 kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /**< Takes real value as reference. */
561 kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
562 kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /**< Takes real value as reference. */
563 kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
564 kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /**< Takes real value as reference. */
565 kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /**< Takes real value as reference. */
566 kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /**< Takes real value as reference. */
567 kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
568 kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /**< Takes real value as reference. */
569 kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /**< Takes real value as reference. */
570 kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /**< Takes real value as reference. */
571 kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
572 kCpumMsrRdFn_IntelI7RaplPp0Policy, /**< Takes real value as reference. */
573 kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /**< Takes real value as reference. */
574 kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /**< Takes real value as reference. */
575 kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
576 kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */
577 kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */
578 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */
579 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */
580 kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
581 kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
582 kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
583 kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
584 kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
585 kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
586 kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
587 kCpumMsrRdFn_IntelI7UncCBoxConfig,
588 kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
589 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
590 kCpumMsrRdFn_IntelI7SmiCount,
591 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */
592 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
593 kCpumMsrRdFn_IntelCore1ExtConfig,
594 kCpumMsrRdFn_IntelCore1DtsCalControl,
595 kCpumMsrRdFn_IntelCore2PeciControl,
596 kCpumMsrRdFn_IntelAtSilvCoreC1Recidency,
597
598 kCpumMsrRdFn_P6LastBranchFromIp,
599 kCpumMsrRdFn_P6LastBranchToIp,
600 kCpumMsrRdFn_P6LastIntFromIp,
601 kCpumMsrRdFn_P6LastIntToIp,
602
603 kCpumMsrRdFn_AmdFam15hTscRate,
604 kCpumMsrRdFn_AmdFam15hLwpCfg,
605 kCpumMsrRdFn_AmdFam15hLwpCbAddr,
606 kCpumMsrRdFn_AmdFam10hMc4MiscN,
607 kCpumMsrRdFn_AmdK8PerfCtlN,
608 kCpumMsrRdFn_AmdK8PerfCtrN,
609 kCpumMsrRdFn_AmdK8SysCfg, /**< Range value returned. */
610 kCpumMsrRdFn_AmdK8HwCr,
611 kCpumMsrRdFn_AmdK8IorrBaseN,
612 kCpumMsrRdFn_AmdK8IorrMaskN,
613 kCpumMsrRdFn_AmdK8TopOfMemN,
614 kCpumMsrRdFn_AmdK8NbCfg1,
615 kCpumMsrRdFn_AmdK8McXcptRedir,
616 kCpumMsrRdFn_AmdK8CpuNameN,
617 kCpumMsrRdFn_AmdK8HwThermalCtrl, /**< Range value returned. */
618 kCpumMsrRdFn_AmdK8SwThermalCtrl,
619 kCpumMsrRdFn_AmdK8FidVidControl, /**< Range value returned. */
620 kCpumMsrRdFn_AmdK8FidVidStatus, /**< Range value returned. */
621 kCpumMsrRdFn_AmdK8McCtlMaskN,
622 kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
623 kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
624 kCpumMsrRdFn_AmdK8IntPendingMessage,
625 kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
626 kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
627 kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
628 kCpumMsrRdFn_AmdFam10hPStateCurLimit, /**< Returns range value. */
629 kCpumMsrRdFn_AmdFam10hPStateControl, /**< Returns range value. */
630 kCpumMsrRdFn_AmdFam10hPStateStatus, /**< Returns range value. */
631 kCpumMsrRdFn_AmdFam10hPStateN, /**< Returns range value. This isn't an register index! */
632 kCpumMsrRdFn_AmdFam10hCofVidControl, /**< Returns range value. */
633 kCpumMsrRdFn_AmdFam10hCofVidStatus, /**< Returns range value. */
634 kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
635 kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
636 kCpumMsrRdFn_AmdK8SmmBase,
637 kCpumMsrRdFn_AmdK8SmmAddr,
638 kCpumMsrRdFn_AmdK8SmmMask,
639 kCpumMsrRdFn_AmdK8VmCr,
640 kCpumMsrRdFn_AmdK8IgnNe,
641 kCpumMsrRdFn_AmdK8SmmCtl,
642 kCpumMsrRdFn_AmdK8VmHSavePa,
643 kCpumMsrRdFn_AmdFam10hVmLockKey,
644 kCpumMsrRdFn_AmdFam10hSmmLockKey,
645 kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
646 kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
647 kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
648 kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
649 kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
650 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
651 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
652 kCpumMsrRdFn_AmdK7MicrocodeCtl, /**< Returns range value. */
653 kCpumMsrRdFn_AmdK7ClusterIdMaybe, /**< Returns range value. */
654 kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
655 kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
656 kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
657 kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
658 kCpumMsrRdFn_AmdK8PatchLevel, /**< Returns range value. */
659 kCpumMsrRdFn_AmdK7DebugStatusMaybe,
660 kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
661 kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
662 kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
663 kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
664 kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
665 kCpumMsrRdFn_AmdK7NodeId,
666 kCpumMsrRdFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
667 kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
668 kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
669 kCpumMsrRdFn_AmdK7LoadStoreCfg,
670 kCpumMsrRdFn_AmdK7InstrCacheCfg,
671 kCpumMsrRdFn_AmdK7DataCacheCfg,
672 kCpumMsrRdFn_AmdK7BusUnitCfg,
673 kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
674 kCpumMsrRdFn_AmdFam15hFpuCfg,
675 kCpumMsrRdFn_AmdFam15hDecoderCfg,
676 kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
677 kCpumMsrRdFn_AmdFam15hCombUnitCfg,
678 kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
679 kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
680 kCpumMsrRdFn_AmdFam15hExecUnitCfg,
681 kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
682 kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
683 kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
684 kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
685 kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
686 kCpumMsrRdFn_AmdFam10hIbsOpRip,
687 kCpumMsrRdFn_AmdFam10hIbsOpData,
688 kCpumMsrRdFn_AmdFam10hIbsOpData2,
689 kCpumMsrRdFn_AmdFam10hIbsOpData3,
690 kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
691 kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
692 kCpumMsrRdFn_AmdFam10hIbsCtl,
693 kCpumMsrRdFn_AmdFam14hIbsBrTarget,
694
695 kCpumMsrRdFn_Gim,
696
697 /** End of valid MSR read function indexes. */
698 kCpumMsrRdFn_End
699} CPUMMSRRDFN;
700
701/**
702 * MSR write functions.
703 */
704typedef enum CPUMMSRWRFN
705{
706 /** Invalid zero value. */
707 kCpumMsrWrFn_Invalid = 0,
708 /** Writes are ignored, the fWrGpMask is observed though. */
709 kCpumMsrWrFn_IgnoreWrite,
710 /** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
711 kCpumMsrWrFn_ReadOnly,
712 /** Alias to the MSR range starting at the MSR given by
713 * CPUMMSRRANGE::uValue. Must be used in pair with
714 * kCpumMsrRdFn_MsrAlias. */
715 kCpumMsrWrFn_MsrAlias,
716
717 kCpumMsrWrFn_Ia32P5McAddr,
718 kCpumMsrWrFn_Ia32P5McType,
719 kCpumMsrWrFn_Ia32TimestampCounter,
720 kCpumMsrWrFn_Ia32ApicBase,
721 kCpumMsrWrFn_Ia32FeatureControl,
722 kCpumMsrWrFn_Ia32BiosSignId,
723 kCpumMsrWrFn_Ia32BiosUpdateTrigger,
724 kCpumMsrWrFn_Ia32SmmMonitorCtl,
725 kCpumMsrWrFn_Ia32PmcN,
726 kCpumMsrWrFn_Ia32MonitorFilterLineSize,
727 kCpumMsrWrFn_Ia32MPerf,
728 kCpumMsrWrFn_Ia32APerf,
729 kCpumMsrWrFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
730 kCpumMsrWrFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
731 kCpumMsrWrFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
732 kCpumMsrWrFn_Ia32MtrrDefType,
733 kCpumMsrWrFn_Ia32Pat,
734 kCpumMsrWrFn_Ia32SysEnterCs,
735 kCpumMsrWrFn_Ia32SysEnterEsp,
736 kCpumMsrWrFn_Ia32SysEnterEip,
737 kCpumMsrWrFn_Ia32McgStatus,
738 kCpumMsrWrFn_Ia32McgCtl,
739 kCpumMsrWrFn_Ia32DebugCtl,
740 kCpumMsrWrFn_Ia32SmrrPhysBase,
741 kCpumMsrWrFn_Ia32SmrrPhysMask,
742 kCpumMsrWrFn_Ia32PlatformDcaCap,
743 kCpumMsrWrFn_Ia32Dca0Cap,
744 kCpumMsrWrFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
745 kCpumMsrWrFn_Ia32PerfStatus,
746 kCpumMsrWrFn_Ia32PerfCtl,
747 kCpumMsrWrFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
748 kCpumMsrWrFn_Ia32PerfCapabilities,
749 kCpumMsrWrFn_Ia32FixedCtrCtrl,
750 kCpumMsrWrFn_Ia32PerfGlobalStatus,
751 kCpumMsrWrFn_Ia32PerfGlobalCtrl,
752 kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
753 kCpumMsrWrFn_Ia32PebsEnable,
754 kCpumMsrWrFn_Ia32ClockModulation,
755 kCpumMsrWrFn_Ia32ThermInterrupt,
756 kCpumMsrWrFn_Ia32ThermStatus,
757 kCpumMsrWrFn_Ia32Therm2Ctl,
758 kCpumMsrWrFn_Ia32MiscEnable,
759 kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
760 kCpumMsrWrFn_Ia32McNCtl2, /**< Takes register number of start of range. */
761 kCpumMsrWrFn_Ia32DsArea,
762 kCpumMsrWrFn_Ia32TscDeadline,
763 kCpumMsrWrFn_Ia32X2ApicN,
764 kCpumMsrWrFn_Ia32DebugInterface,
765 kCpumMsrWrFn_Ia32SpecCtrl,
766 kCpumMsrWrFn_Ia32PredCmd,
767 kCpumMsrWrFn_Ia32FlushCmd,
768
769 kCpumMsrWrFn_Amd64Efer,
770 kCpumMsrWrFn_Amd64SyscallTarget,
771 kCpumMsrWrFn_Amd64LongSyscallTarget,
772 kCpumMsrWrFn_Amd64CompSyscallTarget,
773 kCpumMsrWrFn_Amd64SyscallFlagMask,
774 kCpumMsrWrFn_Amd64FsBase,
775 kCpumMsrWrFn_Amd64GsBase,
776 kCpumMsrWrFn_Amd64KernelGsBase,
777 kCpumMsrWrFn_Amd64TscAux,
778 kCpumMsrWrFn_IntelEblCrPowerOn,
779 kCpumMsrWrFn_IntelP4EbcHardPowerOn,
780 kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
781 kCpumMsrWrFn_IntelP4EbcFrequencyId,
782 kCpumMsrWrFn_IntelFlexRatio,
783 kCpumMsrWrFn_IntelPkgCStConfigControl,
784 kCpumMsrWrFn_IntelPmgIoCaptureBase,
785 kCpumMsrWrFn_IntelLastBranchFromToN,
786 kCpumMsrWrFn_IntelLastBranchFromN,
787 kCpumMsrWrFn_IntelLastBranchToN,
788 kCpumMsrWrFn_IntelLastBranchTos,
789 kCpumMsrWrFn_IntelBblCrCtl,
790 kCpumMsrWrFn_IntelBblCrCtl3,
791 kCpumMsrWrFn_IntelI7TemperatureTarget,
792 kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
793 kCpumMsrWrFn_IntelI7MiscPwrMgmt,
794 kCpumMsrWrFn_IntelP6CrN,
795 kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
796 kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
797 kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
798 kCpumMsrWrFn_IntelI7SandyAesNiCtl,
799 kCpumMsrWrFn_IntelI7TurboRatioLimit,
800 kCpumMsrWrFn_IntelI7LbrSelect,
801 kCpumMsrWrFn_IntelI7SandyErrorControl,
802 kCpumMsrWrFn_IntelI7PowerCtl,
803 kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
804 kCpumMsrWrFn_IntelI7PebsLdLat,
805 kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
806 kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
807 kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /**< R/O but found writable bits on a Silvermont CPU here. */
808 kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
809 kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /**< R/O but found writable bits on a Silvermont CPU here. */
810 kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
811 kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
812 kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
813 kCpumMsrWrFn_IntelI7RaplPp0Policy,
814 kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
815 kCpumMsrWrFn_IntelI7RaplPp1Policy,
816 kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
817 kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
818 kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
819 kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
820 kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
821 kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
822 kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
823 kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
824 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
825 kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
826 kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
827 kCpumMsrWrFn_IntelCore1ExtConfig,
828 kCpumMsrWrFn_IntelCore1DtsCalControl,
829 kCpumMsrWrFn_IntelCore2PeciControl,
830
831 kCpumMsrWrFn_P6LastIntFromIp,
832 kCpumMsrWrFn_P6LastIntToIp,
833
834 kCpumMsrWrFn_AmdFam15hTscRate,
835 kCpumMsrWrFn_AmdFam15hLwpCfg,
836 kCpumMsrWrFn_AmdFam15hLwpCbAddr,
837 kCpumMsrWrFn_AmdFam10hMc4MiscN,
838 kCpumMsrWrFn_AmdK8PerfCtlN,
839 kCpumMsrWrFn_AmdK8PerfCtrN,
840 kCpumMsrWrFn_AmdK8SysCfg,
841 kCpumMsrWrFn_AmdK8HwCr,
842 kCpumMsrWrFn_AmdK8IorrBaseN,
843 kCpumMsrWrFn_AmdK8IorrMaskN,
844 kCpumMsrWrFn_AmdK8TopOfMemN,
845 kCpumMsrWrFn_AmdK8NbCfg1,
846 kCpumMsrWrFn_AmdK8McXcptRedir,
847 kCpumMsrWrFn_AmdK8CpuNameN,
848 kCpumMsrWrFn_AmdK8HwThermalCtrl,
849 kCpumMsrWrFn_AmdK8SwThermalCtrl,
850 kCpumMsrWrFn_AmdK8FidVidControl,
851 kCpumMsrWrFn_AmdK8McCtlMaskN,
852 kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
853 kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
854 kCpumMsrWrFn_AmdK8IntPendingMessage,
855 kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
856 kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
857 kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
858 kCpumMsrWrFn_AmdFam10hPStateControl,
859 kCpumMsrWrFn_AmdFam10hPStateStatus,
860 kCpumMsrWrFn_AmdFam10hPStateN,
861 kCpumMsrWrFn_AmdFam10hCofVidControl,
862 kCpumMsrWrFn_AmdFam10hCofVidStatus,
863 kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
864 kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
865 kCpumMsrWrFn_AmdK8SmmBase,
866 kCpumMsrWrFn_AmdK8SmmAddr,
867 kCpumMsrWrFn_AmdK8SmmMask,
868 kCpumMsrWrFn_AmdK8VmCr,
869 kCpumMsrWrFn_AmdK8IgnNe,
870 kCpumMsrWrFn_AmdK8SmmCtl,
871 kCpumMsrWrFn_AmdK8VmHSavePa,
872 kCpumMsrWrFn_AmdFam10hVmLockKey,
873 kCpumMsrWrFn_AmdFam10hSmmLockKey,
874 kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
875 kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
876 kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
877 kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
878 kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
879 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
880 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
881 kCpumMsrWrFn_AmdK7MicrocodeCtl,
882 kCpumMsrWrFn_AmdK7ClusterIdMaybe,
883 kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
884 kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
885 kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
886 kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
887 kCpumMsrWrFn_AmdK8PatchLoader,
888 kCpumMsrWrFn_AmdK7DebugStatusMaybe,
889 kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
890 kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
891 kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
892 kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
893 kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
894 kCpumMsrWrFn_AmdK7NodeId,
895 kCpumMsrWrFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
896 kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
897 kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
898 kCpumMsrWrFn_AmdK7LoadStoreCfg,
899 kCpumMsrWrFn_AmdK7InstrCacheCfg,
900 kCpumMsrWrFn_AmdK7DataCacheCfg,
901 kCpumMsrWrFn_AmdK7BusUnitCfg,
902 kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
903 kCpumMsrWrFn_AmdFam15hFpuCfg,
904 kCpumMsrWrFn_AmdFam15hDecoderCfg,
905 kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
906 kCpumMsrWrFn_AmdFam15hCombUnitCfg,
907 kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
908 kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
909 kCpumMsrWrFn_AmdFam15hExecUnitCfg,
910 kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
911 kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
912 kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
913 kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
914 kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
915 kCpumMsrWrFn_AmdFam10hIbsOpRip,
916 kCpumMsrWrFn_AmdFam10hIbsOpData,
917 kCpumMsrWrFn_AmdFam10hIbsOpData2,
918 kCpumMsrWrFn_AmdFam10hIbsOpData3,
919 kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
920 kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
921 kCpumMsrWrFn_AmdFam10hIbsCtl,
922 kCpumMsrWrFn_AmdFam14hIbsBrTarget,
923
924 kCpumMsrWrFn_Gim,
925
926 /** End of valid MSR write function indexes. */
927 kCpumMsrWrFn_End
928} CPUMMSRWRFN;
929
930/**
931 * MSR range.
932 */
933typedef struct CPUMMSRRANGE
934{
935 /** The first MSR. [0] */
936 uint32_t uFirst;
937 /** The last MSR. [4] */
938 uint32_t uLast;
939 /** The read function (CPUMMSRRDFN). [8] */
940 uint16_t enmRdFn;
941 /** The write function (CPUMMSRWRFN). [10] */
942 uint16_t enmWrFn;
943 /** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
944 * UINT16_MAX if not used by the read and write functions. [12] */
945 uint16_t offCpumCpu;
946 /** Reserved for future hacks. [14] */
947 uint16_t fReserved;
948 /** The init/read value. [16]
949 * When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
950 * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
951 * offset into CPUM. */
952 uint64_t uValue;
953 /** The bits to ignore when writing. [24] */
954 uint64_t fWrIgnMask;
955 /** The bits that will cause a GP(0) when writing. [32]
956 * This is always checked prior to calling the write function. Using
957 * UINT64_MAX effectively marks the MSR as read-only. */
958 uint64_t fWrGpMask;
959 /** The register name, if applicable. [40] */
960 char szName[56];
961
962#ifdef VBOX_WITH_STATISTICS
963 /** The number of reads. */
964 STAMCOUNTER cReads;
965 /** The number of writes. */
966 STAMCOUNTER cWrites;
967 /** The number of times ignored bits were written. */
968 STAMCOUNTER cIgnoredBits;
969 /** The number of GPs generated. */
970 STAMCOUNTER cGps;
971#endif
972} CPUMMSRRANGE;
973#ifndef VBOX_FOR_DTRACE_LIB
974# ifdef VBOX_WITH_STATISTICS
975AssertCompileSize(CPUMMSRRANGE, 128);
976# else
977AssertCompileSize(CPUMMSRRANGE, 96);
978# endif
979#endif
980/** Pointer to an MSR range. */
981typedef CPUMMSRRANGE *PCPUMMSRRANGE;
982/** Pointer to a const MSR range. */
983typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
984
985
986/**
987 * MSRs.
988 * MSRs which are required while exploding features.
989 */
990typedef struct CPUMMSRS
991{
992 union
993 {
994 VMXMSRS vmx;
995 SVMMSRS svm;
996 } hwvirt;
997} CPUMMSRS;
998/** Pointer to an CPUMMSRS struct. */
999typedef CPUMMSRS *PCPUMMSRS;
1000/** Pointer to a const CPUMMSRS struct. */
1001typedef CPUMMSRS const *PCCPUMMSRS;
1002
1003
1004/**
1005 * CPU features and quirks.
1006 * This is mostly exploded CPUID info.
1007 */
1008typedef struct CPUMFEATURES
1009{
1010 /** The CPU vendor (CPUMCPUVENDOR). */
1011 uint8_t enmCpuVendor;
1012 /** The CPU family. */
1013 uint8_t uFamily;
1014 /** The CPU model. */
1015 uint8_t uModel;
1016 /** The CPU stepping. */
1017 uint8_t uStepping;
1018 /** The microarchitecture. */
1019#ifndef VBOX_FOR_DTRACE_LIB
1020 CPUMMICROARCH enmMicroarch;
1021#else
1022 uint32_t enmMicroarch;
1023#endif
1024 /** The maximum physical address width of the CPU. */
1025 uint8_t cMaxPhysAddrWidth;
1026 /** The maximum linear address width of the CPU. */
1027 uint8_t cMaxLinearAddrWidth;
1028 /** Max size of the extended state (or FPU state if no XSAVE). */
1029 uint16_t cbMaxExtendedState;
1030
1031 /** Supports MSRs. */
1032 uint32_t fMsr : 1;
1033 /** Supports the page size extension (4/2 MB pages). */
1034 uint32_t fPse : 1;
1035 /** Supports 36-bit page size extension (4 MB pages can map memory above
1036 * 4GB). */
1037 uint32_t fPse36 : 1;
1038 /** Supports physical address extension (PAE). */
1039 uint32_t fPae : 1;
1040 /** Page attribute table (PAT) support (page level cache control). */
1041 uint32_t fPat : 1;
1042 /** Supports the FXSAVE and FXRSTOR instructions. */
1043 uint32_t fFxSaveRstor : 1;
1044 /** Supports the XSAVE and XRSTOR instructions. */
1045 uint32_t fXSaveRstor : 1;
1046 /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
1047 uint32_t fOpSysXSaveRstor : 1;
1048 /** Supports MMX. */
1049 uint32_t fMmx : 1;
1050 /** Supports AMD extensions to MMX instructions. */
1051 uint32_t fAmdMmxExts : 1;
1052 /** Supports SSE. */
1053 uint32_t fSse : 1;
1054 /** Supports SSE2. */
1055 uint32_t fSse2 : 1;
1056 /** Supports SSE3. */
1057 uint32_t fSse3 : 1;
1058 /** Supports SSSE3. */
1059 uint32_t fSsse3 : 1;
1060 /** Supports SSE4.1. */
1061 uint32_t fSse41 : 1;
1062 /** Supports SSE4.2. */
1063 uint32_t fSse42 : 1;
1064 /** Supports AVX. */
1065 uint32_t fAvx : 1;
1066 /** Supports AVX2. */
1067 uint32_t fAvx2 : 1;
1068 /** Supports AVX512 foundation. */
1069 uint32_t fAvx512Foundation : 1;
1070 /** Supports RDTSC. */
1071 uint32_t fTsc : 1;
1072 /** Intel SYSENTER/SYSEXIT support */
1073 uint32_t fSysEnter : 1;
1074 /** First generation APIC. */
1075 uint32_t fApic : 1;
1076 /** Second generation APIC. */
1077 uint32_t fX2Apic : 1;
1078 /** Hypervisor present. */
1079 uint32_t fHypervisorPresent : 1;
1080 /** MWAIT & MONITOR instructions supported. */
1081 uint32_t fMonitorMWait : 1;
1082 /** MWAIT Extensions present. */
1083 uint32_t fMWaitExtensions : 1;
1084 /** Supports CMPXCHG16B in 64-bit mode. */
1085 uint32_t fMovCmpXchg16b : 1;
1086 /** Supports CLFLUSH. */
1087 uint32_t fClFlush : 1;
1088 /** Supports CLFLUSHOPT. */
1089 uint32_t fClFlushOpt : 1;
1090 /** Supports IA32_PRED_CMD.IBPB. */
1091 uint32_t fIbpb : 1;
1092 /** Supports IA32_SPEC_CTRL.IBRS. */
1093 uint32_t fIbrs : 1;
1094 /** Supports IA32_SPEC_CTRL.STIBP. */
1095 uint32_t fStibp : 1;
1096 /** Supports IA32_FLUSH_CMD. */
1097 uint32_t fFlushCmd : 1;
1098 /** Supports IA32_ARCH_CAP. */
1099 uint32_t fArchCap : 1;
1100 /** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */
1101 uint32_t fMdsClear : 1;
1102 /** Supports PCID. */
1103 uint32_t fPcid : 1;
1104 /** Supports INVPCID. */
1105 uint32_t fInvpcid : 1;
1106 /** Supports read/write FSGSBASE instructions. */
1107 uint32_t fFsGsBase : 1;
1108
1109 /** Supports AMD 3DNow instructions. */
1110 uint32_t f3DNow : 1;
1111 /** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
1112 uint32_t f3DNowPrefetch : 1;
1113
1114 /** AMD64: Supports long mode. */
1115 uint32_t fLongMode : 1;
1116 /** AMD64: SYSCALL/SYSRET support. */
1117 uint32_t fSysCall : 1;
1118 /** AMD64: No-execute page table bit. */
1119 uint32_t fNoExecute : 1;
1120 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
1121 uint32_t fLahfSahf : 1;
1122 /** AMD64: Supports RDTSCP. */
1123 uint32_t fRdTscP : 1;
1124 /** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
1125 uint32_t fMovCr8In32Bit : 1;
1126 /** AMD64: Supports XOP (similar to VEX3/AVX). */
1127 uint32_t fXop : 1;
1128
1129 /** Indicates that FPU instruction and data pointers may leak.
1130 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
1131 * is only saved and restored if an exception is pending. */
1132 uint32_t fLeakyFxSR : 1;
1133
1134 /** AMD64: Supports AMD SVM. */
1135 uint32_t fSvm : 1;
1136
1137 /** Support for Intel VMX. */
1138 uint32_t fVmx : 1;
1139
1140 /** Indicates that speculative execution control CPUID bits and MSRs are exposed.
1141 * The details are different for Intel and AMD but both have similar
1142 * functionality. */
1143 uint32_t fSpeculationControl : 1;
1144
1145 /** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0).
1146 * @remarks Only safe use after CPUM ring-0 init! */
1147 uint32_t fArchRdclNo : 1;
1148 /** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1).
1149 * @remarks Only safe use after CPUM ring-0 init! */
1150 uint32_t fArchIbrsAll : 1;
1151 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2).
1152 * @remarks Only safe use after CPUM ring-0 init! */
1153 uint32_t fArchRsbOverride : 1;
1154 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3).
1155 * @remarks Only safe use after CPUM ring-0 init! */
1156 uint32_t fArchVmmNeedNotFlushL1d : 1;
1157 /** MSR_IA32_ARCH_CAPABILITIES: MDS_NO (bit 4).
1158 * @remarks Only safe use after CPUM ring-0 init! */
1159 uint32_t fArchMdsNo : 1;
1160
1161 /** Alignment padding / reserved for future use. */
1162 uint32_t fPadding : 8;
1163
1164 /** SVM: Supports Nested-paging. */
1165 uint32_t fSvmNestedPaging : 1;
1166 /** SVM: Support LBR (Last Branch Record) virtualization. */
1167 uint32_t fSvmLbrVirt : 1;
1168 /** SVM: Supports SVM lock. */
1169 uint32_t fSvmSvmLock : 1;
1170 /** SVM: Supports Next RIP save. */
1171 uint32_t fSvmNextRipSave : 1;
1172 /** SVM: Supports TSC rate MSR. */
1173 uint32_t fSvmTscRateMsr : 1;
1174 /** SVM: Supports VMCB clean bits. */
1175 uint32_t fSvmVmcbClean : 1;
1176 /** SVM: Supports Flush-by-ASID. */
1177 uint32_t fSvmFlusbByAsid : 1;
1178 /** SVM: Supports decode assist. */
1179 uint32_t fSvmDecodeAssists : 1;
1180 /** SVM: Supports Pause filter. */
1181 uint32_t fSvmPauseFilter : 1;
1182 /** SVM: Supports Pause filter threshold. */
1183 uint32_t fSvmPauseFilterThreshold : 1;
1184 /** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
1185 uint32_t fSvmAvic : 1;
1186 /** SVM: Supports Virtualized VMSAVE/VMLOAD. */
1187 uint32_t fSvmVirtVmsaveVmload : 1;
1188 /** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
1189 uint32_t fSvmVGif : 1;
1190 /** SVM: Supports GMET (Guest Mode Execute Trap Extension). */
1191 uint32_t fSvmGmet : 1;
1192 /** SVM: Padding / reserved for future features. */
1193 uint32_t fSvmPadding0 : 18;
1194 /** SVM: Maximum supported ASID. */
1195 uint32_t uSvmMaxAsid;
1196
1197 /** VMX: Maximum physical address width. */
1198 uint8_t cVmxMaxPhysAddrWidth;
1199 /** VMX: Padding / reserved for future. */
1200 uint8_t abVmxPadding[3];
1201 /** VMX: Padding / reserved for future. */
1202 uint32_t fVmxPadding0;
1203
1204 /** @name VMX basic controls.
1205 * @{ */
1206 /** VMX: Supports INS/OUTS VM-exit instruction info. */
1207 uint32_t fVmxInsOutInfo : 1;
1208 /** @} */
1209
1210 /** @name VMX Pin-based controls.
1211 * @{ */
1212 /** VMX: Supports external interrupt VM-exit. */
1213 uint32_t fVmxExtIntExit : 1;
1214 /** VMX: Supports NMI VM-exit. */
1215 uint32_t fVmxNmiExit : 1;
1216 /** VMX: Supports Virtual NMIs. */
1217 uint32_t fVmxVirtNmi : 1;
1218 /** VMX: Supports preemption timer. */
1219 uint32_t fVmxPreemptTimer : 1;
1220 /** VMX: Supports posted interrupts. */
1221 uint32_t fVmxPostedInt : 1;
1222 /** @} */
1223
1224 /** @name VMX Processor-based controls.
1225 * @{ */
1226 /** VMX: Supports Interrupt-window exiting. */
1227 uint32_t fVmxIntWindowExit : 1;
1228 /** VMX: Supports TSC offsetting. */
1229 uint32_t fVmxTscOffsetting : 1;
1230 /** VMX: Supports HLT exiting. */
1231 uint32_t fVmxHltExit : 1;
1232 /** VMX: Supports INVLPG exiting. */
1233 uint32_t fVmxInvlpgExit : 1;
1234 /** VMX: Supports MWAIT exiting. */
1235 uint32_t fVmxMwaitExit : 1;
1236 /** VMX: Supports RDPMC exiting. */
1237 uint32_t fVmxRdpmcExit : 1;
1238 /** VMX: Supports RDTSC exiting. */
1239 uint32_t fVmxRdtscExit : 1;
1240 /** VMX: Supports CR3-load exiting. */
1241 uint32_t fVmxCr3LoadExit : 1;
1242 /** VMX: Supports CR3-store exiting. */
1243 uint32_t fVmxCr3StoreExit : 1;
1244 /** VMX: Supports CR8-load exiting. */
1245 uint32_t fVmxCr8LoadExit : 1;
1246 /** VMX: Supports CR8-store exiting. */
1247 uint32_t fVmxCr8StoreExit : 1;
1248 /** VMX: Supports TPR shadow. */
1249 uint32_t fVmxUseTprShadow : 1;
1250 /** VMX: Supports NMI-window exiting. */
1251 uint32_t fVmxNmiWindowExit : 1;
1252 /** VMX: Supports Mov-DRx exiting. */
1253 uint32_t fVmxMovDRxExit : 1;
1254 /** VMX: Supports Unconditional I/O exiting. */
1255 uint32_t fVmxUncondIoExit : 1;
1256 /** VMX: Supportgs I/O bitmaps. */
1257 uint32_t fVmxUseIoBitmaps : 1;
1258 /** VMX: Supports Monitor Trap Flag. */
1259 uint32_t fVmxMonitorTrapFlag : 1;
1260 /** VMX: Supports MSR bitmap. */
1261 uint32_t fVmxUseMsrBitmaps : 1;
1262 /** VMX: Supports MONITOR exiting. */
1263 uint32_t fVmxMonitorExit : 1;
1264 /** VMX: Supports PAUSE exiting. */
1265 uint32_t fVmxPauseExit : 1;
1266 /** VMX: Supports secondary processor-based VM-execution controls. */
1267 uint32_t fVmxSecondaryExecCtls : 1;
1268 /** @} */
1269
1270 /** @name VMX Secondary processor-based controls.
1271 * @{ */
1272 /** VMX: Supports virtualize-APIC access. */
1273 uint32_t fVmxVirtApicAccess : 1;
1274 /** VMX: Supports EPT (Extended Page Tables). */
1275 uint32_t fVmxEpt : 1;
1276 /** VMX: Supports descriptor-table exiting. */
1277 uint32_t fVmxDescTableExit : 1;
1278 /** VMX: Supports RDTSCP. */
1279 uint32_t fVmxRdtscp : 1;
1280 /** VMX: Supports virtualize-x2APIC mode. */
1281 uint32_t fVmxVirtX2ApicMode : 1;
1282 /** VMX: Supports VPID. */
1283 uint32_t fVmxVpid : 1;
1284 /** VMX: Supports WBIND exiting. */
1285 uint32_t fVmxWbinvdExit : 1;
1286 /** VMX: Supports Unrestricted guest. */
1287 uint32_t fVmxUnrestrictedGuest : 1;
1288 /** VMX: Supports APIC-register virtualization. */
1289 uint32_t fVmxApicRegVirt : 1;
1290 /** VMX: Supports virtual-interrupt delivery. */
1291 uint32_t fVmxVirtIntDelivery : 1;
1292 /** VMX: Supports Pause-loop exiting. */
1293 uint32_t fVmxPauseLoopExit : 1;
1294 /** VMX: Supports RDRAND exiting. */
1295 uint32_t fVmxRdrandExit : 1;
1296 /** VMX: Supports INVPCID. */
1297 uint32_t fVmxInvpcid : 1;
1298 /** VMX: Supports VM functions. */
1299 uint32_t fVmxVmFunc : 1;
1300 /** VMX: Supports VMCS shadowing. */
1301 uint32_t fVmxVmcsShadowing : 1;
1302 /** VMX: Supports RDSEED exiting. */
1303 uint32_t fVmxRdseedExit : 1;
1304 /** VMX: Supports PML. */
1305 uint32_t fVmxPml : 1;
1306 /** VMX: Supports EPT-violations \#VE. */
1307 uint32_t fVmxEptXcptVe : 1;
1308 /** VMX: Supports XSAVES/XRSTORS. */
1309 uint32_t fVmxXsavesXrstors : 1;
1310 /** VMX: Supports TSC scaling. */
1311 uint32_t fVmxUseTscScaling : 1;
1312 /** @} */
1313
1314 /** @name VMX VM-entry controls.
1315 * @{ */
1316 /** VMX: Supports load-debug controls on VM-entry. */
1317 uint32_t fVmxEntryLoadDebugCtls : 1;
1318 /** VMX: Supports IA32e mode guest. */
1319 uint32_t fVmxIa32eModeGuest : 1;
1320 /** VMX: Supports load guest EFER MSR on VM-entry. */
1321 uint32_t fVmxEntryLoadEferMsr : 1;
1322 /** VMX: Supports load guest PAT MSR on VM-entry. */
1323 uint32_t fVmxEntryLoadPatMsr : 1;
1324 /** @} */
1325
1326 /** @name VMX VM-exit controls.
1327 * @{ */
1328 /** VMX: Supports save debug controls on VM-exit. */
1329 uint32_t fVmxExitSaveDebugCtls : 1;
1330 /** VMX: Supports host-address space size. */
1331 uint32_t fVmxHostAddrSpaceSize : 1;
1332 /** VMX: Supports acknowledge external interrupt on VM-exit. */
1333 uint32_t fVmxExitAckExtInt : 1;
1334 /** VMX: Supports save guest PAT MSR on VM-exit. */
1335 uint32_t fVmxExitSavePatMsr : 1;
1336 /** VMX: Supports load hsot PAT MSR on VM-exit. */
1337 uint32_t fVmxExitLoadPatMsr : 1;
1338 /** VMX: Supports save guest EFER MSR on VM-exit. */
1339 uint32_t fVmxExitSaveEferMsr : 1;
1340 /** VMX: Supports load host EFER MSR on VM-exit. */
1341 uint32_t fVmxExitLoadEferMsr : 1;
1342 /** VMX: Supports save VMX preemption timer on VM-exit. */
1343 uint32_t fVmxSavePreemptTimer : 1;
1344 /** @} */
1345
1346 /** @name VMX Miscellaneous data.
1347 * @{ */
1348 /** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */
1349 uint32_t fVmxExitSaveEferLma : 1;
1350 /** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */
1351 uint32_t fVmxIntelPt : 1;
1352 /** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1353 * VMWRITE cannot modify read-only VM-exit information fields. */
1354 uint32_t fVmxVmwriteAll : 1;
1355 /** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero
1356 * length instructions. */
1357 uint32_t fVmxEntryInjectSoftInt : 1;
1358 /** @} */
1359
1360 /** VMX: Padding / reserved for future features. */
1361 uint32_t fVmxPadding1 : 1;
1362 uint32_t fVmxPadding2;
1363} CPUMFEATURES;
1364#ifndef VBOX_FOR_DTRACE_LIB
1365AssertCompileSize(CPUMFEATURES, 48);
1366#endif
1367/** Pointer to a CPU feature structure. */
1368typedef CPUMFEATURES *PCPUMFEATURES;
1369/** Pointer to a const CPU feature structure. */
1370typedef CPUMFEATURES const *PCCPUMFEATURES;
1371
1372
1373#ifndef VBOX_FOR_DTRACE_LIB
1374
1375/** @name Guest Register Getters.
1376 * @{ */
1377VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR);
1378VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit);
1379VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden);
1380VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu);
1381VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
1382VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu);
1383VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu);
1384VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu);
1385VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu);
1386VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu);
1387VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue);
1388VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu);
1389VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu);
1390VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu);
1391VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu);
1392VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu);
1393VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu);
1394VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu);
1395VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu);
1396VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu);
1397VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu);
1398VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu);
1399VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu);
1400VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu);
1401VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu);
1402VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu);
1403VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu);
1404VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu);
1405VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu);
1406VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu);
1407VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu);
1408VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu);
1409VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu);
1410VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu);
1411VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu);
1412VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu);
1413VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1414VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t iLeaf, uint32_t iSubLeaf,
1415 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
1416VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu);
1417VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PCVMCPU pVCpu);
1418VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPU pVCpu);
1419VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *puValue);
1420VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t uValue);
1421VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1422VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM);
1423VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1424VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM);
1425/** @} */
1426
1427/** @name Guest Register Setters.
1428 * @{ */
1429VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1430VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1431VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1432VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1433VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0);
1434VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1435VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1436VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1437VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0);
1438VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1);
1439VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2);
1440VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3);
1441VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1442VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7);
1443VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value);
1444VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue);
1445VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1446VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1447VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1448VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1449VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1450VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1451VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1452VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1453VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1454VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1455VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1456VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1457VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1458VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1459VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1460VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1461VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1462VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1463VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1464VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1465VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible);
1466VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1467VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPUCC pVCpu, uint64_t uValue);
1468VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPUCC pVCpu);
1469VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPUCC pVCpu, uint64_t uValue);
1470VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPUCC pVCpu);
1471VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM);
1472/** @} */
1473
1474
1475/** @name Misc Guest Predicate Functions.
1476 * @{ */
1477VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
1478VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu);
1479VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu);
1480VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu);
1481VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu);
1482VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu);
1483VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu);
1484VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu);
1485VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu);
1486VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu);
1487VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu);
1488/** @} */
1489
1490/** @name Nested Hardware-Virtualization Helpers.
1491 * @{ */
1492VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu);
1493VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu);
1494VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1495VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1496
1497/* SVM helpers. */
1498VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1499VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1500VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx);
1501VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx);
1502VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr);
1503VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
1504 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
1505 PSVMIOIOEXITINFO pIoExitInfo);
1506VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit);
1507
1508/* VMX helpers. */
1509VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField);
1510VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess);
1511VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3);
1512VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc);
1513VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick);
1514VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu);
1515VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr);
1516/** @} */
1517
1518/** @name Externalized State Helpers.
1519 * @{ */
1520/** @def CPUM_ASSERT_NOT_EXTRN
1521 * Macro for asserting that @a a_fNotExtrn are present.
1522 *
1523 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1524 * @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
1525 *
1526 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1527 */
1528#define CPUM_ASSERT_NOT_EXTRN(a_pVCpu, a_fNotExtrn) \
1529 AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fNotExtrn)), \
1530 ("%#RX64; a_fNotExtrn=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, (a_fNotExtrn)))
1531
1532/** @def CPUM_IMPORT_EXTRN_RET
1533 * Macro for making sure the state specified by @a fExtrnImport is present,
1534 * calling CPUMImportGuestStateOnDemand() to get it if necessary.
1535 *
1536 * Will return if CPUMImportGuestStateOnDemand() fails.
1537 *
1538 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1539 * @param a_fExtrnImport Mask of CPUMCTX_EXTRN_XXX bits to get.
1540 * @thread EMT(a_pVCpu)
1541 *
1542 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1543 */
1544#define CPUM_IMPORT_EXTRN_RET(a_pVCpu, a_fExtrnImport) \
1545 do { \
1546 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1547 { /* already present, consider this likely */ } \
1548 else \
1549 { \
1550 int rcCpumImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1551 AssertRCReturn(rcCpumImport, rcCpumImport); \
1552 } \
1553 } while (0)
1554
1555/** @def CPUM_IMPORT_EXTRN_RCSTRICT
1556 * Macro for making sure the state specified by @a fExtrnImport is present,
1557 * calling CPUMImportGuestStateOnDemand() to get it if necessary.
1558 *
1559 * Will update a_rcStrict if CPUMImportGuestStateOnDemand() fails.
1560 *
1561 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1562 * @param a_fExtrnImport Mask of CPUMCTX_EXTRN_XXX bits to get.
1563 * @param a_rcStrict Strict status code variable to update on failure.
1564 * @thread EMT(a_pVCpu)
1565 *
1566 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1567 */
1568#define CPUM_IMPORT_EXTRN_RCSTRICT(a_pVCpu, a_fExtrnImport, a_rcStrict) \
1569 do { \
1570 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1571 { /* already present, consider this likely */ } \
1572 else \
1573 { \
1574 int rcCpumImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1575 AssertStmt(RT_SUCCESS(rcCpumImport) || RT_FAILURE_NP(a_rcStrict), a_rcStrict = rcCpumImport); \
1576 } \
1577 } while (0)
1578
1579VMM_INT_DECL(int) CPUMImportGuestStateOnDemand(PVMCPUCC pVCpu, uint64_t fExtrnImport);
1580/** @} */
1581
1582#if (!defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS) && defined(RT_ARCH_AMD64)) || defined(DOXYGEN_RUNNING)
1583/** @name Inlined Guest Getters and predicates Functions.
1584 * @{ */
1585
1586/**
1587 * Gets valid CR0 bits for the guest.
1588 *
1589 * @returns Valid CR0 bits.
1590 */
1591DECLINLINE(uint64_t) CPUMGetGuestCR0ValidMask(void)
1592{
1593 return ( X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
1594 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM
1595 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG);
1596}
1597
1598/**
1599 * Tests if the guest is running in real mode or not.
1600 *
1601 * @returns true if in real mode, otherwise false.
1602 * @param pCtx Current CPU context.
1603 */
1604DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCCPUMCTX pCtx)
1605{
1606 return !(pCtx->cr0 & X86_CR0_PE);
1607}
1608
1609/**
1610 * Tests if the guest is running in real or virtual 8086 mode.
1611 *
1612 * @returns @c true if it is, @c false if not.
1613 * @param pCtx Current CPU context.
1614 */
1615DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCCPUMCTX pCtx)
1616{
1617 return !(pCtx->cr0 & X86_CR0_PE)
1618 || pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1619}
1620
1621/**
1622 * Tests if the guest is running in virtual 8086 mode.
1623 *
1624 * @returns @c true if it is, @c false if not.
1625 * @param pCtx Current CPU context.
1626 */
1627DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCCPUMCTX pCtx)
1628{
1629 return (pCtx->eflags.Bits.u1VM == 1);
1630}
1631
1632/**
1633 * Tests if the guest is running in paged protected or not.
1634 *
1635 * @returns true if in paged protected mode, otherwise false.
1636 * @param pCtx Current CPU context.
1637 */
1638DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1639{
1640 return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1641}
1642
1643/**
1644 * Tests if the guest is running in long mode or not.
1645 *
1646 * @returns true if in long mode, otherwise false.
1647 * @param pCtx Current CPU context.
1648 */
1649DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCCPUMCTX pCtx)
1650{
1651 return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1652}
1653
1654VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1655
1656/**
1657 * Tests if the guest is running in 64 bits mode or not.
1658 *
1659 * @returns true if in 64 bits protected mode, otherwise false.
1660 * @param pCtx Current CPU context.
1661 */
1662DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1663{
1664 if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1665 return false;
1666 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1667 return CPUMIsGuestIn64BitCodeSlow(pCtx);
1668 return pCtx->cs.Attr.n.u1Long;
1669}
1670
1671/**
1672 * Tests if the guest has paging enabled or not.
1673 *
1674 * @returns true if paging is enabled, otherwise false.
1675 * @param pCtx Current CPU context.
1676 */
1677DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCCPUMCTX pCtx)
1678{
1679 return !!(pCtx->cr0 & X86_CR0_PG);
1680}
1681
1682/**
1683 * Tests if the guest is running in PAE mode or not.
1684 *
1685 * @returns true if in PAE mode, otherwise false.
1686 * @param pCtx Current CPU context.
1687 */
1688DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCCPUMCTX pCtx)
1689{
1690 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1691 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1692 return ( (pCtx->cr4 & X86_CR4_PAE)
1693 && CPUMIsGuestPagingEnabledEx(pCtx)
1694 && !(pCtx->msrEFER & MSR_K6_EFER_LMA));
1695}
1696
1697/**
1698 * Tests if the guest has AMD SVM enabled or not.
1699 *
1700 * @returns true if SMV is enabled, otherwise false.
1701 * @param pCtx Current CPU context.
1702 */
1703DECLINLINE(bool) CPUMIsGuestSvmEnabled(PCCPUMCTX pCtx)
1704{
1705 return RT_BOOL(pCtx->msrEFER & MSR_K6_EFER_SVME);
1706}
1707
1708/**
1709 * Tests if the guest has Intel VT-x enabled or not.
1710 *
1711 * @returns true if VMX is enabled, otherwise false.
1712 * @param pCtx Current CPU context.
1713 */
1714DECLINLINE(bool) CPUMIsGuestVmxEnabled(PCCPUMCTX pCtx)
1715{
1716 return RT_BOOL(pCtx->cr4 & X86_CR4_VMXE);
1717}
1718
1719/**
1720 * Returns the guest's global-interrupt (GIF) flag.
1721 *
1722 * @returns true when global-interrupts are enabled, otherwise false.
1723 * @param pCtx Current CPU context.
1724 */
1725DECLINLINE(bool) CPUMGetGuestGif(PCCPUMCTX pCtx)
1726{
1727 return pCtx->hwvirt.fGif;
1728}
1729
1730/**
1731 * Sets the guest's global-interrupt flag (GIF).
1732 *
1733 * @param pCtx Current CPU context.
1734 * @param fGif The value to set.
1735 */
1736DECLINLINE(void) CPUMSetGuestGif(PCPUMCTX pCtx, bool fGif)
1737{
1738 pCtx->hwvirt.fGif = fGif;
1739}
1740
1741/**
1742 * Checks if we are executing inside an SVM nested hardware-virtualized guest.
1743 *
1744 * @returns @c true if in SVM nested-guest mode, @c false otherwise.
1745 * @param pCtx Current CPU context.
1746 */
1747DECLINLINE(bool) CPUMIsGuestInSvmNestedHwVirtMode(PCCPUMCTX pCtx)
1748{
1749 /*
1750 * With AMD-V, the VMRUN intercept is a pre-requisite to entering SVM guest-mode.
1751 * See AMD spec. 15.5 "VMRUN instruction" subsection "Canonicalization and Consistency Checks".
1752 */
1753#ifndef IN_RC
1754 if ( pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM
1755 || !(pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN))
1756 return false;
1757 return true;
1758#else
1759 NOREF(pCtx);
1760 return false;
1761#endif
1762}
1763
1764/**
1765 * Checks if the guest is in VMX non-root operation.
1766 *
1767 * @returns @c true if in VMX non-root operation, @c false otherwise.
1768 * @param pCtx Current CPU context.
1769 */
1770DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx)
1771{
1772#ifndef IN_RC
1773 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
1774 return false;
1775 Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode || pCtx->hwvirt.vmx.fInVmxRootMode);
1776 return pCtx->hwvirt.vmx.fInVmxNonRootMode;
1777#else
1778 NOREF(pCtx);
1779 return false;
1780#endif
1781}
1782
1783/**
1784 * Checks if we are executing inside an SVM or VMX nested hardware-virtualized
1785 * guest.
1786 *
1787 * @returns @c true if in nested-guest mode, @c false otherwise.
1788 * @param pCtx Current CPU context.
1789 */
1790DECLINLINE(bool) CPUMIsGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
1791{
1792 return CPUMIsGuestInVmxNonRootMode(pCtx) || CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
1793}
1794
1795/**
1796 * Checks if the guest is in VMX root operation.
1797 *
1798 * @returns @c true if in VMX root operation, @c false otherwise.
1799 * @param pCtx Current CPU context.
1800 */
1801DECLINLINE(bool) CPUMIsGuestInVmxRootMode(PCCPUMCTX pCtx)
1802{
1803#ifndef IN_RC
1804 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
1805 return false;
1806 return pCtx->hwvirt.vmx.fInVmxRootMode;
1807#else
1808 NOREF(pCtx);
1809 return false;
1810#endif
1811}
1812
1813# ifndef IN_RC
1814
1815/**
1816 * Checks if the nested-guest VMCB has the specified ctrl/instruction intercept
1817 * active.
1818 *
1819 * @returns @c true if in intercept is set, @c false otherwise.
1820 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1821 * @param pCtx Pointer to the context.
1822 * @param fIntercept The SVM control/instruction intercept, see
1823 * SVM_CTRL_INTERCEPT_*.
1824 */
1825DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint64_t fIntercept)
1826{
1827 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1828 return false;
1829 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1830 Assert(pVmcb);
1831 uint64_t u64Intercepts;
1832 if (!HMGetGuestSvmCtrlIntercepts(pVCpu, &u64Intercepts))
1833 u64Intercepts = pVmcb->ctrl.u64InterceptCtrl;
1834 return RT_BOOL(u64Intercepts & fIntercept);
1835}
1836
1837/**
1838 * Checks if the nested-guest VMCB has the specified CR read intercept active.
1839 *
1840 * @returns @c true if in intercept is set, @c false otherwise.
1841 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1842 * @param pCtx Pointer to the context.
1843 * @param uCr The CR register number (0 to 15).
1844 */
1845DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1846{
1847 Assert(uCr < 16);
1848 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1849 return false;
1850 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1851 Assert(pVmcb);
1852 uint16_t u16Intercepts;
1853 if (!HMGetGuestSvmReadCRxIntercepts(pVCpu, &u16Intercepts))
1854 u16Intercepts = pVmcb->ctrl.u16InterceptRdCRx;
1855 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
1856}
1857
1858/**
1859 * Checks if the nested-guest VMCB has the specified CR write intercept active.
1860 *
1861 * @returns @c true if in intercept is set, @c false otherwise.
1862 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1863 * @param pCtx Pointer to the context.
1864 * @param uCr The CR register number (0 to 15).
1865 */
1866DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1867{
1868 Assert(uCr < 16);
1869 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1870 return false;
1871 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1872 Assert(pVmcb);
1873 uint16_t u16Intercepts;
1874 if (!HMGetGuestSvmWriteCRxIntercepts(pVCpu, &u16Intercepts))
1875 u16Intercepts = pVmcb->ctrl.u16InterceptWrCRx;
1876 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
1877}
1878
1879/**
1880 * Checks if the nested-guest VMCB has the specified DR read intercept active.
1881 *
1882 * @returns @c true if in intercept is set, @c false otherwise.
1883 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1884 * @param pCtx Pointer to the context.
1885 * @param uDr The DR register number (0 to 15).
1886 */
1887DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1888{
1889 Assert(uDr < 16);
1890 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1891 return false;
1892 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1893 Assert(pVmcb);
1894 uint16_t u16Intercepts;
1895 if (!HMGetGuestSvmReadDRxIntercepts(pVCpu, &u16Intercepts))
1896 u16Intercepts = pVmcb->ctrl.u16InterceptRdDRx;
1897 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
1898}
1899
1900/**
1901 * Checks if the nested-guest VMCB has the specified DR write intercept active.
1902 *
1903 * @returns @c true if in intercept is set, @c false otherwise.
1904 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1905 * @param pCtx Pointer to the context.
1906 * @param uDr The DR register number (0 to 15).
1907 */
1908DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1909{
1910 Assert(uDr < 16);
1911 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1912 return false;
1913 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1914 Assert(pVmcb);
1915 uint16_t u16Intercepts;
1916 if (!HMGetGuestSvmWriteDRxIntercepts(pVCpu, &u16Intercepts))
1917 u16Intercepts = pVmcb->ctrl.u16InterceptWrDRx;
1918 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
1919}
1920
1921/**
1922 * Checks if the nested-guest VMCB has the specified exception intercept active.
1923 *
1924 * @returns @c true if in intercept is active, @c false otherwise.
1925 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1926 * @param pCtx Pointer to the context.
1927 * @param uVector The exception / interrupt vector.
1928 */
1929DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
1930{
1931 Assert(uVector <= X86_XCPT_LAST);
1932 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1933 return false;
1934 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1935 Assert(pVmcb);
1936 uint32_t u32Intercepts;
1937 if (!HMGetGuestSvmXcptIntercepts(pVCpu, &u32Intercepts))
1938 u32Intercepts = pVmcb->ctrl.u32InterceptXcpt;
1939 return RT_BOOL(u32Intercepts & RT_BIT(uVector));
1940}
1941
1942/**
1943 * Checks if the nested-guest VMCB has virtual-interrupt masking enabled.
1944 *
1945 * @returns @c true if virtual-interrupts are masked, @c false otherwise.
1946 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1947 * @param pCtx Pointer to the context.
1948 *
1949 * @remarks Should only be called when SVM feature is exposed to the guest.
1950 */
1951DECLINLINE(bool) CPUMIsGuestSvmVirtIntrMasking(PCVMCPU pVCpu, PCCPUMCTX pCtx)
1952{
1953 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1954 return false;
1955 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1956 Assert(pVmcb);
1957 bool fVIntrMasking;
1958 if (!HMGetGuestSvmVirtIntrMasking(pVCpu, &fVIntrMasking))
1959 fVIntrMasking = pVmcb->ctrl.IntCtrl.n.u1VIntrMasking;
1960 return fVIntrMasking;
1961}
1962
1963/**
1964 * Checks if the nested-guest VMCB has nested-paging enabled.
1965 *
1966 * @returns @c true if nested-paging is enabled, @c false otherwise.
1967 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1968 * @param pCtx Pointer to the context.
1969 *
1970 * @remarks Should only be called when SVM feature is exposed to the guest.
1971 */
1972DECLINLINE(bool) CPUMIsGuestSvmNestedPagingEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
1973{
1974 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1975 return false;
1976 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1977 Assert(pVmcb);
1978 bool fNestedPaging;
1979 if (!HMGetGuestSvmNestedPaging(pVCpu, &fNestedPaging))
1980 fNestedPaging = pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging;
1981 return fNestedPaging;
1982}
1983
1984/**
1985 * Gets the nested-guest VMCB pause-filter count.
1986 *
1987 * @returns The pause-filter count.
1988 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1989 * @param pCtx Pointer to the context.
1990 *
1991 * @remarks Should only be called when SVM feature is exposed to the guest.
1992 */
1993DECLINLINE(uint16_t) CPUMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, PCCPUMCTX pCtx)
1994{
1995 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1996 return false;
1997 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1998 Assert(pVmcb);
1999 uint16_t u16PauseFilterCount;
2000 if (!HMGetGuestSvmPauseFilterCount(pVCpu, &u16PauseFilterCount))
2001 u16PauseFilterCount = pVmcb->ctrl.u16PauseFilterCount;
2002 return u16PauseFilterCount;
2003}
2004
2005/**
2006 * Updates the NextRIP (NRIP) field in the nested-guest VMCB.
2007 *
2008 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2009 * @param pCtx Pointer to the context.
2010 * @param cbInstr The length of the current instruction in bytes.
2011 *
2012 * @remarks Should only be called when SVM feature is exposed to the guest.
2013 */
2014DECLINLINE(void) CPUMGuestSvmUpdateNRip(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t cbInstr)
2015{
2016 RT_NOREF(pVCpu);
2017 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2018 PSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2019 Assert(pVmcb);
2020 pVmcb->ctrl.u64NextRIP = pCtx->rip + cbInstr;
2021}
2022
2023/**
2024 * Checks whether one of the given Pin-based VM-execution controls are set when
2025 * executing a nested-guest.
2026 *
2027 * @returns @c true if set, @c false otherwise.
2028 * @param pCtx Pointer to the context.
2029 * @param uPinCtls The Pin-based VM-execution controls to check.
2030 *
2031 * @remarks This does not check if all given controls are set if more than one
2032 * control is passed in @a uPinCtl.
2033 */
2034DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PCCPUMCTX pCtx, uint32_t uPinCtls)
2035{
2036 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2037 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2038 Assert(pVmcs);
2039 return RT_BOOL(pVmcs->u32PinCtls & uPinCtls);
2040}
2041
2042/**
2043 * Checks whether one of the given Processor-based VM-execution controls are set
2044 * when executing a nested-guest.
2045 *
2046 * @returns @c true if set, @c false otherwise.
2047 * @param pCtx Pointer to the context.
2048 * @param uProcCtls The Processor-based VM-execution controls to check.
2049 *
2050 * @remarks This does not check if all given controls are set if more than one
2051 * control is passed in @a uProcCtls.
2052 */
2053DECLINLINE(bool) CPUMIsGuestVmxProcCtlsSet(PCCPUMCTX pCtx, uint32_t uProcCtls)
2054{
2055 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2056 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2057 Assert(pVmcs);
2058 return RT_BOOL(pVmcs->u32ProcCtls & uProcCtls);
2059}
2060
2061/**
2062 * Checks whether one of the given Secondary Processor-based VM-execution controls
2063 * are set when executing a nested-guest.
2064 *
2065 * @returns @c true if set, @c false otherwise.
2066 * @param pCtx Pointer to the context.
2067 * @param uProcCtls2 The Secondary Processor-based VM-execution controls to
2068 * check.
2069 *
2070 * @remarks This does not check if all given controls are set if more than one
2071 * control is passed in @a uProcCtls2.
2072 */
2073DECLINLINE(bool) CPUMIsGuestVmxProcCtls2Set(PCCPUMCTX pCtx, uint32_t uProcCtls2)
2074{
2075 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2076 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2077 Assert(pVmcs);
2078 return RT_BOOL(pVmcs->u32ProcCtls2 & uProcCtls2);
2079}
2080
2081/**
2082 * Checks whether one of the given VM-exit controls are set when executing a
2083 * nested-guest.
2084 *
2085 * @returns @c true if set, @c false otherwise.
2086 * @param pCtx Pointer to the context.
2087 * @param uExitCtls The VM-exit controls to check.
2088 *
2089 * @remarks This does not check if all given controls are set if more than one
2090 * control is passed in @a uExitCtls.
2091 */
2092DECLINLINE(bool) CPUMIsGuestVmxExitCtlsSet(PCCPUMCTX pCtx, uint32_t uExitCtls)
2093{
2094 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2095 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2096 Assert(pVmcs);
2097 return RT_BOOL(pVmcs->u32ExitCtls & uExitCtls);
2098}
2099
2100/**
2101 * Checks whether one of the given VM-entry controls are set when executing a
2102 * nested-guest.
2103 *
2104 * @returns @c true if set, @c false otherwise.
2105 * @param pCtx Pointer to the context.
2106 * @param uEntryCtls The VM-entry controls to check.
2107 *
2108 * @remarks This does not check if all given controls are set if more than one
2109 * control is passed in @a uEntryCtls.
2110 */
2111DECLINLINE(bool) CPUMIsGuestVmxEntryCtlsSet(PCCPUMCTX pCtx, uint32_t uEntryCtls)
2112{
2113 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2114 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2115 Assert(pVmcs);
2116 return RT_BOOL(pVmcs->u32EntryCtls & uEntryCtls);
2117}
2118
2119/**
2120 * Checks whether events injected in the nested-guest are subject to VM-exit checks.
2121 *
2122 * @returns @c true if set, @c false otherwise.
2123 * @param pCtx Pointer to the context.
2124 */
2125DECLINLINE(bool) CPUMIsGuestVmxInterceptEvents(PCCPUMCTX pCtx)
2126{
2127 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2128 return pCtx->hwvirt.vmx.fInterceptEvents;
2129}
2130
2131/**
2132 * Sets whether events injected in the nested-guest are subject to VM-exit checks.
2133 *
2134 * @param pCtx Pointer to the context.
2135 * @param fIntercept Whether to subject injected events to VM-exits or not.
2136 */
2137DECLINLINE(void) CPUMSetGuestVmxInterceptEvents(PCPUMCTX pCtx, bool fInterceptEvents)
2138{
2139 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2140 pCtx->hwvirt.vmx.fInterceptEvents = fInterceptEvents;
2141}
2142
2143/**
2144 * Checks whether the given exception causes a VM-exit.
2145 *
2146 * The exception type include hardware exceptions, software exceptions (#BP, #OF)
2147 * and privileged software exceptions (#DB generated by INT1/ICEBP).
2148 *
2149 * Software interrupts do -not- cause VM-exits and hence must not be used with this
2150 * function.
2151 *
2152 * @returns @c true if the exception causes a VM-exit, @c false otherwise.
2153 * @param pCtx Pointer to the context.
2154 * @param uVector The exception vector.
2155 * @param uErrCode The error code associated with the exception. Pass 0 if not
2156 * applicable.
2157 */
2158DECLINLINE(bool) CPUMIsGuestVmxXcptInterceptSet(PCCPUMCTX pCtx, uint8_t uVector, uint32_t uErrCode)
2159{
2160 Assert(uVector <= X86_XCPT_LAST);
2161
2162 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2163 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2164 Assert(pVmcs);
2165
2166 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
2167 if (uVector == X86_XCPT_NMI)
2168 return RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
2169
2170 /* Page-faults are subject to masking using its error code. */
2171 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
2172 if (uVector == X86_XCPT_PF)
2173 {
2174 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
2175 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
2176 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
2177 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
2178 }
2179
2180 /* Consult the exception bitmap for all other exceptions. */
2181 if (fXcptBitmap & RT_BIT(uVector))
2182 return true;
2183 return false;
2184}
2185
2186/**
2187 * Implements VMSucceed for VMX instruction success.
2188 *
2189 * @param pVCpu The cross context virtual CPU structure.
2190 */
2191DECLINLINE(void) CPUMSetGuestVmxVmSucceed(PCPUMCTX pCtx)
2192{
2193 pCtx->eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2194}
2195
2196/**
2197 * Implements VMFailInvalid for VMX instruction failure.
2198 *
2199 * @param pVCpu The cross context virtual CPU structure.
2200 */
2201DECLINLINE(void) CPUMSetGuestVmxVmFailInvalid(PCPUMCTX pCtx)
2202{
2203 pCtx->eflags.u32 &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2204 pCtx->eflags.u32 |= X86_EFL_CF;
2205}
2206
2207/**
2208 * Implements VMFailValid for VMX instruction failure.
2209 *
2210 * @param pVCpu The cross context virtual CPU structure.
2211 * @param enmInsErr The VM instruction error.
2212 */
2213DECLINLINE(void) CPUMSetGuestVmxVmFailValid(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2214{
2215 pCtx->eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2216 pCtx->eflags.u32 |= X86_EFL_ZF;
2217 pCtx->hwvirt.vmx.CTX_SUFF(pVmcs)->u32RoVmInstrError = enmInsErr;
2218}
2219
2220/**
2221 * Implements VMFail for VMX instruction failure.
2222 *
2223 * @param pVCpu The cross context virtual CPU structure.
2224 * @param enmInsErr The VM instruction error.
2225 */
2226DECLINLINE(void) CPUMSetGuestVmxVmFail(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2227{
2228 if (pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS)
2229 CPUMSetGuestVmxVmFailValid(pCtx, enmInsErr);
2230 else
2231 CPUMSetGuestVmxVmFailInvalid(pCtx);
2232}
2233
2234/**
2235 * Returns the guest-physical address of the APIC-access page when executing a
2236 * nested-guest.
2237 *
2238 * @returns The APIC-access page guest-physical address.
2239 * @param pCtx Pointer to the context.
2240 */
2241DECLINLINE(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PCCPUMCTX pCtx)
2242{
2243 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2244 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2245 Assert(pVmcs);
2246 return pVmcs->u64AddrApicAccess.u;
2247}
2248
2249/**
2250 * Gets the nested-guest CR0 subject to the guest/host mask and the read-shadow.
2251 *
2252 * @returns The nested-guest CR0.
2253 * @param pCtx Pointer to the context.
2254 * @param fGstHostMask The CR0 guest/host mask to use.
2255 */
2256DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr0(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2257{
2258 /*
2259 * For each CR0 bit owned by the host, the corresponding bit from the
2260 * CR0 read shadow is loaded. For each CR0 bit that is not owned by the host,
2261 * the corresponding bit from the guest CR0 is loaded.
2262 *
2263 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2264 */
2265 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2266 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2267 Assert(pVmcs);
2268 uint64_t const uGstCr0 = pCtx->cr0;
2269 uint64_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2270 return (fReadShadow & fGstHostMask) | (uGstCr0 & ~fGstHostMask);
2271}
2272
2273/**
2274 * Gets the nested-guest CR4 subject to the guest/host mask and the read-shadow.
2275 *
2276 * @returns The nested-guest CR4.
2277 * @param pCtx Pointer to the context.
2278 * @param fGstHostMask The CR4 guest/host mask to use.
2279 */
2280DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr4(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2281{
2282 /*
2283 * For each CR4 bit owned by the host, the corresponding bit from the
2284 * CR4 read shadow is loaded. For each CR4 bit that is not owned by the host,
2285 * the corresponding bit from the guest CR4 is loaded.
2286 *
2287 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2288 */
2289 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2290 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2291 Assert(pVmcs);
2292 uint64_t const uGstCr4 = pCtx->cr4;
2293 uint64_t const fReadShadow = pVmcs->u64Cr4ReadShadow.u;
2294 return (fReadShadow & fGstHostMask) | (uGstCr4 & ~fGstHostMask);
2295}
2296
2297/**
2298 * Checks whether the LMSW access causes a VM-exit or not.
2299 *
2300 * @returns @c true if the LMSW access causes a VM-exit, @c false otherwise.
2301 * @param pCtx Pointer to the context.
2302 * @param uNewMsw The LMSW source operand (the Machine Status Word).
2303 */
2304DECLINLINE(bool) CPUMIsGuestVmxLmswInterceptSet(PCCPUMCTX pCtx, uint16_t uNewMsw)
2305{
2306 /*
2307 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
2308 *
2309 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
2310 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2311 */
2312 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2313 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2314 Assert(pVmcs);
2315
2316 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
2317 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2318
2319 /*
2320 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
2321 * CR0.PE case first, before the rest of the bits in the MSW.
2322 *
2323 * If CR0.PE is owned by the host and CR0.PE differs between the
2324 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
2325 */
2326 if ( (fGstHostMask & X86_CR0_PE)
2327 && (uNewMsw & X86_CR0_PE)
2328 && !(fReadShadow & X86_CR0_PE))
2329 return true;
2330
2331 /*
2332 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
2333 * bits differ between the MSW (source operand) and the read-shadow, we must
2334 * cause a VM-exit.
2335 */
2336 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2337 if ((fReadShadow & fGstHostLmswMask) != (uNewMsw & fGstHostLmswMask))
2338 return true;
2339
2340 return false;
2341}
2342
2343/**
2344 * Checks whether the Mov-to-CR0/CR4 access causes a VM-exit or not.
2345 *
2346 * @returns @c true if the Mov CRX access causes a VM-exit, @c false otherwise.
2347 * @param pCtx Pointer to the context.
2348 * @param iCrReg The control register number (must be 0 or 4).
2349 * @param uNewCrX The CR0/CR4 value being written.
2350 */
2351DECLINLINE(bool) CPUMIsGuestVmxMovToCr0Cr4InterceptSet(PCCPUMCTX pCtx, uint8_t iCrReg, uint64_t uNewCrX)
2352{
2353 /*
2354 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
2355 * corresponding bits differ between the source operand and the read-shadow,
2356 * we must cause a VM-exit.
2357 *
2358 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2359 */
2360 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2361 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2362 Assert(pVmcs);
2363 Assert(iCrReg == 0 || iCrReg == 4);
2364
2365 uint64_t fGstHostMask;
2366 uint64_t fReadShadow;
2367 if (iCrReg == 0)
2368 {
2369 fGstHostMask = pVmcs->u64Cr0Mask.u;
2370 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2371 }
2372 else
2373 {
2374 fGstHostMask = pVmcs->u64Cr4Mask.u;
2375 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
2376 }
2377
2378 if ((fReadShadow & fGstHostMask) != (uNewCrX & fGstHostMask))
2379 {
2380 Assert(fGstHostMask != 0);
2381 return true;
2382 }
2383
2384 return false;
2385}
2386
2387/**
2388 * Returns whether the guest has an active, current VMCS.
2389 *
2390 * @returns @c true if the guest has an active, current VMCS, @c false otherwise.
2391 * @param pCtx Pointer to the context.
2392 */
2393DECLINLINE(bool) CPUMIsGuestVmxCurrentVmcsValid(PCCPUMCTX pCtx)
2394{
2395 RTGCPHYS const GCPhysVmcs = pCtx->hwvirt.vmx.GCPhysVmcs;
2396 return RT_BOOL(GCPhysVmcs != NIL_RTGCPHYS);
2397}
2398
2399/**
2400 * Gets the nested-guest virtual-APIC page.
2401 *
2402 * @returns The virtual-APIC page.
2403 * @param pCtx Pointer to the context.
2404 * @param pHCPhys Where to store the host-physical address of the virtual-APIC
2405 * page.
2406 */
2407DECLINLINE(void *) CPUMGetGuestVmxVirtApicPage(PCCPUMCTX pCtx, PRTHCPHYS pHCPhysVirtApicPage)
2408{
2409 Assert(pHCPhysVirtApicPage);
2410 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
2411 *pHCPhysVirtApicPage = pCtx->hwvirt.vmx.HCPhysVirtApicPage;
2412 return pCtx->hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
2413}
2414
2415# endif /* !IN_RC */
2416
2417/**
2418 * Checks whether the VMX nested-guest is in a state to receive physical (APIC)
2419 * interrupts.
2420 *
2421 * @returns @c true if it's ready, @c false otherwise.
2422 * @param pCtx The guest-CPU context.
2423 */
2424DECLINLINE(bool) CPUMIsGuestVmxPhysIntrEnabled(PCCPUMCTX pCtx)
2425{
2426#ifdef IN_RC
2427 AssertReleaseFailedReturn(false);
2428#else
2429 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2430 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2431#endif
2432}
2433
2434/**
2435 * Checks whether the VMX nested-guest is blocking virtual-NMIs.
2436 *
2437 * @returns @c true if it's blocked, @c false otherwise.
2438 * @param pCtx The guest-CPU context.
2439 */
2440DECLINLINE(bool) CPUMIsGuestVmxVirtNmiBlocking(PCCPUMCTX pCtx)
2441{
2442#ifdef IN_RC
2443 RT_NOREF(pCtx);
2444 AssertReleaseFailedReturn(false);
2445#else
2446 /*
2447 * Return the state of virtual-NMI blocking, if we are executing a
2448 * VMX nested-guest with virtual-NMIs enabled.
2449 */
2450 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2451 Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2452 return pCtx->hwvirt.vmx.fVirtNmiBlocking;
2453#endif
2454}
2455
2456/**
2457 * Sets or clears VMX nested-guest virtual-NMI blocking.
2458 *
2459 * @param pCtx The guest-CPU context.
2460 * @param fBlocking Whether virtual-NMI blocking is in effect or not.
2461 */
2462DECLINLINE(void) CPUMSetGuestVmxVirtNmiBlocking(PCPUMCTX pCtx, bool fBlocking)
2463{
2464#ifdef IN_RC
2465 RT_NOREF2(pCtx, fBlocking);
2466 AssertReleaseFailedReturnVoid();
2467#else
2468 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2469 Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2470 pCtx->hwvirt.vmx.fVirtNmiBlocking = fBlocking;
2471#endif
2472}
2473
2474/**
2475 * Checks whether the VMX nested-guest is in a state to receive virtual interrupts
2476 * (those injected with the "virtual-interrupt delivery" feature).
2477 *
2478 * @returns @c true if it's ready, @c false otherwise.
2479 * @param pCtx The guest-CPU context.
2480 */
2481DECLINLINE(bool) CPUMIsGuestVmxVirtIntrEnabled(PCCPUMCTX pCtx)
2482{
2483#ifdef IN_RC
2484 RT_NOREF2(pCtx);
2485 AssertReleaseFailedReturn(false);
2486#else
2487 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2488 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2489#endif
2490}
2491
2492/** @} */
2493#endif /* !IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS && RT_ARCH_AMD64 */
2494
2495
2496
2497/** @name Hypervisor Register Getters.
2498 * @{ */
2499VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
2500VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
2501VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
2502VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
2503VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
2504VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
2505VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
2506/** @} */
2507
2508/** @name Hypervisor Register Setters.
2509 * @{ */
2510VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
2511VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
2512VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
2513VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
2514VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
2515VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
2516VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
2517VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg, bool fForceHyper);
2518/** @} */
2519
2520VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
2521#ifdef VBOX_INCLUDED_vmm_cpumctx_h
2522VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu);
2523#endif
2524VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
2525
2526/** @name Changed flags.
2527 * These flags are used to keep track of which important register that
2528 * have been changed since last they were reset. The only one allowed
2529 * to clear them is REM!
2530 * @{
2531 */
2532#define CPUM_CHANGED_FPU_REM RT_BIT(0)
2533#define CPUM_CHANGED_CR0 RT_BIT(1)
2534#define CPUM_CHANGED_CR4 RT_BIT(2)
2535#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
2536#define CPUM_CHANGED_CR3 RT_BIT(4)
2537#define CPUM_CHANGED_GDTR RT_BIT(5)
2538#define CPUM_CHANGED_IDTR RT_BIT(6)
2539#define CPUM_CHANGED_LDTR RT_BIT(7)
2540#define CPUM_CHANGED_TR RT_BIT(8) /**@< Currently unused. */
2541#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
2542#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /**@< Currently unused. */
2543#define CPUM_CHANGED_CPUID RT_BIT(11)
2544#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
2545 | CPUM_CHANGED_CR0 \
2546 | CPUM_CHANGED_CR4 \
2547 | CPUM_CHANGED_GLOBAL_TLB_FLUSH \
2548 | CPUM_CHANGED_CR3 \
2549 | CPUM_CHANGED_GDTR \
2550 | CPUM_CHANGED_IDTR \
2551 | CPUM_CHANGED_LDTR \
2552 | CPUM_CHANGED_TR \
2553 | CPUM_CHANGED_SYSENTER_MSR \
2554 | CPUM_CHANGED_HIDDEN_SEL_REGS \
2555 | CPUM_CHANGED_CPUID )
2556/** @} */
2557
2558VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
2559VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
2560VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
2561VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
2562VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
2563VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
2564VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
2565VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu);
2566VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu);
2567VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
2568VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu);
2569VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
2570VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
2571VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu);
2572VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
2573VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
2574VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
2575VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
2576VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM);
2577VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
2578VMMDECL(uint64_t) CPUMGetGuestEferMsrValidMask(PVM pVM);
2579VMMDECL(int) CPUMIsGuestEferMsrWriteValid(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
2580 uint64_t *puValidEfer);
2581VMMDECL(void) CPUMSetGuestEferMsrNoChecks(PVMCPUCC pVCpu, uint64_t uOldEfer, uint64_t uValidEfer);
2582VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue);
2583
2584
2585/** Guest CPU interruptibility level, see CPUMGetGuestInterruptibility(). */
2586typedef enum CPUMINTERRUPTIBILITY
2587{
2588 CPUMINTERRUPTIBILITY_INVALID = 0,
2589 CPUMINTERRUPTIBILITY_UNRESTRAINED,
2590 CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED,
2591 CPUMINTERRUPTIBILITY_INT_DISABLED,
2592 CPUMINTERRUPTIBILITY_INT_INHIBITED,
2593 CPUMINTERRUPTIBILITY_NMI_INHIBIT,
2594 CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT,
2595 CPUMINTERRUPTIBILITY_END,
2596 CPUMINTERRUPTIBILITY_32BIT_HACK = 0x7fffffff
2597} CPUMINTERRUPTIBILITY;
2598
2599VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu);
2600VMM_INT_DECL(bool) CPUMIsGuestNmiBlocking(PCVMCPU pVCpu);
2601VMM_INT_DECL(void) CPUMSetGuestNmiBlocking(PVMCPU pVCpu, bool fBlock);
2602
2603/** @name Typical scalable bus frequency values.
2604 * @{ */
2605/** Special internal value indicating that we don't know the frequency.
2606 * @internal */
2607#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
2608#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
2609#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
2610#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
2611#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
2612#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
2613#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
2614#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
2615/** @} */
2616
2617
2618#ifdef IN_RING3
2619/** @defgroup grp_cpum_r3 The CPUM ring-3 API
2620 * @{
2621 */
2622
2623VMMR3DECL(int) CPUMR3Init(PVM pVM);
2624VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
2625VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM);
2626VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
2627VMMR3DECL(int) CPUMR3Term(PVM pVM);
2628VMMR3DECL(void) CPUMR3Reset(PVM pVM);
2629VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
2630VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
2631VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
2632
2633VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
2634VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
2635VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
2636 uint8_t bModel, uint8_t bStepping);
2637VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch);
2638VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);
2639VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
2640VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
2641VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
2642VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor);
2643VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void);
2644
2645VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
2646
2647/** @} */
2648#endif /* IN_RING3 */
2649
2650#ifdef IN_RING0
2651/** @defgroup grp_cpum_r0 The CPUM ring-0 API
2652 * @{
2653 */
2654VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
2655VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
2656VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM);
2657DECLASM(void) CPUMR0RegisterVCpuThread(PVMCPUCC pVCpu);
2658DECLASM(void) CPUMR0TouchHostFpu(void);
2659VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu);
2660VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu);
2661VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu);
2662VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVMCC pVM, PVMCPUCC pVCpu);
2663VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6);
2664VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6);
2665
2666VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6);
2667VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6);
2668#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
2669VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPUCC pVCpu, uint32_t iHostCpuSet);
2670#endif
2671
2672/** @} */
2673#endif /* IN_RING0 */
2674
2675/** @defgroup grp_cpum_rz The CPUM raw-mode and ring-0 context API
2676 * @{
2677 */
2678VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPUCC pVCpu);
2679VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPUCC pVCpu);
2680VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForChange(PVMCPUCC pVCpu);
2681VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPUCC pVCpu);
2682VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeAvxForRead(PVMCPUCC pVCpu);
2683/** @} */
2684
2685
2686#endif /* !VBOX_FOR_DTRACE_LIB */
2687/** @} */
2688RT_C_DECLS_END
2689
2690
2691#endif /* !VBOX_INCLUDED_vmm_cpum_h */
2692
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