VirtualBox

source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 41905

Last change on this file since 41905 was 41905, checked in by vboxsync, 12 years ago

CPUMCTX++: Rearranging the CPUMCTX structure in preparation of some hidden selector register improvments.
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File size: 12.4 KB
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1/** @file
2 * CPUM - CPU Monitor(/ Manager), Context Structures.
3 */
4
5/*
6 * Copyright (C) 2006-2012 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_cpumctx_h
27#define ___VBox_vmm_cpumctx_h
28
29#ifndef VBOX_FOR_DTRACE_LIB
30# include <iprt/x86.h>
31#else
32# pragma D depends_on library x86.d
33#endif
34
35
36RT_C_DECLS_BEGIN
37
38/** @addgroup grp_cpum_ctx The CPUM Context Structures
39 * @ingroup grp_cpum
40 * @{
41 */
42
43/**
44 * Selector hidden registers.
45 */
46typedef struct CPUMSELREGHID
47{
48 /** Base register.
49 *
50 * Long mode remarks:
51 * - Unused in long mode for CS, DS, ES, SS
52 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
53 * - 64 bits for TR & LDTR
54 */
55 uint64_t u64Base;
56 /** Limit (expanded). */
57 uint32_t u32Limit;
58 /** Flags.
59 * This is the high 32-bit word of the descriptor entry.
60 * Only the flags, dpl and type are used. */
61 X86DESCATTR Attr;
62} CPUMSELREGHID;
63
64
65/**
66 * The sysenter register set.
67 */
68typedef struct CPUMSYSENTER
69{
70 /** Ring 0 cs.
71 * This value + 8 is the Ring 0 ss.
72 * This value + 16 is the Ring 3 cs.
73 * This value + 24 is the Ring 3 ss.
74 */
75 uint64_t cs;
76 /** Ring 0 eip. */
77 uint64_t eip;
78 /** Ring 0 esp. */
79 uint64_t esp;
80} CPUMSYSENTER;
81
82/**
83 * For compilers (like DTrace) that does not grok nameless unions, we have a
84 * little hack to make them palatable.
85 */
86#ifdef VBOX_FOR_DTRACE_LIB
87# define CPUM_UNION_NAME(a_Nm) a_Nm
88#elif defined(VBOX_WITHOUT_UNNAMED_UNIONS)
89# define CPUM_UNION_NAME(a_Nm) a_Nm
90#else
91# define CPUM_UNION_NAME(a_Nm)
92#endif
93
94
95/**
96 * CPU context core.
97 *
98 * @todo eliminate this structure!
99 */
100#pragma pack(1)
101typedef struct CPUMCTXCORE
102{
103 /** @name General Register.
104 * @note These follow the encoding order (X86_GREG_XXX) and can be accessed as
105 * an array starting a rax.
106 * @{ */
107 union
108 {
109 uint8_t al;
110 uint16_t ax;
111 uint32_t eax;
112 uint64_t rax;
113 } CPUM_UNION_NAME(rax);
114 union
115 {
116 uint8_t cl;
117 uint16_t cx;
118 uint32_t ecx;
119 uint64_t rcx;
120 } CPUM_UNION_NAME(rcx);
121 union
122 {
123 uint8_t dl;
124 uint16_t dx;
125 uint32_t edx;
126 uint64_t rdx;
127 } CPUM_UNION_NAME(rdx);
128 union
129 {
130 uint8_t bl;
131 uint16_t bx;
132 uint32_t ebx;
133 uint64_t rbx;
134 } CPUM_UNION_NAME(rbx);
135 union
136 {
137 uint16_t sp;
138 uint32_t esp;
139 uint64_t rsp;
140 } CPUM_UNION_NAME(rsp);
141 union
142 {
143 uint16_t bp;
144 uint32_t ebp;
145 uint64_t rbp;
146 } CPUM_UNION_NAME(rbp);
147 union
148 {
149 uint8_t sil;
150 uint16_t si;
151 uint32_t esi;
152 uint64_t rsi;
153 } CPUM_UNION_NAME(rsi);
154 union
155 {
156 uint8_t dil;
157 uint16_t di;
158 uint32_t edi;
159 uint64_t rdi;
160 } CPUM_UNION_NAME(rdi);
161 uint64_t r8;
162 uint64_t r9;
163 uint64_t r10;
164 uint64_t r11;
165 uint64_t r12;
166 uint64_t r13;
167 uint64_t r14;
168 uint64_t r15;
169 /** @} */
170
171 /** @name Segment registers.
172 * @note These follow the encoding order (X86_SREG_XXX) and can be accessed as
173 * an array starting a es.
174 * @todo Combine the selector and hidden bits, effectively expanding the hidden
175 * register structure by 64-bit.
176 *
177 * @{ */
178 RTSEL es;
179 RTSEL esPadding[3];
180 CPUMSELREGHID esHid;
181
182 RTSEL cs;
183 RTSEL csPadding[3];
184 CPUMSELREGHID csHid;
185
186 RTSEL ss;
187 RTSEL ssPadding[3];
188 CPUMSELREGHID ssHid;
189
190 RTSEL ds;
191 RTSEL dsPadding[3];
192 CPUMSELREGHID dsHid;
193
194 RTSEL fs;
195 RTSEL fsPadding[3];
196 CPUMSELREGHID fsHid;
197
198 RTSEL gs;
199 RTSEL gsPadding[3];
200 CPUMSELREGHID gsHid;
201 /** @} */
202
203 /** The program counter. */
204 union
205 {
206 uint16_t ip;
207 uint32_t eip;
208 uint64_t rip;
209 } CPUM_UNION_NAME(rip);
210
211 /** The flags register. */
212 union
213 {
214 X86EFLAGS eflags;
215 X86RFLAGS rflags;
216 } CPUM_UNION_NAME(rflags);
217
218} CPUMCTXCORE;
219#pragma pack()
220
221
222/**
223 * CPU context.
224 */
225#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
226typedef struct CPUMCTX
227{
228 /** FPU state. (16-byte alignment)
229 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
230 * actual format or convert it (waste of time). */
231 X86FXSTATE fpu;
232
233 /** CPUMCTXCORE Part.
234 * @{ */
235
236 /** @name General Register.
237 * @note These follow the encoding order (X86_GREG_XXX) and can be accessed as
238 * an array starting a rax.
239 * @{ */
240 union
241 {
242 uint8_t al;
243 uint16_t ax;
244 uint32_t eax;
245 uint64_t rax;
246 } CPUM_UNION_NAME(rax);
247 union
248 {
249 uint8_t cl;
250 uint16_t cx;
251 uint32_t ecx;
252 uint64_t rcx;
253 } CPUM_UNION_NAME(rcx);
254 union
255 {
256 uint8_t dl;
257 uint16_t dx;
258 uint32_t edx;
259 uint64_t rdx;
260 } CPUM_UNION_NAME(rdx);
261 union
262 {
263 uint8_t bl;
264 uint16_t bx;
265 uint32_t ebx;
266 uint64_t rbx;
267 } CPUM_UNION_NAME(rbx);
268 union
269 {
270 uint16_t sp;
271 uint32_t esp;
272 uint64_t rsp;
273 } CPUM_UNION_NAME(rsp);
274 union
275 {
276 uint16_t bp;
277 uint32_t ebp;
278 uint64_t rbp;
279 } CPUM_UNION_NAME(rbp);
280 union
281 {
282 uint8_t sil;
283 uint16_t si;
284 uint32_t esi;
285 uint64_t rsi;
286 } CPUM_UNION_NAME(rsi);
287 union
288 {
289 uint8_t dil;
290 uint16_t di;
291 uint32_t edi;
292 uint64_t rdi;
293 } CPUM_UNION_NAME(rdi);
294 uint64_t r8;
295 uint64_t r9;
296 uint64_t r10;
297 uint64_t r11;
298 uint64_t r12;
299 uint64_t r13;
300 uint64_t r14;
301 uint64_t r15;
302 /** @} */
303
304 /** @name Segment registers.
305 * @note These follow the encoding order (X86_SREG_XXX) and can be accessed as
306 * an array starting a es.
307 * @todo Combine the selector and hidden bits, effectively expanding the hidden
308 * register structure by 64-bit.
309 *
310 * @{ */
311 RTSEL es;
312 RTSEL esPadding[3];
313 CPUMSELREGHID esHid;
314
315 RTSEL cs;
316 RTSEL csPadding[3];
317 CPUMSELREGHID csHid;
318
319 RTSEL ss;
320 RTSEL ssPadding[3];
321 CPUMSELREGHID ssHid;
322
323 RTSEL ds;
324 RTSEL dsPadding[3];
325 CPUMSELREGHID dsHid;
326
327 RTSEL fs;
328 RTSEL fsPadding[3];
329 CPUMSELREGHID fsHid;
330
331 RTSEL gs;
332 RTSEL gsPadding[3];
333 CPUMSELREGHID gsHid;
334 /** @} */
335
336 /** The program counter. */
337 union
338 {
339 uint16_t ip;
340 uint32_t eip;
341 uint64_t rip;
342 } CPUM_UNION_NAME(rip);
343
344 /** The flags register. */
345 union
346 {
347 X86EFLAGS eflags;
348 X86RFLAGS rflags;
349 } CPUM_UNION_NAME(rflags);
350
351 /** @} */ /*(CPUMCTXCORE)*/
352
353
354 /** @name Control registers.
355 * @{ */
356 uint64_t cr0;
357 uint64_t cr2;
358 uint64_t cr3;
359 uint64_t cr4;
360 /** @} */
361
362 /** Debug registers.
363 * @remarks DR4 and DR5 should not be used since they are aliases for
364 * DR6 and DR7 respectively on both AMD and Intel CPUs.
365 * @remarks DR8-15 are currently not supported by AMD or Intel, so
366 * neither do we.
367 */
368 uint64_t dr[8];
369
370 /** Padding before the structure so the 64-bit member is correctly aligned.
371 * @todo fix this structure! */
372 uint16_t gdtrPadding[3];
373 /** Global Descriptor Table register. */
374 VBOXGDTR gdtr;
375
376 /** Padding before the structure so the 64-bit member is correctly aligned.
377 * @todo fix this structure! */
378 uint16_t idtrPadding[3];
379 /** Interrupt Descriptor Table register. */
380 VBOXIDTR idtr;
381
382 /** The task register.
383 * Only the guest context uses all the members. */
384 RTSEL ldtr;
385 RTSEL ldtrPadding[3];
386 CPUMSELREGHID ldtrHid;
387 /** The task register.
388 * Only the guest context uses all the members. */
389 RTSEL tr;
390 RTSEL trPadding[3];
391 CPUMSELREGHID trHid;
392
393 /** The sysenter msr registers.
394 * This member is not used by the hypervisor context. */
395 CPUMSYSENTER SysEnter;
396
397 /** @name System MSRs.
398 * @{ */
399 uint64_t msrEFER;
400 uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */
401 uint64_t msrPAT; /**< Page attribute table. */
402 uint64_t msrLSTAR; /**< 64 bits mode syscall rip. */
403 uint64_t msrCSTAR; /**< Compatibility mode syscall rip. */
404 uint64_t msrSFMASK; /**< syscall flag mask. */
405 uint64_t msrKERNELGSBASE; /**< swapgs exchange value. */
406 /** @} */
407
408 /** Size padding. */
409 uint32_t au32SizePadding[8];
410} CPUMCTX;
411#pragma pack()
412
413#ifndef VBOX_FOR_DTRACE_LIB
414
415/**
416 * Gets the CPUMCTXCORE part of a CPUMCTX.
417 */
418# define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->rax)
419
420#endif /* VBOX_FOR_DTRACE_LIB */
421
422/**
423 * Additional guest MSRs (i.e. not part of the CPU context structure).
424 *
425 * @remarks Never change the order here because of the saved stated! The size
426 * can in theory be changed, but keep older VBox versions in mind.
427 */
428typedef union CPUMCTXMSRS
429{
430 struct
431 {
432 uint64_t TscAux; /**< MSR_K8_TSC_AUX */
433 uint64_t MiscEnable; /**< MSR_IA32_MISC_ENABLE */
434 uint64_t MtrrDefType; /**< IA32_MTRR_DEF_TYPE */
435 uint64_t MtrrFix64K_00000; /**< IA32_MTRR_FIX16K_80000 */
436 uint64_t MtrrFix16K_80000; /**< IA32_MTRR_FIX16K_80000 */
437 uint64_t MtrrFix16K_A0000; /**< IA32_MTRR_FIX16K_A0000 */
438 uint64_t MtrrFix4K_C0000; /**< IA32_MTRR_FIX4K_C0000 */
439 uint64_t MtrrFix4K_C8000; /**< IA32_MTRR_FIX4K_C8000 */
440 uint64_t MtrrFix4K_D0000; /**< IA32_MTRR_FIX4K_D0000 */
441 uint64_t MtrrFix4K_D8000; /**< IA32_MTRR_FIX4K_D8000 */
442 uint64_t MtrrFix4K_E0000; /**< IA32_MTRR_FIX4K_E0000 */
443 uint64_t MtrrFix4K_E8000; /**< IA32_MTRR_FIX4K_E8000 */
444 uint64_t MtrrFix4K_F0000; /**< IA32_MTRR_FIX4K_F0000 */
445 uint64_t MtrrFix4K_F8000; /**< IA32_MTRR_FIX4K_F8000 */
446 } msr;
447 uint64_t au64[64];
448} CPUMCTXMSRS;
449/** Pointer to the guest MSR state. */
450typedef CPUMCTXMSRS *PCPUMCTXMSRS;
451/** Pointer to the const guest MSR state. */
452typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
453
454/**
455 * The register set returned by a CPUID operation.
456 */
457typedef struct CPUMCPUID
458{
459 uint32_t eax;
460 uint32_t ebx;
461 uint32_t ecx;
462 uint32_t edx;
463} CPUMCPUID;
464/** Pointer to a CPUID leaf. */
465typedef CPUMCPUID *PCPUMCPUID;
466/** Pointer to a const CPUID leaf. */
467typedef const CPUMCPUID *PCCPUMCPUID;
468
469/** @} */
470
471RT_C_DECLS_END
472
473#endif
474
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