Changeset 41905 in vbox
- Timestamp:
- Jun 24, 2012 1:19:25 AM (13 years ago)
- Location:
- trunk
- Files:
-
- 13 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/cpum.mac
r40170 r41905 32 32 ; and other places. 33 33 struc CPUMCTXCORE 34 .edi resq 1 35 .esi resq 1 36 .ebp resq 1 37 .eax resq 1 38 .ebx resq 1 39 .edx resq 1 40 .ecx resq 1 41 .esp resq 1 42 .lss_esp resd 1 43 .ss resw 1 44 .ssPadding resw 1 45 .gs resw 1 46 .gsPadding resw 1 47 .fs resw 1 48 .fsPadding resw 1 49 .es resw 1 50 .esPadding resw 1 51 .ds resw 1 52 .dsPadding resw 1 53 .cs resw 1 54 .csPadding resw 3 55 .eflags resq 1 56 .eip resq 1 57 58 .r8 resq 1 59 .r9 resq 1 60 .r10 resq 1 61 .r11 resq 1 62 .r12 resq 1 63 .r13 resq 1 64 .r14 resq 1 65 .r15 resq 1 66 34 .eax resq 1 35 .ecx resq 1 36 .edx resq 1 37 .ebx resq 1 38 .esp resq 1 39 .ebp resq 1 40 .esi resq 1 41 .edi resq 1 42 .r8 resq 1 43 .r9 resq 1 44 .r10 resq 1 45 .r11 resq 1 46 .r12 resq 1 47 .r13 resq 1 48 .r14 resq 1 49 .r15 resq 1 50 .es resw 1 51 .esPadding resw 3 67 52 .esHid.u64Base resq 1 68 53 .esHid.u32Limit resd 1 69 54 .esHid.Attr resd 1 70 55 .cs resw 1 56 .csPadding resw 3 71 57 .csHid.u64Base resq 1 72 58 .csHid.u32Limit resd 1 73 59 .csHid.Attr resd 1 74 60 .ss resw 1 61 .ssPadding resw 3 75 62 .ssHid.u64Base resq 1 76 63 .ssHid.u32Limit resd 1 77 64 .ssHid.Attr resd 1 78 65 .ds resw 1 66 .dsPadding resw 3 79 67 .dsHid.u64Base resq 1 80 68 .dsHid.u32Limit resd 1 81 69 .dsHid.Attr resd 1 82 70 .fs resw 1 71 .fsPadding resw 3 83 72 .fsHid.u64Base resq 1 84 73 .fsHid.u32Limit resd 1 85 74 .fsHid.Attr resd 1 86 75 .gs resw 1 76 .gsPadding resw 3 87 77 .gsHid.u64Base resq 1 88 78 .gsHid.u32Limit resd 1 89 79 .gsHid.Attr resd 1 90 80 .eip resq 1 81 .eflags resq 1 91 82 endstruc 92 83 93 84 94 85 struc CPUMCTX 95 .fpu resb 512 96 97 .edi resq 1 98 .esi resq 1 99 .ebp resq 1 100 .eax resq 1 101 .ebx resq 1 102 .edx resq 1 103 .ecx resq 1 104 .esp resq 1 105 .lss_esp resd 1 106 .ss resw 1 107 .ssPadding resw 1 108 .gs resw 1 109 .gsPadding resw 1 110 .fs resw 1 111 .fsPadding resw 1 112 .es resw 1 113 .esPadding resw 1 114 .ds resw 1 115 .dsPadding resw 1 116 .cs resw 1 117 .csPadding resw 3 118 .eflags resq 1 119 .eip resq 1 120 121 .r8 resq 1 122 .r9 resq 1 123 .r10 resq 1 124 .r11 resq 1 125 .r12 resq 1 126 .r13 resq 1 127 .r14 resq 1 128 .r15 resq 1 129 86 .fpu resb 512 87 .eax resq 1 88 .ecx resq 1 89 .edx resq 1 90 .ebx resq 1 91 .esp resq 1 92 .ebp resq 1 93 .esi resq 1 94 .edi resq 1 95 .r8 resq 1 96 .r9 resq 1 97 .r10 resq 1 98 .r11 resq 1 99 .r12 resq 1 100 .r13 resq 1 101 .r14 resq 1 102 .r15 resq 1 103 .es resw 1 104 .esPadding resw 3 130 105 .esHid.u64Base resq 1 131 106 .esHid.u32Limit resd 1 132 107 .esHid.Attr resd 1 133 108 .cs resw 1 109 .csPadding resw 3 134 110 .csHid.u64Base resq 1 135 111 .csHid.u32Limit resd 1 136 112 .csHid.Attr resd 1 137 113 .ss resw 1 114 .ssPadding resw 3 138 115 .ssHid.u64Base resq 1 139 116 .ssHid.u32Limit resd 1 140 117 .ssHid.Attr resd 1 141 118 .ds resw 1 119 .dsPadding resw 3 142 120 .dsHid.u64Base resq 1 143 121 .dsHid.u32Limit resd 1 144 122 .dsHid.Attr resd 1 145 123 .fs resw 1 124 .fsPadding resw 3 146 125 .fsHid.u64Base resq 1 147 126 .fsHid.u32Limit resd 1 148 127 .fsHid.Attr resd 1 149 128 .gs resw 1 129 .gsPadding resw 3 150 130 .gsHid.u64Base resq 1 151 131 .gsHid.u32Limit resd 1 152 132 .gsHid.Attr resd 1 153 154 155 .cr0 resq 1 156 .cr2 resq 1 157 .cr3 resq 1 158 .cr4 resq 1 159 160 .dr resq 8 161 162 .gdtr.cbGdt resw 1 163 .gdtr.pGdt resq 1 164 .gdtrPadding resw 1 165 .idtr.cbIdt resw 1 166 .idtr.pIdt resq 1 167 .idtrPadding resw 1 168 .ldtr resw 1 169 .ldtrPadding resw 1 170 .tr resw 1 171 .trPadding resw 1 172 133 .eip resq 1 134 .eflags resq 1 135 .cr0 resq 1 136 .cr2 resq 1 137 .cr3 resq 1 138 .cr4 resq 1 139 .dr resq 8 140 .gdtrPadding resw 3 141 .gdtr resw 0 142 .gdtr.cbGdt resw 1 143 .gdtr.pGdt resq 1 144 .idtrPadding resw 3 145 .idtr resw 0 146 .idtr.cbIdt resw 1 147 .idtr.pIdt resq 1 148 .ldtr resw 1 149 .ldtrPadding resw 3 150 .ldtrHid.u64Base resq 1 151 .ldtrHid.u32Limit resd 1 152 .ldtrHid.Attr resd 1 153 .tr resw 1 154 .trPadding resw 3 155 .trHid.u64Base resq 1 156 .trHid.u32Limit resd 1 157 .trHid.Attr resd 1 173 158 .SysEnter.cs resb 8 174 159 .SysEnter.eip resb 8 175 160 .SysEnter.esp resb 8 176 177 161 .msrEFER resb 8 178 162 .msrSTAR resb 8 … … 182 166 .msrSFMASK resb 8 183 167 .msrKERNELGSBASE resb 8 184 185 .ldtrHid.u64Base resq 1 186 .ldtrHid.u32Limit resd 1 187 .ldtrHid.Attr resd 1 188 189 .trHid.u64Base resq 1 190 .trHid.u32Limit resd 1 191 .trHid.Attr resd 1 192 193 ; padding 194 ;;; .padding resd 6 168 .au32SizePadding resb 32 195 169 endstruc 196 170 -
trunk/include/VBox/vmm/cpumctx.h
r41899 r41905 95 95 /** 96 96 * CPU context core. 97 * 98 * @todo eliminate this structure! 97 99 */ 98 100 #pragma pack(1) 99 101 typedef struct CPUMCTXCORE 100 102 { 101 union 102 { 103 /** @name General Register. 104 * @note These follow the encoding order (X86_GREG_XXX) and can be accessed as 105 * an array starting a rax. 106 * @{ */ 107 union 108 { 109 uint8_t al; 110 uint16_t ax; 111 uint32_t eax; 112 uint64_t rax; 113 } CPUM_UNION_NAME(rax); 114 union 115 { 116 uint8_t cl; 117 uint16_t cx; 118 uint32_t ecx; 119 uint64_t rcx; 120 } CPUM_UNION_NAME(rcx); 121 union 122 { 123 uint8_t dl; 124 uint16_t dx; 125 uint32_t edx; 126 uint64_t rdx; 127 } CPUM_UNION_NAME(rdx); 128 union 129 { 130 uint8_t bl; 131 uint16_t bx; 132 uint32_t ebx; 133 uint64_t rbx; 134 } CPUM_UNION_NAME(rbx); 135 union 136 { 137 uint16_t sp; 138 uint32_t esp; 139 uint64_t rsp; 140 } CPUM_UNION_NAME(rsp); 141 union 142 { 143 uint16_t bp; 144 uint32_t ebp; 145 uint64_t rbp; 146 } CPUM_UNION_NAME(rbp); 147 union 148 { 149 uint8_t sil; 150 uint16_t si; 151 uint32_t esi; 152 uint64_t rsi; 153 } CPUM_UNION_NAME(rsi); 154 union 155 { 156 uint8_t dil; 103 157 uint16_t di; 104 158 uint32_t edi; 105 159 uint64_t rdi; 106 160 } CPUM_UNION_NAME(rdi); 107 union108 {109 uint16_t si;110 uint32_t esi;111 uint64_t rsi;112 } CPUM_UNION_NAME(rsi);113 union114 {115 uint16_t bp;116 uint32_t ebp;117 uint64_t rbp;118 } CPUM_UNION_NAME(rbp);119 union120 {121 uint16_t ax;122 uint32_t eax;123 uint64_t rax;124 } CPUM_UNION_NAME(rax);125 union126 {127 uint16_t bx;128 uint32_t ebx;129 uint64_t rbx;130 } CPUM_UNION_NAME(rbx);131 union132 {133 uint16_t dx;134 uint32_t edx;135 uint64_t rdx;136 } CPUM_UNION_NAME(rdx);137 union138 {139 uint16_t cx;140 uint32_t ecx;141 uint64_t rcx;142 } CPUM_UNION_NAME(rcx);143 union144 {145 uint16_t sp;146 uint32_t esp;147 uint64_t rsp;148 } CPUM_UNION_NAME(rsp);149 /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */150 uint32_t lss_esp;151 RTSEL ss;152 RTSEL ssPadding;153 154 RTSEL gs;155 RTSEL gsPadding;156 RTSEL fs;157 RTSEL fsPadding;158 RTSEL es;159 RTSEL esPadding;160 RTSEL ds;161 RTSEL dsPadding;162 RTSEL cs;163 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */164 165 union166 {167 X86EFLAGS eflags;168 X86RFLAGS rflags;169 } CPUM_UNION_NAME(rflags);170 union171 {172 uint16_t ip;173 uint32_t eip;174 uint64_t rip;175 } CPUM_UNION_NAME(rip);176 177 161 uint64_t r8; 178 162 uint64_t r9; … … 183 167 uint64_t r14; 184 168 uint64_t r15; 185 186 /** Hidden selector registers. 187 * @{ */ 188 CPUMSELREGHID esHid; 189 CPUMSELREGHID csHid; 190 CPUMSELREGHID ssHid; 191 CPUMSELREGHID dsHid; 192 CPUMSELREGHID fsHid; 193 CPUMSELREGHID gsHid; 194 /** @} */ 169 /** @} */ 170 171 /** @name Segment registers. 172 * @note These follow the encoding order (X86_SREG_XXX) and can be accessed as 173 * an array starting a es. 174 * @todo Combine the selector and hidden bits, effectively expanding the hidden 175 * register structure by 64-bit. 176 * 177 * @{ */ 178 RTSEL es; 179 RTSEL esPadding[3]; 180 CPUMSELREGHID esHid; 181 182 RTSEL cs; 183 RTSEL csPadding[3]; 184 CPUMSELREGHID csHid; 185 186 RTSEL ss; 187 RTSEL ssPadding[3]; 188 CPUMSELREGHID ssHid; 189 190 RTSEL ds; 191 RTSEL dsPadding[3]; 192 CPUMSELREGHID dsHid; 193 194 RTSEL fs; 195 RTSEL fsPadding[3]; 196 CPUMSELREGHID fsHid; 197 198 RTSEL gs; 199 RTSEL gsPadding[3]; 200 CPUMSELREGHID gsHid; 201 /** @} */ 202 203 /** The program counter. */ 204 union 205 { 206 uint16_t ip; 207 uint32_t eip; 208 uint64_t rip; 209 } CPUM_UNION_NAME(rip); 210 211 /** The flags register. */ 212 union 213 { 214 X86EFLAGS eflags; 215 X86RFLAGS rflags; 216 } CPUM_UNION_NAME(rflags); 195 217 196 218 } CPUMCTXCORE; … … 201 223 * CPU context. 202 224 */ 203 #pragma pack(1) 225 #pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */ 204 226 typedef struct CPUMCTX 205 227 { … … 211 233 /** CPUMCTXCORE Part. 212 234 * @{ */ 235 236 /** @name General Register. 237 * @note These follow the encoding order (X86_GREG_XXX) and can be accessed as 238 * an array starting a rax. 239 * @{ */ 240 union 241 { 242 uint8_t al; 243 uint16_t ax; 244 uint32_t eax; 245 uint64_t rax; 246 } CPUM_UNION_NAME(rax); 247 union 248 { 249 uint8_t cl; 250 uint16_t cx; 251 uint32_t ecx; 252 uint64_t rcx; 253 } CPUM_UNION_NAME(rcx); 254 union 255 { 256 uint8_t dl; 257 uint16_t dx; 258 uint32_t edx; 259 uint64_t rdx; 260 } CPUM_UNION_NAME(rdx); 261 union 262 { 263 uint8_t bl; 264 uint16_t bx; 265 uint32_t ebx; 266 uint64_t rbx; 267 } CPUM_UNION_NAME(rbx); 268 union 269 { 270 uint16_t sp; 271 uint32_t esp; 272 uint64_t rsp; 273 } CPUM_UNION_NAME(rsp); 274 union 275 { 276 uint16_t bp; 277 uint32_t ebp; 278 uint64_t rbp; 279 } CPUM_UNION_NAME(rbp); 280 union 281 { 282 uint8_t sil; 283 uint16_t si; 284 uint32_t esi; 285 uint64_t rsi; 286 } CPUM_UNION_NAME(rsi); 213 287 union 214 288 { … … 218 292 uint64_t rdi; 219 293 } CPUM_UNION_NAME(rdi); 220 union221 {222 uint8_t sil;223 uint16_t si;224 uint32_t esi;225 uint64_t rsi;226 } CPUM_UNION_NAME(rsi);227 union228 {229 uint16_t bp;230 uint32_t ebp;231 uint64_t rbp;232 } CPUM_UNION_NAME(rbp);233 union234 {235 uint8_t al;236 uint16_t ax;237 uint32_t eax;238 uint64_t rax;239 } CPUM_UNION_NAME(rax);240 union241 {242 uint8_t bl;243 uint16_t bx;244 uint32_t ebx;245 uint64_t rbx;246 } CPUM_UNION_NAME(rbx);247 union248 {249 uint8_t dl;250 uint16_t dx;251 uint32_t edx;252 uint64_t rdx;253 } CPUM_UNION_NAME(rdx);254 union255 {256 uint8_t cl;257 uint16_t cx;258 uint32_t ecx;259 uint64_t rcx;260 } CPUM_UNION_NAME(rcx);261 union262 {263 uint16_t sp;264 uint32_t esp;265 uint64_t rsp;266 } CPUM_UNION_NAME(rsp);267 /** @note lss esp, [] in the switcher needs some space, so we reserve it here268 * instead of relying on the exact esp & ss layout as before (prevented269 * us from using a union with rsp). */270 uint32_t lss_esp;271 RTSEL ss;272 RTSEL ssPadding;273 274 RTSEL gs;275 RTSEL gsPadding;276 RTSEL fs;277 RTSEL fsPadding;278 RTSEL es;279 RTSEL esPadding;280 RTSEL ds;281 RTSEL dsPadding;282 RTSEL cs;283 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */284 285 union286 {287 X86EFLAGS eflags;288 X86RFLAGS rflags;289 } CPUM_UNION_NAME(rflags);290 union291 {292 uint16_t ip;293 uint32_t eip;294 uint64_t rip;295 } CPUM_UNION_NAME(rip);296 297 294 uint64_t r8; 298 295 uint64_t r9; … … 303 300 uint64_t r14; 304 301 uint64_t r15; 305 306 /** Hidden selector registers. 302 /** @} */ 303 304 /** @name Segment registers. 305 * @note These follow the encoding order (X86_SREG_XXX) and can be accessed as 306 * an array starting a es. 307 * @todo Combine the selector and hidden bits, effectively expanding the hidden 308 * register structure by 64-bit. 309 * 310 * @{ */ 311 RTSEL es; 312 RTSEL esPadding[3]; 313 CPUMSELREGHID esHid; 314 315 RTSEL cs; 316 RTSEL csPadding[3]; 317 CPUMSELREGHID csHid; 318 319 RTSEL ss; 320 RTSEL ssPadding[3]; 321 CPUMSELREGHID ssHid; 322 323 RTSEL ds; 324 RTSEL dsPadding[3]; 325 CPUMSELREGHID dsHid; 326 327 RTSEL fs; 328 RTSEL fsPadding[3]; 329 CPUMSELREGHID fsHid; 330 331 RTSEL gs; 332 RTSEL gsPadding[3]; 333 CPUMSELREGHID gsHid; 334 /** @} */ 335 336 /** The program counter. */ 337 union 338 { 339 uint16_t ip; 340 uint32_t eip; 341 uint64_t rip; 342 } CPUM_UNION_NAME(rip); 343 344 /** The flags register. */ 345 union 346 { 347 X86EFLAGS eflags; 348 X86RFLAGS rflags; 349 } CPUM_UNION_NAME(rflags); 350 351 /** @} */ /*(CPUMCTXCORE)*/ 352 353 354 /** @name Control registers. 307 355 * @{ */ 308 CPUMSELREGHID esHid; 309 CPUMSELREGHID csHid; 310 CPUMSELREGHID ssHid; 311 CPUMSELREGHID dsHid; 312 CPUMSELREGHID fsHid; 313 CPUMSELREGHID gsHid; 314 /** @} */ 315 316 /** @} */ 317 318 /** Control registers. 319 * @{ */ 320 uint64_t cr0; 321 uint64_t cr2; 322 uint64_t cr3; 323 uint64_t cr4; 356 uint64_t cr0; 357 uint64_t cr2; 358 uint64_t cr3; 359 uint64_t cr4; 324 360 /** @} */ 325 361 … … 329 365 * @remarks DR8-15 are currently not supported by AMD or Intel, so 330 366 * neither do we. 331 * @{ */367 */ 332 368 uint64_t dr[8]; 333 /** @} */ 334 369 370 /** Padding before the structure so the 64-bit member is correctly aligned. 371 * @todo fix this structure! */ 372 uint16_t gdtrPadding[3]; 335 373 /** Global Descriptor Table register. */ 336 374 VBOXGDTR gdtr; 337 uint16_t gdtrPadding; 375 376 /** Padding before the structure so the 64-bit member is correctly aligned. 377 * @todo fix this structure! */ 378 uint16_t idtrPadding[3]; 338 379 /** Interrupt Descriptor Table register. */ 339 380 VBOXIDTR idtr; 340 uint16_t idtrPadding; 381 341 382 /** The task register. 342 383 * Only the guest context uses all the members. */ 343 384 RTSEL ldtr; 344 RTSEL ldtrPadding; 385 RTSEL ldtrPadding[3]; 386 CPUMSELREGHID ldtrHid; 345 387 /** The task register. 346 388 * Only the guest context uses all the members. */ 347 389 RTSEL tr; 348 RTSEL trPadding; 390 RTSEL trPadding[3]; 391 CPUMSELREGHID trHid; 349 392 350 393 /** The sysenter msr registers. … … 352 395 CPUMSYSENTER SysEnter; 353 396 354 /** System MSRs.397 /** @name System MSRs. 355 398 * @{ */ 356 399 uint64_t msrEFER; 357 400 uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */ 358 uint64_t msrPAT; 401 uint64_t msrPAT; /**< Page attribute table. */ 359 402 uint64_t msrLSTAR; /**< 64 bits mode syscall rip. */ 360 403 uint64_t msrCSTAR; /**< Compatibility mode syscall rip. */ … … 363 406 /** @} */ 364 407 365 /** Hidden selector registers. 366 * @{ */ 367 CPUMSELREGHID ldtrHid; 368 CPUMSELREGHID trHid; 369 /** @} */ 370 371 #if 0 372 /** Padding to align the size on a 64 byte boundary. */ 373 uint32_t padding[6]; 374 #endif 408 /** Size padding. */ 409 uint32_t au32SizePadding[8]; 375 410 } CPUMCTX; 376 411 #pragma pack() … … 381 416 * Gets the CPUMCTXCORE part of a CPUMCTX. 382 417 */ 383 # define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)-> edi)418 # define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->rax) 384 419 385 420 #endif /* VBOX_FOR_DTRACE_LIB */ -
trunk/include/VBox/vmm/vm.h
r41279 r41905 136 136 struct CPUMCPU s; 137 137 #endif 138 uint8_t padding[3 456]; /* multiple of 64 */138 uint8_t padding[3584]; /* multiple of 64 */ 139 139 } cpum; 140 140 … … 222 222 223 223 /** Align the following members on page boundary. */ 224 uint8_t abAlignment2[1024 - 320 ];224 uint8_t abAlignment2[1024 - 320 - 128]; 225 225 226 226 /** PGM part. */ -
trunk/include/VBox/vmm/vm.mac
r41147 r41905 138 138 alignb 64 139 139 140 .cpum resb 3 456140 .cpum resb 3584 141 141 .hwaccm resb 5376 142 142 .em resb 1472 -
trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
r41836 r41905 114 114 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit; 115 115 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr; 116 pVCpu->cpum.s.Hyper.gdtrPadding = 0;117 116 } 118 117 … … 122 121 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit; 123 122 pVCpu->cpum.s.Hyper.idtr.pIdt = addr; 124 pVCpu->cpum.s.Hyper.idtrPadding = 0;125 123 } 126 124 -
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r41904 r41905 87 87 #define CPUM_SAVED_STATE_VERSION_VER1_6 6 88 88 89 //#define CPUM_WITH_CHANGED_CPUMCTX89 #define CPUM_WITH_CHANGED_CPUMCTX 90 90 91 91 /******************************************************************************* -
trunk/src/VBox/VMM/VMMSwitcher/AMD64andLegacy.mac
r37969 r41905 542 542 lidt [edx + CPUMCPU.Hyper.idtr] 543 543 544 ; Setup stack ; use the lss_esp, ss pair for lss544 ; Setup stack. 545 545 DEBUG_CHAR('3') 546 mov eax, [edx + CPUMCPU.Hyper.esp]547 mov [edx + CPUMCPU.Hyper.lss_esp], eax548 lss esp, [edx + CPUMCPU.Hyper.lss_esp]546 mov ax, [edx + CPUMCPU.Hyper.ss] 547 mov ss, ax 548 mov esp, [edx + CPUMCPU.Hyper.esp] 549 549 550 550 ; Restore TSS selector; must mark it as not busy before using ltr (!) -
trunk/src/VBox/VMM/VMMSwitcher/LegacyandAMD64.mac
r37955 r41905 380 380 %endif 381 381 382 ; Setup stack ; use the lss_esp, ss pair for lss382 ; Setup stack. 383 383 DEBUG_CHAR('7') 384 384 mov rsp, 0 385 mov eax, [rdx + CPUMCPU.Hyper. esp]386 mov [rdx + CPUMCPU.Hyper.lss_esp], eax387 lss esp, [rdx + CPUMCPU.Hyper.lss_esp]385 mov eax, [rdx + CPUMCPU.Hyper.ss] 386 mov ss, ax 387 mov esp, [rdx + CPUMCPU.Hyper.esp] 388 388 389 389 %ifdef VBOX_WITH_CRASHDUMP_MAGIC -
trunk/src/VBox/VMM/VMMSwitcher/PAEand32Bit.mac
r37955 r41905 385 385 mov fs, eax 386 386 387 ; Setup stack ; use the lss_esp, ss pair for lss387 ; Setup stack. 388 388 DEBUG_CHAR('3') 389 mov eax, [edx + CPUMCPU.Hyper. esp]390 mov [edx + CPUMCPU.Hyper.lss_esp], eax391 lss esp, [edx + CPUMCPU.Hyper.lss_esp]389 mov eax, [edx + CPUMCPU.Hyper.ss] 390 mov ss, ax 391 mov esp, [edx + CPUMCPU.Hyper.esp] 392 392 393 393 ; Restore TSS selector; must mark it as not busy before using ltr (!) -
trunk/src/VBox/VMM/include/CPUMInternal.h
r41271 r41905 329 329 RTHCPTR pvApicBase; 330 330 uint32_t fApicDisVectors; 331 uint8_t abPadding3[HC_ARCH_BITS == 32 ? 56 : 52]; 332 #endif 333 334 /** 335 * Guest context on raw mode entry. 64-byte aligned! 336 * This a debug feature, see CPUMR3SaveEntryCtx. 337 */ 338 CPUMCTX GuestEntry; 331 uint8_t abPadding3[4]; 332 #endif 339 333 } CPUM; 340 334 /** Pointer to the CPUM instance data residing in the shared VM structure. */ -
trunk/src/VBox/VMM/include/CPUMInternal.mac
r40234 r41905 90 90 .pvApicBase RTR0PTR_RES 1 91 91 .fApicDisVectors resd 1 92 %endif 93 94 alignb 64 95 ; CPUMCTX debug stuff... 96 .GuestEntry resb 1024 92 .abPadding3 resb 4 93 %endif 97 94 endstruc 98 95 … … 101 98 ; Hypervisor Context. 102 99 ; 103 alignb 64 ; the padding 104 .Hyper.fpu resb FPUSTATE_SIZE 105 106 .Hyper.edi resq 1 107 .Hyper.esi resq 1 108 .Hyper.ebp resq 1 109 .Hyper.eax resq 1 110 .Hyper.ebx resq 1 111 .Hyper.edx resq 1 112 .Hyper.ecx resq 1 113 .Hyper.esp resq 1 114 .Hyper.lss_esp resd 1 115 .Hyper.ss resw 1 116 .Hyper.ssPadding resw 1 117 .Hyper.gs resw 1 118 .Hyper.gsPadding resw 1 119 .Hyper.fs resw 1 120 .Hyper.fsPadding resw 1 121 .Hyper.es resw 1 122 .Hyper.esPadding resw 1 123 .Hyper.ds resw 1 124 .Hyper.dsPadding resw 1 125 .Hyper.cs resw 1 126 .Hyper.csPadding resw 3 127 .Hyper.eflags resq 1 128 .Hyper.eip resq 1 129 .Hyper.r8 resq 1 130 .Hyper.r9 resq 1 131 .Hyper.r10 resq 1 132 .Hyper.r11 resq 1 133 .Hyper.r12 resq 1 134 .Hyper.r13 resq 1 135 .Hyper.r14 resq 1 136 .Hyper.r15 resq 1 137 100 .Hyper.fpu resb 512 101 .Hyper.eax resq 1 102 .Hyper.ecx resq 1 103 .Hyper.edx resq 1 104 .Hyper.ebx resq 1 105 .Hyper.esp resq 1 106 .Hyper.ebp resq 1 107 .Hyper.esi resq 1 108 .Hyper.edi resq 1 109 .Hyper.r8 resq 1 110 .Hyper.r9 resq 1 111 .Hyper.r10 resq 1 112 .Hyper.r11 resq 1 113 .Hyper.r12 resq 1 114 .Hyper.r13 resq 1 115 .Hyper.r14 resq 1 116 .Hyper.r15 resq 1 117 .Hyper.es resw 1 118 .Hyper.esPadding resw 3 138 119 .Hyper.esHid.u64Base resq 1 139 120 .Hyper.esHid.u32Limit resd 1 140 121 .Hyper.esHid.Attr resd 1 141 122 .Hyper.cs resw 1 123 .Hyper.csPadding resw 3 142 124 .Hyper.csHid.u64Base resq 1 143 125 .Hyper.csHid.u32Limit resd 1 144 126 .Hyper.csHid.Attr resd 1 145 127 .Hyper.ss resw 1 128 .Hyper.ssPadding resw 3 146 129 .Hyper.ssHid.u64Base resq 1 147 130 .Hyper.ssHid.u32Limit resd 1 148 131 .Hyper.ssHid.Attr resd 1 149 132 .Hyper.ds resw 1 133 .Hyper.dsPadding resw 3 150 134 .Hyper.dsHid.u64Base resq 1 151 135 .Hyper.dsHid.u32Limit resd 1 152 136 .Hyper.dsHid.Attr resd 1 153 137 .Hyper.fs resw 1 138 .Hyper.fsPadding resw 3 154 139 .Hyper.fsHid.u64Base resq 1 155 140 .Hyper.fsHid.u32Limit resd 1 156 141 .Hyper.fsHid.Attr resd 1 157 142 .Hyper.gs resw 1 143 .Hyper.gsPadding resw 3 158 144 .Hyper.gsHid.u64Base resq 1 159 145 .Hyper.gsHid.u32Limit resd 1 160 146 .Hyper.gsHid.Attr resd 1 161 162 .Hyper.cr0 resq 1 163 .Hyper.cr2 resq 1 164 .Hyper.cr3 resq 1 165 .Hyper.cr4 resq 1 166 167 .Hyper.dr resq 8 168 169 .Hyper.gdtr resb 10 ; GDT limit + linear address 170 .Hyper.gdtrPadding resw 1 171 .Hyper.idtr resb 10 ; IDT limit + linear address 172 .Hyper.idtrPadding resw 1 173 .Hyper.ldtr resw 1 174 .Hyper.ldtrPadding resw 1 175 .Hyper.tr resw 1 176 .Hyper.trPadding resw 1 177 147 .Hyper.eip resq 1 148 .Hyper.eflags resq 1 149 .Hyper.cr0 resq 1 150 .Hyper.cr2 resq 1 151 .Hyper.cr3 resq 1 152 .Hyper.cr4 resq 1 153 .Hyper.dr resq 8 154 .Hyper.gdtrPadding resw 3 155 .Hyper.gdtr resw 0 156 .Hyper.gdtr.cbGdt resw 1 157 .Hyper.gdtr.pGdt resq 1 158 .Hyper.idtrPadding resw 3 159 .Hyper.idtr resw 0 160 .Hyper.idtr.cbIdt resw 1 161 .Hyper.idtr.pIdt resq 1 162 .Hyper.ldtr resw 1 163 .Hyper.ldtrPadding resw 3 164 .Hyper.ldtrHid.u64Base resq 1 165 .Hyper.ldtrHid.u32Limit resd 1 166 .Hyper.ldtrHid.Attr resd 1 167 .Hyper.tr resw 1 168 .Hyper.trPadding resw 3 169 .Hyper.trHid.u64Base resq 1 170 .Hyper.trHid.u32Limit resd 1 171 .Hyper.trHid.Attr resd 1 178 172 .Hyper.SysEnter.cs resb 8 179 173 .Hyper.SysEnter.eip resb 8 180 174 .Hyper.SysEnter.esp resb 8 181 182 175 .Hyper.msrEFER resb 8 183 176 .Hyper.msrSTAR resb 8 … … 188 181 .Hyper.msrKERNELGSBASE resb 8 189 182 190 .Hyper.ldtrHid.u64Base resq 1191 .Hyper.ldtrHid.u32Limit resd 1192 .Hyper.ldtrHid.Attr resd 1193 194 .Hyper.trHid.u64Base resq 1195 .Hyper.trHid.u32Limit resd 1196 .Hyper.trHid.Attr resd 1197 198 183 ; 199 184 ; Host context state 200 185 ; 186 alignb 64 201 187 .Host.fpu resb FPUSTATE_SIZE 202 188 … … 316 302 ; 317 303 alignb 64 318 .Guest.fpu resb FPUSTATE_SIZE 319 320 .Guest.edi resq 1 321 .Guest.esi resq 1 322 .Guest.ebp resq 1 323 .Guest.eax resq 1 324 .Guest.ebx resq 1 325 .Guest.edx resq 1 326 .Guest.ecx resq 1 327 .Guest.esp resq 1 328 .Guest.lss_esp resd 1 329 .Guest.ss resw 1 330 .Guest.ssPadding resw 1 331 .Guest.gs resw 1 332 .Guest.gsPadding resw 1 333 .Guest.fs resw 1 334 .Guest.fsPadding resw 1 335 .Guest.es resw 1 336 .Guest.esPadding resw 1 337 .Guest.ds resw 1 338 .Guest.dsPadding resw 1 339 .Guest.cs resw 1 340 .Guest.csPadding resw 3 341 .Guest.eflags resq 1 342 .Guest.eip resq 1 343 .Guest.r8 resq 1 344 .Guest.r9 resq 1 345 .Guest.r10 resq 1 346 .Guest.r11 resq 1 347 .Guest.r12 resq 1 348 .Guest.r13 resq 1 349 .Guest.r14 resq 1 350 .Guest.r15 resq 1 351 304 .Guest.fpu resb 512 305 .Guest.eax resq 1 306 .Guest.ecx resq 1 307 .Guest.edx resq 1 308 .Guest.ebx resq 1 309 .Guest.esp resq 1 310 .Guest.ebp resq 1 311 .Guest.esi resq 1 312 .Guest.edi resq 1 313 .Guest.r8 resq 1 314 .Guest.r9 resq 1 315 .Guest.r10 resq 1 316 .Guest.r11 resq 1 317 .Guest.r12 resq 1 318 .Guest.r13 resq 1 319 .Guest.r14 resq 1 320 .Guest.r15 resq 1 321 .Guest.es resw 1 322 .Guest.esPadding resw 3 352 323 .Guest.esHid.u64Base resq 1 353 324 .Guest.esHid.u32Limit resd 1 354 325 .Guest.esHid.Attr resd 1 355 326 .Guest.cs resw 1 327 .Guest.csPadding resw 3 356 328 .Guest.csHid.u64Base resq 1 357 329 .Guest.csHid.u32Limit resd 1 358 330 .Guest.csHid.Attr resd 1 359 331 .Guest.ss resw 1 332 .Guest.ssPadding resw 3 360 333 .Guest.ssHid.u64Base resq 1 361 334 .Guest.ssHid.u32Limit resd 1 362 335 .Guest.ssHid.Attr resd 1 363 336 .Guest.ds resw 1 337 .Guest.dsPadding resw 3 364 338 .Guest.dsHid.u64Base resq 1 365 339 .Guest.dsHid.u32Limit resd 1 366 340 .Guest.dsHid.Attr resd 1 367 341 .Guest.fs resw 1 342 .Guest.fsPadding resw 3 368 343 .Guest.fsHid.u64Base resq 1 369 344 .Guest.fsHid.u32Limit resd 1 370 345 .Guest.fsHid.Attr resd 1 371 346 .Guest.gs resw 1 347 .Guest.gsPadding resw 3 372 348 .Guest.gsHid.u64Base resq 1 373 349 .Guest.gsHid.u32Limit resd 1 374 350 .Guest.gsHid.Attr resd 1 375 376 .Guest.cr0 resq 1 377 .Guest.cr2 resq 1 378 .Guest.cr3 resq 1 379 .Guest.cr4 resq 1 380 381 .Guest.dr resq 8 382 383 .Guest.gdtr.cbGdt resw 1 384 .Guest.gdtr.pGdt resq 1 385 .Guest.gdtrPadding resw 1 386 .Guest.idtr.cbIdt resw 1 387 .Guest.idtr.pIdt resq 1 388 .Guest.idtrPadding resw 1 389 .Guest.ldtr resw 1 390 .Guest.ldtrPadding resw 1 391 .Guest.tr resw 1 392 .Guest.trPadding resw 1 393 351 .Guest.eip resq 1 352 .Guest.eflags resq 1 353 .Guest.cr0 resq 1 354 .Guest.cr2 resq 1 355 .Guest.cr3 resq 1 356 .Guest.cr4 resq 1 357 .Guest.dr resq 8 358 .Guest.gdtrPadding resw 3 359 .Guest.gdtr resw 0 360 .Guest.gdtr.cbGdt resw 1 361 .Guest.gdtr.pGdt resq 1 362 .Guest.idtrPadding resw 3 363 .Guest.idtr resw 0 364 .Guest.idtr.cbIdt resw 1 365 .Guest.idtr.pIdt resq 1 366 .Guest.ldtr resw 1 367 .Guest.ldtrPadding resw 3 368 .Guest.ldtrHid.u64Base resq 1 369 .Guest.ldtrHid.u32Limit resd 1 370 .Guest.ldtrHid.Attr resd 1 371 .Guest.tr resw 1 372 .Guest.trPadding resw 3 373 .Guest.trHid.u64Base resq 1 374 .Guest.trHid.u32Limit resd 1 375 .Guest.trHid.Attr resd 1 394 376 .Guest.SysEnter.cs resb 8 395 377 .Guest.SysEnter.eip resb 8 396 378 .Guest.SysEnter.esp resb 8 397 398 379 .Guest.msrEFER resb 8 399 380 .Guest.msrSTAR resb 8 … … 404 385 .Guest.msrKERNELGSBASE resb 8 405 386 406 .Guest.ldtrHid.u64Base resq 1 407 .Guest.ldtrHid.u32Limit resd 1 408 .Guest.ldtrHid.Attr resd 1 409 410 .Guest.trHid.u64Base resq 1 411 .Guest.trHid.u32Limit resd 1 412 .Guest.trHid.Attr resd 1 413 387 388 alignb 64 414 389 .GuestMsrs.au64 resq 64 415 390 … … 417 392 ; Other stuff. 418 393 ; 419 alignb 64420 394 ; hypervisor core context. 421 395 .pHyperCoreR3 RTR3PTR_RES 1 -
trunk/src/VBox/VMM/testcase/tstVMStruct.h
r41899 r41905 49 49 GEN_CHECK_OFF(CPUM, fApicDisVectors); 50 50 #endif 51 GEN_CHECK_OFF(CPUM, GuestEntry);52 51 53 52 GEN_CHECK_SIZE(CPUMCPU); // has .mac … … 149 148 GEN_CHECK_OFF(CPUMCTX, rcx); 150 149 GEN_CHECK_OFF(CPUMCTX, rsp); 151 GEN_CHECK_OFF(CPUMCTX, lss_esp);152 150 GEN_CHECK_OFF(CPUMCTX, ss); 153 151 GEN_CHECK_OFF(CPUMCTX, gs); -
trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp
r41692 r41905 101 101 #define CHECK_CPUMCTXCORE(member) \ 102 102 do { \ 103 if (RT_OFFSETOF(CPUMCTX, member) - RT_OFFSETOF(CPUMCTX, edi) != RT_OFFSETOF(CPUMCTXCORE, member)) \ 103 unsigned off1 = RT_OFFSETOF(CPUMCTX, member) - RT_OFFSETOF(CPUMCTX, rax); \ 104 unsigned off2 = RT_OFFSETOF(CPUMCTXCORE, member); \ 105 if (off1 != off2) \ 104 106 { \ 105 printf("error! CPUMCTX/CORE:: %s! \n", #member); \107 printf("error! CPUMCTX/CORE:: %s! (%#x vs %#x (ctx))\n", #member, off1, off2); \ 106 108 rc++; \ 107 109 } \ … … 269 271 CHECK_MEMBER_ALIGNMENT(VM, cpum.s.pvApicBase, 8); 270 272 #endif 271 CHECK_MEMBER_ALIGNMENT(VM, cpum.s.GuestEntry, 64);272 273 273 274 CHECK_MEMBER_ALIGNMENT(VMCPU, vmm.s.u64CallRing3Arg, 8); … … 289 290 /* cpumctx */ 290 291 CHECK_MEMBER_ALIGNMENT(CPUMCTX, fpu, 32); 291 CHECK_MEMBER_ALIGNMENT(CPUMCTX, edi, 32); 292 CHECK_MEMBER_ALIGNMENT(CPUMCTX, idtr, 4); 292 CHECK_MEMBER_ALIGNMENT(CPUMCTX, rax, 32); 293 CHECK_MEMBER_ALIGNMENT(CPUMCTX, idtr.pIdt, 8); 294 CHECK_MEMBER_ALIGNMENT(CPUMCTX, gdtr.pGdt, 8); 293 295 CHECK_MEMBER_ALIGNMENT(CPUMCTX, SysEnter, 8); 294 CHECK_CPUMCTXCORE( eax);295 CHECK_CPUMCTXCORE( ebx);296 CHECK_CPUMCTXCORE( ecx);297 CHECK_CPUMCTXCORE( edx);298 CHECK_CPUMCTXCORE( ebp);299 CHECK_CPUMCTXCORE( esp);300 CHECK_CPUMCTXCORE( edi);301 CHECK_CPUMCTXCORE( esi);302 CHECK_CPUMCTXCORE( eip);303 CHECK_CPUMCTXCORE( eflags);296 CHECK_CPUMCTXCORE(rax); 297 CHECK_CPUMCTXCORE(rbx); 298 CHECK_CPUMCTXCORE(rcx); 299 CHECK_CPUMCTXCORE(rdx); 300 CHECK_CPUMCTXCORE(rbp); 301 CHECK_CPUMCTXCORE(rsp); 302 CHECK_CPUMCTXCORE(rdi); 303 CHECK_CPUMCTXCORE(rsi); 304 CHECK_CPUMCTXCORE(rip); 305 CHECK_CPUMCTXCORE(rflags); 304 306 CHECK_CPUMCTXCORE(cs); 305 307 CHECK_CPUMCTXCORE(ds);
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