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source: vbox/trunk/include/VBox/vmm/hm_svm.h@ 83263

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1/** @file
2 * HM - SVM (AMD-V) Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_hm_svm_h
27#define VBOX_INCLUDED_vmm_hm_svm_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/types.h>
33#include <iprt/assert.h>
34#include <iprt/asm.h>
35
36#ifdef RT_OS_SOLARIS
37# undef ES
38# undef CS
39# undef DS
40# undef SS
41# undef FS
42# undef GS
43#endif
44
45/** @defgroup grp_hm_svm SVM (AMD-V) Types and Definitions
46 * @ingroup grp_hm
47 * @{
48 */
49
50/** @name SVM generic / convenient defines.
51 * @{
52 */
53/** Number of pages required for the VMCB. */
54#define SVM_VMCB_PAGES 1
55/** Number of pages required for the MSR permission bitmap. */
56#define SVM_MSRPM_PAGES 2
57/** Number of pages required for the IO permission bitmap. */
58#define SVM_IOPM_PAGES 3
59/** @} */
60
61/*
62 * Ugly!
63 * When compiling the recompiler, its own svm.h defines clash with
64 * the following defines. Avoid just the duplicates here as we still
65 * require other definitions and structures in this header.
66 */
67#ifndef IN_REM_R3
68/** @name SVM_EXIT_XXX - SVM Basic Exit Reasons.
69 * @{
70 */
71/** Invalid guest state in VMCB. */
72# define SVM_EXIT_INVALID (uint64_t)(-1)
73/** Read from CR0-CR15. */
74# define SVM_EXIT_READ_CR0 0x0
75# define SVM_EXIT_READ_CR1 0x1
76# define SVM_EXIT_READ_CR2 0x2
77# define SVM_EXIT_READ_CR3 0x3
78# define SVM_EXIT_READ_CR4 0x4
79# define SVM_EXIT_READ_CR5 0x5
80# define SVM_EXIT_READ_CR6 0x6
81# define SVM_EXIT_READ_CR7 0x7
82# define SVM_EXIT_READ_CR8 0x8
83# define SVM_EXIT_READ_CR9 0x9
84# define SVM_EXIT_READ_CR10 0xa
85# define SVM_EXIT_READ_CR11 0xb
86# define SVM_EXIT_READ_CR12 0xc
87# define SVM_EXIT_READ_CR13 0xd
88# define SVM_EXIT_READ_CR14 0xe
89# define SVM_EXIT_READ_CR15 0xf
90/** Writes to CR0-CR15. */
91# define SVM_EXIT_WRITE_CR0 0x10
92# define SVM_EXIT_WRITE_CR1 0x11
93# define SVM_EXIT_WRITE_CR2 0x12
94# define SVM_EXIT_WRITE_CR3 0x13
95# define SVM_EXIT_WRITE_CR4 0x14
96# define SVM_EXIT_WRITE_CR5 0x15
97# define SVM_EXIT_WRITE_CR6 0x16
98# define SVM_EXIT_WRITE_CR7 0x17
99# define SVM_EXIT_WRITE_CR8 0x18
100# define SVM_EXIT_WRITE_CR9 0x19
101# define SVM_EXIT_WRITE_CR10 0x1a
102# define SVM_EXIT_WRITE_CR11 0x1b
103# define SVM_EXIT_WRITE_CR12 0x1c
104# define SVM_EXIT_WRITE_CR13 0x1d
105# define SVM_EXIT_WRITE_CR14 0x1e
106# define SVM_EXIT_WRITE_CR15 0x1f
107/** Read from DR0-DR15. */
108# define SVM_EXIT_READ_DR0 0x20
109# define SVM_EXIT_READ_DR1 0x21
110# define SVM_EXIT_READ_DR2 0x22
111# define SVM_EXIT_READ_DR3 0x23
112# define SVM_EXIT_READ_DR4 0x24
113# define SVM_EXIT_READ_DR5 0x25
114# define SVM_EXIT_READ_DR6 0x26
115# define SVM_EXIT_READ_DR7 0x27
116# define SVM_EXIT_READ_DR8 0x28
117# define SVM_EXIT_READ_DR9 0x29
118# define SVM_EXIT_READ_DR10 0x2a
119# define SVM_EXIT_READ_DR11 0x2b
120# define SVM_EXIT_READ_DR12 0x2c
121# define SVM_EXIT_READ_DR13 0x2d
122# define SVM_EXIT_READ_DR14 0x2e
123# define SVM_EXIT_READ_DR15 0x2f
124/** Writes to DR0-DR15. */
125# define SVM_EXIT_WRITE_DR0 0x30
126# define SVM_EXIT_WRITE_DR1 0x31
127# define SVM_EXIT_WRITE_DR2 0x32
128# define SVM_EXIT_WRITE_DR3 0x33
129# define SVM_EXIT_WRITE_DR4 0x34
130# define SVM_EXIT_WRITE_DR5 0x35
131# define SVM_EXIT_WRITE_DR6 0x36
132# define SVM_EXIT_WRITE_DR7 0x37
133# define SVM_EXIT_WRITE_DR8 0x38
134# define SVM_EXIT_WRITE_DR9 0x39
135# define SVM_EXIT_WRITE_DR10 0x3a
136# define SVM_EXIT_WRITE_DR11 0x3b
137# define SVM_EXIT_WRITE_DR12 0x3c
138# define SVM_EXIT_WRITE_DR13 0x3d
139# define SVM_EXIT_WRITE_DR14 0x3e
140# define SVM_EXIT_WRITE_DR15 0x3f
141/* Exception 0-31. */
142# define SVM_EXIT_XCPT_0 0x40
143# define SVM_EXIT_XCPT_1 0x41
144# define SVM_EXIT_XCPT_2 0x42
145# define SVM_EXIT_XCPT_3 0x43
146# define SVM_EXIT_XCPT_4 0x44
147# define SVM_EXIT_XCPT_5 0x45
148# define SVM_EXIT_XCPT_6 0x46
149# define SVM_EXIT_XCPT_7 0x47
150# define SVM_EXIT_XCPT_8 0x48
151# define SVM_EXIT_XCPT_9 0x49
152# define SVM_EXIT_XCPT_10 0x4a
153# define SVM_EXIT_XCPT_11 0x4b
154# define SVM_EXIT_XCPT_12 0x4c
155# define SVM_EXIT_XCPT_13 0x4d
156# define SVM_EXIT_XCPT_14 0x4e
157# define SVM_EXIT_XCPT_15 0x4f
158# define SVM_EXIT_XCPT_16 0x50
159# define SVM_EXIT_XCPT_17 0x51
160# define SVM_EXIT_XCPT_18 0x52
161# define SVM_EXIT_XCPT_19 0x53
162# define SVM_EXIT_XCPT_20 0x54
163# define SVM_EXIT_XCPT_21 0x55
164# define SVM_EXIT_XCPT_22 0x56
165# define SVM_EXIT_XCPT_23 0x57
166# define SVM_EXIT_XCPT_24 0x58
167# define SVM_EXIT_XCPT_25 0x59
168# define SVM_EXIT_XCPT_26 0x5a
169# define SVM_EXIT_XCPT_27 0x5b
170# define SVM_EXIT_XCPT_28 0x5c
171# define SVM_EXIT_XCPT_29 0x5d
172# define SVM_EXIT_XCPT_30 0x5e
173# define SVM_EXIT_XCPT_31 0x5f
174/* Exception (more readable) */
175# define SVM_EXIT_XCPT_DE SVM_EXIT_XCPT_0
176# define SVM_EXIT_XCPT_DB SVM_EXIT_XCPT_1
177# define SVM_EXIT_XCPT_NMI SVM_EXIT_XCPT_2
178# define SVM_EXIT_XCPT_BP SVM_EXIT_XCPT_3
179# define SVM_EXIT_XCPT_OF SVM_EXIT_XCPT_4
180# define SVM_EXIT_XCPT_BR SVM_EXIT_XCPT_5
181# define SVM_EXIT_XCPT_UD SVM_EXIT_XCPT_6
182# define SVM_EXIT_XCPT_NM SVM_EXIT_XCPT_7
183# define SVM_EXIT_XCPT_DF SVM_EXIT_XCPT_8
184# define SVM_EXIT_XCPT_CO_SEG_OVERRUN SVM_EXIT_XCPT_9
185# define SVM_EXIT_XCPT_TS SVM_EXIT_XCPT_10
186# define SVM_EXIT_XCPT_NP SVM_EXIT_XCPT_11
187# define SVM_EXIT_XCPT_SS SVM_EXIT_XCPT_12
188# define SVM_EXIT_XCPT_GP SVM_EXIT_XCPT_13
189# define SVM_EXIT_XCPT_PF SVM_EXIT_XCPT_14
190# define SVM_EXIT_XCPT_MF SVM_EXIT_XCPT_16
191# define SVM_EXIT_XCPT_AC SVM_EXIT_XCPT_17
192# define SVM_EXIT_XCPT_MC SVM_EXIT_XCPT_18
193# define SVM_EXIT_XCPT_XF SVM_EXIT_XCPT_19
194# define SVM_EXIT_XCPT_VE SVM_EXIT_XCPT_20
195# define SVM_EXIT_XCPT_SX SVM_EXIT_XCPT_30
196/** Physical maskable interrupt. */
197# define SVM_EXIT_INTR 0x60
198/** Non-maskable interrupt. */
199# define SVM_EXIT_NMI 0x61
200/** System Management interrupt. */
201# define SVM_EXIT_SMI 0x62
202/** Physical INIT signal. */
203# define SVM_EXIT_INIT 0x63
204/** Virtual interrupt. */
205# define SVM_EXIT_VINTR 0x64
206/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
207# define SVM_EXIT_CR0_SEL_WRITE 0x65
208/** IDTR read. */
209# define SVM_EXIT_IDTR_READ 0x66
210/** GDTR read. */
211# define SVM_EXIT_GDTR_READ 0x67
212/** LDTR read. */
213# define SVM_EXIT_LDTR_READ 0x68
214/** TR read. */
215# define SVM_EXIT_TR_READ 0x69
216/** IDTR write. */
217# define SVM_EXIT_IDTR_WRITE 0x6a
218/** GDTR write. */
219# define SVM_EXIT_GDTR_WRITE 0x6b
220/** LDTR write. */
221# define SVM_EXIT_LDTR_WRITE 0x6c
222/** TR write. */
223# define SVM_EXIT_TR_WRITE 0x6d
224/** RDTSC instruction. */
225# define SVM_EXIT_RDTSC 0x6e
226/** RDPMC instruction. */
227# define SVM_EXIT_RDPMC 0x6f
228/** PUSHF instruction. */
229# define SVM_EXIT_PUSHF 0x70
230/** POPF instruction. */
231# define SVM_EXIT_POPF 0x71
232/** CPUID instruction. */
233# define SVM_EXIT_CPUID 0x72
234/** RSM instruction. */
235# define SVM_EXIT_RSM 0x73
236/** IRET instruction. */
237# define SVM_EXIT_IRET 0x74
238/** Software interrupt (INTn instructions). */
239# define SVM_EXIT_SWINT 0x75
240/** INVD instruction. */
241# define SVM_EXIT_INVD 0x76
242/** PAUSE instruction. */
243# define SVM_EXIT_PAUSE 0x77
244/** HLT instruction. */
245# define SVM_EXIT_HLT 0x78
246/** INVLPG instructions. */
247# define SVM_EXIT_INVLPG 0x79
248/** INVLPGA instruction. */
249# define SVM_EXIT_INVLPGA 0x7a
250/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
251# define SVM_EXIT_IOIO 0x7b
252/** RDMSR or WRMSR access to protected MSR. */
253# define SVM_EXIT_MSR 0x7c
254/** task switch. */
255# define SVM_EXIT_TASK_SWITCH 0x7d
256/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
257# define SVM_EXIT_FERR_FREEZE 0x7e
258/** Shutdown. */
259# define SVM_EXIT_SHUTDOWN 0x7f
260/** VMRUN instruction. */
261# define SVM_EXIT_VMRUN 0x80
262/** VMMCALL instruction. */
263# define SVM_EXIT_VMMCALL 0x81
264/** VMLOAD instruction. */
265# define SVM_EXIT_VMLOAD 0x82
266/** VMSAVE instruction. */
267# define SVM_EXIT_VMSAVE 0x83
268/** STGI instruction. */
269# define SVM_EXIT_STGI 0x84
270/** CLGI instruction. */
271# define SVM_EXIT_CLGI 0x85
272/** SKINIT instruction. */
273# define SVM_EXIT_SKINIT 0x86
274/** RDTSCP instruction. */
275# define SVM_EXIT_RDTSCP 0x87
276/** ICEBP instruction. */
277# define SVM_EXIT_ICEBP 0x88
278/** WBINVD instruction. */
279# define SVM_EXIT_WBINVD 0x89
280/** MONITOR instruction. */
281# define SVM_EXIT_MONITOR 0x8a
282/** MWAIT instruction. */
283# define SVM_EXIT_MWAIT 0x8b
284/** MWAIT instruction, when armed. */
285# define SVM_EXIT_MWAIT_ARMED 0x8c
286/** XSETBV instruction. */
287# define SVM_EXIT_XSETBV 0x8d
288/** RDPRU instruction. */
289# define SVM_EXIT_RDPRU 0x8e
290/** Write to EFER (after guest instruction completes). */
291# define SVM_EXIT_WRITE_EFER_TRAP 0x8f
292/** Write to CR0-CR15 (after guest instruction completes). */
293# define SVM_EXIT_WRITE_CR0_TRAP 0x90
294# define SVM_EXIT_WRITE_CR1_TRAP 0x91
295# define SVM_EXIT_WRITE_CR2_TRAP 0x92
296# define SVM_EXIT_WRITE_CR3_TRAP 0x93
297# define SVM_EXIT_WRITE_CR4_TRAP 0x94
298# define SVM_EXIT_WRITE_CR5_TRAP 0x95
299# define SVM_EXIT_WRITE_CR6_TRAP 0x96
300# define SVM_EXIT_WRITE_CR7_TRAP 0x97
301# define SVM_EXIT_WRITE_CR8_TRAP 0x98
302# define SVM_EXIT_WRITE_CR9_TRAP 0x99
303# define SVM_EXIT_WRITE_CR10_TRAP 0x9a
304# define SVM_EXIT_WRITE_CR11_TRAP 0x9b
305# define SVM_EXIT_WRITE_CR12_TRAP 0x9c
306# define SVM_EXIT_WRITE_CR13_TRAP 0x9d
307# define SVM_EXIT_WRITE_CR14_TRAP 0x9e
308# define SVM_EXIT_WRITE_CR15_TRAP 0x9f
309/** MCOMMIT instruction. */
310# define SVM_EXIT_MCOMMIT 0xa3
311
312/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
313# define SVM_EXIT_NPF 0x400
314/** AVIC: Virtual IPI delivery not completed. */
315# define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401
316/** AVIC: Attempted access by guest to a vAPIC register not handled by AVIC
317 * hardware. */
318# define SVM_EXIT_AVIC_NOACCEL 0x402
319/** The maximum possible exit value. */
320# define SVM_EXIT_MAX (SVM_EXIT_AVIC_NOACCEL)
321/** @} */
322#endif /* !IN_REM_R3*/
323
324
325/** @name SVMVMCB.u64ExitInfo2 for task switches
326 * @{
327 */
328/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
329#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
330/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
331#define SVM_EXIT2_TASK_SWITCH_JUMP RT_BIT_64(38)
332/** Set to 1 if the task switch has an error code; else cleared to 0. */
333#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
334/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
335#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
336/** @} */
337
338/** @name SVMVMCB.u64ExitInfo1 for MSR accesses
339 * @{
340 */
341/** The access was a read MSR. */
342#define SVM_EXIT1_MSR_READ 0x0
343/** The access was a write MSR. */
344#define SVM_EXIT1_MSR_WRITE 0x1
345/** @} */
346
347/** @name SVMVMCB.u64ExitInfo1 for Mov CRx accesses.
348 * @{
349 */
350/** The mask of whether the access was via a Mov CRx instruction. */
351#define SVM_EXIT1_MOV_CRX_MASK RT_BIT_64(63)
352/** The mask for the GPR number of the Mov CRx instruction. */
353#define SVM_EXIT1_MOV_CRX_GPR_NUMBER 0xf
354/** @} */
355
356/** @name SVMVMCB.u64ExitInfo1 for Mov DRx accesses.
357 * @{
358 */
359/** The mask for the GPR number of the Mov DRx instruction. */
360#define SVM_EXIT1_MOV_DRX_GPR_NUMBER 0xf
361/** @} */
362
363/** @name SVMVMCB.ctrl.u64InterceptCtrl
364 * @{
365 */
366/** Intercept INTR (physical maskable interrupt). */
367#define SVM_CTRL_INTERCEPT_INTR RT_BIT_64(0)
368/** Intercept NMI. */
369#define SVM_CTRL_INTERCEPT_NMI RT_BIT_64(1)
370/** Intercept SMI. */
371#define SVM_CTRL_INTERCEPT_SMI RT_BIT_64(2)
372/** Intercept INIT. */
373#define SVM_CTRL_INTERCEPT_INIT RT_BIT_64(3)
374/** Intercept VINTR (virtual maskable interrupt). */
375#define SVM_CTRL_INTERCEPT_VINTR RT_BIT_64(4)
376/** Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
377#define SVM_CTRL_INTERCEPT_CR0_SEL_WRITE RT_BIT_64(5)
378/** Intercept reads of IDTR. */
379#define SVM_CTRL_INTERCEPT_IDTR_READS RT_BIT_64(6)
380/** Intercept reads of GDTR. */
381#define SVM_CTRL_INTERCEPT_GDTR_READS RT_BIT_64(7)
382/** Intercept reads of LDTR. */
383#define SVM_CTRL_INTERCEPT_LDTR_READS RT_BIT_64(8)
384/** Intercept reads of TR. */
385#define SVM_CTRL_INTERCEPT_TR_READS RT_BIT_64(9)
386/** Intercept writes of IDTR. */
387#define SVM_CTRL_INTERCEPT_IDTR_WRITES RT_BIT_64(10)
388/** Intercept writes of GDTR. */
389#define SVM_CTRL_INTERCEPT_GDTR_WRITES RT_BIT_64(11)
390/** Intercept writes of LDTR. */
391#define SVM_CTRL_INTERCEPT_LDTR_WRITES RT_BIT_64(12)
392/** Intercept writes of TR. */
393#define SVM_CTRL_INTERCEPT_TR_WRITES RT_BIT_64(13)
394/** Intercept RDTSC instruction. */
395#define SVM_CTRL_INTERCEPT_RDTSC RT_BIT_64(14)
396/** Intercept RDPMC instruction. */
397#define SVM_CTRL_INTERCEPT_RDPMC RT_BIT_64(15)
398/** Intercept PUSHF instruction. */
399#define SVM_CTRL_INTERCEPT_PUSHF RT_BIT_64(16)
400/** Intercept POPF instruction. */
401#define SVM_CTRL_INTERCEPT_POPF RT_BIT_64(17)
402/** Intercept CPUID instruction. */
403#define SVM_CTRL_INTERCEPT_CPUID RT_BIT_64(18)
404/** Intercept RSM instruction. */
405#define SVM_CTRL_INTERCEPT_RSM RT_BIT_64(19)
406/** Intercept IRET instruction. */
407#define SVM_CTRL_INTERCEPT_IRET RT_BIT_64(20)
408/** Intercept INTn instruction. */
409#define SVM_CTRL_INTERCEPT_INTN RT_BIT_64(21)
410/** Intercept INVD instruction. */
411#define SVM_CTRL_INTERCEPT_INVD RT_BIT_64(22)
412/** Intercept PAUSE instruction. */
413#define SVM_CTRL_INTERCEPT_PAUSE RT_BIT_64(23)
414/** Intercept HLT instruction. */
415#define SVM_CTRL_INTERCEPT_HLT RT_BIT_64(24)
416/** Intercept INVLPG instruction. */
417#define SVM_CTRL_INTERCEPT_INVLPG RT_BIT_64(25)
418/** Intercept INVLPGA instruction. */
419#define SVM_CTRL_INTERCEPT_INVLPGA RT_BIT_64(26)
420/** IOIO_PROT Intercept IN/OUT accesses to selected ports. */
421#define SVM_CTRL_INTERCEPT_IOIO_PROT RT_BIT_64(27)
422/** MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
423#define SVM_CTRL_INTERCEPT_MSR_PROT RT_BIT_64(28)
424/** Intercept task switches. */
425#define SVM_CTRL_INTERCEPT_TASK_SWITCH RT_BIT_64(29)
426/** FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
427#define SVM_CTRL_INTERCEPT_FERR_FREEZE RT_BIT_64(30)
428/** Intercept shutdown events. */
429#define SVM_CTRL_INTERCEPT_SHUTDOWN RT_BIT_64(31)
430/** Intercept VMRUN instruction. */
431#define SVM_CTRL_INTERCEPT_VMRUN RT_BIT_64(32 + 0)
432/** Intercept VMMCALL instruction. */
433#define SVM_CTRL_INTERCEPT_VMMCALL RT_BIT_64(32 + 1)
434/** Intercept VMLOAD instruction. */
435#define SVM_CTRL_INTERCEPT_VMLOAD RT_BIT_64(32 + 2)
436/** Intercept VMSAVE instruction. */
437#define SVM_CTRL_INTERCEPT_VMSAVE RT_BIT_64(32 + 3)
438/** Intercept STGI instruction. */
439#define SVM_CTRL_INTERCEPT_STGI RT_BIT_64(32 + 4)
440/** Intercept CLGI instruction. */
441#define SVM_CTRL_INTERCEPT_CLGI RT_BIT_64(32 + 5)
442/** Intercept SKINIT instruction. */
443#define SVM_CTRL_INTERCEPT_SKINIT RT_BIT_64(32 + 6)
444/** Intercept RDTSCP instruction. */
445#define SVM_CTRL_INTERCEPT_RDTSCP RT_BIT_64(32 + 7)
446/** Intercept ICEBP instruction. */
447#define SVM_CTRL_INTERCEPT_ICEBP RT_BIT_64(32 + 8)
448/** Intercept WBINVD instruction. */
449#define SVM_CTRL_INTERCEPT_WBINVD RT_BIT_64(32 + 9)
450/** Intercept MONITOR instruction. */
451#define SVM_CTRL_INTERCEPT_MONITOR RT_BIT_64(32 + 10)
452/** Intercept MWAIT instruction unconditionally. */
453#define SVM_CTRL_INTERCEPT_MWAIT RT_BIT_64(32 + 11)
454/** Intercept MWAIT instruction when armed. */
455#define SVM_CTRL_INTERCEPT_MWAIT_ARMED RT_BIT_64(32 + 12)
456/** Intercept XSETBV instruction. */
457#define SVM_CTRL_INTERCEPT_XSETBV RT_BIT_64(32 + 13)
458/** Intercept RDPRU instruction. */
459#define SVM_CTRL_INTERCEPT_RDPRU RT_BIT_64(32 + 14)
460/** Intercept EFER writes after guest instruction finishes. */
461#define SVM_CTRL_INTERCEPT_EFER_WRITES_TRAP RT_BIT_64(32 + 15)
462/** Intercept CR0 writes after guest instruction finishes. */
463#define SVM_CTRL_INTERCEPT_CR0_WRITES_TRAP RT_BIT_64(32 + 16)
464/** Intercept CR0 writes after guest instruction finishes. */
465#define SVM_CTRL_INTERCEPT_CR1_WRITES_TRAP RT_BIT_64(32 + 17)
466/** Intercept CR0 writes after guest instruction finishes. */
467#define SVM_CTRL_INTERCEPT_CR2_WRITES_TRAP RT_BIT_64(32 + 18)
468/** Intercept CR0 writes after guest instruction finishes. */
469#define SVM_CTRL_INTERCEPT_CR3_WRITES_TRAP RT_BIT_64(32 + 19)
470/** Intercept CR0 writes after guest instruction finishes. */
471#define SVM_CTRL_INTERCEPT_CR4_WRITES_TRAP RT_BIT_64(32 + 20)
472/** Intercept CR0 writes after guest instruction finishes. */
473#define SVM_CTRL_INTERCEPT_CR5_WRITES_TRAP RT_BIT_64(32 + 21)
474/** Intercept CR0 writes after guest instruction finishes. */
475#define SVM_CTRL_INTERCEPT_CR6_WRITES_TRAP RT_BIT_64(32 + 22)
476/** Intercept CR0 writes after guest instruction finishes. */
477#define SVM_CTRL_INTERCEPT_CR7_WRITES_TRAP RT_BIT_64(32 + 23)
478/** Intercept CR0 writes after guest instruction finishes. */
479#define SVM_CTRL_INTERCEPT_CR8_WRITES_TRAP RT_BIT_64(32 + 24)
480/** Intercept CR0 writes after guest instruction finishes. */
481#define SVM_CTRL_INTERCEPT_CR9_WRITES_TRAP RT_BIT_64(32 + 25)
482/** Intercept CR0 writes after guest instruction finishes. */
483#define SVM_CTRL_INTERCEPT_CR10_WRITES_TRAP RT_BIT_64(32 + 26)
484/** Intercept CR0 writes after guest instruction finishes. */
485#define SVM_CTRL_INTERCEPT_CR11_WRITES_TRAP RT_BIT_64(32 + 27)
486/** Intercept CR0 writes after guest instruction finishes. */
487#define SVM_CTRL_INTERCEPT_CR12_WRITES_TRAP RT_BIT_64(32 + 28)
488/** Intercept CR0 writes after guest instruction finishes. */
489#define SVM_CTRL_INTERCEPT_CR13_WRITES_TRAP RT_BIT_64(32 + 29)
490/** Intercept CR0 writes after guest instruction finishes. */
491#define SVM_CTRL_INTERCEPT_CR14_WRITES_TRAP RT_BIT_64(32 + 30)
492/** Intercept CR0 writes after guest instruction finishes. */
493#define SVM_CTRL_INTERCEPT_CR15_WRITES_TRAP RT_BIT_64(32 + 31)
494/** @} */
495
496/** @name SVMINTCTRL.u3Type
497 * @{
498 */
499/** External or virtual interrupt. */
500#define SVM_EVENT_EXTERNAL_IRQ 0
501/** Non-maskable interrupt. */
502#define SVM_EVENT_NMI 2
503/** Exception; fault or trap. */
504#define SVM_EVENT_EXCEPTION 3
505/** Software interrupt. */
506#define SVM_EVENT_SOFTWARE_INT 4
507/** @} */
508
509/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
510 * @{
511 */
512/** Flush nothing. */
513#define SVM_TLB_FLUSH_NOTHING 0
514/** Flush entire TLB (host+guest entries) */
515#define SVM_TLB_FLUSH_ENTIRE 1
516/** Flush this guest's TLB entries (by ASID) */
517#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
518/** Flush this guest's non-global TLB entries (by ASID) */
519#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
520/** @} */
521
522/**
523 * SVM selector/segment register type.
524 */
525typedef struct
526{
527 uint16_t u16Sel;
528 uint16_t u16Attr;
529 uint32_t u32Limit;
530 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
531} SVMSELREG;
532AssertCompileSize(SVMSELREG, 16);
533/** Pointer to the SVMSELREG struct. */
534typedef SVMSELREG *PSVMSELREG;
535/** Pointer to a const SVMSELREG struct. */
536typedef const SVMSELREG *PCSVMSELREG;
537
538/**
539 * SVM GDTR/IDTR type.
540 */
541typedef struct
542{
543 uint16_t u16Reserved0;
544 uint16_t u16Reserved1;
545 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
546 uint64_t u64Base;
547} SVMXDTR;
548AssertCompileSize(SVMXDTR, 16);
549typedef SVMXDTR SVMIDTR;
550typedef SVMXDTR SVMGDTR;
551/** Pointer to the SVMXDTR struct. */
552typedef SVMXDTR *PSVMXDTR;
553/** Pointer to a const SVMXDTR struct. */
554typedef const SVMXDTR *PCSVMXDTR;
555
556/**
557 * SVM Event injection structure (EVENTINJ and EXITINTINFO).
558 */
559typedef union
560{
561 struct
562 {
563 uint32_t u8Vector : 8;
564 uint32_t u3Type : 3;
565 uint32_t u1ErrorCodeValid : 1;
566 uint32_t u19Reserved : 19;
567 uint32_t u1Valid : 1;
568 uint32_t u32ErrorCode : 32;
569 } n;
570 uint64_t u;
571} SVMEVENT;
572/** Pointer to the SVMEVENT union. */
573typedef SVMEVENT *PSVMEVENT;
574/** Pointer to a const SVMEVENT union. */
575typedef const SVMEVENT *PCSVMEVENT;
576
577/** Gets the event type given an SVMEVENT parameter. */
578#define SVM_EVENT_GET_TYPE(a_SvmEvent) (((a_SvmEvent) >> 8) & 7)
579
580/**
581 * SVM Interrupt control structure (Virtual Interrupt Control).
582 */
583typedef union
584{
585 struct
586 {
587 uint32_t u8VTPR : 8; /* V_TPR */
588 uint32_t u1VIrqPending : 1; /* V_IRQ */
589 uint32_t u1VGif : 1; /* VGIF */
590 uint32_t u6Reserved : 6;
591 uint32_t u4VIntrPrio : 4; /* V_INTR_PRIO */
592 uint32_t u1IgnoreTPR : 1; /* V_IGN_TPR */
593 uint32_t u3Reserved : 3;
594 uint32_t u1VIntrMasking : 1; /* V_INTR_MASKING */
595 uint32_t u1VGifEnable : 1; /* VGIF enable */
596 uint32_t u5Reserved : 5;
597 uint32_t u1AvicEnable : 1; /* AVIC enable */
598 uint32_t u8VIntrVector : 8; /* V_INTR_VECTOR */
599 uint32_t u24Reserved : 24;
600 } n;
601 uint64_t u;
602} SVMINTCTRL;
603/** Pointer to an SVMINTCTRL structure. */
604typedef SVMINTCTRL *PSVMINTCTRL;
605/** Pointer to a const SVMINTCTRL structure. */
606typedef const SVMINTCTRL *PCSVMINTCTRL;
607
608/**
609 * SVM TLB control structure.
610 */
611typedef union
612{
613 struct
614 {
615 uint32_t u32ASID : 32;
616 uint32_t u8TLBFlush : 8;
617 uint32_t u24Reserved : 24;
618 } n;
619 uint64_t u;
620} SVMTLBCTRL;
621
622/**
623 * SVM IOIO exit info. structure (EXITINFO1 for IOIO intercepts).
624 */
625typedef union
626{
627 struct
628 {
629 uint32_t u1Type : 1; /**< Bit 0: 0 = out, 1 = in */
630 uint32_t u1Reserved : 1; /**< Bit 1: Reserved */
631 uint32_t u1Str : 1; /**< Bit 2: String I/O (1) or not (0). */
632 uint32_t u1Rep : 1; /**< Bit 3: Repeat prefixed string I/O. */
633 uint32_t u1Op8 : 1; /**< Bit 4: 8-bit operand. */
634 uint32_t u1Op16 : 1; /**< Bit 5: 16-bit operand. */
635 uint32_t u1Op32 : 1; /**< Bit 6: 32-bit operand. */
636 uint32_t u1Addr16 : 1; /**< Bit 7: 16-bit address size. */
637 uint32_t u1Addr32 : 1; /**< Bit 8: 32-bit address size. */
638 uint32_t u1Addr64 : 1; /**< Bit 9: 64-bit address size. */
639 uint32_t u3Seg : 3; /**< Bits 12:10: Effective segment number. Added w/ decode assist in APM v3.17. */
640 uint32_t u3Reserved : 3;
641 uint32_t u16Port : 16; /**< Bits 31:16: Port number. */
642 } n;
643 uint32_t u;
644} SVMIOIOEXITINFO;
645/** Pointer to an SVM IOIO exit info. structure. */
646typedef SVMIOIOEXITINFO *PSVMIOIOEXITINFO;
647/** Pointer to a const SVM IOIO exit info. structure. */
648typedef const SVMIOIOEXITINFO *PCSVMIOIOEXITINFO;
649
650/** 8-bit IO transfer. */
651#define SVM_IOIO_8_BIT_OP RT_BIT_32(4)
652/** 16-bit IO transfer. */
653#define SVM_IOIO_16_BIT_OP RT_BIT_32(5)
654/** 32-bit IO transfer. */
655#define SVM_IOIO_32_BIT_OP RT_BIT_32(6)
656/** Number of bits to shift right to get the operand sizes. */
657#define SVM_IOIO_OP_SIZE_SHIFT 4
658/** Mask of all possible IO transfer sizes. */
659#define SVM_IOIO_OP_SIZE_MASK (SVM_IOIO_8_BIT_OP | SVM_IOIO_16_BIT_OP | SVM_IOIO_32_BIT_OP)
660/** 16-bit address for the IO buffer. */
661#define SVM_IOIO_16_BIT_ADDR RT_BIT_32(7)
662/** 32-bit address for the IO buffer. */
663#define SVM_IOIO_32_BIT_ADDR RT_BIT_32(8)
664/** 64-bit address for the IO buffer. */
665#define SVM_IOIO_64_BIT_ADDR RT_BIT_32(9)
666/** Number of bits to shift right to get the address sizes. */
667#define SVM_IOIO_ADDR_SIZE_SHIFT 7
668/** Mask of all the IO address sizes. */
669#define SVM_IOIO_ADDR_SIZE_MASK (SVM_IOIO_16_BIT_ADDR | SVM_IOIO_32_BIT_ADDR | SVM_IOIO_64_BIT_ADDR)
670/** Number of bits to shift right to get the IO port number. */
671#define SVM_IOIO_PORT_SHIFT 16
672/** IO write. */
673#define SVM_IOIO_WRITE 0
674/** IO read. */
675#define SVM_IOIO_READ 1
676/**
677 * SVM IOIO transfer type.
678 */
679typedef enum
680{
681 SVMIOIOTYPE_OUT = SVM_IOIO_WRITE,
682 SVMIOIOTYPE_IN = SVM_IOIO_READ
683} SVMIOIOTYPE;
684
685/**
686 * SVM AVIC.
687 */
688typedef union
689{
690 struct
691 {
692 RT_GCC_EXTENSION uint64_t u12Reserved0 : 12;
693 RT_GCC_EXTENSION uint64_t u40Addr : 40;
694 RT_GCC_EXTENSION uint64_t u12Reserved1 : 12;
695 } n;
696 uint64_t u;
697} SVMAVIC;
698AssertCompileSize(SVMAVIC, 8);
699
700/**
701 * SVM AVIC PHYSICAL_TABLE pointer.
702 */
703typedef union
704{
705 struct
706 {
707 RT_GCC_EXTENSION uint64_t u8LastGuestCoreId : 8;
708 RT_GCC_EXTENSION uint64_t u4Reserved : 4;
709 RT_GCC_EXTENSION uint64_t u40Addr : 40;
710 RT_GCC_EXTENSION uint64_t u12Reserved : 12;
711 } n;
712 uint64_t u;
713} SVMAVICPHYS;
714AssertCompileSize(SVMAVICPHYS, 8);
715
716/**
717 * SVM Nested Paging struct.
718 */
719typedef union
720{
721 struct
722 {
723 uint32_t u1NestedPaging : 1;
724 uint32_t u1Sev : 1;
725 uint32_t u1SevEs : 1;
726 uint32_t u29Reserved : 29;
727 } n;
728 uint64_t u;
729} SVMNP;
730AssertCompileSize(SVMNP, 8);
731
732/**
733 * SVM Interrupt shadow struct.
734 */
735typedef union
736{
737 struct
738 {
739 uint32_t u1IntShadow : 1;
740 uint32_t u1GuestIntMask : 1;
741 uint32_t u30Reserved : 30;
742 } n;
743 uint64_t u;
744} SVMINTSHADOW;
745AssertCompileSize(SVMINTSHADOW, 8);
746
747/**
748 * SVM LBR virtualization struct.
749 */
750typedef union
751{
752 struct
753 {
754 uint32_t u1LbrVirt : 1;
755 uint32_t u1VirtVmsaveVmload : 1;
756 uint32_t u30Reserved : 30;
757 } n;
758 uint64_t u;
759} SVMLBRVIRT;
760AssertCompileSize(SVMLBRVIRT, 8);
761
762/** Maximum number of bytes in the Guest-instruction bytes field. */
763#define SVM_CTRL_GUEST_INSTR_BYTES_MAX 15
764
765/**
766 * SVM VMCB control area.
767 */
768#pragma pack(1)
769typedef struct
770{
771 /** Offset 0x00 - Intercept reads of CR0-CR15. */
772 uint16_t u16InterceptRdCRx;
773 /** Offset 0x02 - Intercept writes to CR0-CR15. */
774 uint16_t u16InterceptWrCRx;
775 /** Offset 0x04 - Intercept reads of DR0-DR15. */
776 uint16_t u16InterceptRdDRx;
777 /** Offset 0x06 - Intercept writes to DR0-DR15. */
778 uint16_t u16InterceptWrDRx;
779 /** Offset 0x08 - Intercept exception vectors 0-31. */
780 uint32_t u32InterceptXcpt;
781 /** Offset 0x0c - Intercept control. */
782 uint64_t u64InterceptCtrl;
783 /** Offset 0x14-0x3f - Reserved. */
784 uint8_t u8Reserved0[0x3c - 0x14];
785 /** Offset 0x3c - PAUSE filter threshold. */
786 uint16_t u16PauseFilterThreshold;
787 /** Offset 0x3e - PAUSE intercept filter count. */
788 uint16_t u16PauseFilterCount;
789 /** Offset 0x40 - Physical address of IOPM. */
790 uint64_t u64IOPMPhysAddr;
791 /** Offset 0x48 - Physical address of MSRPM. */
792 uint64_t u64MSRPMPhysAddr;
793 /** Offset 0x50 - TSC Offset. */
794 uint64_t u64TSCOffset;
795 /** Offset 0x58 - TLB control field. */
796 SVMTLBCTRL TLBCtrl;
797 /** Offset 0x60 - Interrupt control field. */
798 SVMINTCTRL IntCtrl;
799 /** Offset 0x68 - Interrupt shadow. */
800 SVMINTSHADOW IntShadow;
801 /** Offset 0x70 - Exit code. */
802 uint64_t u64ExitCode;
803 /** Offset 0x78 - Exit info 1. */
804 uint64_t u64ExitInfo1;
805 /** Offset 0x80 - Exit info 2. */
806 uint64_t u64ExitInfo2;
807 /** Offset 0x88 - Exit Interrupt info. */
808 SVMEVENT ExitIntInfo;
809 /** Offset 0x90 - Nested Paging control. */
810 SVMNP NestedPagingCtrl;
811 /** Offset 0x98 - AVIC APIC BAR. */
812 SVMAVIC AvicBar;
813 /** Offset 0xa0-0xa7 - Reserved. */
814 uint8_t u8Reserved1[0xa8 - 0xa0];
815 /** Offset 0xa8 - Event injection. */
816 SVMEVENT EventInject;
817 /** Offset 0xb0 - Host CR3 for nested paging. */
818 uint64_t u64NestedPagingCR3;
819 /** Offset 0xb8 - LBR Virtualization. */
820 SVMLBRVIRT LbrVirt;
821 /** Offset 0xc0 - VMCB Clean Bits. */
822 uint32_t u32VmcbCleanBits;
823 uint32_t u32Reserved0;
824 /** Offset 0xc8 - Next sequential instruction pointer. */
825 uint64_t u64NextRIP;
826 /** Offset 0xd0 - Number of bytes fetched. */
827 uint8_t cbInstrFetched;
828 /** Offset 0xd1 - Guest instruction bytes. */
829 uint8_t abInstr[SVM_CTRL_GUEST_INSTR_BYTES_MAX];
830 /** Offset 0xe0 - AVIC APIC_BACKING_PAGE pointer. */
831 SVMAVIC AvicBackingPagePtr;
832 /** Offset 0xe8-0xef - Reserved. */
833 uint8_t u8Reserved2[0xf0 - 0xe8];
834 /** Offset 0xf0 - AVIC LOGICAL_TABLE pointer. */
835 SVMAVIC AvicLogicalTablePtr;
836 /** Offset 0xf8 - AVIC PHYSICAL_TABLE pointer. */
837 SVMAVICPHYS AvicPhysicalTablePtr;
838} SVMVMCBCTRL;
839#pragma pack()
840/** Pointer to the SVMVMCBSTATESAVE structure. */
841typedef SVMVMCBCTRL *PSVMVMCBCTRL;
842/** Pointer to a const SVMVMCBSTATESAVE structure. */
843typedef const SVMVMCBCTRL *PCSVMVMCBCTRL;
844AssertCompileSize(SVMVMCBCTRL, 0x100);
845AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdCRx, 0x00);
846AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrCRx, 0x02);
847AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdDRx, 0x04);
848AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrDRx, 0x06);
849AssertCompileMemberOffset(SVMVMCBCTRL, u32InterceptXcpt, 0x08);
850AssertCompileMemberOffset(SVMVMCBCTRL, u64InterceptCtrl, 0x0c);
851AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved0, 0x14);
852AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterThreshold, 0x3c);
853AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterCount, 0x3e);
854AssertCompileMemberOffset(SVMVMCBCTRL, u64IOPMPhysAddr, 0x40);
855AssertCompileMemberOffset(SVMVMCBCTRL, u64MSRPMPhysAddr, 0x48);
856AssertCompileMemberOffset(SVMVMCBCTRL, u64TSCOffset, 0x50);
857AssertCompileMemberOffset(SVMVMCBCTRL, TLBCtrl, 0x58);
858AssertCompileMemberOffset(SVMVMCBCTRL, IntCtrl, 0x60);
859AssertCompileMemberOffset(SVMVMCBCTRL, IntShadow, 0x68);
860AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitCode, 0x70);
861AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo1, 0x78);
862AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo2, 0x80);
863AssertCompileMemberOffset(SVMVMCBCTRL, ExitIntInfo, 0x88);
864AssertCompileMemberOffset(SVMVMCBCTRL, NestedPagingCtrl, 0x90);
865AssertCompileMemberOffset(SVMVMCBCTRL, AvicBar, 0x98);
866AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved1, 0xa0);
867AssertCompileMemberOffset(SVMVMCBCTRL, EventInject, 0xa8);
868AssertCompileMemberOffset(SVMVMCBCTRL, u64NestedPagingCR3, 0xb0);
869AssertCompileMemberOffset(SVMVMCBCTRL, LbrVirt, 0xb8);
870AssertCompileMemberOffset(SVMVMCBCTRL, u32VmcbCleanBits, 0xc0);
871AssertCompileMemberOffset(SVMVMCBCTRL, u64NextRIP, 0xc8);
872AssertCompileMemberOffset(SVMVMCBCTRL, cbInstrFetched, 0xd0);
873AssertCompileMemberOffset(SVMVMCBCTRL, abInstr, 0xd1);
874AssertCompileMemberOffset(SVMVMCBCTRL, AvicBackingPagePtr, 0xe0);
875AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved2, 0xe8);
876AssertCompileMemberOffset(SVMVMCBCTRL, AvicLogicalTablePtr, 0xf0);
877AssertCompileMemberOffset(SVMVMCBCTRL, AvicPhysicalTablePtr, 0xf8);
878AssertCompileMemberSize(SVMVMCBCTRL, abInstr, 0x0f);
879
880/**
881 * SVM VMCB state save area.
882 */
883#pragma pack(1)
884typedef struct
885{
886 /** Offset 0x400 - Guest ES register + hidden parts. */
887 SVMSELREG ES;
888 /** Offset 0x410 - Guest CS register + hidden parts. */
889 SVMSELREG CS;
890 /** Offset 0x420 - Guest SS register + hidden parts. */
891 SVMSELREG SS;
892 /** Offset 0x430 - Guest DS register + hidden parts. */
893 SVMSELREG DS;
894 /** Offset 0x440 - Guest FS register + hidden parts. */
895 SVMSELREG FS;
896 /** Offset 0x450 - Guest GS register + hidden parts. */
897 SVMSELREG GS;
898 /** Offset 0x460 - Guest GDTR register. */
899 SVMGDTR GDTR;
900 /** Offset 0x470 - Guest LDTR register + hidden parts. */
901 SVMSELREG LDTR;
902 /** Offset 0x480 - Guest IDTR register. */
903 SVMIDTR IDTR;
904 /** Offset 0x490 - Guest TR register + hidden parts. */
905 SVMSELREG TR;
906 /** Offset 0x4A0-0x4CA - Reserved. */
907 uint8_t u8Reserved0[0x4cb - 0x4a0];
908 /** Offset 0x4CB - CPL. */
909 uint8_t u8CPL;
910 /** Offset 0x4CC-0x4CF - Reserved. */
911 uint8_t u8Reserved1[0x4d0 - 0x4cc];
912 /** Offset 0x4D0 - EFER. */
913 uint64_t u64EFER;
914 /** Offset 0x4D8-0x547 - Reserved. */
915 uint8_t u8Reserved2[0x548 - 0x4d8];
916 /** Offset 0x548 - CR4. */
917 uint64_t u64CR4;
918 /** Offset 0x550 - CR3. */
919 uint64_t u64CR3;
920 /** Offset 0x558 - CR0. */
921 uint64_t u64CR0;
922 /** Offset 0x560 - DR7. */
923 uint64_t u64DR7;
924 /** Offset 0x568 - DR6. */
925 uint64_t u64DR6;
926 /** Offset 0x570 - RFLAGS. */
927 uint64_t u64RFlags;
928 /** Offset 0x578 - RIP. */
929 uint64_t u64RIP;
930 /** Offset 0x580-0x5D7 - Reserved. */
931 uint8_t u8Reserved3[0x5d8 - 0x580];
932 /** Offset 0x5D8 - RSP. */
933 uint64_t u64RSP;
934 /** Offset 0x5E0-0x5F7 - Reserved. */
935 uint8_t u8Reserved4[0x5f8 - 0x5e0];
936 /** Offset 0x5F8 - RAX. */
937 uint64_t u64RAX;
938 /** Offset 0x600 - STAR. */
939 uint64_t u64STAR;
940 /** Offset 0x608 - LSTAR. */
941 uint64_t u64LSTAR;
942 /** Offset 0x610 - CSTAR. */
943 uint64_t u64CSTAR;
944 /** Offset 0x618 - SFMASK. */
945 uint64_t u64SFMASK;
946 /** Offset 0x620 - KernelGSBase. */
947 uint64_t u64KernelGSBase;
948 /** Offset 0x628 - SYSENTER_CS. */
949 uint64_t u64SysEnterCS;
950 /** Offset 0x630 - SYSENTER_ESP. */
951 uint64_t u64SysEnterESP;
952 /** Offset 0x638 - SYSENTER_EIP. */
953 uint64_t u64SysEnterEIP;
954 /** Offset 0x640 - CR2. */
955 uint64_t u64CR2;
956 /** Offset 0x648-0x667 - Reserved. */
957 uint8_t u8Reserved5[0x668 - 0x648];
958 /** Offset 0x668 - PAT (Page Attribute Table) MSR. */
959 uint64_t u64PAT;
960 /** Offset 0x670 - DBGCTL. */
961 uint64_t u64DBGCTL;
962 /** Offset 0x678 - BR_FROM. */
963 uint64_t u64BR_FROM;
964 /** Offset 0x680 - BR_TO. */
965 uint64_t u64BR_TO;
966 /** Offset 0x688 - LASTEXCPFROM. */
967 uint64_t u64LASTEXCPFROM;
968 /** Offset 0x690 - LASTEXCPTO. */
969 uint64_t u64LASTEXCPTO;
970} SVMVMCBSTATESAVE;
971#pragma pack()
972/** Pointer to the SVMVMCBSTATESAVE structure. */
973typedef SVMVMCBSTATESAVE *PSVMVMCBSTATESAVE;
974/** Pointer to a const SVMVMCBSTATESAVE structure. */
975typedef const SVMVMCBSTATESAVE *PCSVMVMCBSTATESAVE;
976AssertCompileSize(SVMVMCBSTATESAVE, 0x298);
977AssertCompileMemberOffset(SVMVMCBSTATESAVE, ES, 0x400 - 0x400);
978AssertCompileMemberOffset(SVMVMCBSTATESAVE, CS, 0x410 - 0x400);
979AssertCompileMemberOffset(SVMVMCBSTATESAVE, SS, 0x420 - 0x400);
980AssertCompileMemberOffset(SVMVMCBSTATESAVE, DS, 0x430 - 0x400);
981AssertCompileMemberOffset(SVMVMCBSTATESAVE, FS, 0x440 - 0x400);
982AssertCompileMemberOffset(SVMVMCBSTATESAVE, GS, 0x450 - 0x400);
983AssertCompileMemberOffset(SVMVMCBSTATESAVE, GDTR, 0x460 - 0x400);
984AssertCompileMemberOffset(SVMVMCBSTATESAVE, LDTR, 0x470 - 0x400);
985AssertCompileMemberOffset(SVMVMCBSTATESAVE, IDTR, 0x480 - 0x400);
986AssertCompileMemberOffset(SVMVMCBSTATESAVE, TR, 0x490 - 0x400);
987AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved0, 0x4a0 - 0x400);
988AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8CPL, 0x4cb - 0x400);
989AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved1, 0x4cc - 0x400);
990AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64EFER, 0x4d0 - 0x400);
991AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved2, 0x4d8 - 0x400);
992AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR4, 0x548 - 0x400);
993AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR3, 0x550 - 0x400);
994AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR0, 0x558 - 0x400);
995AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR7, 0x560 - 0x400);
996AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR6, 0x568 - 0x400);
997AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RFlags, 0x570 - 0x400);
998AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RIP, 0x578 - 0x400);
999AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved3, 0x580 - 0x400);
1000AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RSP, 0x5d8 - 0x400);
1001AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved4, 0x5e0 - 0x400);
1002AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RAX, 0x5f8 - 0x400);
1003AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64STAR, 0x600 - 0x400);
1004AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LSTAR, 0x608 - 0x400);
1005AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CSTAR, 0x610 - 0x400);
1006AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SFMASK, 0x618 - 0x400);
1007AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64KernelGSBase, 0x620 - 0x400);
1008AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterCS, 0x628 - 0x400);
1009AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterESP, 0x630 - 0x400);
1010AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterEIP, 0x638 - 0x400);
1011AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR2, 0x640 - 0x400);
1012AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved5, 0x648 - 0x400);
1013AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64PAT, 0x668 - 0x400);
1014AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DBGCTL, 0x670 - 0x400);
1015AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_FROM, 0x678 - 0x400);
1016AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_TO, 0x680 - 0x400);
1017AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPFROM, 0x688 - 0x400);
1018AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPTO, 0x690 - 0x400);
1019
1020/**
1021 * SVM VM Control Block. (VMCB)
1022 */
1023#pragma pack(1)
1024typedef struct SVMVMCB
1025{
1026 /** Offset 0x00 - Control area. */
1027 SVMVMCBCTRL ctrl;
1028 /** Offset 0x100-0x3FF - Reserved. */
1029 uint8_t u8Reserved0[0x400 - 0x100];
1030 /** Offset 0x400 - State save area. */
1031 SVMVMCBSTATESAVE guest;
1032 /** Offset 0x698-0xFFF- Reserved. */
1033 uint8_t u8Reserved1[0x1000 - 0x698];
1034} SVMVMCB;
1035#pragma pack()
1036/** Pointer to the SVMVMCB structure. */
1037typedef SVMVMCB *PSVMVMCB;
1038/** Pointer to a const SVMVMCB structure. */
1039typedef const SVMVMCB *PCSVMVMCB;
1040AssertCompileMemberOffset(SVMVMCB, ctrl, 0x00);
1041AssertCompileMemberOffset(SVMVMCB, u8Reserved0, 0x100);
1042AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
1043AssertCompileMemberOffset(SVMVMCB, u8Reserved1, 0x698);
1044AssertCompileSize(SVMVMCB, 0x1000);
1045
1046/**
1047 * SVM MSRs.
1048 */
1049typedef struct SVMMSRS
1050{
1051 /** HWCR MSR. */
1052 uint64_t u64MsrHwcr;
1053 /** Reserved for future. */
1054 uint64_t u64Padding[27];
1055} SVMMSRS;
1056AssertCompileSizeAlignment(SVMMSRS, 8);
1057AssertCompileSize(SVMMSRS, 224);
1058/** Pointer to a SVMMSRS struct. */
1059typedef SVMMSRS *PSVMMSRS;
1060/** Pointer to a const SVMMSRS struct. */
1061typedef const SVMMSRS *PCSVMMSRS;
1062
1063/**
1064 * SVM nested-guest VMCB cache.
1065 *
1066 * Contains VMCB fields from the nested-guest VMCB before they're modified by
1067 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
1068 *
1069 * A VMCB field needs to be cached when it needs to be modified for execution using
1070 * hardware-assisted SVM and any of the following are true:
1071 * - If the original field needs to be inspected during execution of the
1072 * nested-guest or \#VMEXIT processing.
1073 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
1074 *
1075 * A VMCB field needs to be restored only when the field is written back to
1076 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
1077 * guest.
1078 *
1079 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
1080 * this structure.
1081 */
1082#pragma pack(1)
1083typedef struct SVMNESTEDVMCBCACHE
1084{
1085 /** Cache of CRX read intercepts. */
1086 uint16_t u16InterceptRdCRx;
1087 /** Cache of CRX write intercepts. */
1088 uint16_t u16InterceptWrCRx;
1089 /** Cache of DRX read intercepts. */
1090 uint16_t u16InterceptRdDRx;
1091 /** Cache of DRX write intercepts. */
1092 uint16_t u16InterceptWrDRx;
1093
1094 /** Cache of the pause-filter threshold. */
1095 uint16_t u16PauseFilterThreshold;
1096 /** Cache of the pause-filter count. */
1097 uint16_t u16PauseFilterCount;
1098
1099 /** Cache of exception intercepts. */
1100 uint32_t u32InterceptXcpt;
1101 /** Cache of control intercepts. */
1102 uint64_t u64InterceptCtrl;
1103
1104 /** Cache of the TSC offset. */
1105 uint64_t u64TSCOffset;
1106
1107 /** Cache of V_INTR_MASKING bit. */
1108 bool fVIntrMasking;
1109 /** Cache of the nested-paging bit. */
1110 bool fNestedPaging;
1111 /** Cache of the LBR virtualization bit. */
1112 bool fLbrVirt;
1113 /** Whether the VMCB is cached by HM. */
1114 bool fCacheValid;
1115 /** Alignment. */
1116 bool afPadding0[4];
1117} SVMNESTEDVMCBCACHE;
1118#pragma pack()
1119/** Pointer to the SVMNESTEDVMCBCACHE structure. */
1120typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
1121/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
1122typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
1123AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
1124
1125/**
1126 * Segment attribute conversion between CPU and AMD-V VMCB format.
1127 *
1128 * The CPU format of the segment attribute is described in X86DESCATTRBITS
1129 * which is 16-bits (i.e. includes 4 bits of the segment limit).
1130 *
1131 * The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
1132 * only the attribute bits and nothing else). Upper 4-bits are unused.
1133 */
1134#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0xf000) >> 4) )
1135#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0x0f00) << 4) )
1136
1137/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1138 * Copies the specified segment register to a VMCB from a virtual CPU context.
1139 *
1140 * @param a_pCtx The virtual-CPU context.
1141 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1142 * @param a_REG The segment register in the VMCB state-save
1143 * struct (ES/CS/SS/DS).
1144 * @param a_reg The segment register in the virtual CPU struct
1145 * (es/cs/ss/ds).
1146 */
1147#define HMSVM_SEG_REG_COPY_TO_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1148 do \
1149 { \
1150 Assert((a_pCtx)->a_reg.fFlags & CPUMSELREG_FLAGS_VALID); \
1151 Assert((a_pCtx)->a_reg.ValidSel == (a_pCtx)->a_reg.Sel); \
1152 (a_pVmcbStateSave)->a_REG.u16Sel = (a_pCtx)->a_reg.Sel; \
1153 (a_pVmcbStateSave)->a_REG.u32Limit = (a_pCtx)->a_reg.u32Limit; \
1154 (a_pVmcbStateSave)->a_REG.u64Base = (a_pCtx)->a_reg.u64Base; \
1155 (a_pVmcbStateSave)->a_REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR((a_pCtx)->a_reg.Attr.u); \
1156 } while (0)
1157
1158/** @def HMSVM_SEG_REG_COPY_FROM_VMCB
1159 * Copies the specified segment register from the VMCB to a virtual CPU
1160 * context.
1161 *
1162 * @param a_pCtx The virtual-CPU context.
1163 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1164 * @param a_REG The segment register in the VMCB state-save
1165 * struct (ES/CS/SS/DS).
1166 * @param a_reg The segment register in the virtual CPU struct
1167 * (es/ds/ss/ds).
1168 */
1169#define HMSVM_SEG_REG_COPY_FROM_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1170 do \
1171 { \
1172 (a_pCtx)->a_reg.Sel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1173 (a_pCtx)->a_reg.ValidSel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1174 (a_pCtx)->a_reg.fFlags = CPUMSELREG_FLAGS_VALID; \
1175 (a_pCtx)->a_reg.u32Limit = (a_pVmcbStateSave)->a_REG.u32Limit; \
1176 (a_pCtx)->a_reg.u64Base = (a_pVmcbStateSave)->a_REG.u64Base; \
1177 (a_pCtx)->a_reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR((a_pVmcbStateSave)->a_REG.u16Attr); \
1178 } while (0)
1179
1180
1181/** @defgroup grp_hm_svm_hwexec SVM Hardware-assisted execution Helpers
1182 *
1183 * These functions are only here because the inline functions in cpum.h calls them.
1184 * Don't add any more functions here unless there is no other option.
1185 * @{
1186 */
1187VMM_INT_DECL(bool) HMGetGuestSvmCtrlIntercepts(PCVMCPU pVCpu, uint64_t *pu64Intercepts);
1188VMM_INT_DECL(bool) HMGetGuestSvmReadCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1189VMM_INT_DECL(bool) HMGetGuestSvmWriteCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1190VMM_INT_DECL(bool) HMGetGuestSvmReadDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1191VMM_INT_DECL(bool) HMGetGuestSvmWriteDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1192VMM_INT_DECL(bool) HMGetGuestSvmXcptIntercepts(PCVMCPU pVCpu, uint32_t *pu32Intercepts);
1193VMM_INT_DECL(bool) HMGetGuestSvmVirtIntrMasking(PCVMCPU pVCpu, bool *pfVIntrMasking);
1194VMM_INT_DECL(bool) HMGetGuestSvmNestedPaging(PCVMCPU pVCpu, bool *pfNestedPagingCtrl);
1195VMM_INT_DECL(bool) HMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, uint16_t *pu16PauseFilterCount);
1196VMM_INT_DECL(bool) HMGetGuestSvmTscOffset(PCVMCPU pVCpu, uint64_t *pu64TscOffset);
1197/** @} */
1198
1199
1200/** @} */
1201
1202#endif /* !VBOX_INCLUDED_vmm_hm_svm_h */
1203
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