hm_vmx.h@ 76402

Last change on this file since 76402 was 76397, checked in by vboxsync, 6 years ago
VBox/vmm/hm_svm.h,hm_vmx.h: Try avoid including VBox/err.h in widely used headers, so split out the inline stuff from hm_vmx.h into hmvmxinline.h. bugref:9344
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <iprt/x86.h>
31	#include <iprt/assertcompile.h>
32
33	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
34	when targeting AMD64. */
35	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
36	# pragma warning(push)
37	# pragma warning(disable:4668) /* Several incorrect __cplusplus uses. */
38	# pragma warning(disable:4255) /* Incorrect __slwpcb prototype. */
39	# include <intrin.h>
40	# pragma warning(pop)
41	/* We always want them as intrinsics, no functions. */
42	# pragma intrinsic(__vmx_on)
43	# pragma intrinsic(__vmx_off)
44	# pragma intrinsic(__vmx_vmclear)
45	# pragma intrinsic(__vmx_vmptrld)
46	# pragma intrinsic(__vmx_vmread)
47	# pragma intrinsic(__vmx_vmwrite)
48	# define VMX_USE_MSC_INTRINSICS 1
49	#else
50	# define VMX_USE_MSC_INTRINSICS 0
51	#endif
52
53
54	/** @defgroup grp_hm_vmx VMX Types and Definitions
55	* @ingroup grp_hm
56	* @{
57	*/
58
59	/** @name Host-state restoration flags.
60	* @note If you change these values don't forget to update the assembly
61	* defines as well!
62	* @{
63	*/
64	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
65	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
66	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
67	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
68	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
69	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
70	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
71	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
72	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
73	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
74	/** @} */
75
76	/**
77	* Host-state restoration structure.
78	* This holds host-state fields that require manual restoration.
79	* Assembly version found in hm_vmx.mac (should be automatically verified).
80	*/
81	typedef struct VMXRESTOREHOST
82	{
83	RTSEL uHostSelDS; /* 0x00 */
84	RTSEL uHostSelES; /* 0x02 */
85	RTSEL uHostSelFS; /* 0x04 */
86	RTSEL uHostSelGS; /* 0x06 */
87	RTSEL uHostSelTR; /* 0x08 */
88	uint8_t abPadding0[4];
89	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
90	uint8_t abPadding1[6];
91	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
92	uint8_t abPadding2[6];
93	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
94	uint64_t uHostFSBase; /* 0x38 */
95	uint64_t uHostGSBase; /* 0x40 */
96	} VMXRESTOREHOST;
97	/** Pointer to VMXRESTOREHOST. */
98	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
99	AssertCompileSize(X86XDTR64, 10);
100	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
101	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
102	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
103	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
104	AssertCompileSize(VMXRESTOREHOST, 72);
105	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
106
107	/** @name Host-state MSR lazy-restoration flags.
108	* @{
109	*/
110	/** The host MSRs have been saved. */
111	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
112	/** The guest MSRs are loaded and in effect. */
113	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
114	/** @} */
115
116	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
117	* UFC = Unsupported Feature Combination.
118	* @{
119	*/
120	/** Unsupported pin-based VM-execution controls combo. */
121	#define VMX_UFC_CTRL_PIN_EXEC 1
122	/** Unsupported processor-based VM-execution controls combo. */
123	#define VMX_UFC_CTRL_PROC_EXEC 2
124	/** Unsupported move debug register VM-exit combo. */
125	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
126	/** Unsupported VM-entry controls combo. */
127	#define VMX_UFC_CTRL_ENTRY 4
128	/** Unsupported VM-exit controls combo. */
129	#define VMX_UFC_CTRL_EXIT 5
130	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
131	* for storing host MSRs. */
132	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
133	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
134	* for storing guest MSRs. */
135	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
136	/** Invalid VMCS size. */
137	#define VMX_UFC_INVALID_VMCS_SIZE 8
138	/** Unsupported secondary processor-based VM-execution controls combo. */
139	#define VMX_UFC_CTRL_PROC_EXEC2 9
140	/** Invalid unrestricted-guest execution controls combo. */
141	#define VMX_UFC_INVALID_UX_COMBO 10
142	/** EPT flush type not supported. */
143	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
144	/** EPT paging structure memory type is not write-back. */
145	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
146	/** EPT requires INVEPT instr. support but it's not available. */
147	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
148	/** EPT requires page-walk length of 4. */
149	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
150	/** @} */
151
152	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
153	* VCI = VMCS-field Cache Invalid.
154	* @{
155	*/
156	/** Cache of VM-entry controls invalid. */
157	#define VMX_VCI_CTRL_ENTRY 300
158	/** Cache of VM-exit controls invalid. */
159	#define VMX_VCI_CTRL_EXIT 301
160	/** Cache of pin-based VM-execution controls invalid. */
161	#define VMX_VCI_CTRL_PIN_EXEC 302
162	/** Cache of processor-based VM-execution controls invalid. */
163	#define VMX_VCI_CTRL_PROC_EXEC 303
164	/** Cache of secondary processor-based VM-execution controls invalid. */
165	#define VMX_VCI_CTRL_PROC_EXEC2 304
166	/** Cache of exception bitmap invalid. */
167	#define VMX_VCI_CTRL_XCPT_BITMAP 305
168	/** Cache of TSC offset invalid. */
169	#define VMX_VCI_CTRL_TSC_OFFSET 306
170	/** @} */
171
172	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
173	* IGS = Invalid Guest State.
174	* @{
175	*/
176	/** An error occurred while checking invalid-guest-state. */
177	#define VMX_IGS_ERROR 500
178	/** The invalid guest-state checks did not find any reason why. */
179	#define VMX_IGS_REASON_NOT_FOUND 501
180	/** CR0 fixed1 bits invalid. */
181	#define VMX_IGS_CR0_FIXED1 502
182	/** CR0 fixed0 bits invalid. */
183	#define VMX_IGS_CR0_FIXED0 503
184	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
185	#define VMX_IGS_CR0_PG_PE_COMBO 504
186	/** CR4 fixed1 bits invalid. */
187	#define VMX_IGS_CR4_FIXED1 505
188	/** CR4 fixed0 bits invalid. */
189	#define VMX_IGS_CR4_FIXED0 506
190	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
191	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
192	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
193	/** CR0.PG not set for long-mode when not using unrestricted guest. */
194	#define VMX_IGS_CR0_PG_LONGMODE 508
195	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
196	#define VMX_IGS_CR4_PAE_LONGMODE 509
197	/** CR4.PCIDE set for 32-bit guest. */
198	#define VMX_IGS_CR4_PCIDE 510
199	/** VMCS' DR7 reserved bits not set to 0. */
200	#define VMX_IGS_DR7_RESERVED 511
201	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
202	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
203	/** VMCS' EFER MSR reserved bits not set to 0. */
204	#define VMX_IGS_EFER_MSR_RESERVED 513
205	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
206	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
207	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
208	* without unrestricted guest. */
209	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
210	/** CS.Attr.P bit invalid. */
211	#define VMX_IGS_CS_ATTR_P_INVALID 516
212	/** CS.Attr reserved bits not set to 0. */
213	#define VMX_IGS_CS_ATTR_RESERVED 517
214	/** CS.Attr.G bit invalid. */
215	#define VMX_IGS_CS_ATTR_G_INVALID 518
216	/** CS is unusable. */
217	#define VMX_IGS_CS_ATTR_UNUSABLE 519
218	/** CS and SS DPL unequal. */
219	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
220	/** CS and SS DPL mismatch. */
221	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
222	/** CS Attr.Type invalid. */
223	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
224	/** CS and SS RPL unequal. */
225	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
226	/** SS.Attr.DPL and SS RPL unequal. */
227	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
228	/** SS.Attr.DPL invalid for segment type. */
229	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
230	/** SS.Attr.Type invalid. */
231	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
232	/** SS.Attr.P bit invalid. */
233	#define VMX_IGS_SS_ATTR_P_INVALID 527
234	/** SS.Attr reserved bits not set to 0. */
235	#define VMX_IGS_SS_ATTR_RESERVED 528
236	/** SS.Attr.G bit invalid. */
237	#define VMX_IGS_SS_ATTR_G_INVALID 529
238	/** DS.Attr.A bit invalid. */
239	#define VMX_IGS_DS_ATTR_A_INVALID 530
240	/** DS.Attr.P bit invalid. */
241	#define VMX_IGS_DS_ATTR_P_INVALID 531
242	/** DS.Attr.DPL and DS RPL unequal. */
243	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
244	/** DS.Attr reserved bits not set to 0. */
245	#define VMX_IGS_DS_ATTR_RESERVED 533
246	/** DS.Attr.G bit invalid. */
247	#define VMX_IGS_DS_ATTR_G_INVALID 534
248	/** DS.Attr.Type invalid. */
249	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
250	/** ES.Attr.A bit invalid. */
251	#define VMX_IGS_ES_ATTR_A_INVALID 536
252	/** ES.Attr.P bit invalid. */
253	#define VMX_IGS_ES_ATTR_P_INVALID 537
254	/** ES.Attr.DPL and DS RPL unequal. */
255	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
256	/** ES.Attr reserved bits not set to 0. */
257	#define VMX_IGS_ES_ATTR_RESERVED 539
258	/** ES.Attr.G bit invalid. */
259	#define VMX_IGS_ES_ATTR_G_INVALID 540
260	/** ES.Attr.Type invalid. */
261	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
262	/** FS.Attr.A bit invalid. */
263	#define VMX_IGS_FS_ATTR_A_INVALID 542
264	/** FS.Attr.P bit invalid. */
265	#define VMX_IGS_FS_ATTR_P_INVALID 543
266	/** FS.Attr.DPL and DS RPL unequal. */
267	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
268	/** FS.Attr reserved bits not set to 0. */
269	#define VMX_IGS_FS_ATTR_RESERVED 545
270	/** FS.Attr.G bit invalid. */
271	#define VMX_IGS_FS_ATTR_G_INVALID 546
272	/** FS.Attr.Type invalid. */
273	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
274	/** GS.Attr.A bit invalid. */
275	#define VMX_IGS_GS_ATTR_A_INVALID 548
276	/** GS.Attr.P bit invalid. */
277	#define VMX_IGS_GS_ATTR_P_INVALID 549
278	/** GS.Attr.DPL and DS RPL unequal. */
279	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
280	/** GS.Attr reserved bits not set to 0. */
281	#define VMX_IGS_GS_ATTR_RESERVED 551
282	/** GS.Attr.G bit invalid. */
283	#define VMX_IGS_GS_ATTR_G_INVALID 552
284	/** GS.Attr.Type invalid. */
285	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
286	/** V86 mode CS.Base invalid. */
287	#define VMX_IGS_V86_CS_BASE_INVALID 554
288	/** V86 mode CS.Limit invalid. */
289	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
290	/** V86 mode CS.Attr invalid. */
291	#define VMX_IGS_V86_CS_ATTR_INVALID 556
292	/** V86 mode SS.Base invalid. */
293	#define VMX_IGS_V86_SS_BASE_INVALID 557
294	/** V86 mode SS.Limit invalid. */
295	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
296	/** V86 mode SS.Attr invalid. */
297	#define VMX_IGS_V86_SS_ATTR_INVALID 559
298	/** V86 mode DS.Base invalid. */
299	#define VMX_IGS_V86_DS_BASE_INVALID 560
300	/** V86 mode DS.Limit invalid. */
301	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
302	/** V86 mode DS.Attr invalid. */
303	#define VMX_IGS_V86_DS_ATTR_INVALID 562
304	/** V86 mode ES.Base invalid. */
305	#define VMX_IGS_V86_ES_BASE_INVALID 563
306	/** V86 mode ES.Limit invalid. */
307	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
308	/** V86 mode ES.Attr invalid. */
309	#define VMX_IGS_V86_ES_ATTR_INVALID 565
310	/** V86 mode FS.Base invalid. */
311	#define VMX_IGS_V86_FS_BASE_INVALID 566
312	/** V86 mode FS.Limit invalid. */
313	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
314	/** V86 mode FS.Attr invalid. */
315	#define VMX_IGS_V86_FS_ATTR_INVALID 568
316	/** V86 mode GS.Base invalid. */
317	#define VMX_IGS_V86_GS_BASE_INVALID 569
318	/** V86 mode GS.Limit invalid. */
319	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
320	/** V86 mode GS.Attr invalid. */
321	#define VMX_IGS_V86_GS_ATTR_INVALID 571
322	/** Longmode CS.Base invalid. */
323	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
324	/** Longmode SS.Base invalid. */
325	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
326	/** Longmode DS.Base invalid. */
327	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
328	/** Longmode ES.Base invalid. */
329	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
330	/** SYSENTER ESP is not canonical. */
331	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
332	/** SYSENTER EIP is not canonical. */
333	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
334	/** PAT MSR invalid. */
335	#define VMX_IGS_PAT_MSR_INVALID 578
336	/** PAT MSR reserved bits not set to 0. */
337	#define VMX_IGS_PAT_MSR_RESERVED 579
338	/** GDTR.Base is not canonical. */
339	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
340	/** IDTR.Base is not canonical. */
341	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
342	/** GDTR.Limit invalid. */
343	#define VMX_IGS_GDTR_LIMIT_INVALID 582
344	/** IDTR.Limit invalid. */
345	#define VMX_IGS_IDTR_LIMIT_INVALID 583
346	/** Longmode RIP is invalid. */
347	#define VMX_IGS_LONGMODE_RIP_INVALID 584
348	/** RFLAGS reserved bits not set to 0. */
349	#define VMX_IGS_RFLAGS_RESERVED 585
350	/** RFLAGS RA1 reserved bits not set to 1. */
351	#define VMX_IGS_RFLAGS_RESERVED1 586
352	/** RFLAGS.VM (V86 mode) invalid. */
353	#define VMX_IGS_RFLAGS_VM_INVALID 587
354	/** RFLAGS.IF invalid. */
355	#define VMX_IGS_RFLAGS_IF_INVALID 588
356	/** Activity state invalid. */
357	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
358	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
359	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
360	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
361	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
362	/** Activity state SIPI WAIT invalid. */
363	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
364	/** Interruptibility state reserved bits not set to 0. */
365	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
366	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
367	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
368	/** Interruptibility state block-by-STI invalid for EFLAGS. */
369	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
370	/** Interruptibility state invalid while trying to deliver external
371	* interrupt. */
372	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
373	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
374	* NMI. */
375	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
376	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
377	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
378	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
379	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
380	/** Interruptibility state block-by-STI (maybe) invalid when trying to
381	* deliver an NMI. */
382	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
383	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
384	* active. */
385	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
386	/** Pending debug exceptions reserved bits not set to 0. */
387	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
388	/** Longmode pending debug exceptions reserved bits not set to 0. */
389	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
390	/** Pending debug exceptions.BS bit is not set when it should be. */
391	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
392	/** Pending debug exceptions.BS bit is not clear when it should be. */
393	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
394	/** VMCS link pointer reserved bits not set to 0. */
395	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
396	/** TR cannot index into LDT, TI bit MBZ. */
397	#define VMX_IGS_TR_TI_INVALID 607
398	/** LDTR cannot index into LDT. TI bit MBZ. */
399	#define VMX_IGS_LDTR_TI_INVALID 608
400	/** TR.Base is not canonical. */
401	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
402	/** FS.Base is not canonical. */
403	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
404	/** GS.Base is not canonical. */
405	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
406	/** LDTR.Base is not canonical. */
407	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
408	/** TR is unusable. */
409	#define VMX_IGS_TR_ATTR_UNUSABLE 613
410	/** TR.Attr.S bit invalid. */
411	#define VMX_IGS_TR_ATTR_S_INVALID 614
412	/** TR is not present. */
413	#define VMX_IGS_TR_ATTR_P_INVALID 615
414	/** TR.Attr reserved bits not set to 0. */
415	#define VMX_IGS_TR_ATTR_RESERVED 616
416	/** TR.Attr.G bit invalid. */
417	#define VMX_IGS_TR_ATTR_G_INVALID 617
418	/** Longmode TR.Attr.Type invalid. */
419	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
420	/** TR.Attr.Type invalid. */
421	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
422	/** CS.Attr.S invalid. */
423	#define VMX_IGS_CS_ATTR_S_INVALID 620
424	/** CS.Attr.DPL invalid. */
425	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
426	/** PAE PDPTE reserved bits not set to 0. */
427	#define VMX_IGS_PAE_PDPTE_RESERVED 623
428	/** @} */
429
430	/** @name VMX VMCS-Read cache indices.
431	* @{
432	*/
433	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
434	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
435	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
436	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
437	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
438	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
439	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
440	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
441	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
442	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
443	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
444	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
445	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
446	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
447	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
448	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX 15
449	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
450	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 16
451	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
452	/** @} */
453
454	/** @name VMX EPT paging structures
455	* @{
456	*/
457
458	/**
459	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
460	*/
461	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
462
463	/**
464	* EPT Page Directory Pointer Entry. Bit view.
465	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
466	* this did cause trouble with one compiler/version).
467	*/
468	typedef struct EPTPML4EBITS
469	{
470	/** Present bit. */
471	uint64_t u1Present : 1;
472	/** Writable bit. */
473	uint64_t u1Write : 1;
474	/** Executable bit. */
475	uint64_t u1Execute : 1;
476	/** Reserved (must be 0). */
477	uint64_t u5Reserved : 5;
478	/** Available for software. */
479	uint64_t u4Available : 4;
480	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
481	uint64_t u40PhysAddr : 40;
482	/** Available for software. */
483	uint64_t u12Available : 12;
484	} EPTPML4EBITS;
485	AssertCompileSize(EPTPML4EBITS, 8);
486
487	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
488	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
489	/** The page shift to get the PML4 index. */
490	#define EPT_PML4_SHIFT X86_PML4_SHIFT
491	/** The PML4 index mask (apply to a shifted page address). */
492	#define EPT_PML4_MASK X86_PML4_MASK
493
494	/**
495	* EPT PML4E.
496	*/
497	typedef union EPTPML4E
498	{
499	/** Normal view. */
500	EPTPML4EBITS n;
501	/** Unsigned integer view. */
502	X86PGPAEUINT u;
503	/** 64 bit unsigned integer view. */
504	uint64_t au64[1];
505	/** 32 bit unsigned integer view. */
506	uint32_t au32[2];
507	} EPTPML4E;
508	AssertCompileSize(EPTPML4E, 8);
509	/** Pointer to a PML4 table entry. */
510	typedef EPTPML4E *PEPTPML4E;
511	/** Pointer to a const PML4 table entry. */
512	typedef const EPTPML4E *PCEPTPML4E;
513
514	/**
515	* EPT PML4 Table.
516	*/
517	typedef struct EPTPML4
518	{
519	EPTPML4E a[EPT_PG_ENTRIES];
520	} EPTPML4;
521	AssertCompileSize(EPTPML4, 0x1000);
522	/** Pointer to an EPT PML4 Table. */
523	typedef EPTPML4 *PEPTPML4;
524	/** Pointer to a const EPT PML4 Table. */
525	typedef const EPTPML4 *PCEPTPML4;
526
527	/**
528	* EPT Page Directory Pointer Entry. Bit view.
529	*/
530	typedef struct EPTPDPTEBITS
531	{
532	/** Present bit. */
533	uint64_t u1Present : 1;
534	/** Writable bit. */
535	uint64_t u1Write : 1;
536	/** Executable bit. */
537	uint64_t u1Execute : 1;
538	/** Reserved (must be 0). */
539	uint64_t u5Reserved : 5;
540	/** Available for software. */
541	uint64_t u4Available : 4;
542	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
543	uint64_t u40PhysAddr : 40;
544	/** Available for software. */
545	uint64_t u12Available : 12;
546	} EPTPDPTEBITS;
547	AssertCompileSize(EPTPDPTEBITS, 8);
548
549	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
550	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
551	/** The page shift to get the PDPT index. */
552	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
553	/** The PDPT index mask (apply to a shifted page address). */
554	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
555
556	/**
557	* EPT Page Directory Pointer.
558	*/
559	typedef union EPTPDPTE
560	{
561	/** Normal view. */
562	EPTPDPTEBITS n;
563	/** Unsigned integer view. */
564	X86PGPAEUINT u;
565	/** 64 bit unsigned integer view. */
566	uint64_t au64[1];
567	/** 32 bit unsigned integer view. */
568	uint32_t au32[2];
569	} EPTPDPTE;
570	AssertCompileSize(EPTPDPTE, 8);
571	/** Pointer to an EPT Page Directory Pointer Entry. */
572	typedef EPTPDPTE *PEPTPDPTE;
573	/** Pointer to a const EPT Page Directory Pointer Entry. */
574	typedef const EPTPDPTE *PCEPTPDPTE;
575
576	/**
577	* EPT Page Directory Pointer Table.
578	*/
579	typedef struct EPTPDPT
580	{
581	EPTPDPTE a[EPT_PG_ENTRIES];
582	} EPTPDPT;
583	AssertCompileSize(EPTPDPT, 0x1000);
584	/** Pointer to an EPT Page Directory Pointer Table. */
585	typedef EPTPDPT *PEPTPDPT;
586	/** Pointer to a const EPT Page Directory Pointer Table. */
587	typedef const EPTPDPT *PCEPTPDPT;
588
589	/**
590	* EPT Page Directory Table Entry. Bit view.
591	*/
592	typedef struct EPTPDEBITS
593	{
594	/** Present bit. */
595	uint64_t u1Present : 1;
596	/** Writable bit. */
597	uint64_t u1Write : 1;
598	/** Executable bit. */
599	uint64_t u1Execute : 1;
600	/** Reserved (must be 0). */
601	uint64_t u4Reserved : 4;
602	/** Big page (must be 0 here). */
603	uint64_t u1Size : 1;
604	/** Available for software. */
605	uint64_t u4Available : 4;
606	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
607	uint64_t u40PhysAddr : 40;
608	/** Available for software. */
609	uint64_t u12Available : 12;
610	} EPTPDEBITS;
611	AssertCompileSize(EPTPDEBITS, 8);
612
613	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
614	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
615	/** The page shift to get the PD index. */
616	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
617	/** The PD index mask (apply to a shifted page address). */
618	#define EPT_PD_MASK X86_PD_PAE_MASK
619
620	/**
621	* EPT 2MB Page Directory Table Entry. Bit view.
622	*/
623	typedef struct EPTPDE2MBITS
624	{
625	/** Present bit. */
626	uint64_t u1Present : 1;
627	/** Writable bit. */
628	uint64_t u1Write : 1;
629	/** Executable bit. */
630	uint64_t u1Execute : 1;
631	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
632	uint64_t u3EMT : 3;
633	/** Ignore PAT memory type */
634	uint64_t u1IgnorePAT : 1;
635	/** Big page (must be 1 here). */
636	uint64_t u1Size : 1;
637	/** Available for software. */
638	uint64_t u4Available : 4;
639	/** Reserved (must be 0). */
640	uint64_t u9Reserved : 9;
641	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
642	uint64_t u31PhysAddr : 31;
643	/** Available for software. */
644	uint64_t u12Available : 12;
645	} EPTPDE2MBITS;
646	AssertCompileSize(EPTPDE2MBITS, 8);
647
648	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
649	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
650
651	/**
652	* EPT Page Directory Table Entry.
653	*/
654	typedef union EPTPDE
655	{
656	/** Normal view. */
657	EPTPDEBITS n;
658	/** 2MB view (big). */
659	EPTPDE2MBITS b;
660	/** Unsigned integer view. */
661	X86PGPAEUINT u;
662	/** 64 bit unsigned integer view. */
663	uint64_t au64[1];
664	/** 32 bit unsigned integer view. */
665	uint32_t au32[2];
666	} EPTPDE;
667	AssertCompileSize(EPTPDE, 8);
668	/** Pointer to an EPT Page Directory Table Entry. */
669	typedef EPTPDE *PEPTPDE;
670	/** Pointer to a const EPT Page Directory Table Entry. */
671	typedef const EPTPDE *PCEPTPDE;
672
673	/**
674	* EPT Page Directory Table.
675	*/
676	typedef struct EPTPD
677	{
678	EPTPDE a[EPT_PG_ENTRIES];
679	} EPTPD;
680	AssertCompileSize(EPTPD, 0x1000);
681	/** Pointer to an EPT Page Directory Table. */
682	typedef EPTPD *PEPTPD;
683	/** Pointer to a const EPT Page Directory Table. */
684	typedef const EPTPD *PCEPTPD;
685
686	/**
687	* EPT Page Table Entry. Bit view.
688	*/
689	typedef struct EPTPTEBITS
690	{
691	/** 0 - Present bit.
692	* @remarks This is a convenience "misnomer". The bit actually indicates read access
693	* and the CPU will consider an entry with any of the first three bits set
694	* as present. Since all our valid entries will have this bit set, it can
695	* be used as a present indicator and allow some code sharing. */
696	uint64_t u1Present : 1;
697	/** 1 - Writable bit. */
698	uint64_t u1Write : 1;
699	/** 2 - Executable bit. */
700	uint64_t u1Execute : 1;
701	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
702	uint64_t u3EMT : 3;
703	/** 6 - Ignore PAT memory type */
704	uint64_t u1IgnorePAT : 1;
705	/** 11:7 - Available for software. */
706	uint64_t u5Available : 5;
707	/** 51:12 - Physical address of page. Restricted by maximum physical
708	* address width of the cpu. */
709	uint64_t u40PhysAddr : 40;
710	/** 63:52 - Available for software. */
711	uint64_t u12Available : 12;
712	} EPTPTEBITS;
713	AssertCompileSize(EPTPTEBITS, 8);
714
715	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
716	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
717	/** The page shift to get the EPT PTE index. */
718	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
719	/** The EPT PT index mask (apply to a shifted page address). */
720	#define EPT_PT_MASK X86_PT_PAE_MASK
721
722	/**
723	* EPT Page Table Entry.
724	*/
725	typedef union EPTPTE
726	{
727	/** Normal view. */
728	EPTPTEBITS n;
729	/** Unsigned integer view. */
730	X86PGPAEUINT u;
731	/** 64 bit unsigned integer view. */
732	uint64_t au64[1];
733	/** 32 bit unsigned integer view. */
734	uint32_t au32[2];
735	} EPTPTE;
736	AssertCompileSize(EPTPTE, 8);
737	/** Pointer to an EPT Page Directory Table Entry. */
738	typedef EPTPTE *PEPTPTE;
739	/** Pointer to a const EPT Page Directory Table Entry. */
740	typedef const EPTPTE *PCEPTPTE;
741
742	/**
743	* EPT Page Table.
744	*/
745	typedef struct EPTPT
746	{
747	EPTPTE a[EPT_PG_ENTRIES];
748	} EPTPT;
749	AssertCompileSize(EPTPT, 0x1000);
750	/** Pointer to an extended page table. */
751	typedef EPTPT *PEPTPT;
752	/** Pointer to a const extended table. */
753	typedef const EPTPT *PCEPTPT;
754
755	/** @} */
756
757	/**
758	* VMX VPID flush types.
759	* @note Valid enum members are in accordance to the VT-x spec.
760	*/
761	typedef enum
762	{
763	/** Invalidate a specific page. */
764	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
765	/** Invalidate one context (specific VPID). */
766	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
767	/** Invalidate all contexts (all VPIDs). */
768	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
769	/** Invalidate a single VPID context retaining global mappings. */
770	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
771	/** Unsupported by VirtualBox. */
772	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
773	/** Unsupported by CPU. */
774	VMXTLBFLUSHVPID_NONE = 0xbad1
775	} VMXTLBFLUSHVPID;
776	AssertCompileSize(VMXTLBFLUSHVPID, 4);
777
778	/**
779	* VMX EPT flush types.
780	* @note Valid enums values are in accordance to the VT-x spec.
781	*/
782	typedef enum
783	{
784	/** Invalidate one context (specific EPT). */
785	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
786	/* Invalidate all contexts (all EPTs) */
787	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
788	/** Unsupported by VirtualBox. */
789	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
790	/** Unsupported by CPU. */
791	VMXTLBFLUSHEPT_NONE = 0xbad1
792	} VMXTLBFLUSHEPT;
793	AssertCompileSize(VMXTLBFLUSHEPT, 4);
794
795	/**
796	* VMX Posted Interrupt Descriptor.
797	* In accordance to the VT-x spec.
798	*/
799	typedef struct VMXPOSTEDINTRDESC
800	{
801	uint32_t aVectorBitmap[8];
802	uint32_t fOutstandingNotification : 1;
803	uint32_t uReserved0 : 31;
804	uint8_t au8Reserved0[28];
805	} VMXPOSTEDINTRDESC;
806	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
807	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
808	/** Pointer to a posted interrupt descriptor. */
809	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
810	/** Pointer to a const posted interrupt descriptor. */
811	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
812
813	/**
814	* VMX VMCS revision identifier.
815	*/
816	typedef union
817	{
818	struct
819	{
820	/** Revision identifier. */
821	uint32_t u31RevisionId : 31;
822	/** Whether this is a shadow VMCS. */
823	uint32_t fIsShadowVmcs : 1;
824	} n;
825	/* The unsigned integer view. */
826	uint32_t u;
827	} VMXVMCSREVID;
828	AssertCompileSize(VMXVMCSREVID, 4);
829	/** Pointer to the VMXVMCSREVID union. */
830	typedef VMXVMCSREVID *PVMXVMCSREVID;
831	/** Pointer to a const VMXVVMCSREVID union. */
832	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
833
834	/**
835	* VMX VM-exit instruction information.
836	*/
837	typedef union
838	{
839	/** Plain unsigned int representation. */
840	uint32_t u;
841
842	/** INS and OUTS information. */
843	struct
844	{
845	uint32_t u7Reserved0 : 7;
846	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
847	uint32_t u3AddrSize : 3;
848	uint32_t u5Reserved1 : 5;
849	/** The segment register (X86_SREG_XXX). */
850	uint32_t iSegReg : 3;
851	uint32_t uReserved2 : 14;
852	} StrIo;
853
854	struct
855	{
856	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
857	uint32_t u2Scaling : 2;
858	uint32_t u5Undef0 : 5;
859	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
860	uint32_t u3AddrSize : 3;
861	/** Cleared to 0. */
862	uint32_t u1Cleared0 : 1;
863	uint32_t u4Undef0 : 4;
864	/** The segment register (X86_SREG_XXX). */
865	uint32_t iSegReg : 3;
866	/** The index register (X86_GREG_XXX). */
867	uint32_t iIdxReg : 4;
868	/** Set if index register is invalid. */
869	uint32_t fIdxRegInvalid : 1;
870	/** The base register (X86_GREG_XXX). */
871	uint32_t iBaseReg : 4;
872	/** Set if base register is invalid. */
873	uint32_t fBaseRegInvalid : 1;
874	/** Register 2 (X86_GREG_XXX). */
875	uint32_t iReg2 : 4;
876	} Inv;
877
878	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
879	struct
880	{
881	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
882	uint32_t u2Scaling : 2;
883	uint32_t u5Reserved0 : 5;
884	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
885	uint32_t u3AddrSize : 3;
886	/** Cleared to 0. */
887	uint32_t u1Cleared0 : 1;
888	uint32_t u4Reserved0 : 4;
889	/** The segment register (X86_SREG_XXX). */
890	uint32_t iSegReg : 3;
891	/** The index register (X86_GREG_XXX). */
892	uint32_t iIdxReg : 4;
893	/** Set if index register is invalid. */
894	uint32_t fIdxRegInvalid : 1;
895	/** The base register (X86_GREG_XXX). */
896	uint32_t iBaseReg : 4;
897	/** Set if base register is invalid. */
898	uint32_t fBaseRegInvalid : 1;
899	/** Register 2 (X86_GREG_XXX). */
900	uint32_t iReg2 : 4;
901	} VmxXsave;
902
903	/** LIDT, LGDT, SIDT, SGDT information. */
904	struct
905	{
906	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
907	uint32_t u2Scaling : 2;
908	uint32_t u5Undef0 : 5;
909	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
910	uint32_t u3AddrSize : 3;
911	/** Always cleared to 0. */
912	uint32_t u1Cleared0 : 1;
913	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
914	uint32_t uOperandSize : 1;
915	uint32_t u3Undef0 : 3;
916	/** The segment register (X86_SREG_XXX). */
917	uint32_t iSegReg : 3;
918	/** The index register (X86_GREG_XXX). */
919	uint32_t iIdxReg : 4;
920	/** Set if index register is invalid. */
921	uint32_t fIdxRegInvalid : 1;
922	/** The base register (X86_GREG_XXX). */
923	uint32_t iBaseReg : 4;
924	/** Set if base register is invalid. */
925	uint32_t fBaseRegInvalid : 1;
926	/** Instruction identity (VMX_INSTR_ID_XXX). */
927	uint32_t u2InstrId : 2;
928	uint32_t u2Undef0 : 2;
929	} GdtIdt;
930
931	/** LLDT, LTR, SLDT, STR information. */
932	struct
933	{
934	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
935	uint32_t u2Scaling : 2;
936	uint32_t u1Undef0 : 1;
937	/** Register 1 (X86_GREG_XXX). */
938	uint32_t iReg1 : 4;
939	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
940	uint32_t u3AddrSize : 3;
941	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
942	uint32_t fIsRegOperand : 1;
943	uint32_t u4Undef0 : 4;
944	/** The segment register (X86_SREG_XXX). */
945	uint32_t iSegReg : 3;
946	/** The index register (X86_GREG_XXX). */
947	uint32_t iIdxReg : 4;
948	/** Set if index register is invalid. */
949	uint32_t fIdxRegInvalid : 1;
950	/** The base register (X86_GREG_XXX). */
951	uint32_t iBaseReg : 4;
952	/** Set if base register is invalid. */
953	uint32_t fBaseRegInvalid : 1;
954	/** Instruction identity (VMX_INSTR_ID_XXX). */
955	uint32_t u2InstrId : 2;
956	uint32_t u2Undef0 : 2;
957	} LdtTr;
958
959	/** RDRAND, RDSEED information. */
960	struct
961	{
962	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
963	uint32_t u2Undef0 : 2;
964	/** Destination register (X86_GREG_XXX). */
965	uint32_t iReg1 : 4;
966	uint32_t u4Undef0 : 4;
967	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
968	uint32_t u2OperandSize : 2;
969	uint32_t u19Def0 : 20;
970	} RdrandRdseed;
971
972	struct
973	{
974	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
975	uint32_t u2Scaling : 2;
976	uint32_t u1Undef0 : 1;
977	/** Register 1 (X86_GREG_XXX). */
978	uint32_t iReg1 : 4;
979	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
980	uint32_t u3AddrSize : 3;
981	/** Memory or register operand. */
982	uint32_t fIsRegOperand : 1;
983	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
984	uint32_t u4Undef0 : 4;
985	/** The segment register (X86_SREG_XXX). */
986	uint32_t iSegReg : 3;
987	/** The index register (X86_GREG_XXX). */
988	uint32_t iIdxReg : 4;
989	/** Set if index register is invalid. */
990	uint32_t fIdxRegInvalid : 1;
991	/** The base register (X86_GREG_XXX). */
992	uint32_t iBaseReg : 4;
993	/** Set if base register is invalid. */
994	uint32_t fBaseRegInvalid : 1;
995	/** Register 2 (X86_GREG_XXX). */
996	uint32_t iReg2 : 4;
997	} VmreadVmwrite;
998
999	/** This is a combination field of all instruction information. Note! Not all field
1000	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1001	* specialized fields are overwritten by their generic counterparts (e.g. no
1002	* instruction identity field). */
1003	struct
1004	{
1005	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1006	uint32_t u2Scaling : 2;
1007	uint32_t u1Undef0 : 1;
1008	/** Register 1 (X86_GREG_XXX). */
1009	uint32_t iReg1 : 4;
1010	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1011	uint32_t u3AddrSize : 3;
1012	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1013	uint32_t fIsRegOperand : 1;
1014	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1015	uint32_t uOperandSize : 2;
1016	uint32_t u2Undef0 : 2;
1017	/** The segment register (X86_SREG_XXX). */
1018	uint32_t iSegReg : 3;
1019	/** The index register (X86_GREG_XXX). */
1020	uint32_t iIdxReg : 4;
1021	/** Set if index register is invalid. */
1022	uint32_t fIdxRegInvalid : 1;
1023	/** The base register (X86_GREG_XXX). */
1024	uint32_t iBaseReg : 4;
1025	/** Set if base register is invalid. */
1026	uint32_t fBaseRegInvalid : 1;
1027	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1028	uint32_t iReg2 : 4;
1029	} All;
1030	} VMXEXITINSTRINFO;
1031	AssertCompileSize(VMXEXITINSTRINFO, 4);
1032	/** Pointer to a VMX VM-exit instruction info. struct. */
1033	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1034	/** Pointer to a const VMX VM-exit instruction info. struct. */
1035	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1036
1037
1038	/** @name VM-entry failure reported in VM-exit qualification.
1039	* See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1040	*/
1041	/** No errors during VM-entry. */
1042	#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1043	/** Not used. */
1044	#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1045	/** Error while loading PDPTEs. */
1046	#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1047	/** NMI injection when blocking-by-STI is set. */
1048	#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1049	/** Invalid VMCS link pointer. */
1050	#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1051	/** @} */
1052
1053	/**
1054	* VMX MSR-bitmap read permissions.
1055	*/
1056	typedef enum VMXMSREXITREAD
1057	{
1058	/** Reading this MSR causes a VM-exit. */
1059	VMXMSREXIT_INTERCEPT_READ = 1,
1060	/** Reading this MSR doesn't cause a VM-exit. */
1061	VMXMSREXIT_PASSTHRU_READ
1062	} VMXMSREXITREAD;
1063	/** Pointer to MSR-bitmap read permissions. */
1064	typedef VMXMSREXITREAD* PVMXMSREXITREAD;
1065
1066	/**
1067	* VMX MSR-bitmap write permissions.
1068	*/
1069	typedef enum VMXMSREXITWRITE
1070	{
1071	/** Writing to this MSR causes a VM-exit. */
1072	VMXMSREXIT_INTERCEPT_WRITE = 3,
1073	/** Writing to this MSR does not cause a VM-exit. */
1074	VMXMSREXIT_PASSTHRU_WRITE
1075	} VMXMSREXITWRITE;
1076	/** Pointer to MSR-bitmap write permissions. */
1077	typedef VMXMSREXITWRITE* PVMXMSREXITWRITE;
1078
1079	/**
1080	* VMX MSR autoload/store element.
1081	* In accordance to the VT-x spec.
1082	*/
1083	typedef struct VMXAUTOMSR
1084	{
1085	/** The MSR Id. */
1086	uint32_t u32Msr;
1087	/** Reserved (MBZ). */
1088	uint32_t u32Reserved;
1089	/** The MSR value. */
1090	uint64_t u64Value;
1091	} VMXAUTOMSR;
1092	AssertCompileSize(VMXAUTOMSR, 16);
1093	/** Pointer to an MSR load/store element. */
1094	typedef VMXAUTOMSR *PVMXAUTOMSR;
1095	/** Pointer to a const MSR load/store element. */
1096	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1097
1098	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1099	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1100
1101	/**
1102	* VMX tagged-TLB flush types.
1103	*/
1104	typedef enum
1105	{
1106	VMXTLBFLUSHTYPE_EPT,
1107	VMXTLBFLUSHTYPE_VPID,
1108	VMXTLBFLUSHTYPE_EPT_VPID,
1109	VMXTLBFLUSHTYPE_NONE
1110	} VMXTLBFLUSHTYPE;
1111	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1112	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1113	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1114	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1115
1116	/**
1117	* VMX controls MSR.
1118	*/
1119	typedef union
1120	{
1121	struct
1122	{
1123	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1124	uint32_t allowed0;
1125	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1126	* controls. */
1127	uint32_t allowed1;
1128	} n;
1129	uint64_t u;
1130	} VMXCTLSMSR;
1131	AssertCompileSize(VMXCTLSMSR, 8);
1132	/** Pointer to a VMXCTLSMSR union. */
1133	typedef VMXCTLSMSR *PVMXCTLSMSR;
1134	/** Pointer to a const VMXCTLSMSR union. */
1135	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1136
1137	/**
1138	* VMX MSRs.
1139	* @remarks Although treated as a plain-old data (POD) in several places, please
1140	* update HMVmxGetHostMsr() if new MSRs are added here.
1141	*/
1142	typedef struct VMXMSRS
1143	{
1144	uint64_t u64FeatCtrl;
1145	uint64_t u64Basic;
1146	VMXCTLSMSR PinCtls;
1147	VMXCTLSMSR ProcCtls;
1148	VMXCTLSMSR ProcCtls2;
1149	VMXCTLSMSR ExitCtls;
1150	VMXCTLSMSR EntryCtls;
1151	VMXCTLSMSR TruePinCtls;
1152	VMXCTLSMSR TrueProcCtls;
1153	VMXCTLSMSR TrueEntryCtls;
1154	VMXCTLSMSR TrueExitCtls;
1155	uint64_t u64Misc;
1156	uint64_t u64Cr0Fixed0;
1157	uint64_t u64Cr0Fixed1;
1158	uint64_t u64Cr4Fixed0;
1159	uint64_t u64Cr4Fixed1;
1160	uint64_t u64VmcsEnum;
1161	uint64_t u64VmFunc;
1162	uint64_t u64EptVpidCaps;
1163	uint64_t a_u64Reserved[5];
1164	} VMXMSRS;
1165	AssertCompileSizeAlignment(VMXMSRS, 8);
1166	AssertCompileSize(VMXMSRS, 192);
1167	/** Pointer to a VMXMSRS struct. */
1168	typedef VMXMSRS *PVMXMSRS;
1169	/** Pointer to a const VMXMSRS struct. */
1170	typedef const VMXMSRS *PCVMXMSRS;
1171
1172
1173	/** @name VMX Basic Exit Reasons.
1174	* @{
1175	*/
1176	/** -1 Invalid exit code */
1177	#define VMX_EXIT_INVALID (-1)
1178	/** 0 Exception or non-maskable interrupt (NMI). */
1179	#define VMX_EXIT_XCPT_OR_NMI 0
1180	/** 1 External interrupt. */
1181	#define VMX_EXIT_EXT_INT 1
1182	/** 2 Triple fault. */
1183	#define VMX_EXIT_TRIPLE_FAULT 2
1184	/** 3 INIT signal. */
1185	#define VMX_EXIT_INIT_SIGNAL 3
1186	/** 4 Start-up IPI (SIPI). */
1187	#define VMX_EXIT_SIPI 4
1188	/** 5 I/O system-management interrupt (SMI). */
1189	#define VMX_EXIT_IO_SMI 5
1190	/** 6 Other SMI. */
1191	#define VMX_EXIT_SMI 6
1192	/** 7 Interrupt window exiting. */
1193	#define VMX_EXIT_INT_WINDOW 7
1194	/** 8 NMI window exiting. */
1195	#define VMX_EXIT_NMI_WINDOW 8
1196	/** 9 Task switch. */
1197	#define VMX_EXIT_TASK_SWITCH 9
1198	/** 10 Guest software attempted to execute CPUID. */
1199	#define VMX_EXIT_CPUID 10
1200	/** 11 Guest software attempted to execute GETSEC. */
1201	#define VMX_EXIT_GETSEC 11
1202	/** 12 Guest software attempted to execute HLT. */
1203	#define VMX_EXIT_HLT 12
1204	/** 13 Guest software attempted to execute INVD. */
1205	#define VMX_EXIT_INVD 13
1206	/** 14 Guest software attempted to execute INVLPG. */
1207	#define VMX_EXIT_INVLPG 14
1208	/** 15 Guest software attempted to execute RDPMC. */
1209	#define VMX_EXIT_RDPMC 15
1210	/** 16 Guest software attempted to execute RDTSC. */
1211	#define VMX_EXIT_RDTSC 16
1212	/** 17 Guest software attempted to execute RSM in SMM. */
1213	#define VMX_EXIT_RSM 17
1214	/** 18 Guest software executed VMCALL. */
1215	#define VMX_EXIT_VMCALL 18
1216	/** 19 Guest software executed VMCLEAR. */
1217	#define VMX_EXIT_VMCLEAR 19
1218	/** 20 Guest software executed VMLAUNCH. */
1219	#define VMX_EXIT_VMLAUNCH 20
1220	/** 21 Guest software executed VMPTRLD. */
1221	#define VMX_EXIT_VMPTRLD 21
1222	/** 22 Guest software executed VMPTRST. */
1223	#define VMX_EXIT_VMPTRST 22
1224	/** 23 Guest software executed VMREAD. */
1225	#define VMX_EXIT_VMREAD 23
1226	/** 24 Guest software executed VMRESUME. */
1227	#define VMX_EXIT_VMRESUME 24
1228	/** 25 Guest software executed VMWRITE. */
1229	#define VMX_EXIT_VMWRITE 25
1230	/** 26 Guest software executed VMXOFF. */
1231	#define VMX_EXIT_VMXOFF 26
1232	/** 27 Guest software executed VMXON. */
1233	#define VMX_EXIT_VMXON 27
1234	/** 28 Control-register accesses. */
1235	#define VMX_EXIT_MOV_CRX 28
1236	/** 29 Debug-register accesses. */
1237	#define VMX_EXIT_MOV_DRX 29
1238	/** 30 I/O instruction. */
1239	#define VMX_EXIT_IO_INSTR 30
1240	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
1241	#define VMX_EXIT_RDMSR 31
1242	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
1243	#define VMX_EXIT_WRMSR 32
1244	/** 33 VM-entry failure due to invalid guest state. */
1245	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1246	/** 34 VM-entry failure due to MSR loading. */
1247	#define VMX_EXIT_ERR_MSR_LOAD 34
1248	/** 36 Guest software executed MWAIT. */
1249	#define VMX_EXIT_MWAIT 36
1250	/** 37 VM-exit due to monitor trap flag. */
1251	#define VMX_EXIT_MTF 37
1252	/** 39 Guest software attempted to execute MONITOR. */
1253	#define VMX_EXIT_MONITOR 39
1254	/** 40 Guest software attempted to execute PAUSE. */
1255	#define VMX_EXIT_PAUSE 40
1256	/** 41 VM-entry failure due to machine-check. */
1257	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1258	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
1259	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1260	/** 44 APIC access. Guest software attempted to access memory at a physical
1261	* address on the APIC-access page. */
1262	#define VMX_EXIT_APIC_ACCESS 44
1263	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
1264	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
1265	#define VMX_EXIT_VIRTUALIZED_EOI 45
1266	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
1267	* SGDT, or SIDT. */
1268	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1269	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
1270	* SLDT, or STR. */
1271	#define VMX_EXIT_LDTR_TR_ACCESS 47
1272	/** 48 EPT violation. An attempt to access memory with a guest-physical address
1273	* was disallowed by the configuration of the EPT paging structures. */
1274	#define VMX_EXIT_EPT_VIOLATION 48
1275	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1276	* address encountered a misconfigured EPT paging-structure entry. */
1277	#define VMX_EXIT_EPT_MISCONFIG 49
1278	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1279	#define VMX_EXIT_INVEPT 50
1280	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1281	#define VMX_EXIT_RDTSCP 51
1282	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1283	#define VMX_EXIT_PREEMPT_TIMER 52
1284	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1285	#define VMX_EXIT_INVVPID 53
1286	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1287	#define VMX_EXIT_WBINVD 54
1288	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1289	#define VMX_EXIT_XSETBV 55
1290	/** 56 APIC write. Guest completed write to virtual-APIC. */
1291	#define VMX_EXIT_APIC_WRITE 56
1292	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1293	#define VMX_EXIT_RDRAND 57
1294	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1295	#define VMX_EXIT_INVPCID 58
1296	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1297	#define VMX_EXIT_VMFUNC 59
1298	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1299	#define VMX_EXIT_ENCLS 60
1300	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1301	* enabled. */
1302	#define VMX_EXIT_RDSEED 61
1303	/** 62 - Page-modification log full. */
1304	#define VMX_EXIT_PML_FULL 62
1305	/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
1306	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1307	#define VMX_EXIT_XSAVES 63
1308	/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
1309	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1310	#define VMX_EXIT_XRSTORS 64
1311	/** The maximum exit value (inclusive). */
1312	#define VMX_EXIT_MAX (VMX_EXIT_XRSTORS)
1313	/** @} */
1314
1315
1316	/** @name VM Instruction Errors.
1317	* See Intel spec. "30.4 VM Instruction Error Numbers"
1318	* @{
1319	*/
1320	typedef enum
1321	{
1322	/** VMCALL executed in VMX root operation. */
1323	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1324	/** VMCLEAR with invalid physical address. */
1325	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1326	/** VMCLEAR with VMXON pointer. */
1327	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1328	/** VMLAUNCH with non-clear VMCS. */
1329	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1330	/** VMRESUME with non-launched VMCS. */
1331	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1332	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1333	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1334	/** VM-entry with invalid control field(s). */
1335	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1336	/** VM-entry with invalid host-state field(s). */
1337	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1338	/** VMPTRLD with invalid physical address. */
1339	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1340	/** VMPTRLD with VMXON pointer. */
1341	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1342	/** VMPTRLD with incorrect VMCS revision identifier. */
1343	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1344	/** VMREAD from unsupported VMCS component. */
1345	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1346	/** VMWRITE to unsupported VMCS component. */
1347	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1348	/** VMWRITE to read-only VMCS component. */
1349	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1350	/** VMXON executed in VMX root operation. */
1351	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1352	/** VM-entry with invalid executive-VMCS pointer. */
1353	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1354	/** VM-entry with non-launched executive VMCS. */
1355	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1356	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1357	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1358	/** VMCALL with non-clear VMCS. */
1359	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1360	/** VMCALL with invalid VM-exit control fields. */
1361	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1362	/** VMCALL with incorrect MSEG revision identifier. */
1363	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1364	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1365	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1366	/** VMCALL with invalid SMM-monitor features. */
1367	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1368	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1369	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1370	/** VM-entry with events blocked by MOV SS. */
1371	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1372	/** Invalid operand to INVEPT/INVVPID. */
1373	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1374	} VMXINSTRERR;
1375	/** @} */
1376
1377
1378	/** @name VMX abort reasons.
1379	* See Intel spec. "27.7 VMX Aborts".
1380	* Update HMVmxGetAbortDesc() if new reasons are added.
1381	* @{
1382	*/
1383	typedef enum
1384	{
1385	/** None - don't use this / uninitialized value. */
1386	VMXABORT_NONE = 0,
1387	/** VMX abort caused during saving of guest MSRs. */
1388	VMXABORT_SAVE_GUEST_MSRS = 1,
1389	/** VMX abort caused during host PDPTE checks. */
1390	VMXBOART_HOST_PDPTE = 2,
1391	/** VMX abort caused due to current VMCS being corrupted. */
1392	VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1393	/** VMX abort caused during loading of host MSRs. */
1394	VMXABORT_LOAD_HOST_MSR = 4,
1395	/** VMX abort caused due to a machine-check exception during VM-exit. */
1396	VMXABORT_MACHINE_CHECK_XCPT = 5,
1397	/** VMX abort caused due to invalid return from long mode. */
1398	VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1399	/* Type size hack. */
1400	VMXABORT_32BIT_HACK = 0x7fffffff
1401	} VMXABORT;
1402	AssertCompileSize(VMXABORT, 4);
1403	/** @} */
1404
1405
1406	/** @name VMX MSR - Basic VMX information.
1407	* @{
1408	*/
1409	/** VMCS (and related regions) memory type - Uncacheable. */
1410	#define VMX_BASIC_MEM_TYPE_UC 0
1411	/** VMCS (and related regions) memory type - Write back. */
1412	#define VMX_BASIC_MEM_TYPE_WB 6
1413
1414	/** Bit fields for MSR_IA32_VMX_BASIC. */
1415	/** VMCS revision identifier used by the processor. */
1416	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1417	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1418	/** Bit 31 is reserved and RAZ. */
1419	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1420	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1421	/** VMCS size in bytes. */
1422	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1423	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1424	/** Bits 45:47 are reserved. */
1425	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1426	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1427	/** Width of physical addresses used for the VMCS and associated memory regions
1428	* (always 0 on CPUs that support Intel 64 architecture). */
1429	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1430	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1431	/** Dual-monitor treatment of SMI and SMM supported. */
1432	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1433	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1434	/** Memory type that must be used for the VMCS and associated memory regions. */
1435	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1436	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1437	/** VM-exit instruction information for INS/OUTS. */
1438	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1439	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1440	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1441	* bits in VMX control MSRs. */
1442	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1443	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1444	/** Bits 56:63 are reserved and RAZ. */
1445	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 56
1446	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xff00000000000000)
1447	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1448	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1449	VMCS_INS_OUTS, TRUE_CTLS, RSVD_56_63));
1450	/** @} */
1451
1452
1453	/** @name VMX MSR - Miscellaneous data.
1454	* Bit fields for MSR_IA32_VMX_MISC.
1455	* @{
1456	*/
1457	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1458	#define VMX_MISC_EXIT_SAVE_EFER_LMA RT_BIT(5)
1459	/** Whether Intel PT is supported in VMX operation. */
1460	#define VMX_MISC_INTEL_PT RT_BIT(14)
1461	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1462	* VMWRITE cannot modify read-only VM-exit information fields. */
1463	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1464	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1465	* instructions. */
1466	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1467	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1468	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1469	/** Maximum CR3-target count supported by the CPU. */
1470	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1471	/** Relationship between the preemption timer and tsc. */
1472	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1473	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1474	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1475	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT 5
1476	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1477	/** Activity states supported by the implementation. */
1478	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1479	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1480	/** Bits 9:13 is reserved and RAZ. */
1481	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1482	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1483	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1484	#define VMX_BF_MISC_INTEL_PT_SHIFT 14
1485	#define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000)
1486	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1487	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1488	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1489	/** Number of CR3 target values supported by the processor. (0-256) */
1490	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1491	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1492	/** Maximum number of MSRs in the VMCS. */
1493	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1494	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1495	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1496	* SMIs. */
1497	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1498	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1499	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1500	* VMWRITE cannot modify read-only VM-exit information fields. */
1501	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1502	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1503	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1504	* instructions. */
1505	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1506	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1507	/** Bit 31 is reserved and RAZ. */
1508	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1509	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1510	/** 32-bit MSEG revision ID used by the processor. */
1511	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1512	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1513	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1514	(PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
1515	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1516	/** @} */
1517
1518	/** @name VMX MSR - VMCS enumeration.
1519	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1520	* @{
1521	*/
1522	/** Bit 0 is reserved and RAZ. */
1523	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1524	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1525	/** Highest index value used in VMCS field encoding. */
1526	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1527	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1528	/** Bit 10:63 is reserved and RAZ. */
1529	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1530	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1531	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1532	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1533	/** @} */
1534
1535
1536	/** @name VMX MSR - VM Functions.
1537	* Bit fields for MSR_IA32_VMX_VMFUNC.
1538	* @{
1539	*/
1540	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1541	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1542	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1543	/** Bits 1:63 are reserved and RAZ. */
1544	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1545	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1546	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1547	(EPTP_SWITCHING, RSVD_1_63));
1548	/** @} */
1549
1550
1551	/** @name VMX MSR - EPT/VPID capabilities.
1552	* @{
1553	*/
1554	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1555	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1556	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1557	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1558	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1559	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1560	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1561	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1562	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1563	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1564	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1565	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1566	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1567	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1568	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1569	/** @} */
1570
1571
1572	/** @name Extended Page Table Pointer (EPTP)
1573	* @{
1574	*/
1575	/** Uncachable EPT paging structure memory type. */
1576	#define VMX_EPT_MEMTYPE_UC 0
1577	/** Write-back EPT paging structure memory type. */
1578	#define VMX_EPT_MEMTYPE_WB 6
1579	/** Shift value to get the EPT page walk length (bits 5-3) */
1580	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1581	/** Mask value to get the EPT page walk length (bits 5-3) */
1582	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1583	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1584	* length) */
1585	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1586	/** @} */
1587
1588
1589	/** @name VMCS field encoding: 16-bit guest fields.
1590	* @{
1591	*/
1592	#define VMX_VMCS16_VPID 0x0000
1593	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1594	#define VMX_VMCS16_EPTP_INDEX 0x0004
1595	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1596	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1597	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1598	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1599	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1600	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1601	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1602	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1603	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1604	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1605	/** @} */
1606
1607
1608	/** @name VMCS field encoding: 16-bits host fields.
1609	* @{
1610	*/
1611	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1612	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1613	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1614	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1615	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1616	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1617	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1618	/** @} */
1619
1620
1621	/** @name VMCS field encoding: 64-bit control fields.
1622	* @{
1623	*/
1624	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1625	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1626	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1627	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1628	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1629	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1630	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1631	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1632	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1633	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1634	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1635	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1636	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1637	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1638	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1639	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1640	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1641	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1642	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1643	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1644	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1645	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1646	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1647	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1648	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1649	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1650	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1651	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1652	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1653	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1654	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1655	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1656	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1657	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1658	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1659	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1660	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1661	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1662	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1663	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1664	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1665	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1666	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202a
1667	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202b
1668	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1669	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1670	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1671	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1672	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1673	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1674	/** @} */
1675
1676
1677	/** @name VMCS field encoding: 64-bit read-only data fields.
1678	* @{
1679	*/
1680	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1681	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1682	/** @} */
1683
1684
1685	/** @name VMCS field encoding: 64-bit guest fields.
1686	* @{
1687	*/
1688	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1689	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1690	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1691	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1692	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1693	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1694	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1695	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1696	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1697	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1698	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1699	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1700	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1701	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1702	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1703	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1704	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1705	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1706	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1707	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1708	/** @} */
1709
1710
1711	/** @name VMCS field encoding: 64-bit host fields.
1712	* @{
1713	*/
1714	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1715	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1716	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1717	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1718	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1719	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1720	/** @} */
1721
1722
1723	/** @name VMCS field encoding: 32-bit control fields.
1724	* @{
1725	*/
1726	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1727	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1728	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1729	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1730	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1731	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1732	#define VMX_VMCS32_CTRL_EXIT 0x400c
1733	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1734	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1735	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1736	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1737	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1738	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1739	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1740	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1741	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1742	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1743	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1744	/** @} */
1745
1746
1747	/** @name VMCS field encoding: 32-bits read-only fields.
1748	* @{
1749	*/
1750	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1751	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1752	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1753	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1754	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1755	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1756	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1757	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1758	/** @} */
1759
1760
1761	/** @name VMCS field encoding: 32-bit guest-state fields.
1762	* @{
1763	*/
1764	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1765	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1766	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1767	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1768	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1769	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1770	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1771	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1772	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1773	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1774	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1775	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1776	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1777	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1778	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1779	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
1780	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1781	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1782	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
1783	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1784	#define VMX_VMCS32_GUEST_SMBASE 0x4828
1785	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
1786	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
1787	/** @} */
1788
1789
1790	/** @name VMCS field encoding: 32-bit host-state fields.
1791	* @{
1792	*/
1793	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1794	/** @} */
1795
1796
1797	/** @name Natural width control fields.
1798	* @{
1799	*/
1800	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1801	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1802	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1803	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1804	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1805	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
1806	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
1807	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
1808	/** @} */
1809
1810
1811	/** @name Natural width read-only data fields.
1812	* @{
1813	*/
1814	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1815	#define VMX_VMCS_RO_IO_RCX 0x6402
1816	#define VMX_VMCS_RO_IO_RSX 0x6404
1817	#define VMX_VMCS_RO_IO_RDI 0x6406
1818	#define VMX_VMCS_RO_IO_RIP 0x6408
1819	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR 0x640a
1820	/** @} */
1821
1822
1823	/** @name VMCS field encoding: Natural width guest-state fields.
1824	* @{
1825	*/
1826	#define VMX_VMCS_GUEST_CR0 0x6800
1827	#define VMX_VMCS_GUEST_CR3 0x6802
1828	#define VMX_VMCS_GUEST_CR4 0x6804
1829	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1830	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1831	#define VMX_VMCS_GUEST_SS_BASE 0x680a
1832	#define VMX_VMCS_GUEST_DS_BASE 0x680c
1833	#define VMX_VMCS_GUEST_FS_BASE 0x680e
1834	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1835	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1836	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1837	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1838	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1839	#define VMX_VMCS_GUEST_DR7 0x681a
1840	#define VMX_VMCS_GUEST_RSP 0x681c
1841	#define VMX_VMCS_GUEST_RIP 0x681e
1842	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1843	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
1844	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
1845	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
1846	/** @} */
1847
1848
1849	/** @name VMCS field encoding: Natural width host-state fields.
1850	* @{
1851	*/
1852	#define VMX_VMCS_HOST_CR0 0x6c00
1853	#define VMX_VMCS_HOST_CR3 0x6c02
1854	#define VMX_VMCS_HOST_CR4 0x6c04
1855	#define VMX_VMCS_HOST_FS_BASE 0x6c06
1856	#define VMX_VMCS_HOST_GS_BASE 0x6c08
1857	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
1858	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
1859	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
1860	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
1861	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
1862	#define VMX_VMCS_HOST_RSP 0x6c14
1863	#define VMX_VMCS_HOST_RIP 0x6c16
1864	/** @} */
1865
1866
1867	/** @name VMCS field encoding: Access.
1868	* @{ */
1869	typedef enum
1870	{
1871	VMXVMCSFIELDACCESS_FULL = 0,
1872	VMXVMCSFIELDACCESS_HIGH
1873	} VMXVMCSFIELDACCESS;
1874	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
1875	/** @} */
1876
1877
1878	/** @name VMCS field encoding: Type.
1879	* @{ */
1880	typedef enum
1881	{
1882	VMXVMCSFIELDTYPE_CONTROL = 0,
1883	VMXVMCSFIELDTYPE_VMEXIT_INFO,
1884	VMXVMCSFIELDTYPE_GUEST_STATE,
1885	VMXVMCSFIELDTYPE_HOST_STATE
1886	} VMXVMCSFIELDTYPE;
1887	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
1888	/** @} */
1889
1890
1891	/** @name VMCS field encoding: Width.
1892	* @{ */
1893	typedef enum
1894	{
1895	VMXVMCSFIELDWIDTH_16BIT = 0,
1896	VMXVMCSFIELDWIDTH_64BIT,
1897	VMXVMCSFIELDWIDTH_32BIT,
1898	VMXVMCSFIELDWIDTH_NATURAL
1899	} VMXVMCSFIELDWIDTH;
1900	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
1901	/** @} */
1902
1903	/** @name VM-entry instruction length.
1904	* @{ */
1905	/** The maximum valid value for VM-entry instruction length while injecting a
1906	* software interrupt, software exception or privileged software exception. */
1907	#define VMX_ENTRY_INSTR_LEN_MAX 15
1908	/** @} */
1909
1910
1911	/** @name VM-entry register masks.
1912	* @{ */
1913	/** CR0 bits ignored on VM-entry (ET, NW, CD and reserved bits bits 6:15, bit 17,
1914	* bits 19:28). */
1915	#define VMX_ENTRY_CR0_IGNORE_MASK UINT64_C(0x7ffaffc0)
1916	/** DR7 bits set here are always cleared on VM-entry (bit 12, bits 14:15). */
1917	#define VMX_ENTRY_DR7_MBZ_MASK UINT64_C(0xd000)
1918	/** DR7 bits set here are always set on VM-entry (bit 10). */
1919	#define VMX_ENTRY_DR7_MB1_MASK UINT64_C(0x400)
1920	/** @} */
1921
1922
1923	/** @name Pin-based VM-execution controls.
1924	* @{
1925	*/
1926	/** External interrupt exiting. */
1927	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
1928	/** NMI exiting. */
1929	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
1930	/** Virtual NMIs. */
1931	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
1932	/** Activate VMX preemption timer. */
1933	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
1934	/** Process interrupts with the posted-interrupt notification vector. */
1935	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
1936	/** Default1 class when true capability MSRs are not supported. */
1937	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
1938
1939	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
1940	* controls field in the VMCS. */
1941	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
1942	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
1943	#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT 1
1944	#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK UINT32_C(0x00000006)
1945	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
1946	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
1947	#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT 4
1948	#define VMX_BF_PIN_CTLS_UNDEF_4_MASK UINT32_C(0x00000010)
1949	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
1950	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
1951	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
1952	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
1953	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
1954	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
1955	#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT 8
1956	#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK UINT32_C(0xffffff00)
1957	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
1958	(EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
1959	/** @} */
1960
1961
1962	/** @name Processor-based VM-execution controls.
1963	* @{
1964	*/
1965	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1966	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
1967	/** Use timestamp counter offset. */
1968	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
1969	/** VM-exit when executing the HLT instruction. */
1970	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
1971	/** VM-exit when executing the INVLPG instruction. */
1972	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
1973	/** VM-exit when executing the MWAIT instruction. */
1974	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
1975	/** VM-exit when executing the RDPMC instruction. */
1976	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
1977	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1978	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
1979	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
1980	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1981	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
1982	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
1983	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1984	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
1985	/** VM-exit on CR8 loads. */
1986	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
1987	/** VM-exit on CR8 stores. */
1988	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
1989	/** Use TPR shadow. */
1990	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
1991	/** VM-exit when virtual NMI blocking is disabled. */
1992	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
1993	/** VM-exit when executing a MOV DRx instruction. */
1994	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
1995	/** VM-exit when executing IO instructions. */
1996	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
1997	/** Use IO bitmaps. */
1998	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
1999	/** Monitor trap flag. */
2000	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
2001	/** Use MSR bitmaps. */
2002	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
2003	/** VM-exit when executing the MONITOR instruction. */
2004	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
2005	/** VM-exit when executing the PAUSE instruction. */
2006	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
2007	/** Whether the secondary processor based VM-execution controls are used. */
2008	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2009	/** Default1 class when true-capability MSRs are not supported. */
2010	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
2011
2012	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
2013	* controls field in the VMCS. */
2014	#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT 0
2015	#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2016	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
2017	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
2018	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
2019	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
2020	#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT 4
2021	#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK UINT32_C(0x00000070)
2022	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
2023	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
2024	#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT 8
2025	#define VMX_BF_PROC_CTLS_UNDEF_8_MASK UINT32_C(0x00000100)
2026	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2027	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2028	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2029	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2030	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2031	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2032	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2033	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2034	#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT 13
2035	#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2036	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2037	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2038	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2039	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2040	#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT 17
2041	#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK UINT32_C(0x00060000)
2042	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2043	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2044	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2045	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2046	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2047	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2048	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2049	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2050	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2051	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2052	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2053	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2054	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2055	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2056	#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT 26
2057	#define VMX_BF_PROC_CTLS_UNDEF_26_MASK UINT32_C(0x4000000)
2058	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2059	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2060	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2061	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2062	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2063	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2064	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2065	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2066	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2067	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2068	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2069	(UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
2070	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
2071	CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2072	USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2073	USE_SECONDARY_CTLS));
2074	/** @} */
2075
2076
2077	/** @name Secondary Processor-based VM-execution controls.
2078	* @{
2079	*/
2080	/** Virtualize APIC accesses. */
2081	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2082	/** EPT supported/enabled. */
2083	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2084	/** Descriptor table instructions cause VM-exits. */
2085	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2086	/** RDTSCP supported/enabled. */
2087	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2088	/** Virtualize x2APIC mode. */
2089	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2090	/** VPID supported/enabled. */
2091	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2092	/** VM-exit when executing the WBINVD instruction. */
2093	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2094	/** Unrestricted guest execution. */
2095	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2096	/** APIC register virtualization. */
2097	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2098	/** Virtual-interrupt delivery. */
2099	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2100	/** A specified number of pause loops cause a VM-exit. */
2101	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2102	/** VM-exit when executing RDRAND instructions. */
2103	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2104	/** Enables INVPCID instructions. */
2105	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2106	/** Enables VMFUNC instructions. */
2107	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2108	/** Enables VMCS shadowing. */
2109	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2110	/** Enables ENCLS VM-exits. */
2111	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2112	/** VM-exit when executing RDSEED. */
2113	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2114	/** Enables page-modification logging. */
2115	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2116	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2117	#define VMX_PROC_CTLS2_EPT_VE RT_BIT(18)
2118	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2119	#define VMX_PROC_CTLS2_CONCEAL_FROM_PT RT_BIT(19)
2120	/** Enables XSAVES/XRSTORS instructions. */
2121	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2122	/** Use TSC scaling. */
2123	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2124
2125	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2126	* VM-execution controls field in the VMCS. */
2127	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2128	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2129	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2130	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2131	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2132	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2133	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2134	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2135	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2136	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2137	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2138	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2139	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2140	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2141	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2142	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2143	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2144	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2145	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2146	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2147	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2148	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2149	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2150	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2151	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2152	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2153	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2154	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2155	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2156	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2157	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2158	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2159	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2160	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2161	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2162	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2163	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2164	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2165	#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_SHIFT 19
2166	#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_MASK UINT32_C(0x00080000)
2167	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2168	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2169	#define VMX_BF_PROC_CTLS2_UNDEF_21_24_SHIFT 21
2170	#define VMX_BF_PROC_CTLS2_UNDEF_21_24_MASK UINT32_C(0x01e00000)
2171	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2172	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2173	#define VMX_BF_PROC_CTLS2_UNDEF_26_31_SHIFT 26
2174	#define VMX_BF_PROC_CTLS2_UNDEF_26_31_MASK UINT32_C(0xfc000000)
2175	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2176	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2177	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2178	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_FROM_PT, XSAVES_XRSTORS, UNDEF_21_24,
2179	TSC_SCALING, UNDEF_26_31));
2180	/** @} */
2181
2182
2183	/** @name VM-entry controls.
2184	* @{
2185	*/
2186	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2187	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2188	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2189	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2190	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2191	/** In SMM mode after VM-entry. */
2192	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2193	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2194	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2195	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2196	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2197	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2198	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2199	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2200	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2201	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2202	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2203	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2204	#define VMX_ENTRY_CTLS_CONCEAL_VMX_PT RT_BIT(17)
2205	/** Default1 class when true-capability MSRs are not supported. */
2206	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2207
2208	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2209	* VMCS. */
2210	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT 0
2211	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2212	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2213	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2214	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT 3
2215	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2216	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2217	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2218	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2219	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2220	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2221	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2222	#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT 12
2223	#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK UINT32_C(0x00001000)
2224	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2225	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2226	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2227	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2228	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2229	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2230	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2231	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2232	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_PT_SHIFT 17
2233	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_PT_MASK UINT32_C(0x00020000)
2234	#define VMX_BF_ENTRY_CTLS_UNDEF_18_31_SHIFT 18
2235	#define VMX_BF_ENTRY_CTLS_UNDEF_18_31_MASK UINT32_C(0xfffc0000)
2236	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2237	(UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
2238	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_PT, UNDEF_18_31));
2239	/** @} */
2240
2241
2242	/** @name VM-exit controls.
2243	* @{
2244	*/
2245	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2246	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2247	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2248	/** Return to long mode after a VM-exit. */
2249	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2250	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2251	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2252	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2253	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2254	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2255	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2256	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2257	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2258	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2259	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2260	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2261	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2262	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2263	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2264	/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2265	#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2266	/** Default1 class when true-capability MSRs are not supported. */
2267	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2268
2269	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2270	* VMCS. */
2271	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT 0
2272	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2273	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2274	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2275	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT 3
2276	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2277	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2278	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2279	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT 10
2280	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK UINT32_C(0x00000c00)
2281	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2282	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2283	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT 13
2284	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2285	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2286	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2287	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT 16
2288	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK UINT32_C(0x00030000)
2289	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2290	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2291	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2292	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2293	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2294	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2295	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2296	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2297	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2298	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2299	#define VMX_BF_EXIT_CTLS_UNDEF_23_31_SHIFT 23
2300	#define VMX_BF_EXIT_CTLS_UNDEF_23_31_MASK UINT32_C(0xff800000)
2301	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2302	(UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
2303	ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2304	SAVE_PREEMPT_TIMER, UNDEF_23_31));
2305	/** @} */
2306
2307
2308	/** @name VM-exit reason.
2309	* @{
2310	*/
2311	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2312	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2313	#define VMX_EXIT_REASON_ENTRY_FAILED RT_BIT(31)
2314
2315	/** Bit fields for VM-exit reason. */
2316	/** The exit reason. */
2317	#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2318	#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2319	/** Bits 16:26 are reseved and MBZ. */
2320	#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2321	#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2322	/** Whether the VM-exit was incident to enclave mode. */
2323	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2324	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2325	/** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
2326	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT 28
2327	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK UINT32_C(0x10000000)
2328	/** VM-exit from VMX root operation (only possible with SMM). */
2329	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2330	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2331	/** Bit 30 is reserved and MBZ. */
2332	#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2333	#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2334	/** Whether VM-entry failed (currently only happens during loading guest-state
2335	* or MSRs or machine check exceptions). */
2336	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2337	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2338	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2339	(BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2340	/** @} */
2341
2342
2343	/** @name VM-entry interruption information.
2344	* @{
2345	*/
2346	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2347	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2348	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2349	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2350	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2351	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2352	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2353	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2354	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2355	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2356	/** Construct an VM-entry interruption information field from a VM-exit interruption
2357	* info value (same except that bit 12 is reserved). */
2358	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2359	/** Construct a VM-entry interruption information field from an IDT-vectoring
2360	* information field (same except that bit 12 is reserved). */
2361	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2362
2363	/** Bit fields for VM-entry interruption information. */
2364	/** The VM-entry interruption vector. */
2365	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2366	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2367	/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2368	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2369	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2370	/** Whether this event has an error code. */
2371	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2372	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2373	/** Bits 12:30 are reserved and MBZ. */
2374	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2375	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2376	/** Whether this VM-entry interruption info is valid. */
2377	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2378	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2379	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2380	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2381	/** @} */
2382
2383	/** @name VM-entry exception error code.
2384	* @{ */
2385	/** Error code valid mask. */
2386	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2387	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2388	* stack aligned for doubleword pushes, the upper half of the error code is
2389	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2390	* use below. */
2391	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2392	/** @} */
2393
2394	/** @name VM-entry interruption information types.
2395	* @{
2396	*/
2397	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2398	#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2399	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2400	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2401	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2402	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2403	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2404	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2405	/** @} */
2406
2407
2408	/** @name VM-entry interruption information vector types for
2409	* VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2410	* @{ */
2411	#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2412	/** @} */
2413
2414
2415	/** @name VM-exit interruption information.
2416	* @{
2417	*/
2418	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2419	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2420	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2421	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2422	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2423	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2424	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2425	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2426	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2427
2428	/** Bit fields for VM-exit interruption infomration. */
2429	/** The VM-exit interruption vector. */
2430	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2431	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2432	/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
2433	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2434	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2435	/** Whether this event has an error code. */
2436	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2437	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2438	/** Whether NMI-unblocking due to IRET is active. */
2439	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2440	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2441	/** Bits 13:30 is reserved (MBZ). */
2442	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2443	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2444	/** Whether this VM-exit interruption info is valid. */
2445	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2446	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2447	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2448	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2449	/** @} */
2450
2451
2452	/** @name VM-exit interruption information types.
2453	* @{
2454	*/
2455	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2456	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2457	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2458	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2459	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2460	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2461	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2462	/** @} */
2463
2464
2465	/** @name VM-exit instruction identity.
2466	*
2467	* These are found in VM-exit instruction information fields for certain
2468	* instructions.
2469	* @{ */
2470	typedef uint32_t VMXINSTRID;
2471	/** Whether the instruction ID field is valid. */
2472	#define VMXINSTRID_VALID RT_BIT_32(31)
2473	/** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
2474	* read or write. */
2475	#define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30)
2476	/** Gets whether the instruction ID is valid or not. */
2477	#define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1)
2478	#define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1)
2479	/** Gets the instruction ID. */
2480	#define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W))
2481	/** No instruction ID info. */
2482	#define VMXINSTRID_NONE 0
2483
2484	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
2485	#define VMXINSTRID_SGDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2486	#define VMXINSTRID_SIDT (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2487	#define VMXINSTRID_LGDT (0x2 \| VMXINSTRID_VALID)
2488	#define VMXINSTRID_LIDT (0x3 \| VMXINSTRID_VALID)
2489
2490	#define VMXINSTRID_SLDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2491	#define VMXINSTRID_STR (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2492	#define VMXINSTRID_LLDT (0x2 \| VMXINSTRID_VALID)
2493	#define VMXINSTRID_LTR (0x3 \| VMXINSTRID_VALID)
2494
2495	/** The following IDs are used internally (some for logging, others for conveying
2496	* the ModR/M primary operand write bit): */
2497	#define VMXINSTRID_VMLAUNCH (0x10 \| VMXINSTRID_VALID)
2498	#define VMXINSTRID_VMRESUME (0x11 \| VMXINSTRID_VALID)
2499	#define VMXINSTRID_VMREAD (0x12 \| VMXINSTRID_VALID)
2500	#define VMXINSTRID_VMWRITE (0x13 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
2501	#define VMXINSTRID_IO_IN (0x14 \| VMXINSTRID_VALID)
2502	#define VMXINSTRID_IO_INS (0x15 \| VMXINSTRID_VALID)
2503	#define VMXINSTRID_IO_OUT (0x16 \| VMXINSTRID_VALID)
2504	#define VMXINSTRID_IO_OUTS (0x17 \| VMXINSTRID_VALID)
2505	#define VMXINSTRID_MOV_TO_DRX (0x18 \| VMXINSTRID_VALID)
2506	#define VMXINSTRID_MOV_FROM_DRX (0x19 \| VMXINSTRID_VALID)
2507	/** @} */
2508
2509
2510	/** @name IDT-vectoring information.
2511	* @{
2512	*/
2513	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2514	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2515	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2516	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2517
2518	/** Construct an IDT-vectoring information field from an VM-entry interruption
2519	* information field (same except that bit 12 is reserved). */
2520	#define VMX_EXIT_IDT_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
2521
2522	/** Bit fields for IDT-vectoring information. */
2523	/** The IDT-vectoring info vector. */
2524	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2525	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2526	/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
2527	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2528	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2529	/** Whether the event has an error code. */
2530	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2531	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2532	/** Bit 12 is undefined. */
2533	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2534	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2535	/** Bits 13:30 is reserved (MBZ). */
2536	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2537	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2538	/** Whether this IDT-vectoring info is valid. */
2539	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2540	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2541	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2542	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2543	/** @} */
2544
2545
2546	/** @name IDT-vectoring information vector types.
2547	* @{
2548	*/
2549	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2550	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2551	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2552	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2553	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2554	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2555	#define VMX_IDT_VECTORING_INFO_TYPE_UNUSED 7
2556	/** @} */
2557
2558
2559	/** @name TPR threshold.
2560	* @{ */
2561	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
2562	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
2563
2564	/** Bit fields for TPR threshold. */
2565	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
2566	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
2567	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
2568	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
2569	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
2570	(TPR, RSVD_4_31));
2571	/** @} */
2572
2573
2574	/** @name Guest-activity states.
2575	* @{
2576	*/
2577	/** The logical processor is active. */
2578	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
2579	/** The logical processor is inactive, because it executed a HLT instruction. */
2580	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
2581	/** The logical processor is inactive, because of a triple fault or other serious error. */
2582	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
2583	/** The logical processor is inactive, because it's waiting for a startup-IPI */
2584	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
2585	/** @} */
2586
2587
2588	/** @name Guest-interruptibility states.
2589	* @{
2590	*/
2591	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
2592	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
2593	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
2594	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
2595	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
2596
2597	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
2598	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
2599	/** @} */
2600
2601
2602	/** @name Exit qualification for debug exceptions.
2603	* @{
2604	*/
2605	/** Hardware breakpoint 0 was met. */
2606	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 RT_BIT_64(0)
2607	/** Hardware breakpoint 1 was met. */
2608	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 RT_BIT_64(1)
2609	/** Hardware breakpoint 2 was met. */
2610	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 RT_BIT_64(2)
2611	/** Hardware breakpoint 3 was met. */
2612	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 RT_BIT_64(3)
2613	/** Debug register access detected. */
2614	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD RT_BIT_64(13)
2615	/** A debug exception would have been triggered by single-step execution mode. */
2616	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS RT_BIT_64(14)
2617	/** Mask of all valid bits. */
2618	#define VMX_VMCS_EXIT_QUAL_VALID_MASK ( VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
2619	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
2620	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
2621	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
2622	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD \
2623	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
2624
2625	/** Bit fields for Exit qualifications due to debug exceptions. */
2626	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT 0
2627	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
2628	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT 1
2629	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
2630	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT 2
2631	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
2632	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT 3
2633	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
2634	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT 4
2635	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK UINT64_C(0x0000000000001ff0)
2636	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT 13
2637	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK UINT64_C(0x0000000000002000)
2638	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT 14
2639	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
2640	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT 15
2641	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK UINT64_C(0xffffffffffff8000)
2642	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
2643	(BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
2644	/** @} */
2645
2646	/** @name Exit qualification for Mov DRx.
2647	* @{
2648	*/
2649	/** 0-2: Debug register number */
2650	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
2651	/** 3: Reserved; cleared to 0. */
2652	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
2653	/** 4: Direction of move (0 = write, 1 = read) */
2654	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
2655	/** 5-7: Reserved; cleared to 0. */
2656	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
2657	/** 8-11: General purpose register number. */
2658	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
2659
2660	/** Bit fields for Exit qualification due to Mov DRx. */
2661	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT 0
2662	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK UINT64_C(0x0000000000000007)
2663	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT 3
2664	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK UINT64_C(0x0000000000000008)
2665	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT 4
2666	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK UINT64_C(0x0000000000000010)
2667	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT 5
2668	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK UINT64_C(0x00000000000000e0)
2669	#define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT 8
2670	#define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK UINT64_C(0x0000000000000f00)
2671	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT 12
2672	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK UINT64_C(0xfffffffffffff000)
2673	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
2674	(REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
2675	/** @} */
2676
2677
2678	/** @name Exit qualification for debug exceptions types.
2679	* @{
2680	*/
2681	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
2682	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
2683	/** @} */
2684
2685
2686	/** @name Exit qualification for control-register accesses.
2687	* @{
2688	*/
2689	/** 0-3: Control register number (0 for CLTS & LMSW) */
2690	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
2691	/** 4-5: Access type. */
2692	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
2693	/** 6: LMSW operand type */
2694	#define VMX_EXIT_QUAL_CRX_LMSW_OP(a) (((a) >> 6) & 1)
2695	/** 7: Reserved; cleared to 0. */
2696	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
2697	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
2698	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
2699	/** 12-15: Reserved; cleared to 0. */
2700	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
2701	/** 16-31: LMSW source data (else 0). */
2702	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
2703
2704	/** Bit fields for Exit qualification for control-register accesses. */
2705	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT 0
2706	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK UINT64_C(0x000000000000000f)
2707	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT 4
2708	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK UINT64_C(0x0000000000000030)
2709	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT 6
2710	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK UINT64_C(0x0000000000000040)
2711	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT 7
2712	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK UINT64_C(0x0000000000000080)
2713	#define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT 8
2714	#define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK UINT64_C(0x0000000000000f00)
2715	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT 12
2716	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK UINT64_C(0x000000000000f000)
2717	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT 16
2718	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK UINT64_C(0x00000000ffff0000)
2719	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT 32
2720	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
2721	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
2722	(REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
2723	/** @} */
2724
2725
2726	/** @name Exit qualification for control-register access types.
2727	* @{
2728	*/
2729	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
2730	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
2731	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
2732	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
2733	/** @} */
2734
2735
2736	/** @name Exit qualification for task switch.
2737	* @{
2738	*/
2739	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
2740	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
2741	/** Task switch caused by a call instruction. */
2742	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
2743	/** Task switch caused by an iret instruction. */
2744	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
2745	/** Task switch caused by a jmp instruction. */
2746	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
2747	/** Task switch caused by an interrupt gate. */
2748	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
2749
2750	/** Bit fields for Exit qualification for task switches. */
2751	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT 0
2752	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK UINT64_C(0x000000000000ffff)
2753	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT 16
2754	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK UINT64_C(0x000000003fff0000)
2755	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT 30
2756	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK UINT64_C(0x00000000c0000000)
2757	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT 32
2758	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
2759	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
2760	(NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
2761	/** @} */
2762
2763
2764	/** @name Exit qualification for EPT violations.
2765	* @{
2766	*/
2767	/** Set if the violation was caused by a data read. */
2768	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
2769	/** Set if the violation was caused by a data write. */
2770	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
2771	/** Set if the violation was caused by an instruction fetch. */
2772	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
2773	/** AND of the present bit of all EPT structures. */
2774	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
2775	/** AND of the write bit of all EPT structures. */
2776	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
2777	/** AND of the execute bit of all EPT structures. */
2778	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
2779	/** Set if the guest linear address field contains the faulting address. */
2780	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
2781	/** If bit 7 is one: (reserved otherwise)
2782	* 1 - violation due to physical address access.
2783	* 0 - violation caused by page walk or access/dirty bit updates
2784	*/
2785	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
2786	/** @} */
2787
2788
2789	/** @name Exit qualification for I/O instructions.
2790	* @{
2791	*/
2792	/** 0-2: IO operation width. */
2793	#define VMX_EXIT_QUAL_IO_WIDTH(a) ((a) & 7)
2794	/** 3: IO operation direction. */
2795	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
2796	/** 4: String IO operation (INS / OUTS). */
2797	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
2798	/** 5: Repeated IO operation. */
2799	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
2800	/** 6: Operand encoding. */
2801	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
2802	/** 16-31: IO Port (0-0xffff). */
2803	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
2804
2805	/** Bit fields for Exit qualification for I/O instructions. */
2806	#define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT 0
2807	#define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK UINT64_C(0x0000000000000007)
2808	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT 3
2809	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK UINT64_C(0x0000000000000008)
2810	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT 4
2811	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK UINT64_C(0x0000000000000010)
2812	#define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT 5
2813	#define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK UINT64_C(0x0000000000000020)
2814	#define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT 6
2815	#define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK UINT64_C(0x0000000000000040)
2816	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT 7
2817	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK UINT64_C(0x000000000000ff80)
2818	#define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT 16
2819	#define VMX_BF_EXIT_QUAL_IO_PORT_MASK UINT64_C(0x00000000ffff0000)
2820	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT 32
2821	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
2822	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
2823	(WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
2824	/** @} */
2825
2826
2827	/** @name Exit qualification for I/O instruction types.
2828	* @{
2829	*/
2830	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
2831	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
2832	/** @} */
2833
2834
2835	/** @name Exit qualification for I/O instruction encoding.
2836	* @{
2837	*/
2838	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
2839	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
2840	/** @} */
2841
2842
2843	/** @name Exit qualification for APIC-access VM-exits from linear and
2844	* guest-physical accesses.
2845	* @{
2846	*/
2847	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
2848	* access within the APIC page. */
2849	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
2850	/** 12-15: Access type. */
2851	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
2852	/* Rest reserved. */
2853
2854	/** Bit fields for Exit qualification for APIC-access VM-exits. */
2855	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT 0
2856	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK UINT64_C(0x0000000000000fff)
2857	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT 12
2858	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK UINT64_C(0x000000000000f000)
2859	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT 16
2860	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK UINT64_C(0xffffffffffff0000)
2861	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
2862	(OFFSET, TYPE, RSVD_16_63));
2863	/** @} */
2864
2865
2866	/** @name Exit qualification for linear address APIC-access types.
2867	* @{
2868	*/
2869	/** Linear access for a data read during instruction execution. */
2870	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
2871	/** Linear access for a data write during instruction execution. */
2872	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
2873	/** Linear access for an instruction fetch. */
2874	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
2875	/** Linear read/write access during event delivery. */
2876	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
2877	/** Physical read/write access during event delivery. */
2878	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
2879	/** Physical access for an instruction fetch or during instruction execution. */
2880	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
2881
2882	/**
2883	* APIC-access type.
2884	*/
2885	typedef enum
2886	{
2887	VMXAPICACCESS_LINEAR_READ = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
2888	VMXAPICACCESS_LINEAR_WRITE = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
2889	VMXAPICACCESS_LINEAR_INSTR_FETCH = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
2890	VMXAPICACCESS_LINEAR_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
2891	VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
2892	VMXAPICACCESS_PHYSICAL_INSTR = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
2893	} VMXAPICACCESS;
2894	AssertCompileSize(VMXAPICACCESS, 4);
2895	/** @} */
2896
2897
2898	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
2899	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
2900	* @{
2901	*/
2902	/** Address calculation scaling field (powers of two). */
2903	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
2904	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
2905	/** Bits 2 thru 6 are undefined. */
2906	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
2907	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
2908	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
2909	* @remarks anyone's guess why this is a 3 bit field... */
2910	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
2911	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
2912	/** Bit 10 is defined as zero. */
2913	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
2914	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
2915	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
2916	* for exits from 64-bit code as the operand size there is fixed. */
2917	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
2918	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
2919	/** Bits 12 thru 14 are undefined. */
2920	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
2921	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
2922	/** Applicable segment register (X86_SREG_XXX values). */
2923	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
2924	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
2925	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
2926	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
2927	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
2928	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
2929	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
2930	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
2931	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
2932	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
2933	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
2934	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
2935	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
2936	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
2937	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
2938	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
2939	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
2940	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
2941	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
2942	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
2943	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
2944	/** Bits 30 & 31 are undefined. */
2945	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
2946	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
2947	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
2948	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
2949	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
2950	/** @} */
2951
2952
2953	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
2954	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
2955	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
2956	* @{
2957	*/
2958	/** Address calculation scaling field (powers of two). */
2959	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
2960	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
2961	/** Bit 2 is undefined. */
2962	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
2963	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
2964	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
2965	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
2966	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
2967	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
2968	* @remarks anyone's guess why this is a 3 bit field... */
2969	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
2970	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
2971	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
2972	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
2973	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
2974	/** Bits 11 thru 14 are undefined. */
2975	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
2976	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
2977	/** Applicable segment register (X86_SREG_XXX values). */
2978	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
2979	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
2980	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
2981	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
2982	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
2983	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
2984	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
2985	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
2986	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
2987	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
2988	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
2989	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
2990	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
2991	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
2992	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
2993	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
2994	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
2995	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
2996	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
2997	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
2998	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
2999	/** Bits 30 & 31 are undefined. */
3000	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
3001	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3002	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3003	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
3004	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3005	/** @} */
3006
3007
3008	/** @name Format of Pending-Debug-Exceptions.
3009	* Bits 4-11, 13, 15 and 17-63 are reserved.
3010	* Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
3011	* possibly valid here but not in DR6.
3012	* @{
3013	*/
3014	/** Hardware breakpoint 0 was met. */
3015	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
3016	/** Hardware breakpoint 1 was met. */
3017	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
3018	/** Hardware breakpoint 2 was met. */
3019	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
3020	/** Hardware breakpoint 3 was met. */
3021	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
3022	/** At least one data or IO breakpoint was hit. */
3023	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
3024	/** A debug exception would have been triggered by single-step execution mode. */
3025	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
3026	/** A debug exception occurred inside an RTM region. */
3027	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
3028	/** Mask of valid bits. */
3029	#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
3030	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
3031	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
3032	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
3033	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3034	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3035	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3036	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3037	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3038	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3039	/** Bit fields for Pending debug exceptions. */
3040	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
3041	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3042	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
3043	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3044	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
3045	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3046	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
3047	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3048	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
3049	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
3050	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
3051	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
3052	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
3053	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
3054	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
3055	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3056	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
3057	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3058	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
3059	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
3060	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
3061	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3062	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
3063	(BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
3064	/** @} */
3065
3066
3067	/** @name VMCS field encoding.
3068	* @{ */
3069	typedef union
3070	{
3071	struct
3072	{
3073	/** The access type; 0=full, 1=high of 64-bit fields. */
3074	uint32_t fAccessType : 1;
3075	/** The index. */
3076	uint32_t u8Index : 8;
3077	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
3078	uint32_t u2Type : 2;
3079	/** Reserved (MBZ). */
3080	uint32_t u1Reserved0 : 1;
3081	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
3082	uint32_t u2Width : 2;
3083	/** Reserved (MBZ). */
3084	uint32_t u18Reserved0 : 18;
3085	} n;
3086	/* The unsigned integer view. */
3087	uint32_t u;
3088	} VMXVMCSFIELDENC;
3089	AssertCompileSize(VMXVMCSFIELDENC, 4);
3090	/** Pointer to a VMCS field encoding. */
3091	typedef VMXVMCSFIELDENC *PVMXVMCSFIELDENC;
3092	/** Pointer to a const VMCS field encoding. */
3093	typedef const VMXVMCSFIELDENC *PCVMXVMCSFIELDENC;
3094
3095	/** VMCS field encoding type: Full. */
3096	#define VMX_VMCS_ENC_ACCESS_TYPE_FULL 0
3097	/** VMCS field encoding type: High. */
3098	#define VMX_VMCS_ENC_ACCESS_TYPE_HIGH 1
3099
3100	/** VMCS field encoding type: Control. */
3101	#define VMX_VMCS_ENC_TYPE_CONTROL 0
3102	/** VMCS field encoding type: VM-exit information / read-only fields. */
3103	#define VMX_VMCS_ENC_TYPE_VMEXIT_INFO 1
3104	/** VMCS field encoding type: Guest-state. */
3105	#define VMX_VMCS_ENC_TYPE_GUEST_STATE 2
3106	/** VMCS field encoding type: Host-state. */
3107	#define VMX_VMCS_ENC_TYPE_HOST_STATE 3
3108
3109	/** VMCS field encoding width: 16-bit. */
3110	#define VMX_VMCS_ENC_WIDTH_16BIT 0
3111	/** VMCS field encoding width: 64-bit. */
3112	#define VMX_VMCS_ENC_WIDTH_64BIT 1
3113	/** VMCS field encoding width: 32-bit. */
3114	#define VMX_VMCS_ENC_WIDTH_32BIT 2
3115	/** VMCS field encoding width: Natural width. */
3116	#define VMX_VMCS_ENC_WIDTH_NATURAL 3
3117
3118	/** VMCS field encoding: Mask of reserved bits (bits 63:15 MBZ), bit 12 is
3119	* not included! */
3120	#define VMX_VMCS_ENC_RSVD_MASK UINT64_C(0xffffffffffff8000)
3121
3122	/** Bits fields for VMCS field encoding. */
3123	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_SHIFT 0
3124	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_MASK UINT32_C(0x00000001)
3125	#define VMX_BF_VMCS_ENC_INDEX_SHIFT 1
3126	#define VMX_BF_VMCS_ENC_INDEX_MASK UINT32_C(0x000003fe)
3127	#define VMX_BF_VMCS_ENC_TYPE_SHIFT 10
3128	#define VMX_BF_VMCS_ENC_TYPE_MASK UINT32_C(0x00000c00)
3129	#define VMX_BF_VMCS_ENC_RSVD_12_SHIFT 12
3130	#define VMX_BF_VMCS_ENC_RSVD_12_MASK UINT32_C(0x00001000)
3131	#define VMX_BF_VMCS_ENC_WIDTH_SHIFT 13
3132	#define VMX_BF_VMCS_ENC_WIDTH_MASK UINT32_C(0x00006000)
3133	#define VMX_BF_VMCS_ENC_RSVD_15_31_SHIFT 15
3134	#define VMX_BF_VMCS_ENC_RSVD_15_31_MASK UINT32_C(0xffff8000)
3135	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENC_, UINT32_C(0), UINT32_MAX,
3136	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
3137	/** @} */
3138
3139
3140	/** @defgroup grp_hm_vmx_virt VMX virtualization.
3141	* @{
3142	*/
3143
3144	/** @name Virtual VMX MSR - Miscellaneous data.
3145	* @{ */
3146	/** Number of CR3-target values supported. */
3147	#define VMX_V_CR3_TARGET_COUNT 4
3148	/** Activity states supported. */
3149	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
3150	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
3151	#define VMX_V_PREEMPT_TIMER_SHIFT 5
3152	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
3153	#define VMX_V_AUTOMSR_COUNT_MAX 0
3154	/** SMM MSEG revision ID. */
3155	#define VMX_V_MSEG_REV_ID 0
3156	/** @} */
3157
3158	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS state.
3159	* @{ */
3160	/** VMCS state clear. */
3161	#define VMX_V_VMCS_STATE_CLEAR RT_BIT(1)
3162	/** VMCS state launched. */
3163	#define VMX_V_VMCS_STATE_LAUNCHED RT_BIT(2)
3164	/** @} */
3165
3166	/** CR0 bits set here must always be set when in VMX operation. */
3167	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
3168	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
3169	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
3170	/** CR4 bits set here must always be set when in VMX operation. */
3171	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
3172
3173	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
3174	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
3175	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x1d000001)
3176	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
3177
3178	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
3179	* complications when teleporation may be implemented). */
3180	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
3181	/** The size of the virtual VMCS region (in pages). */
3182	#define VMX_V_VMCS_PAGES 1
3183
3184	/** The size of the Virtual-APIC page (in bytes). */
3185	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3186	/** The size of the Virtual-APIC page (in pages). */
3187	#define VMX_V_VIRT_APIC_PAGES 1
3188
3189	/** Virtual X2APIC MSR range start. */
3190	#define VMX_V_VIRT_APIC_MSR_START 0x800
3191	/** Virtual X2APIC MSR range end. */
3192	#define VMX_V_VIRT_APIC_MSR_END 0x8ff
3193
3194	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3195	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3196	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3197	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3198
3199	/** The size of the MSR bitmap (in bytes). */
3200	#define VMX_V_MSR_BITMAP_SIZE X86_PAGE_4K_SIZE
3201	/** The size of the MSR bitmap (in pages). */
3202	#define VMX_V_MSR_BITMAP_PAGES 1
3203
3204	/** The size of I/O bitmap A (in bytes). */
3205	#define VMX_V_IO_BITMAP_A_SIZE X86_PAGE_4K_SIZE
3206	/** The size of I/O bitmap A (in pages). */
3207	#define VMX_V_IO_BITMAP_A_PAGES 1
3208
3209	/** The size of I/O bitmap B (in bytes). */
3210	#define VMX_V_IO_BITMAP_B_SIZE X86_PAGE_4K_SIZE
3211	/** The size of I/O bitmap B (in pages). */
3212	#define VMX_V_IO_BITMAP_B_PAGES 1
3213
3214	/** The size of the auto-load/store MSR area (in bytes). */
3215	#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3216	/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3217	AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3218	/** The size of the auto-load/store MSR area (in pages). */
3219	#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3220
3221	/** The highest index value used for supported virtual VMCS field encoding. */
3222	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH, VMX_BF_VMCS_ENC_INDEX)
3223
3224	/**
3225	* Virtual VM-Exit information.
3226	*
3227	* This is a convenience structure that bundles some VM-exit information related
3228	* fields together.
3229	*/
3230	typedef struct
3231	{
3232	/** The VM-exit reason. */
3233	uint32_t uReason;
3234	/** The VM-exit instruction length. */
3235	uint32_t cbInstr;
3236	/** The VM-exit instruction information. */
3237	VMXEXITINSTRINFO InstrInfo;
3238	/** The VM-exit instruction ID. */
3239	VMXINSTRID uInstrId;
3240
3241	/** The VM-exit qualification field. */
3242	uint64_t u64Qual;
3243	/** The guest-linear address field. */
3244	uint64_t u64GuestLinearAddr;
3245	/** The guest-physical address field. */
3246	uint64_t u64GuestPhysAddr;
3247	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
3248	* instruction VM-exit. */
3249	RTGCPTR GCPtrEffAddr;
3250	} VMXVEXITINFO;
3251	/** Pointer to the VMXVEXITINFO struct. */
3252	typedef VMXVEXITINFO *PVMXVEXITINFO;
3253	/** Pointer to a const VMXVEXITINFO struct. */
3254	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3255	AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
3256
3257	/**
3258	* Virtual VMCS.
3259	* This is our custom format and merged into the actual VMCS (/shadow) when we
3260	* execute nested-guest code using hardware-assisted VMX.
3261	*
3262	* The first 8 bytes are as per Intel spec. 24.2 "Format of the VMCS Region".
3263	*
3264	* The offset and size of the VMCS state field (fVmcsState) is also fixed (not by
3265	* Intel but for our own requirements) as we use it to offset into guest memory.
3266	*
3267	* Although the guest is supposed to access the VMCS only through the execution of
3268	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
3269	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
3270	* for teleportation purposes, any newly added fields should be added to the
3271	* appropriate reserved sections or at the end of the structure.
3272	*
3273	* We always treat natural-width fields as 64-bit in our implementation since
3274	* it's easier, allows for teleporation in the future and does not affect guest
3275	* software.
3276	*/
3277	#pragma pack(1)
3278	typedef struct
3279	{
3280	/** 0x0 - VMX VMCS revision identifier. */
3281	VMXVMCSREVID u32VmcsRevId;
3282	/** 0x4 - VMX-abort indicator. */
3283	uint32_t u32VmxAbortId;
3284	/** 0x8 - VMCS state, see VMX_V_VMCS_STATE_XXX. */
3285	uint8_t fVmcsState;
3286	/** 0x9 - Reserved for future. */
3287	uint8_t au8Padding0[3];
3288	/** 0xc - Reserved for future. */
3289	uint32_t au32Reserved0[7];
3290
3291	/** @name 16-bit control fields.
3292	* @{ */
3293	/** 0x28 - Virtual processor ID. */
3294	uint16_t u16Vpid;
3295	/** 0x2a - Posted interrupt notify vector. */
3296	uint16_t u16PostIntNotifyVector;
3297	/** 0x2c - EPTP index. */
3298	uint16_t u16EptpIndex;
3299	/** 0x2e - Reserved for future. */
3300	uint16_t au16Reserved0[8];
3301	/** @} */
3302
3303	/** @name 16-bit Guest-state fields.
3304	* Order of [ES..GS] is important, must match X86_SREG_XXX.
3305	* @{ */
3306	/** 0x3e - Guest ES selector. */
3307	RTSEL GuestEs;
3308	/** 0x40 - Guest ES selector. */
3309	RTSEL GuestCs;
3310	/** 0x42 - Guest ES selector. */
3311	RTSEL GuestSs;
3312	/** 0x44 - Guest ES selector. */
3313	RTSEL GuestDs;
3314	/** 0x46 - Guest ES selector. */
3315	RTSEL GuestFs;
3316	/** 0x48 - Guest ES selector. */
3317	RTSEL GuestGs;
3318	/** 0x4a - Guest LDTR selector. */
3319	RTSEL GuestLdtr;
3320	/** 0x4c - Guest TR selector. */
3321	RTSEL GuestTr;
3322	/** 0x4e - Guest interrupt status (virtual-interrupt delivery). */
3323	uint16_t u16GuestIntStatus;
3324	/** 0x50 - PML index. */
3325	uint16_t u16PmlIndex;
3326	/** 0x52 - Reserved for future. */
3327	uint16_t au16Reserved1[8];
3328	/** @} */
3329
3330	/** @name 16-bit Host-state fields.
3331	* @{ */
3332	/** 0x62 - Host ES selector. */
3333	RTSEL HostEs;
3334	/** 0x64 - Host CS selector. */
3335	RTSEL HostCs;
3336	/** 0x66 - Host SS selector. */
3337	RTSEL HostSs;
3338	/** 0x68 - Host DS selector. */
3339	RTSEL HostDs;
3340	/** 0x6a - Host FS selector. */
3341	RTSEL HostFs;
3342	/** 0x6c - Host GS selector. */
3343	RTSEL HostGs;
3344	/** 0x6e - Host TR selector. */
3345	RTSEL HostTr;
3346	/** 0x70 - Reserved for future. */
3347	uint16_t au16Reserved2[10];
3348	/** @} */
3349
3350	/** @name 32-bit Control fields.
3351	* @{ */
3352	/** 0x84 - Pin-based VM-execution controls. */
3353	uint32_t u32PinCtls;
3354	/** 0x88 - Processor-based VM-execution controls. */
3355	uint32_t u32ProcCtls;
3356	/** 0x8c - Exception bitmap. */
3357	uint32_t u32XcptBitmap;
3358	/** 0x90 - Page-fault exception error mask. */
3359	uint32_t u32XcptPFMask;
3360	/** 0x94 - Page-fault exception error match. */
3361	uint32_t u32XcptPFMatch;
3362	/** 0x98 - CR3-target count. */
3363	uint32_t u32Cr3TargetCount;
3364	/** 0x9c - VM-exit controls. */
3365	uint32_t u32ExitCtls;
3366	/** 0xa0 - VM-exit MSR store count. */
3367	uint32_t u32ExitMsrStoreCount;
3368	/** 0xa4 - VM-exit MSR load count. */
3369	uint32_t u32ExitMsrLoadCount;
3370	/** 0xa8 - VM-entry controls. */
3371	uint32_t u32EntryCtls;
3372	/** 0xac - VM-entry MSR load count. */
3373	uint32_t u32EntryMsrLoadCount;
3374	/** 0xb0 - VM-entry interruption information. */
3375	uint32_t u32EntryIntInfo;
3376	/** 0xb4 - VM-entry exception error code. */
3377	uint32_t u32EntryXcptErrCode;
3378	/** 0xb8 - VM-entry instruction length. */
3379	uint32_t u32EntryInstrLen;
3380	/** 0xbc - TPR-threshold. */
3381	uint32_t u32TprThreshold;
3382	/** 0xc0 - Secondary-processor based VM-execution controls. */
3383	uint32_t u32ProcCtls2;
3384	/** 0xc4 - Pause-loop exiting Gap. */
3385	uint32_t u32PleGap;
3386	/** 0xc8 - Pause-loop exiting Window. */
3387	uint32_t u32PleWindow;
3388	/** 0xcc - Reserved for future. */
3389	uint32_t au32Reserved1[8];
3390	/** @} */
3391
3392	/** @name 32-bit Read-only Data fields.
3393	* @{ */
3394	/** 0xec - VM-instruction error. */
3395	uint32_t u32RoVmInstrError;
3396	/** 0xf0 - VM-exit reason. */
3397	uint32_t u32RoExitReason;
3398	/** 0xf4 - VM-exit interruption information. */
3399	uint32_t u32RoExitIntInfo;
3400	/** 0xf8 - VM-exit interruption error code. */
3401	uint32_t u32RoExitIntErrCode;
3402	/** 0xfc - IDT-vectoring information. */
3403	uint32_t u32RoIdtVectoringInfo;
3404	/** 0x100 - IDT-vectoring error code. */
3405	uint32_t u32RoIdtVectoringErrCode;
3406	/** 0x104 - VM-exit instruction length. */
3407	uint32_t u32RoExitInstrLen;
3408	/** 0x108 - VM-exit instruction information. */
3409	uint32_t u32RoExitInstrInfo;
3410	/** 0x10c - Reserved for future. */
3411	uint32_t au32RoReserved2[8];
3412	/** @} */
3413
3414	/** @name 32-bit Guest-state fields.
3415	* Order of [ES..GS] limit and attributes are important, must match X86_SREG_XXX.
3416	* @{ */
3417	/** 0x12c - Guest ES limit. */
3418	uint32_t u32GuestEsLimit;
3419	/** 0x130 - Guest CS limit. */
3420	uint32_t u32GuestCsLimit;
3421	/** 0x134 - Guest SS limit. */
3422	uint32_t u32GuestSsLimit;
3423	/** 0x138 - Guest DS limit. */
3424	uint32_t u32GuestDsLimit;
3425	/** 0x13c - Guest FS limit. */
3426	uint32_t u32GuestFsLimit;
3427	/** 0x140 - Guest GS limit. */
3428	uint32_t u32GuestGsLimit;
3429	/** 0x144 - Guest LDTR limit. */
3430	uint32_t u32GuestLdtrLimit;
3431	/** 0x148 - Guest TR limit. */
3432	uint32_t u32GuestTrLimit;
3433	/** 0x14c - Guest GDTR limit. */
3434	uint32_t u32GuestGdtrLimit;
3435	/** 0x150 - Guest IDTR limit. */
3436	uint32_t u32GuestIdtrLimit;
3437	/** 0x154 - Guest ES attributes. */
3438	uint32_t u32GuestEsAttr;
3439	/** 0x158 - Guest CS attributes. */
3440	uint32_t u32GuestCsAttr;
3441	/** 0x15c - Guest SS attributes. */
3442	uint32_t u32GuestSsAttr;
3443	/** 0x160 - Guest DS attributes. */
3444	uint32_t u32GuestDsAttr;
3445	/** 0x164 - Guest FS attributes. */
3446	uint32_t u32GuestFsAttr;
3447	/** 0x168 - Guest GS attributes. */
3448	uint32_t u32GuestGsAttr;
3449	/** 0x16c - Guest LDTR attributes. */
3450	uint32_t u32GuestLdtrAttr;
3451	/** 0x170 - Guest TR attributes. */
3452	uint32_t u32GuestTrAttr;
3453	/** 0x174 - Guest interruptibility state. */
3454	uint32_t u32GuestIntrState;
3455	/** 0x178 - Guest activity state. */
3456	uint32_t u32GuestActivityState;
3457	/** 0x17c - Guest SMBASE. */
3458	uint32_t u32GuestSmBase;
3459	/** 0x180 - Guest SYSENTER CS. */
3460	uint32_t u32GuestSysenterCS;
3461	/** 0x184 - Preemption timer value. */
3462	uint32_t u32PreemptTimer;
3463	/** 0x188 - Reserved for future. */
3464	uint32_t au32Reserved3[8];
3465	/** @} */
3466
3467	/** @name 32-bit Host-state fields.
3468	* @{ */
3469	/** 0x1a8 - Host SYSENTER CS. */
3470	uint32_t u32HostSysenterCs;
3471	/** 0x1ac - Reserved for future. */
3472	uint32_t au32Reserved4[11];
3473	/** @} */
3474
3475	/** @name 64-bit Control fields.
3476	* @{ */
3477	/** 0x1d8 - I/O bitmap A address. */
3478	RTUINT64U u64AddrIoBitmapA;
3479	/** 0x1e0 - I/O bitmap B address. */
3480	RTUINT64U u64AddrIoBitmapB;
3481	/** 0x1e8 - MSR bitmap address. */
3482	RTUINT64U u64AddrMsrBitmap;
3483	/** 0x1f0 - VM-exit MSR-store area address. */
3484	RTUINT64U u64AddrExitMsrStore;
3485	/** 0x1f8 - VM-exit MSR-load area address. */
3486	RTUINT64U u64AddrExitMsrLoad;
3487	/** 0x200 - VM-entry MSR-load area address. */
3488	RTUINT64U u64AddrEntryMsrLoad;
3489	/** 0x208 - Executive-VMCS pointer. */
3490	RTUINT64U u64ExecVmcsPtr;
3491	/** 0x210 - PML address. */
3492	RTUINT64U u64AddrPml;
3493	/** 0x218 - TSC offset. */
3494	RTUINT64U u64TscOffset;
3495	/** 0x220 - Virtual-APIC address. */
3496	RTUINT64U u64AddrVirtApic;
3497	/** 0x228 - APIC-access address. */
3498	RTUINT64U u64AddrApicAccess;
3499	/** 0x230 - Posted-interrupt descriptor address. */
3500	RTUINT64U u64AddrPostedIntDesc;
3501	/** 0x238 - VM-functions control. */
3502	RTUINT64U u64VmFuncCtls;
3503	/** 0x240 - EPTP pointer. */
3504	RTUINT64U u64EptpPtr;
3505	/** 0x248 - EOI-exit bitmap 0. */
3506	RTUINT64U u64EoiExitBitmap0;
3507	/** 0x250 - EOI-exit bitmap 1. */
3508	RTUINT64U u64EoiExitBitmap1;
3509	/** 0x258 - EOI-exit bitmap 2. */
3510	RTUINT64U u64EoiExitBitmap2;
3511	/** 0x260 - EOI-exit bitmap 3. */
3512	RTUINT64U u64EoiExitBitmap3;
3513	/** 0x268 - EPTP-list address. */
3514	RTUINT64U u64AddrEptpList;
3515	/** 0x270 - VMREAD-bitmap address. */
3516	RTUINT64U u64AddrVmreadBitmap;
3517	/** 0x278 - VMWRITE-bitmap address. */
3518	RTUINT64U u64AddrVmwriteBitmap;
3519	/** 0x280 - Virtualization-exception information address. */
3520	RTUINT64U u64AddrXcptVeInfo;
3521	/** 0x288 - XSS-exiting bitmap. */
3522	RTUINT64U u64XssBitmap;
3523	/** 0x290 - ENCLS-exiting bitmap address. */
3524	RTUINT64U u64AddrEnclsBitmap;
3525	/** 0x298 - TSC multiplier. */
3526	RTUINT64U u64TscMultiplier;
3527	/** 0x2a0 - Reserved for future. */
3528	RTUINT64U au64Reserved0[16];
3529	/** @} */
3530
3531	/** @name 64-bit Read-only Data fields.
3532	* @{ */
3533	/** 0x320 - Guest-physical address. */
3534	RTUINT64U u64RoGuestPhysAddr;
3535	/** 0x328 - Reserved for future. */
3536	RTUINT64U au64Reserved1[8];
3537	/** @} */
3538
3539	/** @name 64-bit Guest-state fields.
3540	* @{ */
3541	/** 0x368 - VMCS link pointer. */
3542	RTUINT64U u64VmcsLinkPtr;
3543	/** 0x370 - Guest debug-control MSR. */
3544	RTUINT64U u64GuestDebugCtlMsr;
3545	/** 0x378 - Guest PAT MSR. */
3546	RTUINT64U u64GuestPatMsr;
3547	/** 0x380 - Guest EFER MSR. */
3548	RTUINT64U u64GuestEferMsr;
3549	/** 0x388 - Guest global performance-control MSR. */
3550	RTUINT64U u64GuestPerfGlobalCtlMsr;
3551	/** 0x390 - Guest PDPTE 0. */
3552	RTUINT64U u64GuestPdpte0;
3553	/** 0x398 - Guest PDPTE 0. */
3554	RTUINT64U u64GuestPdpte1;
3555	/** 0x3a0 - Guest PDPTE 1. */
3556	RTUINT64U u64GuestPdpte2;
3557	/** 0x3a8 - Guest PDPTE 2. */
3558	RTUINT64U u64GuestPdpte3;
3559	/** 0x3b0 - Guest Bounds-config MSR (Intel MPX - Memory Protection Extensions). */
3560	RTUINT64U u64GuestBndcfgsMsr;
3561	/** 0x3b8 - Reserved for future. */
3562	RTUINT64U au64Reserved2[16];
3563	/** @} */
3564
3565	/** @name 64-bit Host-state Fields.
3566	* @{ */
3567	/** 0x438 - Host PAT MSR. */
3568	RTUINT64U u64HostPatMsr;
3569	/** 0x440 - Host EFER MSR. */
3570	RTUINT64U u64HostEferMsr;
3571	/** 0x448 - Host global performance-control MSR. */
3572	RTUINT64U u64HostPerfGlobalCtlMsr;
3573	/** 0x450 - Reserved for future. */
3574	RTUINT64U au64Reserved3[16];
3575	/** @} */
3576
3577	/** @name Natural-width Control fields.
3578	* @{ */
3579	/** 0x4d0 - CR0 guest/host Mask. */
3580	RTUINT64U u64Cr0Mask;
3581	/** 0x4d8 - CR4 guest/host Mask. */
3582	RTUINT64U u64Cr4Mask;
3583	/** 0x4e0 - CR0 read shadow. */
3584	RTUINT64U u64Cr0ReadShadow;
3585	/** 0x4e8 - CR4 read shadow. */
3586	RTUINT64U u64Cr4ReadShadow;
3587	/** 0x4f0 - CR3-target value 0. */
3588	RTUINT64U u64Cr3Target0;
3589	/** 0x4f8 - CR3-target value 1. */
3590	RTUINT64U u64Cr3Target1;
3591	/** 0x500 - CR3-target value 2. */
3592	RTUINT64U u64Cr3Target2;
3593	/** 0x508 - CR3-target value 3. */
3594	RTUINT64U u64Cr3Target3;
3595	/** 0x510 - Reserved for future. */
3596	RTUINT64U au64Reserved4[32];
3597	/** @} */
3598
3599	/** @name Natural-width Read-only Data fields. */
3600	/** 0x610 - Exit qualification. */
3601	RTUINT64U u64RoExitQual;
3602	/** 0x618 - I/O RCX. */
3603	RTUINT64U u64RoIoRcx;
3604	/** 0x620 - I/O RSI. */
3605	RTUINT64U u64RoIoRsi;
3606	/** 0x628 - I/O RDI. */
3607	RTUINT64U u64RoIoRdi;
3608	/** 0x630 - I/O RIP. */
3609	RTUINT64U u64RoIoRip;
3610	/** 0x638 - Guest-linear address. */
3611	RTUINT64U u64RoGuestLinearAddr;
3612	/** 0x640 - Reserved for future. */
3613	RTUINT64U au64Reserved5[16];
3614	/** @} */
3615
3616	/** @name Natural-width Guest-state Fields.
3617	* Order of [ES..GS] base is important, must match X86_SREG_XXX.
3618	* @{ */
3619	/** 0x6c0 - Guest CR0. */
3620	RTUINT64U u64GuestCr0;
3621	/** 0x6c8 - Guest CR3. */
3622	RTUINT64U u64GuestCr3;
3623	/** 0x6d0 - Guest CR4. */
3624	RTUINT64U u64GuestCr4;
3625	/** 0x6d8 - Guest ES base. */
3626	RTUINT64U u64GuestEsBase;
3627	/** 0x6e0 - Guest CS base. */
3628	RTUINT64U u64GuestCsBase;
3629	/** 0x6e8 - Guest SS base. */
3630	RTUINT64U u64GuestSsBase;
3631	/** 0x6f0 - Guest DS base. */
3632	RTUINT64U u64GuestDsBase;
3633	/** 0x6f8 - Guest FS base. */
3634	RTUINT64U u64GuestFsBase;
3635	/** 0x700 - Guest GS base. */
3636	RTUINT64U u64GuestGsBase;
3637	/** 0x708 - Guest LDTR base. */
3638	RTUINT64U u64GuestLdtrBase;
3639	/** 0x710 - Guest TR base. */
3640	RTUINT64U u64GuestTrBase;
3641	/** 0x718 - Guest GDTR base. */
3642	RTUINT64U u64GuestGdtrBase;
3643	/** 0x720 - Guest IDTR base. */
3644	RTUINT64U u64GuestIdtrBase;
3645	/** 0x728 - Guest DR7. */
3646	RTUINT64U u64GuestDr7;
3647	/** 0x730 - Guest RSP. */
3648	RTUINT64U u64GuestRsp;
3649	/** 0x738 - Guest RIP. */
3650	RTUINT64U u64GuestRip;
3651	/** 0x740 - Guest RFLAGS. */
3652	RTUINT64U u64GuestRFlags;
3653	/** 0x748 - Guest pending debug exception. */
3654	RTUINT64U u64GuestPendingDbgXcpt;
3655	/** 0x750 - Guest SYSENTER ESP. */
3656	RTUINT64U u64GuestSysenterEsp;
3657	/** 0x758 - Guest SYSENTER EIP. */
3658	RTUINT64U u64GuestSysenterEip;
3659	/** 0x760 - Reserved for future. */
3660	RTUINT64U au64Reserved6[32];
3661	/** @} */
3662
3663	/** @name Natural-width Host-state fields.
3664	* @{ */
3665	/** 0x860 - Host CR0. */
3666	RTUINT64U u64HostCr0;
3667	/** 0x868 - Host CR3. */
3668	RTUINT64U u64HostCr3;
3669	/** 0x870 - Host CR4. */
3670	RTUINT64U u64HostCr4;
3671	/** 0x878 - Host FS base. */
3672	RTUINT64U u64HostFsBase;
3673	/** 0x880 - Host GS base. */
3674	RTUINT64U u64HostGsBase;
3675	/** 0x888 - Host TR base. */
3676	RTUINT64U u64HostTrBase;
3677	/** 0x890 - Host GDTR base. */
3678	RTUINT64U u64HostGdtrBase;
3679	/** 0x898 - Host IDTR base. */
3680	RTUINT64U u64HostIdtrBase;
3681	/** 0x8a0 - Host SYSENTER ESP base. */
3682	RTUINT64U u64HostSysenterEsp;
3683	/** 0x8a8 - Host SYSENTER ESP base. */
3684	RTUINT64U u64HostSysenterEip;
3685	/** 0x8b0 - Host RSP. */
3686	RTUINT64U u64HostRsp;
3687	/** 0x8b8 - Host RIP. */
3688	RTUINT64U u64HostRip;
3689	/** 0x8c0 - Reserved for future. */
3690	RTUINT64U au64Reserved7[32];
3691	/** @} */
3692
3693	/** 0x9c0 - Padding. */
3694	uint8_t abPadding[X86_PAGE_4K_SIZE - 0x9c0];
3695	} VMXVVMCS;
3696	#pragma pack()
3697	/** Pointer to the VMXVVMCS struct. */
3698	typedef VMXVVMCS *PVMXVVMCS;
3699	/** Pointer to a const VMXVVMCS struct. */
3700	typedef const VMXVVMCS *PCVMXVVMCS;
3701	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
3702	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
3703	AssertCompileMemberOffset(VMXVVMCS, u32VmxAbortId, 0x004);
3704	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
3705	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x028);
3706	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x03e);
3707	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x062);
3708	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x084);
3709	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x0ec);
3710	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x12c);
3711	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x1a8);
3712	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x1d8);
3713	AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x320);
3714	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x368);
3715	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x438);
3716	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x4d0);
3717	AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual, 0x610);
3718	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x6c0);
3719	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x860);
3720	/** @} */
3721
3722	/**
3723	* Virtual VMX-instruction and VM-exit diagnostics.
3724	*
3725	* These are not the same as VM instruction errors that are enumerated in the Intel
3726	* spec. These are purely internal, fine-grained definitions used for diagnostic
3727	* purposes and are not reported to guest software under the VM-instruction error
3728	* field in its VMCS.
3729	*
3730	* @note Members of this enum are used as array indices, so no gaps are allowed.
3731	* Please update g_apszVmxInstrDiagDesc when you add new fields to this
3732	* enum.
3733	*/
3734	typedef enum
3735	{
3736	/* Internal processing errors. */
3737	kVmxVDiag_None = 0,
3738	kVmxVDiag_Ipe_1,
3739	kVmxVDiag_Ipe_2,
3740	kVmxVDiag_Ipe_3,
3741	kVmxVDiag_Ipe_4,
3742	kVmxVDiag_Ipe_5,
3743	kVmxVDiag_Ipe_6,
3744	kVmxVDiag_Ipe_7,
3745	kVmxVDiag_Ipe_8,
3746	kVmxVDiag_Ipe_9,
3747	kVmxVDiag_Ipe_10,
3748	kVmxVDiag_Ipe_11,
3749	kVmxVDiag_Ipe_12,
3750	kVmxVDiag_Ipe_13,
3751	kVmxVDiag_Ipe_14,
3752	kVmxVDiag_Ipe_15,
3753	kVmxVDiag_Ipe_16,
3754	/* VMXON. */
3755	kVmxVDiag_Vmxon_A20M,
3756	kVmxVDiag_Vmxon_Cpl,
3757	kVmxVDiag_Vmxon_Cr0Fixed0,
3758	kVmxVDiag_Vmxon_Cr0Fixed1,
3759	kVmxVDiag_Vmxon_Cr4Fixed0,
3760	kVmxVDiag_Vmxon_Cr4Fixed1,
3761	kVmxVDiag_Vmxon_Intercept,
3762	kVmxVDiag_Vmxon_LongModeCS,
3763	kVmxVDiag_Vmxon_MsrFeatCtl,
3764	kVmxVDiag_Vmxon_PtrAbnormal,
3765	kVmxVDiag_Vmxon_PtrAlign,
3766	kVmxVDiag_Vmxon_PtrMap,
3767	kVmxVDiag_Vmxon_PtrReadPhys,
3768	kVmxVDiag_Vmxon_PtrWidth,
3769	kVmxVDiag_Vmxon_RealOrV86Mode,
3770	kVmxVDiag_Vmxon_ShadowVmcs,
3771	kVmxVDiag_Vmxon_VmxAlreadyRoot,
3772	kVmxVDiag_Vmxon_Vmxe,
3773	kVmxVDiag_Vmxon_VmcsRevId,
3774	kVmxVDiag_Vmxon_VmxRootCpl,
3775	/* VMXOFF. */
3776	kVmxVDiag_Vmxoff_Cpl,
3777	kVmxVDiag_Vmxoff_Intercept,
3778	kVmxVDiag_Vmxoff_LongModeCS,
3779	kVmxVDiag_Vmxoff_RealOrV86Mode,
3780	kVmxVDiag_Vmxoff_Vmxe,
3781	kVmxVDiag_Vmxoff_VmxRoot,
3782	/* VMPTRLD. */
3783	kVmxVDiag_Vmptrld_Cpl,
3784	kVmxVDiag_Vmptrld_LongModeCS,
3785	kVmxVDiag_Vmptrld_PtrAbnormal,
3786	kVmxVDiag_Vmptrld_PtrAlign,
3787	kVmxVDiag_Vmptrld_PtrMap,
3788	kVmxVDiag_Vmptrld_PtrReadPhys,
3789	kVmxVDiag_Vmptrld_PtrVmxon,
3790	kVmxVDiag_Vmptrld_PtrWidth,
3791	kVmxVDiag_Vmptrld_RealOrV86Mode,
3792	kVmxVDiag_Vmptrld_ShadowVmcs,
3793	kVmxVDiag_Vmptrld_VmcsRevId,
3794	kVmxVDiag_Vmptrld_VmxRoot,
3795	/* VMPTRST. */
3796	kVmxVDiag_Vmptrst_Cpl,
3797	kVmxVDiag_Vmptrst_LongModeCS,
3798	kVmxVDiag_Vmptrst_PtrMap,
3799	kVmxVDiag_Vmptrst_RealOrV86Mode,
3800	kVmxVDiag_Vmptrst_VmxRoot,
3801	/* VMCLEAR. */
3802	kVmxVDiag_Vmclear_Cpl,
3803	kVmxVDiag_Vmclear_LongModeCS,
3804	kVmxVDiag_Vmclear_PtrAbnormal,
3805	kVmxVDiag_Vmclear_PtrAlign,
3806	kVmxVDiag_Vmclear_PtrMap,
3807	kVmxVDiag_Vmclear_PtrReadPhys,
3808	kVmxVDiag_Vmclear_PtrVmxon,
3809	kVmxVDiag_Vmclear_PtrWidth,
3810	kVmxVDiag_Vmclear_RealOrV86Mode,
3811	kVmxVDiag_Vmclear_VmxRoot,
3812	/* VMWRITE. */
3813	kVmxVDiag_Vmwrite_Cpl,
3814	kVmxVDiag_Vmwrite_FieldInvalid,
3815	kVmxVDiag_Vmwrite_FieldRo,
3816	kVmxVDiag_Vmwrite_LinkPtrInvalid,
3817	kVmxVDiag_Vmwrite_LongModeCS,
3818	kVmxVDiag_Vmwrite_PtrInvalid,
3819	kVmxVDiag_Vmwrite_PtrMap,
3820	kVmxVDiag_Vmwrite_RealOrV86Mode,
3821	kVmxVDiag_Vmwrite_VmxRoot,
3822	/* VMREAD. */
3823	kVmxVDiag_Vmread_Cpl,
3824	kVmxVDiag_Vmread_FieldInvalid,
3825	kVmxVDiag_Vmread_LinkPtrInvalid,
3826	kVmxVDiag_Vmread_LongModeCS,
3827	kVmxVDiag_Vmread_PtrInvalid,
3828	kVmxVDiag_Vmread_PtrMap,
3829	kVmxVDiag_Vmread_RealOrV86Mode,
3830	kVmxVDiag_Vmread_VmxRoot,
3831	/* VMLAUNCH/VMRESUME. */
3832	kVmxVDiag_Vmentry_AddrApicAccess,
3833	kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
3834	kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
3835	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
3836	kVmxVDiag_Vmentry_AddrExitMsrLoad,
3837	kVmxVDiag_Vmentry_AddrExitMsrStore,
3838	kVmxVDiag_Vmentry_AddrIoBitmapA,
3839	kVmxVDiag_Vmentry_AddrIoBitmapB,
3840	kVmxVDiag_Vmentry_AddrMsrBitmap,
3841	kVmxVDiag_Vmentry_AddrVirtApicPage,
3842	kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
3843	kVmxVDiag_Vmentry_AddrVmreadBitmap,
3844	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
3845	kVmxVDiag_Vmentry_ApicRegVirt,
3846	kVmxVDiag_Vmentry_BlocKMovSS,
3847	kVmxVDiag_Vmentry_Cpl,
3848	kVmxVDiag_Vmentry_Cr3TargetCount,
3849	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
3850	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
3851	kVmxVDiag_Vmentry_EntryInstrLen,
3852	kVmxVDiag_Vmentry_EntryInstrLenZero,
3853	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
3854	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
3855	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
3856	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
3857	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
3858	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
3859	kVmxVDiag_Vmentry_GuestActStateHlt,
3860	kVmxVDiag_Vmentry_GuestActStateRsvd,
3861	kVmxVDiag_Vmentry_GuestActStateShutdown,
3862	kVmxVDiag_Vmentry_GuestActStateSsDpl,
3863	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
3864	kVmxVDiag_Vmentry_GuestCr0Fixed0,
3865	kVmxVDiag_Vmentry_GuestCr0Fixed1,
3866	kVmxVDiag_Vmentry_GuestCr0PgPe,
3867	kVmxVDiag_Vmentry_GuestCr3,
3868	kVmxVDiag_Vmentry_GuestCr4Fixed0,
3869	kVmxVDiag_Vmentry_GuestCr4Fixed1,
3870	kVmxVDiag_Vmentry_GuestDebugCtl,
3871	kVmxVDiag_Vmentry_GuestDr7,
3872	kVmxVDiag_Vmentry_GuestEferMsr,
3873	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
3874	kVmxVDiag_Vmentry_GuestGdtrBase,
3875	kVmxVDiag_Vmentry_GuestGdtrLimit,
3876	kVmxVDiag_Vmentry_GuestIdtrBase,
3877	kVmxVDiag_Vmentry_GuestIdtrLimit,
3878	kVmxVDiag_Vmentry_GuestIntStateEnclave,
3879	kVmxVDiag_Vmentry_GuestIntStateExtInt,
3880	kVmxVDiag_Vmentry_GuestIntStateNmi,
3881	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
3882	kVmxVDiag_Vmentry_GuestIntStateRsvd,
3883	kVmxVDiag_Vmentry_GuestIntStateSmi,
3884	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
3885	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
3886	kVmxVDiag_Vmentry_GuestPae,
3887	kVmxVDiag_Vmentry_GuestPatMsr,
3888	kVmxVDiag_Vmentry_GuestPcide,
3889	kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys,
3890	kVmxVDiag_Vmentry_GuestPdpte0Rsvd,
3891	kVmxVDiag_Vmentry_GuestPdpte1Rsvd,
3892	kVmxVDiag_Vmentry_GuestPdpte2Rsvd,
3893	kVmxVDiag_Vmentry_GuestPdpte3Rsvd,
3894	kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
3895	kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
3896	kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
3897	kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
3898	kVmxVDiag_Vmentry_GuestRip,
3899	kVmxVDiag_Vmentry_GuestRipRsvd,
3900	kVmxVDiag_Vmentry_GuestRFlagsIf,
3901	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
3902	kVmxVDiag_Vmentry_GuestRFlagsVm,
3903	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
3904	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
3905	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
3906	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
3907	kVmxVDiag_Vmentry_GuestSegAttrCsType,
3908	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
3909	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
3910	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
3911	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
3912	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
3913	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
3914	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
3915	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
3916	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
3917	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
3918	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
3919	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
3920	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
3921	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
3922	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
3923	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
3924	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
3925	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
3926	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
3927	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
3928	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
3929	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
3930	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
3931	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
3932	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
3933	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
3934	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
3935	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
3936	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
3937	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
3938	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
3939	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
3940	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
3941	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
3942	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
3943	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
3944	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
3945	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
3946	kVmxVDiag_Vmentry_GuestSegAttrSsType,
3947	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
3948	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
3949	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
3950	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
3951	kVmxVDiag_Vmentry_GuestSegAttrTrType,
3952	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
3953	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
3954	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
3955	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
3956	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
3957	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
3958	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
3959	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
3960	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
3961	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
3962	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
3963	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
3964	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
3965	kVmxVDiag_Vmentry_GuestSegBaseCs,
3966	kVmxVDiag_Vmentry_GuestSegBaseDs,
3967	kVmxVDiag_Vmentry_GuestSegBaseEs,
3968	kVmxVDiag_Vmentry_GuestSegBaseFs,
3969	kVmxVDiag_Vmentry_GuestSegBaseGs,
3970	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
3971	kVmxVDiag_Vmentry_GuestSegBaseSs,
3972	kVmxVDiag_Vmentry_GuestSegBaseTr,
3973	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
3974	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
3975	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
3976	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
3977	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
3978	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
3979	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
3980	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
3981	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
3982	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
3983	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
3984	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
3985	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
3986	kVmxVDiag_Vmentry_GuestSegSelLdtr,
3987	kVmxVDiag_Vmentry_GuestSegSelTr,
3988	kVmxVDiag_Vmentry_GuestSysenterEspEip,
3989	kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
3990	kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
3991	kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
3992	kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
3993	kVmxVDiag_Vmentry_HostCr0Fixed0,
3994	kVmxVDiag_Vmentry_HostCr0Fixed1,
3995	kVmxVDiag_Vmentry_HostCr3,
3996	kVmxVDiag_Vmentry_HostCr4Fixed0,
3997	kVmxVDiag_Vmentry_HostCr4Fixed1,
3998	kVmxVDiag_Vmentry_HostCr4Pae,
3999	kVmxVDiag_Vmentry_HostCr4Pcide,
4000	kVmxVDiag_Vmentry_HostCsTr,
4001	kVmxVDiag_Vmentry_HostEferMsr,
4002	kVmxVDiag_Vmentry_HostEferMsrRsvd,
4003	kVmxVDiag_Vmentry_HostGuestLongMode,
4004	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
4005	kVmxVDiag_Vmentry_HostLongMode,
4006	kVmxVDiag_Vmentry_HostPatMsr,
4007	kVmxVDiag_Vmentry_HostRip,
4008	kVmxVDiag_Vmentry_HostRipRsvd,
4009	kVmxVDiag_Vmentry_HostSel,
4010	kVmxVDiag_Vmentry_HostSegBase,
4011	kVmxVDiag_Vmentry_HostSs,
4012	kVmxVDiag_Vmentry_HostSysenterEspEip,
4013	kVmxVDiag_Vmentry_LongModeCS,
4014	kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
4015	kVmxVDiag_Vmentry_MsrLoad,
4016	kVmxVDiag_Vmentry_MsrLoadCount,
4017	kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
4018	kVmxVDiag_Vmentry_MsrLoadRing3,
4019	kVmxVDiag_Vmentry_MsrLoadRsvd,
4020	kVmxVDiag_Vmentry_NmiWindowExit,
4021	kVmxVDiag_Vmentry_PinCtlsAllowed1,
4022	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
4023	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
4024	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
4025	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
4026	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
4027	kVmxVDiag_Vmentry_PtrInvalid,
4028	kVmxVDiag_Vmentry_PtrReadPhys,
4029	kVmxVDiag_Vmentry_RealOrV86Mode,
4030	kVmxVDiag_Vmentry_SavePreemptTimer,
4031	kVmxVDiag_Vmentry_TprThresholdRsvd,
4032	kVmxVDiag_Vmentry_TprThresholdVTpr,
4033	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
4034	kVmxVDiag_Vmentry_VirtIntDelivery,
4035	kVmxVDiag_Vmentry_VirtNmi,
4036	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
4037	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
4038	kVmxVDiag_Vmentry_VmcsClear,
4039	kVmxVDiag_Vmentry_VmcsLaunch,
4040	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
4041	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
4042	kVmxVDiag_Vmentry_VmxRoot,
4043	kVmxVDiag_Vmentry_Vpid,
4044	kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys,
4045	kVmxVDiag_Vmexit_HostPdpte0Rsvd,
4046	kVmxVDiag_Vmexit_HostPdpte1Rsvd,
4047	kVmxVDiag_Vmexit_HostPdpte2Rsvd,
4048	kVmxVDiag_Vmexit_HostPdpte3Rsvd,
4049	kVmxVDiag_Vmexit_MsrLoad,
4050	kVmxVDiag_Vmexit_MsrLoadCount,
4051	kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
4052	kVmxVDiag_Vmexit_MsrLoadRing3,
4053	kVmxVDiag_Vmexit_MsrLoadRsvd,
4054	kVmxVDiag_Vmexit_MsrStore,
4055	kVmxVDiag_Vmexit_MsrStoreCount,
4056	kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
4057	kVmxVDiag_Vmexit_MsrStoreRing3,
4058	kVmxVDiag_Vmexit_MsrStoreRsvd,
4059	/* Last member for determining array index limit. */
4060	kVmxVDiag_End
4061	} VMXVDIAG;
4062	AssertCompileSize(VMXVDIAG, 4);
4063
4064
4065	/** @defgroup grp_hm_vmx_c VMX C Helpers
4066	*
4067	* These are functions that strictly only implement VT-x functionality that is in
4068	* accordance to the VT-X spec. and thus fit to use by IEM/REM/HM.
4069	*
4070	* These are not HM all-context API functions, those are to be placed in hm.h.
4071	* @{
4072	*/
4073	VMM_INT_DECL(int) HMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead,
4074	PVMXMSREXITWRITE penmWrite);
4075	VMM_INT_DECL(bool) HMVmxGetIoBitmapPermission(void const pvIoBitmapA, void const pvIoBitmapB, uint16_t uPort,
4076	uint8_t cbAccess);
4077	/** @} */
4078
4079
4080	/** @} */
4081
4082	#endif
4083

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 76402

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