VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 47999

Last change on this file since 47999 was 47999, checked in by vboxsync, 12 years ago

VMM/HM: Better error reporting for unsupported VT-x feature combos.
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1/** @file
2 * HM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2013 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_vmx_h
27#define ___VBox_vmm_vmx_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/x86.h>
32#include <iprt/assert.h>
33
34/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35 when targeting AMD64. */
36#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37# include <intrin.h>
38/* We always want them as intrinsics, no functions. */
39# pragma intrinsic(__vmx_on)
40# pragma intrinsic(__vmx_off)
41# pragma intrinsic(__vmx_vmclear)
42# pragma intrinsic(__vmx_vmptrld)
43# pragma intrinsic(__vmx_vmread)
44# pragma intrinsic(__vmx_vmwrite)
45# define VMX_USE_MSC_INTRINSICS 1
46#else
47# define VMX_USE_MSC_INTRINSICS 0
48#endif
49
50
51/** @defgroup grp_vmx vmx Types and Definitions
52 * @ingroup grp_hm
53 * @{
54 */
55
56/** @name Host-state restoration flags.
57 * @{
58 */
59/* If you change these values don't forget to update the assembly defines as well! */
60#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
61#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
62#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
63#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
64#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
65#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
66#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
67/** @} */
68
69/**
70 * Host-state restoration structure.
71 * This holds host-state fields that require manual restoration.
72 * Assembly version found in hm_vmx.mac (should be automatically verified).
73 */
74typedef struct VMXRESTOREHOST
75{
76 RTSEL uHostSelDS; /* 0x00 */
77 RTSEL uHostSelES; /* 0x02 */
78 RTSEL uHostSelFS; /* 0x04 */
79 RTSEL uHostSelGS; /* 0x06 */
80 RTSEL uHostSelTR; /* 0x08 */
81 uint8_t abPadding0[4];
82 X86XDTR64 HostGdtr; /**< 0x0e - should be aligned by it's 64-bit member. */
83 uint8_t abPadding1[6];
84 X86XDTR64 HostIdtr; /**< 0x1e - should be aligned by it's 64-bit member. */
85 uint64_t uHostFSBase; /* 0x28 */
86 uint64_t uHostGSBase; /* 0x30 */
87} VMXRESTOREHOST;
88/** Pointer to VMXRESTOREHOST. */
89typedef VMXRESTOREHOST *PVMXRESTOREHOST;
90AssertCompileSize(X86XDTR64, 10);
91AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
92AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
93AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
94AssertCompileSize(VMXRESTOREHOST, 56);
95
96/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
97 * UFC = Unsupported Feature Combination.
98 * @{
99 */
100/** Unsupported pin-based VM-execution controls combo. */
101#define VMX_UFC_CTRL_PIN_EXEC 0
102/** Unsupported processor-based VM-execution controls combo. */
103#define VMX_UFC_CTRL_PROC_EXEC 1
104/** Unsupported pin-based VM-execution controls combo. */
105#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 2
106/** Unsupported VM-entry controls combo. */
107#define VMX_UFC_CTRL_ENTRY 3
108/** Unsupported VM-exit controls combo. */
109#define VMX_UFC_CTRL_EXIT 4
110/** MSR storage capacity of the VMCS autoload/store area is not sufficient
111 * for storing host MSRs. */
112#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 5
113/** MSR storage capacity of the VMCS autoload/store area is not sufficient
114 * for storing guest MSRs. */
115#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 6
116/** @} */
117
118/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
119 * IGS = Invalid Guest State.
120 * @{
121 */
122/** An error occurred while checking invalid-guest-state. */
123#define VMX_IGS_ERROR 0
124/** The invalid guest-state checks did not find any reason why. */
125#define VMX_IGS_REASON_NOT_FOUND 1
126/** CR0 fixed1 bits invalid. */
127#define VMX_IGS_CR0_FIXED1 2
128/** CR0 fixed0 bits invalid. */
129#define VMX_IGS_CR0_FIXED0 3
130/** CR0.PE and CR0.PE invalid VT-x/host combination. */
131#define VMX_IGS_CR0_PG_PE_COMBO 4
132/** CR4 fixed1 bits invalid. */
133#define VMX_IGS_CR4_FIXED1 5
134/** CR4 fixed0 bits invalid. */
135#define VMX_IGS_CR4_FIXED0 6
136/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
137 * VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
138#define VMX_IGS_DEBUGCTL_MSR_RESERVED 7
139/** CR0.PG not set for long-mode when not using unrestricted guest. */
140#define VMX_IGS_CR0_PG_LONGMODE 8
141/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
142#define VMX_IGS_CR4_PAE_LONGMODE 9
143/** CR4.PCIDE set for 32-bit guest. */
144#define VMX_IGS_CR4_PCIDE 10
145/** VMCS' DR7 reserved bits not set to 0. */
146#define VMX_IGS_DR7_RESERVED 11
147/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
148#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 12
149/** VMCS' EFER MSR reserved bits not set to 0. */
150#define VMX_IGS_EFER_MSR_RESERVED 13
151/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
152#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 14
153/** VMCS' EFER MSR.LMA does not match CR0.PG of the guest when not using
154 * unrestricted guest. */
155#define VMX_IGS_EFER_LMA_PG_MISMATCH 15
156/** CS.Attr.P bit invalid. */
157#define VMX_IGS_CS_ATTR_P_INVALID 16
158/** CS.Attr reserved bits not set to 0. */
159#define VMX_IGS_CS_ATTR_RESERVED 17
160/** CS.Attr.G bit invalid. */
161#define VMX_IGS_CS_ATTR_G_INVALID 18
162/** CS is unusable. */
163#define VMX_IGS_CS_ATTR_UNUSABLE 19
164/** CS and SS DPL unequal. */
165#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 20
166/** CS and SS DPL mismatch. */
167#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 21
168/** CS Attr.Type invalid. */
169#define VMX_IGS_CS_ATTR_TYPE_INVALID 22
170/** CS and SS RPL unequal. */
171#define VMX_IGS_SS_CS_RPL_UNEQUAL 23
172/** SS.Attr.DPL and SS RPL unequal. */
173#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 24
174/** SS.Attr.DPL invalid for segment type. */
175#define VMX_IGS_SS_ATTR_DPL_INVALID 25
176/** SS.Attr.Type invalid. */
177#define VMX_IGS_SS_ATTR_TYPE_INVALID 26
178/** SS.Attr.P bit invalid. */
179#define VMX_IGS_SS_ATTR_P_INVALID 27
180/** SS.Attr reserved bits not set to 0. */
181#define VMX_IGS_SS_ATTR_RESERVED 28
182/** SS.Attr.G bit invalid. */
183#define VMX_IGS_SS_ATTR_G_INVALID 29
184/** DS.Attr.A bit invalid. */
185#define VMX_IGS_DS_ATTR_A_INVALID 30
186/** DS.Attr.P bit invalid. */
187#define VMX_IGS_DS_ATTR_P_INVALID 31
188/** DS.Attr.DPL and DS RPL unequal. */
189#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 32
190/** DS.Attr reserved bits not set to 0. */
191#define VMX_IGS_DS_ATTR_RESERVED 33
192/** DS.Attr.G bit invalid. */
193#define VMX_IGS_DS_ATTR_G_INVALID 34
194/** DS.Attr.Type invalid. */
195#define VMX_IGS_DS_ATTR_TYPE_INVALID 35
196/** ES.Attr.A bit invalid. */
197#define VMX_IGS_ES_ATTR_A_INVALID 36
198/** ES.Attr.P bit invalid. */
199#define VMX_IGS_ES_ATTR_P_INVALID 37
200/** ES.Attr.DPL and DS RPL unequal. */
201#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 38
202/** ES.Attr reserved bits not set to 0. */
203#define VMX_IGS_ES_ATTR_RESERVED 39
204/** ES.Attr.G bit invalid. */
205#define VMX_IGS_ES_ATTR_G_INVALID 40
206/** ES.Attr.Type invalid. */
207#define VMX_IGS_ES_ATTR_TYPE_INVALID 41
208/** FS.Attr.A bit invalid. */
209#define VMX_IGS_FS_ATTR_A_INVALID 42
210/** FS.Attr.P bit invalid. */
211#define VMX_IGS_FS_ATTR_P_INVALID 43
212/** FS.Attr.DPL and DS RPL unequal. */
213#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 44
214/** FS.Attr reserved bits not set to 0. */
215#define VMX_IGS_FS_ATTR_RESERVED 45
216/** FS.Attr.G bit invalid. */
217#define VMX_IGS_FS_ATTR_G_INVALID 46
218/** FS.Attr.Type invalid. */
219#define VMX_IGS_FS_ATTR_TYPE_INVALID 47
220/** GS.Attr.A bit invalid. */
221#define VMX_IGS_GS_ATTR_A_INVALID 48
222/** GS.Attr.P bit invalid. */
223#define VMX_IGS_GS_ATTR_P_INVALID 49
224/** GS.Attr.DPL and DS RPL unequal. */
225#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 50
226/** GS.Attr reserved bits not set to 0. */
227#define VMX_IGS_GS_ATTR_RESERVED 51
228/** GS.Attr.G bit invalid. */
229#define VMX_IGS_GS_ATTR_G_INVALID 52
230/** GS.Attr.Type invalid. */
231#define VMX_IGS_GS_ATTR_TYPE_INVALID 53
232/** V86 mode CS.Base invalid. */
233#define VMX_IGS_V86_CS_BASE_INVALID 54
234/** V86 mode CS.Limit invalid. */
235#define VMX_IGS_V86_CS_LIMIT_INVALID 55
236/** V86 mode CS.Attr invalid. */
237#define VMX_IGS_V86_CS_ATTR_INVALID 56
238/** V86 mode SS.Base invalid. */
239#define VMX_IGS_V86_SS_BASE_INVALID 57
240/** V86 mode SS.Limit invalid. */
241#define VMX_IGS_V86_SS_LIMIT_INVALID 59
242/** V86 mode SS.Attr invalid. */
243#define VMX_IGS_V86_SS_ATTR_INVALID 59
244/** V86 mode DS.Base invalid. */
245#define VMX_IGS_V86_DS_BASE_INVALID 60
246/** V86 mode DS.Limit invalid. */
247#define VMX_IGS_V86_DS_LIMIT_INVALID 61
248/** V86 mode DS.Attr invalid. */
249#define VMX_IGS_V86_DS_ATTR_INVALID 62
250/** V86 mode ES.Base invalid. */
251#define VMX_IGS_V86_ES_BASE_INVALID 63
252/** V86 mode ES.Limit invalid. */
253#define VMX_IGS_V86_ES_LIMIT_INVALID 64
254/** V86 mode ES.Attr invalid. */
255#define VMX_IGS_V86_ES_ATTR_INVALID 65
256/** V86 mode FS.Base invalid. */
257#define VMX_IGS_V86_FS_BASE_INVALID 66
258/** V86 mode FS.Limit invalid. */
259#define VMX_IGS_V86_FS_LIMIT_INVALID 67
260/** V86 mode FS.Attr invalid. */
261#define VMX_IGS_V86_FS_ATTR_INVALID 68
262/** V86 mode GS.Base invalid. */
263#define VMX_IGS_V86_GS_BASE_INVALID 69
264/** V86 mode GS.Limit invalid. */
265#define VMX_IGS_V86_GS_LIMIT_INVALID 70
266/** V86 mode GS.Attr invalid. */
267#define VMX_IGS_V86_GS_ATTR_INVALID 71
268/** Longmode CS.Base invalid. */
269#define VMX_IGS_LONGMODE_CS_BASE_INVALID 72
270/** Longmode SS.Base invalid. */
271#define VMX_IGS_LONGMODE_SS_BASE_INVALID 73
272/** Longmode DS.Base invalid. */
273#define VMX_IGS_LONGMODE_DS_BASE_INVALID 74
274/** Longmode ES.Base invalid. */
275#define VMX_IGS_LONGMODE_ES_BASE_INVALID 75
276/** SYSENTER ESP is not canonical. */
277#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 76
278/** SYSENTER EIP is not canonical. */
279#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 77
280/** PAT MSR invalid. */
281#define VMX_IGS_PAT_MSR_INVALID 78
282/** PAT MSR reserved bits not set to 0. */
283#define VMX_IGS_PAT_MSR_RESERVED 79
284/** GDTR.Base is not canonical. */
285#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 80
286/** IDTR.Base is not canonical. */
287#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 81
288/** GDTR.Limit invalid. */
289#define VMX_IGS_GDTR_LIMIT_INVALID 82
290/** IDTR.Limit invalid. */
291#define VMX_IGS_IDTR_LIMIT_INVALID 83
292/** Longmode RIP is invalid. */
293#define VMX_IGS_LONGMODE_RIP_INVALID 84
294/** RFLAGS reserved bits not set to 0. */
295#define VMX_IGS_RFLAGS_RESERVED 85
296/** RFLAGS RA1 reserved bits not set to 1. */
297#define VMX_IGS_RFLAGS_RESERVED1 86
298/** RFLAGS.VM (V86 mode) invalid. */
299#define VMX_IGS_RFLAGS_VM_INVALID 87
300/** RFLAGS.IF invalid. */
301#define VMX_IGS_RFLAGS_IF_INVALID 88
302/** Activity state invalid. */
303#define VMX_IGS_ACTIVITY_STATE_INVALID 89
304/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
305#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 90
306/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
307#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 91
308/** Activity state SIPI WAIT invalid. */
309#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 92
310/** Interruptibility state reserved bits not set to 0. */
311#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 93
312/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
313#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 94
314/** Interruptibility state block-by-STI invalid for EFLAGS. */
315#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 95
316/** Interruptibility state invalid while trying to deliver external
317 * interrupt. */
318#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 96
319/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
320 * NMI. */
321#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 97
322/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
323#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 98
324/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
325#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 99
326/** Interruptibilty state block-by-STI (maybe) invalid when trying to deliver
327 * an NMI. */
328#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 100
329/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
330 * active. */
331#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 101
332/** Pending debug exceptions reserved bits not set to 0. */
333#define VMX_IGS_PENDING_DEBUG_RESERVED 102
334/** Longmode pending debug exceptions reserved bits not set to 0. */
335#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 103
336/** Pending debug exceptions.BS bit is not set when it should be. */
337#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 104
338/** Pending debug exceptions.BS bit is not clear when it should be. */
339#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 105
340/** VMCS link pointer reserved bits not set to 0. */
341#define VMX_IGS_VMCS_LINK_PTR_RESERVED 106
342/** TR cannot index into LDT, TI bit MBZ. */
343#define VMX_IGS_TR_TI_INVALID 107
344/** LDTR cannot index into LDT. TI bit MBZ. */
345#define VMX_IGS_LDTR_TI_INVALID 108
346/** TR.Base is not canonical. */
347#define VMX_IGS_TR_BASE_NOT_CANONICAL 109
348/** FS.Base is not canonical. */
349#define VMX_IGS_FS_BASE_NOT_CANONICAL 110
350/** GS.Base is not canonical. */
351#define VMX_IGS_GS_BASE_NOT_CANONICAL 111
352/** LDTR.Base is not canonical. */
353#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 112
354/** TR is unusable. */
355#define VMX_IGS_TR_ATTR_UNUSABLE 113
356/** TR.Attr.S bit invalid. */
357#define VMX_IGS_TR_ATTR_S_INVALID 114
358/** TR is not present. */
359#define VMX_IGS_TR_ATTR_P_INVALID 115
360/** TR.Attr reserved bits not set to 0. */
361#define VMX_IGS_TR_ATTR_RESERVED 116
362/** TR.Attr.G bit invalid. */
363#define VMX_IGS_TR_ATTR_G_INVALID 117
364/** Longmode TR.Attr.Type invalid. */
365#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 118
366/** TR.Attr.Type invalid. */
367#define VMX_IGS_TR_ATTR_TYPE_INVALID 119
368/** CS.Attr.S invalid. */
369#define VMX_IGS_CS_ATTR_S_INVALID 120
370/** CS.Attr.DPL invalid. */
371#define VMX_IGS_CS_ATTR_DPL_INVALID 121
372/** @} */
373
374/** @name VMX VMCS-Read cache indices.
375 * @{
376 */
377#ifndef VBOX_WITH_OLD_VTX_CODE
378# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
379# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
380# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
381# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
382# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
383# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
384# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
385# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
386# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
387# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
388# define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
389# define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
390# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
391# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
392# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
393# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
394# define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
395# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
396#else /* VBOX_WITH_OLD_VTX_CODE */
397# define VMX_VMCS_GUEST_RIP_CACHE_IDX 0
398# define VMX_VMCS_GUEST_RSP_CACHE_IDX 1
399# define VMX_VMCS_GUEST_RFLAGS_CACHE_IDX 2
400# define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE_CACHE_IDX 3
401# define VMX_VMCS_CTRL_CR0_READ_SHADOW_CACHE_IDX 4
402# define VMX_VMCS_GUEST_CR0_CACHE_IDX 5
403# define VMX_VMCS_CTRL_CR4_READ_SHADOW_CACHE_IDX 6
404# define VMX_VMCS_GUEST_CR4_CACHE_IDX 7
405# define VMX_VMCS_GUEST_DR7_CACHE_IDX 8
406# define VMX_VMCS32_GUEST_SYSENTER_CS_CACHE_IDX 9
407# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 10
408# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 11
409# define VMX_VMCS32_GUEST_GDTR_LIMIT_CACHE_IDX 12
410# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 13
411# define VMX_VMCS32_GUEST_IDTR_LIMIT_CACHE_IDX 14
412# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 15
413# define VMX_VMCS16_GUEST_FIELD_CS_CACHE_IDX 16
414# define VMX_VMCS32_GUEST_CS_LIMIT_CACHE_IDX 17
415# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 18
416# define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS_CACHE_IDX 19
417# define VMX_VMCS16_GUEST_FIELD_DS_CACHE_IDX 20
418# define VMX_VMCS32_GUEST_DS_LIMIT_CACHE_IDX 21
419# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 22
420# define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS_CACHE_IDX 23
421# define VMX_VMCS16_GUEST_FIELD_ES_CACHE_IDX 24
422# define VMX_VMCS32_GUEST_ES_LIMIT_CACHE_IDX 25
423# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 26
424# define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS_CACHE_IDX 27
425# define VMX_VMCS16_GUEST_FIELD_FS_CACHE_IDX 28
426# define VMX_VMCS32_GUEST_FS_LIMIT_CACHE_IDX 29
427# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 30
428# define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS_CACHE_IDX 31
429# define VMX_VMCS16_GUEST_FIELD_GS_CACHE_IDX 32
430# define VMX_VMCS32_GUEST_GS_LIMIT_CACHE_IDX 33
431# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 34
432# define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS_CACHE_IDX 35
433# define VMX_VMCS16_GUEST_FIELD_SS_CACHE_IDX 36
434# define VMX_VMCS32_GUEST_SS_LIMIT_CACHE_IDX 37
435# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 38
436# define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS_CACHE_IDX 39
437# define VMX_VMCS16_GUEST_FIELD_TR_CACHE_IDX 40
438# define VMX_VMCS32_GUEST_TR_LIMIT_CACHE_IDX 41
439# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 42
440# define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS_CACHE_IDX 43
441# define VMX_VMCS16_GUEST_FIELD_LDTR_CACHE_IDX 44
442# define VMX_VMCS32_GUEST_LDTR_LIMIT_CACHE_IDX 45
443# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 46
444# define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS_CACHE_IDX 47
445# define VMX_VMCS32_RO_EXIT_REASON_CACHE_IDX 48
446# define VMX_VMCS32_RO_VM_INSTR_ERROR_CACHE_IDX 49
447# define VMX_VMCS32_RO_EXIT_INSTR_LENGTH_CACHE_IDX 50
448# define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE_CACHE_IDX 51
449# define VMX_VMCS32_RO_EXIT_INSTR_INFO_CACHE_IDX 52
450# define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO_CACHE_IDX 53
451# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 54
452# define VMX_VMCS32_RO_IDT_INFO_CACHE_IDX 55
453# define VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX 56
454# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX + 1)
455# define VMX_VMCS_GUEST_CR3_CACHE_IDX 57
456# define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX 58
457# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX + 1)
458#endif /* VBOX_WITH_OLD_VTX_CODE */
459/** @} */
460
461/** @name VMX EPT paging structures
462 * @{
463 */
464
465/**
466 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
467 */
468#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
469
470/**
471 * EPT Page Directory Pointer Entry. Bit view.
472 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
473 * this did cause trouble with one compiler/version).
474 */
475#pragma pack(1)
476typedef struct EPTPML4EBITS
477{
478 /** Present bit. */
479 uint64_t u1Present : 1;
480 /** Writable bit. */
481 uint64_t u1Write : 1;
482 /** Executable bit. */
483 uint64_t u1Execute : 1;
484 /** Reserved (must be 0). */
485 uint64_t u5Reserved : 5;
486 /** Available for software. */
487 uint64_t u4Available : 4;
488 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
489 uint64_t u40PhysAddr : 40;
490 /** Availabe for software. */
491 uint64_t u12Available : 12;
492} EPTPML4EBITS;
493#pragma pack()
494AssertCompileSize(EPTPML4EBITS, 8);
495
496/** Bits 12-51 - - EPT - Physical Page number of the next level. */
497#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
498/** The page shift to get the PML4 index. */
499#define EPT_PML4_SHIFT X86_PML4_SHIFT
500/** The PML4 index mask (apply to a shifted page address). */
501#define EPT_PML4_MASK X86_PML4_MASK
502
503/**
504 * EPT PML4E.
505 */
506#pragma pack(1)
507typedef union EPTPML4E
508{
509 /** Normal view. */
510 EPTPML4EBITS n;
511 /** Unsigned integer view. */
512 X86PGPAEUINT u;
513 /** 64 bit unsigned integer view. */
514 uint64_t au64[1];
515 /** 32 bit unsigned integer view. */
516 uint32_t au32[2];
517} EPTPML4E;
518#pragma pack()
519/** Pointer to a PML4 table entry. */
520typedef EPTPML4E *PEPTPML4E;
521/** Pointer to a const PML4 table entry. */
522typedef const EPTPML4E *PCEPTPML4E;
523AssertCompileSize(EPTPML4E, 8);
524
525/**
526 * EPT PML4 Table.
527 */
528#pragma pack(1)
529typedef struct EPTPML4
530{
531 EPTPML4E a[EPT_PG_ENTRIES];
532} EPTPML4;
533#pragma pack()
534/** Pointer to an EPT PML4 Table. */
535typedef EPTPML4 *PEPTPML4;
536/** Pointer to a const EPT PML4 Table. */
537typedef const EPTPML4 *PCEPTPML4;
538
539/**
540 * EPT Page Directory Pointer Entry. Bit view.
541 */
542#pragma pack(1)
543typedef struct EPTPDPTEBITS
544{
545 /** Present bit. */
546 uint64_t u1Present : 1;
547 /** Writable bit. */
548 uint64_t u1Write : 1;
549 /** Executable bit. */
550 uint64_t u1Execute : 1;
551 /** Reserved (must be 0). */
552 uint64_t u5Reserved : 5;
553 /** Available for software. */
554 uint64_t u4Available : 4;
555 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
556 uint64_t u40PhysAddr : 40;
557 /** Availabe for software. */
558 uint64_t u12Available : 12;
559} EPTPDPTEBITS;
560#pragma pack()
561AssertCompileSize(EPTPDPTEBITS, 8);
562
563/** Bits 12-51 - - EPT - Physical Page number of the next level. */
564#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
565/** The page shift to get the PDPT index. */
566#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
567/** The PDPT index mask (apply to a shifted page address). */
568#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
569
570/**
571 * EPT Page Directory Pointer.
572 */
573#pragma pack(1)
574typedef union EPTPDPTE
575{
576 /** Normal view. */
577 EPTPDPTEBITS n;
578 /** Unsigned integer view. */
579 X86PGPAEUINT u;
580 /** 64 bit unsigned integer view. */
581 uint64_t au64[1];
582 /** 32 bit unsigned integer view. */
583 uint32_t au32[2];
584} EPTPDPTE;
585#pragma pack()
586/** Pointer to an EPT Page Directory Pointer Entry. */
587typedef EPTPDPTE *PEPTPDPTE;
588/** Pointer to a const EPT Page Directory Pointer Entry. */
589typedef const EPTPDPTE *PCEPTPDPTE;
590AssertCompileSize(EPTPDPTE, 8);
591
592/**
593 * EPT Page Directory Pointer Table.
594 */
595#pragma pack(1)
596typedef struct EPTPDPT
597{
598 EPTPDPTE a[EPT_PG_ENTRIES];
599} EPTPDPT;
600#pragma pack()
601/** Pointer to an EPT Page Directory Pointer Table. */
602typedef EPTPDPT *PEPTPDPT;
603/** Pointer to a const EPT Page Directory Pointer Table. */
604typedef const EPTPDPT *PCEPTPDPT;
605
606
607/**
608 * EPT Page Directory Table Entry. Bit view.
609 */
610#pragma pack(1)
611typedef struct EPTPDEBITS
612{
613 /** Present bit. */
614 uint64_t u1Present : 1;
615 /** Writable bit. */
616 uint64_t u1Write : 1;
617 /** Executable bit. */
618 uint64_t u1Execute : 1;
619 /** Reserved (must be 0). */
620 uint64_t u4Reserved : 4;
621 /** Big page (must be 0 here). */
622 uint64_t u1Size : 1;
623 /** Available for software. */
624 uint64_t u4Available : 4;
625 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
626 uint64_t u40PhysAddr : 40;
627 /** Availabe for software. */
628 uint64_t u12Available : 12;
629} EPTPDEBITS;
630#pragma pack()
631AssertCompileSize(EPTPDEBITS, 8);
632
633/** Bits 12-51 - - EPT - Physical Page number of the next level. */
634#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
635/** The page shift to get the PD index. */
636#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
637/** The PD index mask (apply to a shifted page address). */
638#define EPT_PD_MASK X86_PD_PAE_MASK
639
640/**
641 * EPT 2MB Page Directory Table Entry. Bit view.
642 */
643#pragma pack(1)
644typedef struct EPTPDE2MBITS
645{
646 /** Present bit. */
647 uint64_t u1Present : 1;
648 /** Writable bit. */
649 uint64_t u1Write : 1;
650 /** Executable bit. */
651 uint64_t u1Execute : 1;
652 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
653 uint64_t u3EMT : 3;
654 /** Ignore PAT memory type */
655 uint64_t u1IgnorePAT : 1;
656 /** Big page (must be 1 here). */
657 uint64_t u1Size : 1;
658 /** Available for software. */
659 uint64_t u4Available : 4;
660 /** Reserved (must be 0). */
661 uint64_t u9Reserved : 9;
662 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
663 uint64_t u31PhysAddr : 31;
664 /** Availabe for software. */
665 uint64_t u12Available : 12;
666} EPTPDE2MBITS;
667#pragma pack()
668AssertCompileSize(EPTPDE2MBITS, 8);
669
670/** Bits 21-51 - - EPT - Physical Page number of the next level. */
671#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
672
673/**
674 * EPT Page Directory Table Entry.
675 */
676#pragma pack(1)
677typedef union EPTPDE
678{
679 /** Normal view. */
680 EPTPDEBITS n;
681 /** 2MB view (big). */
682 EPTPDE2MBITS b;
683 /** Unsigned integer view. */
684 X86PGPAEUINT u;
685 /** 64 bit unsigned integer view. */
686 uint64_t au64[1];
687 /** 32 bit unsigned integer view. */
688 uint32_t au32[2];
689} EPTPDE;
690#pragma pack()
691/** Pointer to an EPT Page Directory Table Entry. */
692typedef EPTPDE *PEPTPDE;
693/** Pointer to a const EPT Page Directory Table Entry. */
694typedef const EPTPDE *PCEPTPDE;
695AssertCompileSize(EPTPDE, 8);
696
697/**
698 * EPT Page Directory Table.
699 */
700#pragma pack(1)
701typedef struct EPTPD
702{
703 EPTPDE a[EPT_PG_ENTRIES];
704} EPTPD;
705#pragma pack()
706/** Pointer to an EPT Page Directory Table. */
707typedef EPTPD *PEPTPD;
708/** Pointer to a const EPT Page Directory Table. */
709typedef const EPTPD *PCEPTPD;
710
711
712/**
713 * EPT Page Table Entry. Bit view.
714 */
715#pragma pack(1)
716typedef struct EPTPTEBITS
717{
718 /** 0 - Present bit.
719 * @remark This is a convenience "misnomer". The bit actually indicates
720 * read access and the CPU will consider an entry with any of the
721 * first three bits set as present. Since all our valid entries
722 * will have this bit set, it can be used as a present indicator
723 * and allow some code sharing. */
724 uint64_t u1Present : 1;
725 /** 1 - Writable bit. */
726 uint64_t u1Write : 1;
727 /** 2 - Executable bit. */
728 uint64_t u1Execute : 1;
729 /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
730 uint64_t u3EMT : 3;
731 /** 6 - Ignore PAT memory type */
732 uint64_t u1IgnorePAT : 1;
733 /** 11:7 - Available for software. */
734 uint64_t u5Available : 5;
735 /** 51:12 - Physical address of page. Restricted by maximum physical
736 * address width of the cpu. */
737 uint64_t u40PhysAddr : 40;
738 /** 63:52 - Available for software. */
739 uint64_t u12Available : 12;
740} EPTPTEBITS;
741#pragma pack()
742AssertCompileSize(EPTPTEBITS, 8);
743
744/** Bits 12-51 - - EPT - Physical Page number of the next level. */
745#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
746/** The page shift to get the EPT PTE index. */
747#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
748/** The EPT PT index mask (apply to a shifted page address). */
749#define EPT_PT_MASK X86_PT_PAE_MASK
750
751/**
752 * EPT Page Table Entry.
753 */
754#pragma pack(1)
755typedef union EPTPTE
756{
757 /** Normal view. */
758 EPTPTEBITS n;
759 /** Unsigned integer view. */
760 X86PGPAEUINT u;
761 /** 64 bit unsigned integer view. */
762 uint64_t au64[1];
763 /** 32 bit unsigned integer view. */
764 uint32_t au32[2];
765} EPTPTE;
766#pragma pack()
767/** Pointer to an EPT Page Directory Table Entry. */
768typedef EPTPTE *PEPTPTE;
769/** Pointer to a const EPT Page Directory Table Entry. */
770typedef const EPTPTE *PCEPTPTE;
771AssertCompileSize(EPTPTE, 8);
772
773/**
774 * EPT Page Table.
775 */
776#pragma pack(1)
777typedef struct EPTPT
778{
779 EPTPTE a[EPT_PG_ENTRIES];
780} EPTPT;
781#pragma pack()
782/** Pointer to an extended page table. */
783typedef EPTPT *PEPTPT;
784/** Pointer to a const extended table. */
785typedef const EPTPT *PCEPTPT;
786
787/**
788 * VPID flush types.
789 */
790typedef enum
791{
792 /** Invalidate a specific page. */
793 VMX_FLUSH_VPID_INDIV_ADDR = 0,
794 /** Invalidate one context (specific VPID). */
795 VMX_FLUSH_VPID_SINGLE_CONTEXT = 1,
796 /** Invalidate all contexts (all VPIDs). */
797 VMX_FLUSH_VPID_ALL_CONTEXTS = 2,
798 /** Invalidate a single VPID context retaining global mappings. */
799 VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
800 /** Unsupported by VirtualBox. */
801 VMX_FLUSH_VPID_NOT_SUPPORTED = 0xbad,
802 /** Unsupported by CPU. */
803 VMX_FLUSH_VPID_NONE = 0xb00,
804 /** 32bit hackishness. */
805 VMX_FLUSH_VPID_32BIT_HACK = 0x7fffffff
806} VMX_FLUSH_VPID;
807
808/**
809 * EPT flush types.
810 */
811typedef enum
812{
813 /** Invalidate one context (specific EPT). */
814 VMX_FLUSH_EPT_SINGLE_CONTEXT = 1,
815 /* Invalidate all contexts (all EPTs) */
816 VMX_FLUSH_EPT_ALL_CONTEXTS = 2,
817 /** Unsupported by VirtualBox. */
818 VMX_FLUSH_EPT_NOT_SUPPORTED = 0xbad,
819 /** Unsupported by CPU. */
820 VMX_FLUSH_EPT_NONE = 0xb00,
821 /** 32bit hackishness. */
822 VMX_FLUSH_EPT_32BIT_HACK = 0x7fffffff
823} VMX_FLUSH_EPT;
824/** @} */
825
826/** @name MSR autoload/store elements
827 * @{
828 */
829#pragma pack(1)
830typedef struct
831{
832 uint32_t u32IndexMSR;
833 uint32_t u32Reserved;
834 uint64_t u64Value;
835} VMXMSR;
836#pragma pack()
837/** Pointer to an MSR load/store element. */
838typedef VMXMSR *PVMXMSR;
839/** Pointer to a const MSR load/store element. */
840typedef const VMXMSR *PCVMXMSR;
841
842/** @} */
843
844
845/** @name VMX-capability qword
846 * @{
847 */
848#pragma pack(1)
849typedef union
850{
851 struct
852 {
853 /** Bits set here -must- be set in the correpsonding VM-execution controls. */
854 uint32_t disallowed0;
855 /** Bits cleared here -must- be cleared in the corresponding VM-execution
856 * controls. */
857 uint32_t allowed1;
858 } n;
859 uint64_t u;
860} VMX_CAPABILITY;
861#pragma pack()
862/** @} */
863
864/** @name VMX EFLAGS reserved bits.
865 * @{
866 */
867/** And-mask for setting reserved bits to zero */
868#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
869/** Or-mask for setting reserved bits to 1 */
870#define VMX_EFLAGS_RESERVED_1 0x00000002
871/** @} */
872
873/** @name VMX Basic Exit Reasons.
874 * @{
875 */
876/** -1 Invalid exit code */
877#define VMX_EXIT_INVALID -1
878/** 0 Exception or non-maskable interrupt (NMI). */
879#define VMX_EXIT_XCPT_OR_NMI 0
880/** 1 External interrupt. */
881#define VMX_EXIT_EXT_INT 1
882/** 2 Triple fault. */
883#define VMX_EXIT_TRIPLE_FAULT 2
884/** 3 INIT signal. */
885#define VMX_EXIT_INIT_SIGNAL 3
886/** 4 Start-up IPI (SIPI). */
887#define VMX_EXIT_SIPI 4
888/** 5 I/O system-management interrupt (SMI). */
889#define VMX_EXIT_IO_SMI 5
890/** 6 Other SMI. */
891#define VMX_EXIT_SMI 6
892/** 7 Interrupt window exiting. */
893#define VMX_EXIT_INT_WINDOW 7
894/** 8 NMI window exiting. */
895#define VMX_EXIT_NMI_WINDOW 8
896/** 9 Task switch. */
897#define VMX_EXIT_TASK_SWITCH 9
898/** 10 Guest software attempted to execute CPUID. */
899#define VMX_EXIT_CPUID 10
900/** 10 Guest software attempted to execute GETSEC. */
901#define VMX_EXIT_GETSEC 11
902/** 12 Guest software attempted to execute HLT. */
903#define VMX_EXIT_HLT 12
904/** 13 Guest software attempted to execute INVD. */
905#define VMX_EXIT_INVD 13
906/** 14 Guest software attempted to execute INVLPG. */
907#define VMX_EXIT_INVLPG 14
908/** 15 Guest software attempted to execute RDPMC. */
909#define VMX_EXIT_RDPMC 15
910/** 16 Guest software attempted to execute RDTSC. */
911#define VMX_EXIT_RDTSC 16
912/** 17 Guest software attempted to execute RSM in SMM. */
913#define VMX_EXIT_RSM 17
914/** 18 Guest software executed VMCALL. */
915#define VMX_EXIT_VMCALL 18
916/** 19 Guest software executed VMCLEAR. */
917#define VMX_EXIT_VMCLEAR 19
918/** 20 Guest software executed VMLAUNCH. */
919#define VMX_EXIT_VMLAUNCH 20
920/** 21 Guest software executed VMPTRLD. */
921#define VMX_EXIT_VMPTRLD 21
922/** 22 Guest software executed VMPTRST. */
923#define VMX_EXIT_VMPTRST 22
924/** 23 Guest software executed VMREAD. */
925#define VMX_EXIT_VMREAD 23
926/** 24 Guest software executed VMRESUME. */
927#define VMX_EXIT_VMRESUME 24
928/** 25 Guest software executed VMWRITE. */
929#define VMX_EXIT_VMWRITE 25
930/** 26 Guest software executed VMXOFF. */
931#define VMX_EXIT_VMXOFF 26
932/** 27 Guest software executed VMXON. */
933#define VMX_EXIT_VMXON 27
934/** 28 Control-register accesses. */
935#define VMX_EXIT_MOV_CRX 28
936/** 29 Debug-register accesses. */
937#define VMX_EXIT_MOV_DRX 29
938/** 30 I/O instruction. */
939#define VMX_EXIT_IO_INSTR 30
940/** 31 RDMSR. Guest software attempted to execute RDMSR. */
941#define VMX_EXIT_RDMSR 31
942/** 32 WRMSR. Guest software attempted to execute WRMSR. */
943#define VMX_EXIT_WRMSR 32
944/** 33 VM-entry failure due to invalid guest state. */
945#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
946/** 34 VM-entry failure due to MSR loading. */
947#define VMX_EXIT_ERR_MSR_LOAD 34
948/** 36 Guest software executed MWAIT. */
949#define VMX_EXIT_MWAIT 36
950/** 37 VM exit due to monitor trap flag. */
951#define VMX_EXIT_MTF 37
952/** 39 Guest software attempted to execute MONITOR. */
953#define VMX_EXIT_MONITOR 39
954/** 40 Guest software attempted to execute PAUSE. */
955#define VMX_EXIT_PAUSE 40
956/** 41 VM-entry failure due to machine-check. */
957#define VMX_EXIT_ERR_MACHINE_CHECK 41
958/** 43 TPR below threshold. Guest software executed MOV to CR8. */
959#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
960/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
961#define VMX_EXIT_APIC_ACCESS 44
962/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
963#define VMX_EXIT_XDTR_ACCESS 46
964/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
965#define VMX_EXIT_TR_ACCESS 47
966/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
967#define VMX_EXIT_EPT_VIOLATION 48
968/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
969#define VMX_EXIT_EPT_MISCONFIG 49
970/** 50 INVEPT. Guest software attempted to execute INVEPT. */
971#define VMX_EXIT_INVEPT 50
972/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
973#define VMX_EXIT_RDTSCP 51
974/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
975#define VMX_EXIT_PREEMPT_TIMER 52
976/** 53 INVVPID. Guest software attempted to execute INVVPID. */
977#define VMX_EXIT_INVVPID 53
978/** 54 WBINVD. Guest software attempted to execute WBINVD. */
979#define VMX_EXIT_WBINVD 54
980/** 55 XSETBV. Guest software attempted to execute XSETBV. */
981#define VMX_EXIT_XSETBV 55
982/** 57 RDRAND. Guest software attempted to execute RDRAND. */
983#define VMX_EXIT_RDRAND 57
984/** 58 INVPCID. Guest software attempted to execute INVPCID. */
985#define VMX_EXIT_INVPCID 58
986/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
987#define VMX_EXIT_VMFUNC 59
988/** The maximum exit value (inclusive). */
989#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
990/** @} */
991
992
993/** @name VM Instruction Errors
994 * @{
995 */
996/** VMCALL executed in VMX root operation. */
997#define VMX_ERROR_VMCALL 1
998/** VMCLEAR with invalid physical address. */
999#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1000/** VMCLEAR with VMXON pointer. */
1001#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1002/** VMLAUNCH with non-clear VMCS. */
1003#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1004/** VMRESUME with non-launched VMCS. */
1005#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1006/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1007#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1008/** VM-entry with invalid control field(s). */
1009#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1010/** VM-entry with invalid host-state field(s). */
1011#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1012/** VMPTRLD with invalid physical address. */
1013#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1014/** VMPTRLD with VMXON pointer. */
1015#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1016/** VMPTRLD with incorrect VMCS revision identifier. */
1017#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1018/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1019#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1020#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1021/** VMWRITE to read-only VMCS component. */
1022#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1023/** VMXON executed in VMX root operation. */
1024#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1025/** VM entry with invalid executive-VMCS pointer. */
1026#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1027/** VM entry with non-launched executive VMCS. */
1028#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1029/** VM entry with executive-VMCS pointer not VMXON pointer. */
1030#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1031/** VMCALL with non-clear VMCS. */
1032#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1033/** VMCALL with invalid VM-exit control fields. */
1034#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1035/** VMCALL with incorrect MSEG revision identifier. */
1036#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1037/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1038#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1039/** VMCALL with invalid SMM-monitor features. */
1040#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1041/** VM entry with invalid VM-execution control fields in executive VMCS. */
1042#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1043/** VM entry with events blocked by MOV SS. */
1044#define VMX_ERROR_VMENTRY_MOV_SS 26
1045/** Invalid operand to INVEPT/INVVPID. */
1046#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1047
1048/** @} */
1049
1050
1051/** @name VMX MSRs - Basic VMX information.
1052 * @{
1053 */
1054/** VMCS revision identifier used by the processor. */
1055#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
1056/** Size of the VMCS. */
1057#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0xFFF)
1058/** Width of physical address used for the VMCS.
1059 * 0 -> limited to the available amount of physical ram
1060 * 1 -> within the first 4 GB
1061 */
1062#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1063/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1064#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1065/** Memory type that must be used for the VMCS. */
1066#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1067/** Whether the processor provides additional information for exits due to INS/OUTS. */
1068#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
1069/** @} */
1070
1071
1072/** @name VMX MSRs - Misc VMX info.
1073 * @{
1074 */
1075/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1076#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1077/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1078#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1079/** Activity states supported by the implementation. */
1080#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1081/** Number of CR3 target values supported by the processor. (0-256) */
1082#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1083/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
1084#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1085/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1086#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1087/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1088#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1089/** Whether VMWRITE can be used to write VM-exit information fields. */
1090#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1091/** MSEG revision identifier used by the processor. */
1092#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1093/** @} */
1094
1095
1096/** @name VMX MSRs - VMCS enumeration field info
1097 * @{
1098 */
1099/** Highest field index. */
1100#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1101/** @} */
1102
1103
1104/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1105 * @{
1106 */
1107#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1108#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
1109#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
1110#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
1111#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
1112#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
1113#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
1114#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
1115#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1116#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
1117#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
1118#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
1119#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1120#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
1121#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
1122#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
1123#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
1124#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1125#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1126#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1127#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1128#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1129#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1130#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1131#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1132
1133/** @} */
1134
1135/** @name Extended Page Table Pointer (EPTP)
1136 * @{
1137 */
1138/** Uncachable EPT paging structure memory type. */
1139#define VMX_EPT_MEMTYPE_UC 0
1140/** Write-back EPT paging structure memory type. */
1141#define VMX_EPT_MEMTYPE_WB 6
1142/** Shift value to get the EPT page walk length (bits 5-3) */
1143#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1144/** Mask value to get the EPT page walk length (bits 5-3) */
1145#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1146/** Default EPT page-walk length (1 less than the actual EPT page-walk
1147 * length) */
1148#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1149/** @} */
1150
1151
1152/** @name VMCS field encoding - 16 bits guest fields
1153 * @{
1154 */
1155#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
1156#define VMX_VMCS16_GUEST_FIELD_ES 0x800
1157#define VMX_VMCS16_GUEST_FIELD_CS 0x802
1158#define VMX_VMCS16_GUEST_FIELD_SS 0x804
1159#define VMX_VMCS16_GUEST_FIELD_DS 0x806
1160#define VMX_VMCS16_GUEST_FIELD_FS 0x808
1161#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
1162#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
1163#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
1164/** @} */
1165
1166/** @name VMCS field encoding - 16 bits host fields
1167 * @{
1168 */
1169#define VMX_VMCS16_HOST_FIELD_ES 0xC00
1170#define VMX_VMCS16_HOST_FIELD_CS 0xC02
1171#define VMX_VMCS16_HOST_FIELD_SS 0xC04
1172#define VMX_VMCS16_HOST_FIELD_DS 0xC06
1173#define VMX_VMCS16_HOST_FIELD_FS 0xC08
1174#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
1175#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
1176/** @} */
1177
1178/** @name VMCS field encoding - 64 bits host fields
1179 * @{
1180 */
1181#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
1182#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
1183#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
1184#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
1185#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
1186#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
1187/** @} */
1188
1189
1190/** @name VMCS field encoding - 64 Bits control fields
1191 * @{
1192 */
1193#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1194#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1195#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1196#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1197
1198/* Optional */
1199#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1200#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1201
1202#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1203#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1204#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1205#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1206
1207#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1208#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1209
1210#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1211#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1212
1213#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1214#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1215
1216/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1217#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1218#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1219
1220/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1221#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1222#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1223
1224/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1225#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1226#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1227
1228/** Extended page table pointer. */
1229#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1230#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1231
1232/** Extended page table pointer lists. */
1233#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1234#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1235
1236/** VM-exit guest phyiscal address. */
1237#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1238#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1239/** @} */
1240
1241
1242/** @name VMCS field encoding - 64 Bits guest fields
1243 * @{
1244 */
1245#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1246#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1247#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
1248#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
1249#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1250#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1251#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1252#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1253#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
1254#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
1255#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1256#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1257#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1258#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1259#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1260#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1261#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1262#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1263/** @} */
1264
1265
1266/** @name VMCS field encoding - 32 Bits control fields
1267 * @{
1268 */
1269#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1270#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1271#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1272#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1273#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1274#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1275#define VMX_VMCS32_CTRL_EXIT 0x400C
1276#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1277#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1278#define VMX_VMCS32_CTRL_ENTRY 0x4012
1279#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1280#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1281#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1282#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1283#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1284#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1285/** @} */
1286
1287
1288/** @name VMX_VMCS_CTRL_PIN_EXEC
1289 * @{
1290 */
1291/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1292#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1293/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1294#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1295/** Virtual NMIs. */
1296#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1297/** Activate VMX preemption timer. */
1298#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1299/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1300/** @} */
1301
1302/** @name VMX_VMCS_CTRL_PROC_EXEC
1303 * @{
1304 */
1305/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
1306#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1307/** Use timestamp counter offset. */
1308#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1309/** VM Exit when executing the HLT instruction. */
1310#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1311/** VM Exit when executing the INVLPG instruction. */
1312#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1313/** VM Exit when executing the MWAIT instruction. */
1314#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1315/** VM Exit when executing the RDPMC instruction. */
1316#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1317/** VM Exit when executing the RDTSC/RDTSCP instruction. */
1318#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1319/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1320#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1321/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1322#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1323/** VM Exit on CR8 loads. */
1324#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1325/** VM Exit on CR8 stores. */
1326#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1327/** Use TPR shadow. */
1328#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1329/** VM Exit when virtual nmi blocking is disabled. */
1330#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1331/** VM Exit when executing a MOV DRx instruction. */
1332#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1333/** VM Exit when executing IO instructions. */
1334#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1335/** Use IO bitmaps. */
1336#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1337/** Monitor trap flag. */
1338#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1339/** Use MSR bitmaps. */
1340#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1341/** VM Exit when executing the MONITOR instruction. */
1342#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1343/** VM Exit when executing the PAUSE instruction. */
1344#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1345/** Determines whether the secondary processor based VM-execution controls are used. */
1346#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1347/** @} */
1348
1349/** @name VMX_VMCS_CTRL_PROC_EXEC2
1350 * @{
1351 */
1352/** Virtualize APIC access. */
1353#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1354/** EPT supported/enabled. */
1355#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1356/** Descriptor table instructions cause VM-exits. */
1357#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1358/** RDTSCP supported/enabled. */
1359#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1360/** Virtualize x2APIC mode. */
1361#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1362/** VPID supported/enabled. */
1363#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1364/** VM Exit when executing the WBINVD instruction. */
1365#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1366/** Unrestricted guest execution. */
1367#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1368/** A specified nr of pause loops cause a VM-exit. */
1369#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1370/** VM Exit when executing RDRAND instructions. */
1371#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1372/** Enables INVPCID instructions. */
1373#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1374/** Enables VMFUNC instructions. */
1375#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1376/** @} */
1377
1378
1379/** @name VMX_VMCS_CTRL_ENTRY
1380 * @{
1381 */
1382/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1383#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1384/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1385#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1386/** In SMM mode after VM-entry. */
1387#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1388/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1389#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1390/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
1391#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1392/** Whether the guest IA32_PAT MSR is loaded on VM entry. */
1393#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1394/** Whether the guest IA32_EFER MSR is loaded on VM entry. */
1395#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1396/** @} */
1397
1398
1399/** @name VMX_VMCS_CTRL_EXIT
1400 * @{
1401 */
1402/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1403#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1404/** Return to long mode after a VM-exit. */
1405#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1406/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
1407#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1408/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1409#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1410/** Whether the guest IA32_PAT MSR is saved on VM exit. */
1411#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1412/** Whether the host IA32_PAT MSR is loaded on VM exit. */
1413#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1414/** Whether the guest IA32_EFER MSR is saved on VM exit. */
1415#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1416/** Whether the host IA32_EFER MSR is loaded on VM exit. */
1417#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1418/** Whether the value of the VMX preemption timer is saved on every VM exit. */
1419#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1420/** @} */
1421
1422
1423/** @name VMX_VMCS_CTRL_VMFUNC
1424 * @{
1425 */
1426/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1427#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1428/** @} */
1429
1430
1431/** @name VMCS field encoding - 32 Bits read-only fields
1432 * @{
1433 */
1434#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1435#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1436#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1437#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1438#define VMX_VMCS32_RO_IDT_INFO 0x4408
1439#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1440#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1441#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1442/** @} */
1443
1444/** @name VMX_VMCS32_RO_EXIT_REASON
1445 * @{
1446 */
1447#define VMX_EXIT_REASON_BASIC(a) (a & 0xffff)
1448/** @} */
1449
1450/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1451 * @{
1452 */
1453#define VMX_ENTRY_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
1454#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1455#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1456/** @} */
1457
1458
1459/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1460 * @{
1461 */
1462#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
1463#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1464#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1465#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1466#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1467#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
1468#ifdef VBOX_WITH_OLD_VTX_CODE
1469# define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
1470#endif
1471#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1472#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) (a & RT_BIT(31))
1473/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1474#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
1475/** @} */
1476
1477/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1478 * @{
1479 */
1480#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1481#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1482#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1483#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4 /**< int xx */
1484#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DB_XCPT 5 /**< Why are we getting this one?? */
1485#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1486/** @} */
1487
1488/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1489 * @{
1490 */
1491#define VMX_IDT_VECTORING_INFO_VECTOR(a) (a & 0xff)
1492#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1493#define VMX_IDT_VECTORING_INFO_TYPE(a) ((a >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1494#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1495#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1496#define VMX_IDT_VECTORING_INFO_VALID(a) (a & RT_BIT(31))
1497#define VMX_ENTRY_INTR_INFO_FROM_EXIT_IDT_INFO(a) (a & ~RT_BIT(12))
1498/** @} */
1499
1500/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1501 * @{
1502 */
1503#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1504#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1505#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1506#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1507#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1508#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1509/** @} */
1510
1511
1512/** @name VMCS field encoding - 32 Bits guest state fields
1513 * @{
1514 */
1515#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1516#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1517#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1518#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1519#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1520#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1521#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1522#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1523#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1524#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1525#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1526#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1527#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1528#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1529#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1530#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1531#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1532#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1533#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1534#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1535#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
1536#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1537/** @} */
1538
1539
1540/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1541 * @{
1542 */
1543/** The logical processor is active. */
1544#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1545/** The logical processor is inactive, because executed a HLT instruction. */
1546#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1547/** The logical processor is inactive, because of a triple fault or other serious error. */
1548#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1549/** The logical processor is inactive, because it's waiting for a startup-IPI */
1550#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1551/** @} */
1552
1553
1554/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1555 * @{
1556 */
1557#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1558#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1559#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1560#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1561/** @} */
1562
1563
1564/** @name VMCS field encoding - 32 Bits host state fields
1565 * @{
1566 */
1567#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1568/** @} */
1569
1570/** @name Natural width control fields
1571 * @{
1572 */
1573#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1574#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1575#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1576#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1577#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1578#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1579#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1580#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1581/** @} */
1582
1583
1584/** @name Natural width read-only data fields
1585 * @{
1586 */
1587#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1588#define VMX_VMCS_RO_IO_RCX 0x6402
1589#define VMX_VMCS_RO_IO_RSX 0x6404
1590#define VMX_VMCS_RO_IO_RDI 0x6406
1591#define VMX_VMCS_RO_IO_RIP 0x6408
1592#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1593/** @} */
1594
1595
1596/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1597 * @{
1598 */
1599/** 0-2: Debug register number */
1600#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1601/** 3: Reserved; cleared to 0. */
1602#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1603/** 4: Direction of move (0 = write, 1 = read) */
1604#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1605/** 5-7: Reserved; cleared to 0. */
1606#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1607/** 8-11: General purpose register number. */
1608#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1609/** Rest: reserved. */
1610/** @} */
1611
1612/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1613 * @{
1614 */
1615#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1616#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1617/** @} */
1618
1619
1620
1621/** @name CRx accesses
1622 * @{
1623 */
1624/** 0-3: Control register number (0 for CLTS & LMSW) */
1625#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1626/** 4-5: Access type. */
1627#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1628/** 6: LMSW operand type */
1629#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1630/** 7: Reserved; cleared to 0. */
1631#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1632/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1633#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1634/** 12-15: Reserved; cleared to 0. */
1635#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1636/** 16-31: LMSW source data (else 0). */
1637#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1638/** Rest: reserved. */
1639/** @} */
1640
1641/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1642 * @{
1643 */
1644#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1645#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1646#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1647#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1648/** @} */
1649
1650/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1651 * @{
1652 */
1653#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1654#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1655/** Task switch caused by a call instruction. */
1656#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1657/** Task switch caused by an iret instruction. */
1658#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1659/** Task switch caused by a jmp instruction. */
1660#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1661/** Task switch caused by an interrupt gate. */
1662#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1663/** @} */
1664
1665
1666/** @name VMX_EXIT_EPT_VIOLATION
1667 * @{
1668 */
1669/** Set if the violation was caused by a data read. */
1670#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1671/** Set if the violation was caused by a data write. */
1672#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1673/** Set if the violation was caused by an insruction fetch. */
1674#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1675/** AND of the present bit of all EPT structures. */
1676#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1677/** AND of the write bit of all EPT structures. */
1678#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1679/** AND of the execute bit of all EPT structures. */
1680#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1681/** Set if the guest linear address field contains the faulting address. */
1682#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1683/** If bit 7 is one: (reserved otherwise)
1684 * 1 - violation due to physical address access.
1685 * 0 - violation caused by page walk or access/dirty bit updates
1686 */
1687#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1688/** @} */
1689
1690
1691/** @name VMX_EXIT_PORT_IO
1692 * @{
1693 */
1694/** 0-2: IO operation width. */
1695#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1696/** 3: IO operation direction. */
1697#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1698/** 4: String IO operation (INS / OUTS). */
1699#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1700/** 5: Repeated IO operation. */
1701#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1702/** 6: Operand encoding. */
1703#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1704/** 16-31: IO Port (0-0xffff). */
1705#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1706/* Rest reserved. */
1707/** @} */
1708
1709/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1710 * @{
1711 */
1712#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1713#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1714/** @} */
1715
1716
1717/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1718 * @{
1719 */
1720#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1721#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1722/** @} */
1723
1724/** @name VMX_EXIT_APIC_ACCESS
1725 * @{
1726 */
1727/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1728#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1729/** 12-15: Access type. */
1730#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a) & 0xf000)
1731/* Rest reserved. */
1732/** @} */
1733
1734
1735/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1736 * @{
1737 */
1738/** Linear read access. */
1739#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1740/** Linear write access. */
1741#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1742/** Linear instruction fetch access. */
1743#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1744/** Linear read/write access during event delivery. */
1745#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1746/** Physical read/write access during event delivery. */
1747#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1748/** Physical access for an instruction fetch or during instruction execution. */
1749#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1750/** @} */
1751
1752/** @} */
1753
1754/** @name VMCS field encoding - Natural width guest state fields
1755 * @{
1756 */
1757#define VMX_VMCS_GUEST_CR0 0x6800
1758#define VMX_VMCS_GUEST_CR3 0x6802
1759#define VMX_VMCS_GUEST_CR4 0x6804
1760#define VMX_VMCS_GUEST_ES_BASE 0x6806
1761#define VMX_VMCS_GUEST_CS_BASE 0x6808
1762#define VMX_VMCS_GUEST_SS_BASE 0x680A
1763#define VMX_VMCS_GUEST_DS_BASE 0x680C
1764#define VMX_VMCS_GUEST_FS_BASE 0x680E
1765#define VMX_VMCS_GUEST_GS_BASE 0x6810
1766#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1767#define VMX_VMCS_GUEST_TR_BASE 0x6814
1768#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1769#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1770#define VMX_VMCS_GUEST_DR7 0x681A
1771#define VMX_VMCS_GUEST_RSP 0x681C
1772#define VMX_VMCS_GUEST_RIP 0x681E
1773#define VMX_VMCS_GUEST_RFLAGS 0x6820
1774#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1775#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1776#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1777/** @} */
1778
1779
1780/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1781 * @{
1782 */
1783/** Hardware breakpoint 0 was met. */
1784#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1785/** Hardware breakpoint 1 was met. */
1786#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1787/** Hardware breakpoint 2 was met. */
1788#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1789/** Hardware breakpoint 3 was met. */
1790#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1791/** At least one data or IO breakpoint was hit. */
1792#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1793/** A debug exception would have been triggered by single-step execution mode. */
1794#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1795/** Bits 4-11, 13 and 15-63 are reserved. */
1796
1797/** @} */
1798
1799/** @name VMCS field encoding - Natural width host state fields
1800 * @{
1801 */
1802#define VMX_VMCS_HOST_CR0 0x6C00
1803#define VMX_VMCS_HOST_CR3 0x6C02
1804#define VMX_VMCS_HOST_CR4 0x6C04
1805#define VMX_VMCS_HOST_FS_BASE 0x6C06
1806#define VMX_VMCS_HOST_GS_BASE 0x6C08
1807#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1808#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1809#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1810#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1811#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1812#define VMX_VMCS_HOST_RSP 0x6C14
1813#define VMX_VMCS_HOST_RIP 0x6C16
1814/** @} */
1815
1816/** @} */
1817
1818
1819/** @defgroup grp_vmx_asm vmx assembly helpers
1820 * @ingroup grp_vmx
1821 * @{
1822 */
1823
1824/**
1825 * Restores some host-state fields that need not be done on every VM-exit.
1826 *
1827 * @returns VBox status code.
1828 * @param fRestoreHostFlags Flags of which host registers needs to be
1829 * restored.
1830 * @param pRestoreHost Pointer to the host-restore structure.
1831 */
1832DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1833
1834
1835/**
1836 * Dispatches an NMI to the host.
1837 */
1838DECLASM(int) VMXDispatchHostNmi(void);
1839
1840
1841/**
1842 * Executes VMXON
1843 *
1844 * @returns VBox status code
1845 * @param pVMXOn Physical address of VMXON structure
1846 */
1847#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1848DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1849#else
1850DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1851{
1852# if RT_INLINE_ASM_GNU_STYLE
1853 int rc = VINF_SUCCESS;
1854 __asm__ __volatile__ (
1855 "push %3 \n\t"
1856 "push %2 \n\t"
1857 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1858 "ja 2f \n\t"
1859 "je 1f \n\t"
1860 "movl $"RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1861 "jmp 2f \n\t"
1862 "1: \n\t"
1863 "movl $"RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
1864 "2: \n\t"
1865 "add $8, %%esp \n\t"
1866 :"=rm"(rc)
1867 :"0"(VINF_SUCCESS),
1868 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1869 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1870 :"memory"
1871 );
1872 return rc;
1873
1874# elif VMX_USE_MSC_INTRINSICS
1875 unsigned char rcMsc = __vmx_on(&pVMXOn);
1876 if (RT_LIKELY(rcMsc == 0))
1877 return VINF_SUCCESS;
1878 return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
1879
1880# else
1881 int rc = VINF_SUCCESS;
1882 __asm
1883 {
1884 push dword ptr [pVMXOn+4]
1885 push dword ptr [pVMXOn]
1886 _emit 0xF3
1887 _emit 0x0F
1888 _emit 0xC7
1889 _emit 0x34
1890 _emit 0x24 /* VMXON [esp] */
1891 jnc vmxon_good
1892 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1893 jmp the_end
1894
1895vmxon_good:
1896 jnz the_end
1897 mov dword ptr [rc], VERR_VMX_VMXON_FAILED
1898the_end:
1899 add esp, 8
1900 }
1901# endif
1902}
1903#endif
1904
1905
1906/**
1907 * Executes VMXOFF
1908 */
1909#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1910DECLASM(void) VMXDisable(void);
1911#else
1912DECLINLINE(void) VMXDisable(void)
1913{
1914# if RT_INLINE_ASM_GNU_STYLE
1915 __asm__ __volatile__ (
1916 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1917 );
1918
1919# elif VMX_USE_MSC_INTRINSICS
1920 __vmx_off();
1921
1922# else
1923 __asm
1924 {
1925 _emit 0x0F
1926 _emit 0x01
1927 _emit 0xC4 /* VMXOFF */
1928 }
1929# endif
1930}
1931#endif
1932
1933
1934/**
1935 * Executes VMCLEAR
1936 *
1937 * @returns VBox status code
1938 * @param pVMCS Physical address of VM control structure
1939 */
1940#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1941DECLASM(int) VMXClearVmcs(RTHCPHYS pVMCS);
1942#else
1943DECLINLINE(int) VMXClearVmcs(RTHCPHYS pVMCS)
1944{
1945# if RT_INLINE_ASM_GNU_STYLE
1946 int rc = VINF_SUCCESS;
1947 __asm__ __volatile__ (
1948 "push %3 \n\t"
1949 "push %2 \n\t"
1950 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1951 "jnc 1f \n\t"
1952 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1953 "1: \n\t"
1954 "add $8, %%esp \n\t"
1955 :"=rm"(rc)
1956 :"0"(VINF_SUCCESS),
1957 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1958 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1959 :"memory"
1960 );
1961 return rc;
1962
1963# elif VMX_USE_MSC_INTRINSICS
1964 unsigned char rcMsc = __vmx_vmclear(&pVMCS);
1965 if (RT_LIKELY(rcMsc == 0))
1966 return VINF_SUCCESS;
1967 return VERR_VMX_INVALID_VMCS_PTR;
1968
1969# else
1970 int rc = VINF_SUCCESS;
1971 __asm
1972 {
1973 push dword ptr [pVMCS+4]
1974 push dword ptr [pVMCS]
1975 _emit 0x66
1976 _emit 0x0F
1977 _emit 0xC7
1978 _emit 0x34
1979 _emit 0x24 /* VMCLEAR [esp] */
1980 jnc success
1981 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1982success:
1983 add esp, 8
1984 }
1985 return rc;
1986# endif
1987}
1988#endif
1989
1990
1991/**
1992 * Executes VMPTRLD
1993 *
1994 * @returns VBox status code
1995 * @param pVMCS Physical address of VMCS structure
1996 */
1997#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1998DECLASM(int) VMXActivateVmcs(RTHCPHYS pVMCS);
1999#else
2000DECLINLINE(int) VMXActivateVmcs(RTHCPHYS pVMCS)
2001{
2002# if RT_INLINE_ASM_GNU_STYLE
2003 int rc = VINF_SUCCESS;
2004 __asm__ __volatile__ (
2005 "push %3 \n\t"
2006 "push %2 \n\t"
2007 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2008 "jnc 1f \n\t"
2009 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2010 "1: \n\t"
2011 "add $8, %%esp \n\t"
2012 :"=rm"(rc)
2013 :"0"(VINF_SUCCESS),
2014 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
2015 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
2016 );
2017 return rc;
2018
2019# elif VMX_USE_MSC_INTRINSICS
2020 unsigned char rcMsc = __vmx_vmptrld(&pVMCS);
2021 if (RT_LIKELY(rcMsc == 0))
2022 return VINF_SUCCESS;
2023 return VERR_VMX_INVALID_VMCS_PTR;
2024
2025# else
2026 int rc = VINF_SUCCESS;
2027 __asm
2028 {
2029 push dword ptr [pVMCS+4]
2030 push dword ptr [pVMCS]
2031 _emit 0x0F
2032 _emit 0xC7
2033 _emit 0x34
2034 _emit 0x24 /* VMPTRLD [esp] */
2035 jnc success
2036 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2037
2038success:
2039 add esp, 8
2040 }
2041 return rc;
2042# endif
2043}
2044#endif
2045
2046/**
2047 * Executes VMPTRST
2048 *
2049 * @returns VBox status code
2050 * @param pVMCS Address that will receive the current pointer
2051 */
2052DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pVMCS);
2053
2054/**
2055 * Executes VMWRITE
2056 *
2057 * @returns VBox status code
2058 * @retval VINF_SUCCESS
2059 * @retval VERR_VMX_INVALID_VMCS_PTR
2060 * @retval VERR_VMX_INVALID_VMCS_FIELD
2061 *
2062 * @param idxField VMCS index
2063 * @param u32Val 32 bits value
2064 *
2065 * @remarks The values of the two status codes can be ORed together, the result
2066 * will be VERR_VMX_INVALID_VMCS_PTR.
2067 */
2068#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2069DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2070#else
2071DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2072{
2073# if RT_INLINE_ASM_GNU_STYLE
2074 int rc = VINF_SUCCESS;
2075 __asm__ __volatile__ (
2076 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2077 "ja 2f \n\t"
2078 "je 1f \n\t"
2079 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2080 "jmp 2f \n\t"
2081 "1: \n\t"
2082 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2083 "2: \n\t"
2084 :"=rm"(rc)
2085 :"0"(VINF_SUCCESS),
2086 "a"(idxField),
2087 "d"(u32Val)
2088 );
2089 return rc;
2090
2091# elif VMX_USE_MSC_INTRINSICS
2092 unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2093 if (RT_LIKELY(rcMsc == 0))
2094 return VINF_SUCCESS;
2095 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2096
2097#else
2098 int rc = VINF_SUCCESS;
2099 __asm
2100 {
2101 push dword ptr [u32Val]
2102 mov eax, [idxField]
2103 _emit 0x0F
2104 _emit 0x79
2105 _emit 0x04
2106 _emit 0x24 /* VMWRITE eax, [esp] */
2107 jnc valid_vmcs
2108 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2109 jmp the_end
2110
2111valid_vmcs:
2112 jnz the_end
2113 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2114the_end:
2115 add esp, 4
2116 }
2117 return rc;
2118# endif
2119}
2120#endif
2121
2122/**
2123 * Executes VMWRITE
2124 *
2125 * @returns VBox status code
2126 * @retval VINF_SUCCESS
2127 * @retval VERR_VMX_INVALID_VMCS_PTR
2128 * @retval VERR_VMX_INVALID_VMCS_FIELD
2129 *
2130 * @param idxField VMCS index
2131 * @param u64Val 16, 32 or 64 bits value
2132 *
2133 * @remarks The values of the two status codes can be ORed together, the result
2134 * will be VERR_VMX_INVALID_VMCS_PTR.
2135 */
2136#if !defined(RT_ARCH_X86) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2137# if !VMX_USE_MSC_INTRINSICS || ARCH_BITS != 64
2138DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2139# else /* VMX_USE_MSC_INTRINSICS */
2140DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2141{
2142 unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2143 if (RT_LIKELY(rcMsc == 0))
2144 return VINF_SUCCESS;
2145 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2146}
2147# endif /* VMX_USE_MSC_INTRINSICS */
2148#else
2149# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2150VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2151#endif
2152
2153#ifdef VBOX_WITH_OLD_VTX_CODE
2154# if ARCH_BITS == 64
2155# define VMXWriteVmcs VMXWriteVmcs64
2156# else
2157# define VMXWriteVmcs VMXWriteVmcs32
2158# endif
2159#else /* !VBOX_WITH_OLD_VTX_CODE */
2160# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2161# define VMXWriteVmcsHstN(idxField, uVal) HMVMX_IS_64BIT_HOST_MODE() ? \
2162 VMXWriteVmcs64(idxField, uVal) \
2163 : VMXWriteVmcs32(idxField, uVal)
2164# define VMXWriteVmcsGstN(idxField, u64Val) (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
2165 VMXWriteVmcs64(idxField, u64Val) \
2166 : VMXWriteVmcs32(idxField, u64Val)
2167# elif ARCH_BITS == 32
2168# define VMXWriteVmcsHstN VMXWriteVmcs32
2169# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2170# else /* ARCH_BITS == 64 */
2171# define VMXWriteVmcsHstN VMXWriteVmcs64
2172# define VMXWriteVmcsGstN VMXWriteVmcs64
2173# endif
2174#endif /* !VBOX_WITH_OLD_VTX_CODE */
2175
2176
2177/**
2178 * Invalidate a page using invept
2179 * @returns VBox status code
2180 * @param enmFlush Type of flush
2181 * @param pDescriptor Descriptor
2182 */
2183DECLASM(int) VMXR0InvEPT(VMX_FLUSH_EPT enmFlush, uint64_t *pDescriptor);
2184
2185/**
2186 * Invalidate a page using invvpid
2187 * @returns VBox status code
2188 * @param enmFlush Type of flush
2189 * @param pDescriptor Descriptor
2190 */
2191DECLASM(int) VMXR0InvVPID(VMX_FLUSH_VPID enmFlush, uint64_t *pDescriptor);
2192
2193/**
2194 * Executes VMREAD
2195 *
2196 * @returns VBox status code
2197 * @retval VINF_SUCCESS
2198 * @retval VERR_VMX_INVALID_VMCS_PTR
2199 * @retval VERR_VMX_INVALID_VMCS_FIELD
2200 *
2201 * @param idxField VMCS index
2202 * @param pData Ptr to store VM field value
2203 *
2204 * @remarks The values of the two status codes can be ORed together, the result
2205 * will be VERR_VMX_INVALID_VMCS_PTR.
2206 */
2207#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2208DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2209#else
2210DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2211{
2212# if RT_INLINE_ASM_GNU_STYLE
2213 int rc = VINF_SUCCESS;
2214 __asm__ __volatile__ (
2215 "movl $"RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2216 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2217 "ja 2f \n\t"
2218 "je 1f \n\t"
2219 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2220 "jmp 2f \n\t"
2221 "1: \n\t"
2222 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2223 "2: \n\t"
2224 :"=&r"(rc),
2225 "=d"(*pData)
2226 :"a"(idxField),
2227 "d"(0)
2228 );
2229 return rc;
2230
2231# elif VMX_USE_MSC_INTRINSICS
2232 unsigned char rcMsc;
2233# if ARCH_BITS == 32
2234 rcMsc = __vmx_vmread(idxField, pData);
2235# else
2236 uint64_t u64Tmp;
2237 rcMsc = __vmx_vmread(idxField, &u64Tmp);
2238 *pData = (uint32_t)u64Tmp;
2239# endif
2240 if (RT_LIKELY(rcMsc == 0))
2241 return VINF_SUCCESS;
2242 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2243
2244#else
2245 int rc = VINF_SUCCESS;
2246 __asm
2247 {
2248 sub esp, 4
2249 mov dword ptr [esp], 0
2250 mov eax, [idxField]
2251 _emit 0x0F
2252 _emit 0x78
2253 _emit 0x04
2254 _emit 0x24 /* VMREAD eax, [esp] */
2255 mov edx, pData
2256 pop dword ptr [edx]
2257 jnc valid_vmcs
2258 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2259 jmp the_end
2260
2261valid_vmcs:
2262 jnz the_end
2263 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2264the_end:
2265 }
2266 return rc;
2267# endif
2268}
2269#endif
2270
2271/**
2272 * Executes VMREAD
2273 *
2274 * @returns VBox status code
2275 * @retval VINF_SUCCESS
2276 * @retval VERR_VMX_INVALID_VMCS_PTR
2277 * @retval VERR_VMX_INVALID_VMCS_FIELD
2278 *
2279 * @param idxField VMCS index
2280 * @param pData Ptr to store VM field value
2281 *
2282 * @remarks The values of the two status codes can be ORed together, the result
2283 * will be VERR_VMX_INVALID_VMCS_PTR.
2284 */
2285#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2286DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2287#else
2288DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2289{
2290# if VMX_USE_MSC_INTRINSICS
2291 unsigned char rcMsc;
2292# if ARCH_BITS == 32
2293 size_t uLow;
2294 size_t uHigh;
2295 rcMsc = __vmx_vmread(idxField, &uLow);
2296 rcMsc |= __vmx_vmread(idxField + 1, &uHigh);
2297 *pData = RT_MAKE_U64(uLow, uHigh);
2298# else
2299 rcMsc = __vmx_vmread(idxField, pData);
2300# endif
2301 if (RT_LIKELY(rcMsc == 0))
2302 return VINF_SUCCESS;
2303 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2304
2305# elif ARCH_BITS == 32
2306 int rc;
2307 uint32_t val_hi, val;
2308 rc = VMXReadVmcs32(idxField, &val);
2309 rc |= VMXReadVmcs32(idxField + 1, &val_hi);
2310 AssertRC(rc);
2311 *pData = RT_MAKE_U64(val, val_hi);
2312 return rc;
2313
2314# else
2315# error "Shouldn't be here..."
2316# endif
2317}
2318#endif
2319
2320#ifdef VBOX_WITH_OLD_VTX_CODE
2321# if ARCH_BITS == 64
2322# define VMXReadVmcsField VMXReadVmcs64
2323# else
2324# define VMXReadVmcsField VMXReadVmcs32
2325# endif
2326#endif
2327
2328/**
2329 * Gets the last instruction error value from the current VMCS
2330 *
2331 * @returns error value
2332 */
2333DECLINLINE(uint32_t) VMXGetLastError(void)
2334{
2335#if ARCH_BITS == 64
2336 uint64_t uLastError = 0;
2337 int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2338 AssertRC(rc);
2339 return (uint32_t)uLastError;
2340
2341#else /* 32-bit host: */
2342 uint32_t uLastError = 0;
2343 int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2344 AssertRC(rc);
2345 return uLastError;
2346#endif
2347}
2348
2349#ifdef IN_RING0
2350VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2351VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2352#endif /* IN_RING0 */
2353
2354/** @} */
2355
2356#endif
2357
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