| 1 | /* $Id: pdmpcidevint.h 82968 2020-02-04 10:35:17Z vboxsync $ */
|
|---|
| 2 | /** @file
|
|---|
| 3 | * DevPCI - PDM PCI Internal header - Only for hiding bits of PDMPCIDEV.
|
|---|
| 4 | */
|
|---|
| 5 |
|
|---|
| 6 | /*
|
|---|
| 7 | * Copyright (C) 2006-2020 Oracle Corporation
|
|---|
| 8 | *
|
|---|
| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
|
|---|
| 10 | * available from http://www.virtualbox.org. This file is free software;
|
|---|
| 11 | * you can redistribute it and/or modify it under the terms of the GNU
|
|---|
| 12 | * General Public License (GPL) as published by the Free Software
|
|---|
| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
|
|---|
| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
|
|---|
| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
|
|---|
| 16 | *
|
|---|
| 17 | * The contents of this file may alternatively be used under the terms
|
|---|
| 18 | * of the Common Development and Distribution License Version 1.0
|
|---|
| 19 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
|
|---|
| 20 | * VirtualBox OSE distribution, in which case the provisions of the
|
|---|
| 21 | * CDDL are applicable instead of those of the GPL.
|
|---|
| 22 | *
|
|---|
| 23 | * You may elect to license modified versions of this file under the
|
|---|
| 24 | * terms and conditions of either the GPL or the CDDL or both.
|
|---|
| 25 | */
|
|---|
| 26 |
|
|---|
| 27 | #ifndef VBOX_INCLUDED_vmm_pdmpcidevint_h
|
|---|
| 28 | #define VBOX_INCLUDED_vmm_pdmpcidevint_h
|
|---|
| 29 | #ifndef RT_WITHOUT_PRAGMA_ONCE
|
|---|
| 30 | # pragma once
|
|---|
| 31 | #endif
|
|---|
| 32 |
|
|---|
| 33 | #include <VBox/vmm/pdmdev.h>
|
|---|
| 34 |
|
|---|
| 35 | /** @defgroup grp_pdm_pcidev_int The PDM PCI Device Internals
|
|---|
| 36 | * @ingroup grp_pdm_pcidev
|
|---|
| 37 | *
|
|---|
| 38 | * @remarks The PDM PCI device internals are visible to both PDM and the PCI Bus
|
|---|
| 39 | * implementation, thus it lives among the the public headers despite
|
|---|
| 40 | * being rather private and internal.
|
|---|
| 41 | *
|
|---|
| 42 | * @{
|
|---|
| 43 | */
|
|---|
| 44 |
|
|---|
| 45 |
|
|---|
| 46 | /**
|
|---|
| 47 | * PCI I/O region.
|
|---|
| 48 | */
|
|---|
| 49 | typedef struct PCIIOREGION
|
|---|
| 50 | {
|
|---|
| 51 | /** Current PCI mapping address, INVALID_PCI_ADDRESS (0xffffffff) means not mapped. */
|
|---|
| 52 | uint64_t addr;
|
|---|
| 53 | /** The region size. Power of 2. */
|
|---|
| 54 | uint64_t size;
|
|---|
| 55 | /** Handle or UINT64_MAX (see PDMPCIDEV_IORGN_F_HANDLE_MASK in fFlags). */
|
|---|
| 56 | uint64_t hHandle;
|
|---|
| 57 | /** PDMPCIDEV_IORGN_F_XXXX. */
|
|---|
| 58 | uint32_t fFlags;
|
|---|
| 59 | /** PCIADDRESSSPACE */
|
|---|
| 60 | uint8_t type;
|
|---|
| 61 | uint8_t abPadding0[3];
|
|---|
| 62 | /** Callback called when the region is mapped or unmapped (new style devs). */
|
|---|
| 63 | R3PTRTYPE(PFNPCIIOREGIONMAP) pfnMap;
|
|---|
| 64 | #if R3_ARCH_BITS == 32
|
|---|
| 65 | uint32_t u32Padding2;
|
|---|
| 66 | #endif
|
|---|
| 67 | } PCIIOREGION;
|
|---|
| 68 | AssertCompileSize(PCIIOREGION, 5*8);
|
|---|
| 69 | /** Pointer to a PCI I/O region. */
|
|---|
| 70 | typedef PCIIOREGION *PPCIIOREGION;
|
|---|
| 71 | /** Pointer to a const PCI I/O region. */
|
|---|
| 72 | typedef PCIIOREGION const *PCPCIIOREGION;
|
|---|
| 73 |
|
|---|
| 74 | /**
|
|---|
| 75 | * Callback function for reading from the PCI configuration space.
|
|---|
| 76 | *
|
|---|
| 77 | * @returns Strict VBox status code.
|
|---|
| 78 | * @param pDevIns Pointer to the device instance of the PCI bus.
|
|---|
| 79 | * @param iBus The bus number this device is on.
|
|---|
| 80 | * @param iDevice The number of the device on the bus.
|
|---|
| 81 | * @param u32Address The configuration space register address. [0..255]
|
|---|
| 82 | * @param cb The register size. [1,2,4]
|
|---|
| 83 | * @param pu32Value Where to return the register value.
|
|---|
| 84 | */
|
|---|
| 85 | typedef DECLCALLBACK(VBOXSTRICTRC) FNPCIBRIDGECONFIGREAD(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
|
|---|
| 86 | uint32_t u32Address, unsigned cb, uint32_t *pu32Value);
|
|---|
| 87 | /** Pointer to a FNPCICONFIGREAD() function. */
|
|---|
| 88 | typedef FNPCIBRIDGECONFIGREAD *PFNPCIBRIDGECONFIGREAD;
|
|---|
| 89 | /** Pointer to a PFNPCICONFIGREAD. */
|
|---|
| 90 | typedef PFNPCIBRIDGECONFIGREAD *PPFNPCIBRIDGECONFIGREAD;
|
|---|
| 91 |
|
|---|
| 92 | /**
|
|---|
| 93 | * Callback function for writing to the PCI configuration space.
|
|---|
| 94 | *
|
|---|
| 95 | * @returns Strict VBox status code.
|
|---|
| 96 | * @param pDevIns Pointer to the device instance of the PCI bus.
|
|---|
| 97 | * @param iBus The bus number this device is on.
|
|---|
| 98 | * @param iDevice The number of the device on the bus.
|
|---|
| 99 | * @param u32Address The configuration space register address. [0..255]
|
|---|
| 100 | * @param cb The register size. [1,2,4]
|
|---|
| 101 | * @param u32Value The value that's being written. The number of bits actually used from
|
|---|
| 102 | * this value is determined by the cb parameter.
|
|---|
| 103 | */
|
|---|
| 104 | typedef DECLCALLBACK(VBOXSTRICTRC) FNPCIBRIDGECONFIGWRITE(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
|
|---|
| 105 | uint32_t u32Address, unsigned cb, uint32_t u32Value);
|
|---|
| 106 | /** Pointer to a FNPCICONFIGWRITE() function. */
|
|---|
| 107 | typedef FNPCIBRIDGECONFIGWRITE *PFNPCIBRIDGECONFIGWRITE;
|
|---|
| 108 | /** Pointer to a PFNPCICONFIGWRITE. */
|
|---|
| 109 | typedef PFNPCIBRIDGECONFIGWRITE *PPFNPCIBRIDGECONFIGWRITE;
|
|---|
| 110 |
|
|---|
| 111 | /* Forward declaration */
|
|---|
| 112 | struct DEVPCIBUS;
|
|---|
| 113 |
|
|---|
| 114 | enum {
|
|---|
| 115 | /** Flag whether the device is a pci-to-pci bridge.
|
|---|
| 116 | * This is set prior to device registration. */
|
|---|
| 117 | PCIDEV_FLAG_PCI_TO_PCI_BRIDGE = RT_BIT_32(1),
|
|---|
| 118 | /** Flag whether the device is a PCI Express device.
|
|---|
| 119 | * This is set prior to device registration. */
|
|---|
| 120 | PCIDEV_FLAG_PCI_EXPRESS_DEVICE = RT_BIT_32(2),
|
|---|
| 121 | /** Flag whether the device is capable of MSI.
|
|---|
| 122 | * This one is set by MsiInit(). */
|
|---|
| 123 | PCIDEV_FLAG_MSI_CAPABLE = RT_BIT_32(3),
|
|---|
| 124 | /** Flag whether the device is capable of MSI-X.
|
|---|
| 125 | * This one is set by MsixInit(). */
|
|---|
| 126 | PCIDEV_FLAG_MSIX_CAPABLE = RT_BIT_32(4),
|
|---|
| 127 | /** Flag if device represents real physical device in passthrough mode. */
|
|---|
| 128 | PCIDEV_FLAG_PASSTHROUGH = RT_BIT_32(5),
|
|---|
| 129 | /** Flag whether the device is capable of MSI using 64-bit address. */
|
|---|
| 130 | PCIDEV_FLAG_MSI64_CAPABLE = RT_BIT_32(6)
|
|---|
| 131 |
|
|---|
| 132 | };
|
|---|
| 133 |
|
|---|
| 134 |
|
|---|
| 135 | /**
|
|---|
| 136 | * PDM PCI Device - Internal data.
|
|---|
| 137 | *
|
|---|
| 138 | * @sa PDMPCIDEV
|
|---|
| 139 | */
|
|---|
| 140 | typedef struct PDMPCIDEVINT
|
|---|
| 141 | {
|
|---|
| 142 | /** @name Owned by PDM.
|
|---|
| 143 | * @remarks The bus may use the device instance pointers.
|
|---|
| 144 | * @{
|
|---|
| 145 | */
|
|---|
| 146 | /** Pointer to the PDM device the PCI device belongs to. (R3 ptr) */
|
|---|
| 147 | PPDMDEVINSR3 pDevInsR3;
|
|---|
| 148 | /** The CFGM device configuration index (default, PciDev1..255).
|
|---|
| 149 | * This also works as the internal sub-device ordinal with MMIOEx.
|
|---|
| 150 | * @note Same value as idxSubDev, can therefore be removed later. */
|
|---|
| 151 | uint8_t idxDevCfg;
|
|---|
| 152 | /** Set if the it can be reassigned to a different PCI device number. */
|
|---|
| 153 | bool fReassignableDevNo;
|
|---|
| 154 | /** Set if the it can be reassigned to a different PCI function number. */
|
|---|
| 155 | bool fReassignableFunNo;
|
|---|
| 156 | /** Alignment padding - used by ICH9 for region swapping (DevVGA hack). */
|
|---|
| 157 | uint8_t bPadding0;
|
|---|
| 158 | /** Index into the PDM internal bus array (PDM::aPciBuses). */
|
|---|
| 159 | uint8_t idxPdmBus;
|
|---|
| 160 | /** Set if this device has been registered. */
|
|---|
| 161 | bool fRegistered;
|
|---|
| 162 | /** Index into PDMDEVINSR3::apPciDevs (same as PDMPCIDEV::idxSubDev). */
|
|---|
| 163 | uint16_t idxSubDev;
|
|---|
| 164 | /** @} */
|
|---|
| 165 |
|
|---|
| 166 | /** @name Owned by the PCI Bus
|
|---|
| 167 | * @remarks PDM will not touch anything here (includes not relocating anything).
|
|---|
| 168 | * @{
|
|---|
| 169 | */
|
|---|
| 170 | /** Pointer to the PCI bus of the device. (R3 ptr) */
|
|---|
| 171 | R3PTRTYPE(struct DEVPCIBUS *) pBusR3;
|
|---|
| 172 | /** Read config callback. */
|
|---|
| 173 | R3PTRTYPE(PFNPCICONFIGREAD) pfnConfigRead;
|
|---|
| 174 | /** Write config callback. */
|
|---|
| 175 | R3PTRTYPE(PFNPCICONFIGWRITE) pfnConfigWrite;
|
|---|
| 176 | /** Read config callback for PCI bridges to pass requests
|
|---|
| 177 | * to devices on another bus. */
|
|---|
| 178 | R3PTRTYPE(PFNPCIBRIDGECONFIGREAD) pfnBridgeConfigRead;
|
|---|
| 179 | /** Write config callback for PCI bridges to pass requests
|
|---|
| 180 | * to devices on another bus. */
|
|---|
| 181 | R3PTRTYPE(PFNPCIBRIDGECONFIGWRITE) pfnBridgeConfigWrite;
|
|---|
| 182 |
|
|---|
| 183 | /** Flags of this PCI device, see PCIDEV_FLAG_XXX constants. */
|
|---|
| 184 | uint32_t fFlags;
|
|---|
| 185 | /** Current state of the IRQ pin of the device. */
|
|---|
| 186 | int32_t uIrqPinState;
|
|---|
| 187 |
|
|---|
| 188 | /** Offset of MSI PCI capability in config space, or 0.
|
|---|
| 189 | * @todo fix non-standard naming. */
|
|---|
| 190 | uint8_t u8MsiCapOffset;
|
|---|
| 191 | /** Size of MSI PCI capability in config space, or 0.
|
|---|
| 192 | * @todo fix non-standard naming. */
|
|---|
| 193 | uint8_t u8MsiCapSize;
|
|---|
| 194 | /** Offset of MSI-X PCI capability in config space, or 0.
|
|---|
| 195 | * @todo fix non-standard naming. */
|
|---|
| 196 | uint8_t u8MsixCapOffset;
|
|---|
| 197 | /** Size of MSI-X PCI capability in config space, or 0.
|
|---|
| 198 | * @todo fix non-standard naming. */
|
|---|
| 199 | uint8_t u8MsixCapSize;
|
|---|
| 200 | /** Size of the MSI-X region. */
|
|---|
| 201 | uint16_t cbMsixRegion;
|
|---|
| 202 | /** Offset to the PBA for MSI-X. */
|
|---|
| 203 | uint16_t offMsixPba;
|
|---|
| 204 | /** Add padding to align aIORegions to an 16 byte boundary. */
|
|---|
| 205 | uint8_t abPadding2[HC_ARCH_BITS == 32 ? 12 : 8];
|
|---|
| 206 | /** The MMIO handle for the MSI-X MMIO bar. */
|
|---|
| 207 | IOMMMIOHANDLE hMmioMsix;
|
|---|
| 208 |
|
|---|
| 209 | /** Pointer to bus specific data. (R3 ptr) */
|
|---|
| 210 | R3PTRTYPE(const void *) pvPciBusPtrR3;
|
|---|
| 211 | /** I/O regions. */
|
|---|
| 212 | PCIIOREGION aIORegions[VBOX_PCI_NUM_REGIONS];
|
|---|
| 213 | /** @} */
|
|---|
| 214 | } PDMPCIDEVINT;
|
|---|
| 215 | AssertCompileMemberAlignment(PDMPCIDEVINT, aIORegions, 8);
|
|---|
| 216 | AssertCompileSize(PDMPCIDEVINT, HC_ARCH_BITS == 32 ? 0x98 : 0x178);
|
|---|
| 217 |
|
|---|
| 218 | /** Indicate that PDMPCIDEV::Int.s can be declared. */
|
|---|
| 219 | #define PDMPCIDEVINT_DECLARED
|
|---|
| 220 |
|
|---|
| 221 | /** @} */
|
|---|
| 222 |
|
|---|
| 223 | #endif /* !VBOX_INCLUDED_vmm_pdmpcidevint_h */
|
|---|
| 224 |
|
|---|
