VirtualBox

source: vbox/trunk/include/VBox/vmm/vm.h@ 54693

Last change on this file since 54693 was 54256, checked in by vboxsync, 10 years ago

VMCPU: Added a iHostCpuSet field to go with the idHostCpu one. This allows for better GIP time & TSC code in raw-mode context.

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1/** @file
2 * VM - The Virtual Machine, data.
3 */
4
5/*
6 * Copyright (C) 2006-2014 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_vm_h
27#define ___VBox_vmm_vm_h
28
29#ifndef VBOX_FOR_DTRACE_LIB
30# include <VBox/types.h>
31# include <VBox/vmm/cpum.h>
32# include <VBox/vmm/stam.h>
33# include <VBox/vmm/vmapi.h>
34# include <VBox/vmm/vmm.h>
35# include <VBox/sup.h>
36#else
37# pragma D depends_on library vbox-types.d
38# pragma D depends_on library CPUMInternal.d
39# define ___CPUMInternal_h
40#endif
41
42
43
44/** @defgroup grp_vm The Virtual Machine
45 * @{
46 */
47
48/**
49 * The state of a Virtual CPU.
50 *
51 * The basic state indicated here is whether the CPU has been started or not. In
52 * addition, there are sub-states when started for assisting scheduling (GVMM
53 * mostly).
54 *
55 * The transition out of the STOPPED state is done by a vmR3PowerOn.
56 * The transition back to the STOPPED state is done by vmR3PowerOff.
57 *
58 * (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
59 * handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
60 */
61typedef enum VMCPUSTATE
62{
63 /** The customary invalid zero. */
64 VMCPUSTATE_INVALID = 0,
65
66 /** Virtual CPU has not yet been started. */
67 VMCPUSTATE_STOPPED,
68
69 /** CPU started. */
70 VMCPUSTATE_STARTED,
71 /** CPU started in HM context. */
72 VMCPUSTATE_STARTED_HM,
73 /** Executing guest code and can be poked (RC or STI bits of HM). */
74 VMCPUSTATE_STARTED_EXEC,
75 /** Executing guest code in the recompiler. */
76 VMCPUSTATE_STARTED_EXEC_REM,
77 /** Halted. */
78 VMCPUSTATE_STARTED_HALTED,
79
80 /** The end of valid virtual CPU states. */
81 VMCPUSTATE_END,
82
83 /** Ensure 32-bit type. */
84 VMCPUSTATE_32BIT_HACK = 0x7fffffff
85} VMCPUSTATE;
86
87
88/**
89 * The cross context virtual CPU structure.
90 *
91 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
92 */
93typedef struct VMCPU
94{
95 /** Per CPU forced action.
96 * See the VMCPU_FF_* \#defines. Updated atomically. */
97 uint32_t volatile fLocalForcedActions; /* 0 */
98 /** The CPU state. */
99 VMCPUSTATE volatile enmState; /* 4 */
100
101 /** Pointer to the ring-3 UVMCPU structure. */
102 PUVMCPU pUVCpu; /* 8 */
103 /** Ring-3 Host Context VM Pointer. */
104 PVMR3 pVMR3; /* 16 / 12 */
105 /** Ring-0 Host Context VM Pointer. */
106 PVMR0 pVMR0; /* 24 / 16 */
107 /** Raw-mode Context VM Pointer. */
108 PVMRC pVMRC; /* 32 / 20 */
109 /** The CPU ID.
110 * This is the index into the VM::aCpu array. */
111 VMCPUID idCpu; /* 36 / 24 */
112 /** The native thread handle. */
113 RTNATIVETHREAD hNativeThread; /* 40 / 28 */
114 /** The native R0 thread handle. (different from the R3 handle!) */
115 RTNATIVETHREAD hNativeThreadR0; /* 48 / 32 */
116 /** Which host CPU ID is this EMT running on.
117 * Only valid when in RC or HMR0 with scheduling disabled. */
118 RTCPUID volatile idHostCpu; /* 56 / 36 */
119 /** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
120 * @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
121 uint32_t volatile iHostCpuSet; /* 60 / 40 */
122
123 /** Trace groups enable flags. */
124 uint32_t fTraceGroups; /* 64 / 44 */
125 /** Align the structures below bit on a 64-byte boundary and make sure it starts
126 * at the same offset in both 64-bit and 32-bit builds.
127 *
128 * @remarks The alignments of the members that are larger than 48 bytes should be
129 * 64-byte for cache line reasons. structs containing small amounts of
130 * data could be lumped together at the end with a < 64 byte padding
131 * following it (to grow into and align the struct size).
132 * */
133 uint8_t abAlignment1[HC_ARCH_BITS == 64 ? 56 : 12+64];
134 /** State data for use by ad hoc profiling. */
135 uint32_t uAdHoc;
136 /** Profiling samples for use by ad hoc profiling. */
137 STAMPROFILEADV aStatAdHoc[8]; /* size: 40*8 = 320 */
138
139 /** CPUM part. */
140 union
141 {
142#ifdef ___CPUMInternal_h
143 struct CPUMCPU s;
144#endif
145 uint8_t padding[3584]; /* multiple of 64 */
146 } cpum;
147
148 /** HM part. */
149 union
150 {
151#ifdef ___HMInternal_h
152 struct HMCPU s;
153#endif
154 uint8_t padding[5760]; /* multiple of 64 */
155 } hm;
156
157 /** EM part. */
158 union
159 {
160#ifdef ___EMInternal_h
161 struct EMCPU s;
162#endif
163 uint8_t padding[1408]; /* multiple of 64 */
164 } em;
165
166 /** IEM part. */
167 union
168 {
169#ifdef ___IEMInternal_h
170 struct IEMCPU s;
171#endif
172 uint8_t padding[3072]; /* multiple of 64 */
173 } iem;
174
175 /** TRPM part. */
176 union
177 {
178#ifdef ___TRPMInternal_h
179 struct TRPMCPU s;
180#endif
181 uint8_t padding[128]; /* multiple of 64 */
182 } trpm;
183
184 /** TM part. */
185 union
186 {
187#ifdef ___TMInternal_h
188 struct TMCPU s;
189#endif
190 uint8_t padding[384]; /* multiple of 64 */
191 } tm;
192
193 /** VMM part. */
194 union
195 {
196#ifdef ___VMMInternal_h
197 struct VMMCPU s;
198#endif
199 uint8_t padding[704]; /* multiple of 64 */
200 } vmm;
201
202 /** PDM part. */
203 union
204 {
205#ifdef ___PDMInternal_h
206 struct PDMCPU s;
207#endif
208 uint8_t padding[256]; /* multiple of 64 */
209 } pdm;
210
211 /** IOM part. */
212 union
213 {
214#ifdef ___IOMInternal_h
215 struct IOMCPU s;
216#endif
217 uint8_t padding[512]; /* multiple of 64 */
218 } iom;
219
220 /** DBGF part.
221 * @todo Combine this with other tiny structures. */
222 union
223 {
224#ifdef ___DBGFInternal_h
225 struct DBGFCPU s;
226#endif
227 uint8_t padding[64]; /* multiple of 64 */
228 } dbgf;
229
230 /** GIM part. */
231 union
232 {
233#ifdef ___GIMInternal_h
234 struct GIMCPU s;
235#endif
236 uint8_t padding[64]; /* multiple of 64 */
237 } gim;
238
239 /** Align the following members on page boundary. */
240 /*uint8_t abAlignment2[64];*/
241
242 /** PGM part. */
243 union
244 {
245#ifdef ___PGMInternal_h
246 struct PGMCPU s;
247#endif
248 uint8_t padding[4096]; /* multiple of 4096 */
249 } pgm;
250
251} VMCPU;
252
253
254#ifndef VBOX_FOR_DTRACE_LIB
255
256/** @name Operations on VMCPU::enmState
257 * @{ */
258/** Gets the VMCPU state. */
259#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
260/** Sets the VMCPU state. */
261#define VMCPU_SET_STATE(pVCpu, enmNewState) \
262 ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
263/** Cmpares and sets the VMCPU state. */
264#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
265 ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
266/** Checks the VMCPU state. */
267#ifdef VBOX_STRICT
268# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
269 do { \
270 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
271 AssertMsg(enmState == (enmExpectedState), \
272 ("enmState=%d enmExpectedState=%d idCpu=%u\n", \
273 enmState, enmExpectedState, (pVCpu)->idCpu)); \
274 } while (0)
275#else
276# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
277#endif
278/** Tests if the state means that the CPU is started. */
279#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
280/** Tests if the state means that the CPU is stopped. */
281#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
282/** @} */
283
284
285/** The name of the Guest Context VMM Core module. */
286#define VMMGC_MAIN_MODULE_NAME "VMMGC.gc"
287/** The name of the Ring 0 Context VMM Core module. */
288#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
289
290/**
291 * Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
292 */
293#ifdef VBOX_WITH_RAW_MODE
294# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
295#else
296# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
297#endif
298
299
300/** VM Forced Action Flags.
301 *
302 * Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
303 * action mask of a VM.
304 *
305 * @{
306 */
307/** The virtual sync clock has been stopped, go to TM until it has been
308 * restarted... */
309#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(2)
310/** PDM Queues are pending. */
311#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
312/** The bit number for VM_FF_PDM_QUEUES. */
313#define VM_FF_PDM_QUEUES_BIT 3
314/** PDM DMA transfers are pending. */
315#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
316/** The bit number for VM_FF_PDM_DMA. */
317#define VM_FF_PDM_DMA_BIT 4
318/** This action forces the VM to call DBGF so DBGF can service debugger
319 * requests in the emulation thread.
320 * This action flag stays asserted till DBGF clears it.*/
321#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
322/** The bit number for VM_FF_DBGF. */
323#define VM_FF_DBGF_BIT 8
324/** This action forces the VM to service pending requests from other
325 * thread or requests which must be executed in another context. */
326#define VM_FF_REQUEST RT_BIT_32(9)
327/** Check for VM state changes and take appropriate action. */
328#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
329/** The bit number for VM_FF_CHECK_VM_STATE. */
330#define VM_FF_CHECK_VM_STATE_BIT 10
331/** Reset the VM. (postponed) */
332#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
333/** The bit number for VM_FF_RESET. */
334#define VM_FF_RESET_BIT 11
335/** EMT rendezvous in VMM. */
336#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
337/** The bit number for VM_FF_EMT_RENDEZVOUS. */
338#define VM_FF_EMT_RENDEZVOUS_BIT 12
339
340/** PGM needs to allocate handy pages. */
341#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(18)
342/** PGM is out of memory.
343 * Abandon all loops and code paths which can be resumed and get up to the EM
344 * loops. */
345#define VM_FF_PGM_NO_MEMORY RT_BIT_32(19)
346 /** PGM is about to perform a lightweight pool flush
347 * Guest SMP: all EMT threads should return to ring 3
348 */
349#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(20)
350/** REM needs to be informed about handler changes. */
351#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
352/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
353#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
354/** Suspend the VM - debug only. */
355#define VM_FF_DEBUG_SUSPEND RT_BIT_32(31)
356
357
358/** This action forces the VM to check any pending interrups on the APIC. */
359#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(0)
360/** This action forces the VM to check any pending interrups on the PIC. */
361#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(1)
362/** This action forces the VM to schedule and run pending timer (TM).
363 * @remarks Don't move - PATM compatibility. */
364#define VMCPU_FF_TIMER RT_BIT_32(2)
365/** This action forces the VM to check any pending NMIs. */
366#define VMCPU_FF_INTERRUPT_NMI_BIT 3
367#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
368/** This action forces the VM to check any pending SMIs. */
369#define VMCPU_FF_INTERRUPT_SMI_BIT 4
370#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
371/** PDM critical section unlocking is pending, process promptly upon return to R3. */
372#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(5)
373/** This action forces the VM to service pending requests from other
374 * thread or requests which must be executed in another context. */
375#define VMCPU_FF_REQUEST RT_BIT_32(9)
376/** This action forces the VM to service any pending updates to CR3 (used only
377 * by HM). */
378#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_32(12)
379/** This action forces the VM to service any pending updates to PAE PDPEs (used
380 * only by HM). */
381#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_32(13)
382/** This action forces the VM to resync the page tables before going
383 * back to execute guest code. (GLOBAL FLUSH) */
384#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(16)
385/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
386 * (NON-GLOBAL FLUSH) */
387#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(17)
388/** Check for pending TLB shootdown actions.
389 * Consumer: HM
390 * @todo rename to VMCPU_FF_HM_TLB_SHOOTDOWN */
391#define VMCPU_FF_TLB_SHOOTDOWN RT_BIT_32(18)
392/** Check for pending TLB flush action.
393 * Consumer: HM
394 * @todo rename to VMCPU_FF_HM_TLB_FLUSH */
395#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
396/** The bit number for VMCPU_FF_TLB_FLUSH. */
397#define VMCPU_FF_TLB_FLUSH_BIT 19
398#ifdef VBOX_WITH_RAW_MODE
399/** Check the interrupt and trap gates */
400# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(20)
401/** Check Guest's TSS ring 0 stack */
402# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(21)
403/** Check Guest's GDT table */
404# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(22)
405/** Check Guest's LDT table */
406# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(23)
407#endif /* VBOX_WITH_RAW_MODE */
408/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
409#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(24)
410/** Block injection of non-maskable interrupts to the guest. */
411#define VMCPU_FF_BLOCK_NMIS RT_BIT_32(25)
412#ifdef VBOX_WITH_RAW_MODE
413/** CSAM needs to scan the page that's being executed */
414# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(26)
415/** CSAM needs to do some homework. */
416# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(27)
417#endif /* VBOX_WITH_RAW_MODE */
418/** Force return to Ring-3. */
419#define VMCPU_FF_TO_R3 RT_BIT_32(28)
420
421/** Externally VM forced actions. Used to quit the idle/wait loop. */
422#define VM_FF_EXTERNAL_SUSPENDED_MASK (VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST | VM_FF_EMT_RENDEZVOUS)
423/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
424#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK (VMCPU_FF_REQUEST)
425
426/** Externally forced VM actions. Used to quit the idle/wait loop. */
427#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST \
428 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_EMT_RENDEZVOUS)
429/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
430#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_REQUEST \
431 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_TIMER)
432
433/** High priority VM pre-execution actions. */
434#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_TM_VIRTUAL_SYNC \
435 | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
436 | VM_FF_EMT_RENDEZVOUS)
437/** High priority VMCPU pre-execution actions. */
438#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
439 | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
440 | VMCPU_FF_INHIBIT_INTERRUPTS \
441 | VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT \
442 | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT, 0 ) )
443
444/** High priority VM pre raw-mode execution mask. */
445#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK (VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY)
446/** High priority VMCPU pre raw-mode execution mask. */
447#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
448 | VMCPU_FF_INHIBIT_INTERRUPTS \
449 | VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT \
450 | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT, 0) )
451
452/** High priority post-execution actions. */
453#define VM_FF_HIGH_PRIORITY_POST_MASK (VM_FF_PGM_NO_MEMORY)
454/** High priority post-execution actions. */
455#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT | VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
456 | VMCPU_FF_HM_UPDATE_CR3 | VMCPU_FF_HM_UPDATE_PAE_PDPES)
457
458/** Normal priority VM post-execution actions. */
459#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET \
460 | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS)
461/** Normal priority VMCPU post-execution actions. */
462#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0)
463
464/** Normal priority VM actions. */
465#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY \
466 | VM_FF_EMT_RENDEZVOUS)
467/** Normal priority VMCPU actions. */
468#define VMCPU_FF_NORMAL_PRIORITY_MASK (VMCPU_FF_REQUEST)
469
470/** Flags to clear before resuming guest execution. */
471#define VMCPU_FF_RESUME_GUEST_MASK (VMCPU_FF_TO_R3)
472
473/** VM Flags that cause the HM loops to go back to ring-3. */
474#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
475 | VM_FF_PDM_QUEUES | VM_FF_EMT_RENDEZVOUS)
476/** VMCPU Flags that cause the HM loops to go back to ring-3. */
477#define VMCPU_FF_HM_TO_R3_MASK (VMCPU_FF_TO_R3 | VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT)
478
479/** High priority ring-0 VM pre HM-mode execution mask. */
480#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
481/** High priority ring-0 VMCPU pre HM-mode execution mask. */
482#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 \
483 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST)
484/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
485#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PDM_QUEUES \
486 | VM_FF_EMT_RENDEZVOUS | VM_FF_REQUEST \
487 | VM_FF_PDM_DMA) )
488/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
489#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER \
490 | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_REQUEST) )
491
492/** All the forced VM flags. */
493#define VM_FF_ALL_MASK (~0U)
494/** All the forced VMCPU flags. */
495#define VMCPU_FF_ALL_MASK (~0U)
496
497/** All the forced VM flags except those related to raw-mode and hardware
498 * assisted execution. */
499#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) | VM_FF_PGM_NO_MEMORY)
500/** All the forced VMCPU flags except those related to raw-mode and hardware
501 * assisted execution. */
502#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK | VMCPU_FF_PDM_CRITSECT \
503 | VMCPU_FF_TLB_FLUSH | VMCPU_FF_TLB_SHOOTDOWN \
504 | VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
505/** @} */
506
507/** @def VM_FF_SET
508 * Sets a force action flag.
509 *
510 * @param pVM Pointer to the VM.
511 * @param fFlag The flag to set.
512 */
513#if 1
514# define VM_FF_SET(pVM, fFlag) ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag))
515#else
516# define VM_FF_SET(pVM, fFlag) \
517 do { ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
518 RTLogPrintf("VM_FF_SET : %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
519 } while (0)
520#endif
521
522/** @def VMCPU_FF_SET
523 * Sets a force action flag for the given VCPU.
524 *
525 * @param pVCpu Pointer to the VMCPU.
526 * @param fFlag The flag to set.
527 */
528#define VMCPU_FF_SET(pVCpu, fFlag) ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag))
529
530/** @def VM_FF_CLEAR
531 * Clears a force action flag.
532 *
533 * @param pVM Pointer to the VM.
534 * @param fFlag The flag to clear.
535 */
536#if 1
537# define VM_FF_CLEAR(pVM, fFlag) ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag))
538#else
539# define VM_FF_CLEAR(pVM, fFlag) \
540 do { ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
541 RTLogPrintf("VM_FF_CLEAR: %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
542 } while (0)
543#endif
544
545/** @def VMCPU_FF_CLEAR
546 * Clears a force action flag for the given VCPU.
547 *
548 * @param pVCpu Pointer to the VMCPU.
549 * @param fFlag The flag to clear.
550 */
551#define VMCPU_FF_CLEAR(pVCpu, fFlag) ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag))
552
553/** @def VM_FF_IS_SET
554 * Checks if a force action flag is set.
555 *
556 * @param pVM Pointer to the VM.
557 * @param fFlag The flag to check.
558 */
559#define VM_FF_IS_SET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
560
561/** @def VMCPU_FF_IS_SET
562 * Checks if a force action flag is set for the given VCPU.
563 *
564 * @param pVCpu Pointer to the VMCPU.
565 * @param fFlag The flag to check.
566 */
567#define VMCPU_FF_IS_SET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
568
569/** @def VM_FF_IS_PENDING
570 * Checks if one or more force action in the specified set is pending.
571 *
572 * @param pVM Pointer to the VM.
573 * @param fFlags The flags to check for.
574 */
575#define VM_FF_IS_PENDING(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
576
577/** @def VM_FF_TESTANDCLEAR
578 * Checks if one (!) force action in the specified set is pending and clears it atomically
579 *
580 * @returns true if the bit was set.
581 * @returns false if the bit was clear.
582 * @param pVM Pointer to the VM.
583 * @param iBit Bit position to check and clear
584 */
585#define VM_FF_TEST_AND_CLEAR(pVM, iBit) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit##_BIT))
586
587/** @def VMCPU_FF_TESTANDCLEAR
588 * Checks if one (!) force action in the specified set is pending and clears it atomically
589 *
590 * @returns true if the bit was set.
591 * @returns false if the bit was clear.
592 * @param pVCpu Pointer to the VMCPU.
593 * @param iBit Bit position to check and clear
594 */
595#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, iBit) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit##_BIT))
596
597/** @def VMCPU_FF_IS_PENDING
598 * Checks if one or more force action in the specified set is pending for the given VCPU.
599 *
600 * @param pVCpu Pointer to the VMCPU.
601 * @param fFlags The flags to check for.
602 */
603#define VMCPU_FF_IS_PENDING(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
604
605/** @def VM_FF_IS_PENDING_EXCEPT
606 * Checks if one or more force action in the specified set is pending while one
607 * or more other ones are not.
608 *
609 * @param pVM Pointer to the VM.
610 * @param fFlags The flags to check for.
611 * @param fExcpt The flags that should not be set.
612 */
613#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
614
615/** @def VMCPU_FF_IS_PENDING_EXCEPT
616 * Checks if one or more force action in the specified set is pending for the given
617 * VCPU while one or more other ones are not.
618 *
619 * @param pVCpu Pointer to the VMCPU.
620 * @param fFlags The flags to check for.
621 * @param fExcpt The flags that should not be set.
622 */
623#define VMCPU_FF_IS_PENDING_EXCEPT(pVCpu, fFlags, fExcpt) ( ((pVCpu)->fLocalForcedActions & (fFlags)) && !((pVCpu)->fLocalForcedActions & (fExcpt)) )
624
625/** @def VM_IS_EMT
626 * Checks if the current thread is the emulation thread (EMT).
627 *
628 * @remark The ring-0 variation will need attention if we expand the ring-0
629 * code to let threads other than EMT mess around with the VM.
630 */
631#ifdef IN_RC
632# define VM_IS_EMT(pVM) true
633#else
634# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
635#endif
636
637/** @def VMCPU_IS_EMT
638 * Checks if the current thread is the emulation thread (EMT) for the specified
639 * virtual CPU.
640 */
641#ifdef IN_RC
642# define VMCPU_IS_EMT(pVCpu) true
643#else
644# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
645#endif
646
647/** @def VM_ASSERT_EMT
648 * Asserts that the current thread IS the emulation thread (EMT).
649 */
650#ifdef IN_RC
651# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
652#elif defined(IN_RING0)
653# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
654#else
655# define VM_ASSERT_EMT(pVM) \
656 AssertMsg(VM_IS_EMT(pVM), \
657 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
658#endif
659
660/** @def VMCPU_ASSERT_EMT
661 * Asserts that the current thread IS the emulation thread (EMT) of the
662 * specified virtual CPU.
663 */
664#ifdef IN_RC
665# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
666#elif defined(IN_RING0)
667# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
668 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
669 RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
670 (pVCpu) ? (pVCpu)->idCpu : 0))
671#else
672# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
673 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
674 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
675#endif
676
677/** @def VM_ASSERT_EMT_RETURN
678 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
679 */
680#ifdef IN_RC
681# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
682#elif defined(IN_RING0)
683# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
684#else
685# define VM_ASSERT_EMT_RETURN(pVM, rc) \
686 AssertMsgReturn(VM_IS_EMT(pVM), \
687 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
688 (rc))
689#endif
690
691/** @def VMCPU_ASSERT_EMT_RETURN
692 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
693 */
694#ifdef IN_RC
695# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
696#elif defined(IN_RING0)
697# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
698#else
699# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
700 AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
701 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
702 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
703 (rc))
704#endif
705
706/** @def VMCPU_ASSERT_EMT_OR_GURU
707 * Asserts that the current thread IS the emulation thread (EMT) of the
708 * specified virtual CPU.
709 */
710#if defined(IN_RC) || defined(IN_RING0)
711# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
712 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
713 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
714#else
715# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
716 AssertMsg( VMCPU_IS_EMT(pVCpu) \
717 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
718 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
719 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
720 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
721#endif
722
723/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
724 * Asserts that the current thread IS the emulation thread (EMT) of the
725 * specified virtual CPU when the VM is running.
726 */
727#if defined(IN_RC) || defined(IN_RING0)
728# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
729 Assert( VMCPU_IS_EMT(pVCpu) \
730 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING \
731 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING_LS \
732 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING_FT )
733#else
734# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
735 AssertMsg( VMCPU_IS_EMT(pVCpu) \
736 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING \
737 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING_LS \
738 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING_FT, \
739 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
740 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
741#endif
742
743/** @def VM_ASSERT_EMT0
744 * Asserts that the current thread IS emulation thread \#0 (EMT0).
745 */
746#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
747
748/** @def VM_ASSERT_EMT0_RETURN
749 * Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
750 * it isn't.
751 */
752#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
753
754
755/**
756 * Asserts that the current thread is NOT the emulation thread.
757 */
758#define VM_ASSERT_OTHER_THREAD(pVM) \
759 AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
760
761
762/** @def VM_ASSERT_STATE_RETURN
763 * Asserts a certain VM state.
764 */
765#define VM_ASSERT_STATE(pVM, _enmState) \
766 AssertMsg((pVM)->enmVMState == (_enmState), \
767 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
768
769/** @def VM_ASSERT_STATE_RETURN
770 * Asserts a certain VM state and returns if it doesn't match.
771 */
772#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
773 AssertMsgReturn((pVM)->enmVMState == (_enmState), \
774 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
775 (rc))
776
777/** @def VM_IS_VALID_EXT
778 * Asserts a the VM handle is valid for external access, i.e. not being destroy
779 * or terminated. */
780#define VM_IS_VALID_EXT(pVM) \
781 ( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
782 && ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
783 || ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
784 && VM_IS_EMT(pVM))) )
785
786/** @def VM_ASSERT_VALID_EXT_RETURN
787 * Asserts a the VM handle is valid for external access, i.e. not being
788 * destroy or terminated.
789 */
790#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
791 AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
792 ("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
793 ? VMGetStateName(pVM->enmVMState) : ""), \
794 (rc))
795
796/** @def VMCPU_ASSERT_VALID_EXT_RETURN
797 * Asserts a the VMCPU handle is valid for external access, i.e. not being
798 * destroy or terminated.
799 */
800#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
801 AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
802 && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
803 && (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
804 ("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
805 RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
806 ? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
807 (rc))
808
809#endif /* !VBOX_FOR_DTRACE_LIB */
810
811
812
813/**
814 * The cross context VM structure.
815 *
816 * It contains all the VM data which have to be available in all contexts.
817 * Even if it contains all the data the idea is to use APIs not to modify all
818 * the members all around the place. Therefore we make use of unions to hide
819 * everything which isn't local to the current source module. This means we'll
820 * have to pay a little bit of attention when adding new members to structures
821 * in the unions and make sure to keep the padding sizes up to date.
822 *
823 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
824 */
825typedef struct VM
826{
827 /** The state of the VM.
828 * This field is read only to everyone except the VM and EM. */
829 VMSTATE volatile enmVMState;
830 /** Forced action flags.
831 * See the VM_FF_* \#defines. Updated atomically.
832 */
833 volatile uint32_t fGlobalForcedActions;
834 /** Pointer to the array of page descriptors for the VM structure allocation. */
835 R3PTRTYPE(PSUPPAGE) paVMPagesR3;
836 /** Session handle. For use when calling SUPR0 APIs. */
837 PSUPDRVSESSION pSession;
838 /** Pointer to the ring-3 VM structure. */
839 PUVM pUVM;
840 /** Ring-3 Host Context VM Pointer. */
841 R3PTRTYPE(struct VM *) pVMR3;
842 /** Ring-0 Host Context VM Pointer. */
843 R0PTRTYPE(struct VM *) pVMR0;
844 /** Raw-mode Context VM Pointer. */
845 RCPTRTYPE(struct VM *) pVMRC;
846
847 /** The GVM VM handle. Only the GVM should modify this field. */
848 uint32_t hSelf;
849 /** Number of virtual CPUs. */
850 uint32_t cCpus;
851 /** CPU excution cap (1-100) */
852 uint32_t uCpuExecutionCap;
853
854 /** Size of the VM structure including the VMCPU array. */
855 uint32_t cbSelf;
856
857 /** Offset to the VMCPU array starting from beginning of this structure. */
858 uint32_t offVMCPU;
859
860 /**
861 * VMMSwitcher assembly entry point returning to host context.
862 *
863 * Depending on how the host handles the rc status given in @a eax, this may
864 * return and let the caller resume whatever it was doing prior to the call.
865 *
866 *
867 * @param eax The return code, register.
868 * @remark Assume interrupts disabled.
869 * @remark This method pointer lives here because TRPM needs it.
870 */
871 RTRCPTR pfnVMMRCToHostAsm/*(int32_t eax)*/;
872
873 /**
874 * VMMSwitcher assembly entry point returning to host context without saving the
875 * raw-mode context (hyper) registers.
876 *
877 * Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
878 * expects the caller to save a RC context in CPUM where one might return if the
879 * return code indicate that this is possible.
880 *
881 * This method pointer lives here because TRPM needs it.
882 *
883 * @param eax The return code, register.
884 * @remark Assume interrupts disabled.
885 * @remark This method pointer lives here because TRPM needs it.
886 */
887 RTRCPTR pfnVMMRCToHostAsmNoReturn/*(int32_t eax)*/;
888
889 /** @name Various items that are frequently accessed.
890 * @{ */
891 /** Whether to recompile user mode code or run it raw/hm. */
892 bool fRecompileUser;
893 /** Whether to recompile supervisor mode code or run it raw/hm. */
894 bool fRecompileSupervisor;
895 /** Whether raw mode supports ring-1 code or not. */
896 bool fRawRing1Enabled;
897 /** PATM enabled flag.
898 * This is placed here for performance reasons. */
899 bool fPATMEnabled;
900 /** CSAM enabled flag.
901 * This is placed here for performance reasons. */
902 bool fCSAMEnabled;
903 /** Hardware VM support is available and enabled.
904 * Determined very early during init.
905 * This is placed here for performance reasons. */
906 bool fHMEnabled;
907 /** For asserting on fHMEnable usage. */
908 bool fHMEnabledFixed;
909 /** Hardware VM support requires a minimal raw-mode context.
910 * This is never set on 64-bit hosts, only 32-bit hosts requires it. */
911 bool fHMNeedRawModeCtx;
912 /** Set when this VM is the master FT node.
913 * @todo This doesn't need to be here, FTM should store it in it's own
914 * structures instead. */
915 bool fFaultTolerantMaster;
916 /** Large page enabled flag.
917 * @todo This doesn't need to be here, PGM should store it in it's own
918 * structures instead. */
919 bool fUseLargePages;
920 /** @} */
921
922 /** Alignment padding.. */
923 uint8_t uPadding1[2];
924
925 /** @name Debugging
926 * @{ */
927 /** Raw-mode Context VM Pointer. */
928 RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
929 /** Ring-3 Host Context VM Pointer. */
930 R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
931 /** Ring-0 Host Context VM Pointer. */
932 R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
933 /** @} */
934
935#if HC_ARCH_BITS == 32
936 /** Alignment padding.. */
937 uint32_t uPadding2;
938#endif
939
940 /** @name Switcher statistics (remove)
941 * @{ */
942 /** Profiling the total time from Qemu to GC. */
943 STAMPROFILEADV StatTotalQemuToGC;
944 /** Profiling the total time from GC to Qemu. */
945 STAMPROFILEADV StatTotalGCToQemu;
946 /** Profiling the total time spent in GC. */
947 STAMPROFILEADV StatTotalInGC;
948 /** Profiling the total time spent not in Qemu. */
949 STAMPROFILEADV StatTotalInQemu;
950 /** Profiling the VMMSwitcher code for going to GC. */
951 STAMPROFILEADV StatSwitcherToGC;
952 /** Profiling the VMMSwitcher code for going to HC. */
953 STAMPROFILEADV StatSwitcherToHC;
954 STAMPROFILEADV StatSwitcherSaveRegs;
955 STAMPROFILEADV StatSwitcherSysEnter;
956 STAMPROFILEADV StatSwitcherDebug;
957 STAMPROFILEADV StatSwitcherCR0;
958 STAMPROFILEADV StatSwitcherCR4;
959 STAMPROFILEADV StatSwitcherJmpCR3;
960 STAMPROFILEADV StatSwitcherRstrRegs;
961 STAMPROFILEADV StatSwitcherLgdt;
962 STAMPROFILEADV StatSwitcherLidt;
963 STAMPROFILEADV StatSwitcherLldt;
964 STAMPROFILEADV StatSwitcherTSS;
965 /** @} */
966
967 /** Padding - the unions must be aligned on a 64 bytes boundary and the unions
968 * must start at the same offset on both 64-bit and 32-bit hosts. */
969 uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
970
971 /** CPUM part. */
972 union
973 {
974#ifdef ___CPUMInternal_h
975 struct CPUM s;
976#endif
977 uint8_t padding[1536]; /* multiple of 64 */
978 } cpum;
979
980 /** VMM part. */
981 union
982 {
983#ifdef ___VMMInternal_h
984 struct VMM s;
985#endif
986 uint8_t padding[1600]; /* multiple of 64 */
987 } vmm;
988
989 /** PGM part. */
990 union
991 {
992#ifdef ___PGMInternal_h
993 struct PGM s;
994#endif
995 uint8_t padding[4096*2+6080]; /* multiple of 64 */
996 } pgm;
997
998 /** HM part. */
999 union
1000 {
1001#ifdef ___HMInternal_h
1002 struct HM s;
1003#endif
1004 uint8_t padding[5440]; /* multiple of 64 */
1005 } hm;
1006
1007 /** TRPM part. */
1008 union
1009 {
1010#ifdef ___TRPMInternal_h
1011 struct TRPM s;
1012#endif
1013 uint8_t padding[5248]; /* multiple of 64 */
1014 } trpm;
1015
1016 /** SELM part. */
1017 union
1018 {
1019#ifdef ___SELMInternal_h
1020 struct SELM s;
1021#endif
1022 uint8_t padding[768]; /* multiple of 64 */
1023 } selm;
1024
1025 /** MM part. */
1026 union
1027 {
1028#ifdef ___MMInternal_h
1029 struct MM s;
1030#endif
1031 uint8_t padding[192]; /* multiple of 64 */
1032 } mm;
1033
1034 /** PDM part. */
1035 union
1036 {
1037#ifdef ___PDMInternal_h
1038 struct PDM s;
1039#endif
1040 uint8_t padding[1920]; /* multiple of 64 */
1041 } pdm;
1042
1043 /** IOM part. */
1044 union
1045 {
1046#ifdef ___IOMInternal_h
1047 struct IOM s;
1048#endif
1049 uint8_t padding[896]; /* multiple of 64 */
1050 } iom;
1051
1052 /** PATM part. */
1053 union
1054 {
1055#ifdef ___PATMInternal_h
1056 struct PATM s;
1057#endif
1058 uint8_t padding[768]; /* multiple of 64 */
1059 } patm;
1060
1061 /** CSAM part. */
1062 union
1063 {
1064#ifdef ___CSAMInternal_h
1065 struct CSAM s;
1066#endif
1067 uint8_t padding[1088]; /* multiple of 64 */
1068 } csam;
1069
1070 /** EM part. */
1071 union
1072 {
1073#ifdef ___EMInternal_h
1074 struct EM s;
1075#endif
1076 uint8_t padding[256]; /* multiple of 64 */
1077 } em;
1078
1079 /** TM part. */
1080 union
1081 {
1082#ifdef ___TMInternal_h
1083 struct TM s;
1084#endif
1085 uint8_t padding[2496]; /* multiple of 64 */
1086 } tm;
1087
1088 /** DBGF part. */
1089 union
1090 {
1091#ifdef ___DBGFInternal_h
1092 struct DBGF s;
1093#endif
1094 uint8_t padding[2368]; /* multiple of 64 */
1095 } dbgf;
1096
1097 /** SSM part. */
1098 union
1099 {
1100#ifdef ___SSMInternal_h
1101 struct SSM s;
1102#endif
1103 uint8_t padding[128]; /* multiple of 64 */
1104 } ssm;
1105
1106 /** FTM part. */
1107 union
1108 {
1109#ifdef ___FTMInternal_h
1110 struct FTM s;
1111#endif
1112 uint8_t padding[512]; /* multiple of 64 */
1113 } ftm;
1114
1115 /** REM part. */
1116 union
1117 {
1118#ifdef ___REMInternal_h
1119 struct REM s;
1120#endif
1121 uint8_t padding[0x11100]; /* multiple of 64 */
1122 } rem;
1123
1124 union
1125 {
1126#ifdef ___GIMInternal_h
1127 struct GIM s;
1128#endif
1129 uint8_t padding[256]; /* multiple of 64 */
1130 } gim;
1131
1132 /* ---- begin small stuff ---- */
1133
1134 /** VM part. */
1135 union
1136 {
1137#ifdef ___VMInternal_h
1138 struct VMINT s;
1139#endif
1140 uint8_t padding[24]; /* multiple of 8 */
1141 } vm;
1142
1143 /** CFGM part. */
1144 union
1145 {
1146#ifdef ___CFGMInternal_h
1147 struct CFGM s;
1148#endif
1149 uint8_t padding[8]; /* multiple of 8 */
1150 } cfgm;
1151
1152
1153 /** Padding for aligning the cpu array on a page boundary. */
1154 uint8_t abAlignment2[94];
1155
1156 /* ---- end small stuff ---- */
1157
1158 /** VMCPU array for the configured number of virtual CPUs.
1159 * Must be aligned on a page boundary for TLB hit reasons as well as
1160 * alignment of VMCPU members. */
1161 VMCPU aCpus[1];
1162} VM;
1163
1164
1165#ifdef IN_RC
1166RT_C_DECLS_BEGIN
1167
1168/** The VM structure.
1169 * This is imported from the VMMGCBuiltin module, i.e. it's a one
1170 * of those magic globals which we should avoid using.
1171 */
1172extern DECLIMPORT(VM) g_VM;
1173
1174RT_C_DECLS_END
1175#endif
1176
1177/** @} */
1178
1179#endif
1180
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