vm.h@ 76290

Last change on this file since 76290 was 75997, checked in by vboxsync, 6 years ago
VMM/EM: Nested VMX: bugref:9180 Include APIC-write FF in the high-priority post-execution FF mask. Add VMCPU_FF_INTERRUPT_NESTED_GUEST among the flags we check to reschedule from a MWAIT keeping in mind when virtual posted-interrupts may be implemented.
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Executing guest code using NEM. */
80	VMCPUSTATE_STARTED_EXEC_NEM,
81	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83	/** Halted. */
84	VMCPUSTATE_STARTED_HALTED,
85
86	/** The end of valid virtual CPU states. */
87	VMCPUSTATE_END,
88
89	/** Ensure 32-bit type. */
90	VMCPUSTATE_32BIT_HACK = 0x7fffffff
91	} VMCPUSTATE;
92
93	/** Enables 64-bit FFs. */
94	#define VMCPU_WITH_64_BIT_FFS
95
96
97	/**
98	* The cross context virtual CPU structure.
99	*
100	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
101	*/
102	typedef struct VMCPU
103	{
104	/** @name Volatile per-cpu data.
105	* @{ */
106	/** Per CPU forced action.
107	* See the VMCPU_FF_* \#defines. Updated atomically. */
108	#ifdef VMCPU_WITH_64_BIT_FFS
109	uint64_t volatile fLocalForcedActions;
110	#else
111	uint32_t volatile fLocalForcedActions;
112	uint32_t fForLocalForcedActionsExpansion;
113	#endif
114	/** The CPU state. */
115	VMCPUSTATE volatile enmState;
116
117	/** Which host CPU ID is this EMT running on.
118	* Only valid when in RC or HMR0 with scheduling disabled. */
119	RTCPUID volatile idHostCpu;
120	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
121	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
122	uint32_t volatile iHostCpuSet;
123	/** Padding up to 64 bytes. */
124	uint8_t abAlignment0[64 - 20];
125	/** @} */
126
127	/** IEM part.
128	* @remarks This comes first as it allows the use of 8-bit immediates for the
129	* first 64 bytes of the structure, reducing code size a wee bit. */
130	#ifdef ___IEMInternal_h /* For PDB hacking. */
131	union VMCPUUNIONIEMFULL
132	#else
133	union VMCPUUNIONIEMSTUB
134	#endif
135	{
136	#ifdef ___IEMInternal_h
137	struct IEMCPU s;
138	#endif
139	uint8_t padding[18496]; /* multiple of 64 */
140	} iem;
141
142	/** @name Static per-cpu data.
143	* (Putting this after IEM, hoping that it's less frequently used than it.)
144	* @{ */
145	/** The CPU ID.
146	* This is the index into the VM::aCpu array. */
147	VMCPUID idCpu;
148	/** Raw-mode Context VM Pointer. */
149	PVMRC pVMRC;
150	/** Ring-3 Host Context VM Pointer. */
151	PVMR3 pVMR3;
152	/** Ring-0 Host Context VM Pointer. */
153	PVMR0 pVMR0;
154	/** Pointer to the ring-3 UVMCPU structure. */
155	PUVMCPU pUVCpu;
156	/** The native thread handle. */
157	RTNATIVETHREAD hNativeThread;
158	/** The native R0 thread handle. (different from the R3 handle!) */
159	RTNATIVETHREAD hNativeThreadR0;
160	/** Align the structures below bit on a 64-byte boundary and make sure it starts
161	* at the same offset in both 64-bit and 32-bit builds.
162	*
163	* @remarks The alignments of the members that are larger than 48 bytes should be
164	* 64-byte for cache line reasons. structs containing small amounts of
165	* data could be lumped together at the end with a < 64 byte padding
166	* following it (to grow into and align the struct size).
167	*/
168	uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
169	/** @} */
170
171	/** HM part. */
172	union VMCPUUNIONHM
173	{
174	#ifdef ___HMInternal_h
175	struct HMCPU s;
176	#endif
177	uint8_t padding[5888]; /* multiple of 64 */
178	} hm;
179
180	/** NEM part. */
181	union VMCPUUNIONNEM
182	{
183	#ifdef ___NEMInternal_h
184	struct NEMCPU s;
185	#endif
186	uint8_t padding[512]; /* multiple of 64 */
187	} nem;
188
189	/** TRPM part. */
190	union VMCPUUNIONTRPM
191	{
192	#ifdef ___TRPMInternal_h
193	struct TRPMCPU s;
194	#endif
195	uint8_t padding[128]; /* multiple of 64 */
196	} trpm;
197
198	/** TM part. */
199	union VMCPUUNIONTM
200	{
201	#ifdef ___TMInternal_h
202	struct TMCPU s;
203	#endif
204	uint8_t padding[384]; /* multiple of 64 */
205	} tm;
206
207	/** VMM part. */
208	union VMCPUUNIONVMM
209	{
210	#ifdef ___VMMInternal_h
211	struct VMMCPU s;
212	#endif
213	uint8_t padding[896]; /* multiple of 64 */
214	} vmm;
215
216	/** PDM part. */
217	union VMCPUUNIONPDM
218	{
219	#ifdef ___PDMInternal_h
220	struct PDMCPU s;
221	#endif
222	uint8_t padding[256]; /* multiple of 64 */
223	} pdm;
224
225	/** IOM part. */
226	union VMCPUUNIONIOM
227	{
228	#ifdef ___IOMInternal_h
229	struct IOMCPU s;
230	#endif
231	uint8_t padding[512]; /* multiple of 64 */
232	} iom;
233
234	/** DBGF part.
235	* @todo Combine this with other tiny structures. */
236	union VMCPUUNIONDBGF
237	{
238	#ifdef ___DBGFInternal_h
239	struct DBGFCPU s;
240	#endif
241	uint8_t padding[256]; /* multiple of 64 */
242	} dbgf;
243
244	/** GIM part. */
245	union VMCPUUNIONGIM
246	{
247	#ifdef ___GIMInternal_h
248	struct GIMCPU s;
249	#endif
250	uint8_t padding[512]; /* multiple of 64 */
251	} gim;
252
253	/** APIC part. */
254	union VMCPUUNIONAPIC
255	{
256	#ifdef ___APICInternal_h
257	struct APICCPU s;
258	#endif
259	uint8_t padding[1792]; /* multiple of 64 */
260	} apic;
261
262	/*
263	* Some less frequently used global members that doesn't need to take up
264	* precious space at the head of the structure.
265	*/
266
267	/** Trace groups enable flags. */
268	uint32_t fTraceGroups; /* 64 / 44 */
269	/** State data for use by ad hoc profiling. */
270	uint32_t uAdHoc;
271	/** Profiling samples for use by ad hoc profiling. */
272	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
273
274	/** Align the following members on page boundary. */
275	uint8_t abAlignment2[2680];
276
277	/** PGM part. */
278	union VMCPUUNIONPGM
279	{
280	#ifdef ___PGMInternal_h
281	struct PGMCPU s;
282	#endif
283	uint8_t padding[4096]; /* multiple of 4096 */
284	} pgm;
285
286	/** CPUM part. */
287	union VMCPUUNIONCPUM
288	{
289	#ifdef ___CPUMInternal_h
290	struct CPUMCPU s;
291	#endif
292	#ifdef VMCPU_INCL_CPUM_GST_CTX
293	/** The guest CPUM context for direct use by execution engines.
294	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
295	* others. The rest will use the function based CPUM API. */
296	CPUMCTX GstCtx;
297	#endif
298	uint8_t padding[4096]; /* multiple of 4096 */
299	} cpum;
300
301	/** EM part. */
302	union VMCPUUNIONEM
303	{
304	#ifdef ___EMInternal_h
305	struct EMCPU s;
306	#endif
307	uint8_t padding[40960]; /* multiple of 4096 */
308	} em;
309	} VMCPU;
310
311
312	#ifndef VBOX_FOR_DTRACE_LIB
313
314	/** @name Operations on VMCPU::enmState
315	* @{ */
316	/** Gets the VMCPU state. */
317	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
318	/** Sets the VMCPU state. */
319	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
320	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
321	/** Cmpares and sets the VMCPU state. */
322	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
323	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
324	/** Checks the VMCPU state. */
325	#ifdef VBOX_STRICT
326	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
327	do { \
328	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
329	AssertMsg(enmState == (enmExpectedState), \
330	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
331	enmState, enmExpectedState, (pVCpu)->idCpu)); \
332	} while (0)
333	#else
334	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
335	#endif
336	/** Tests if the state means that the CPU is started. */
337	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
338	/** Tests if the state means that the CPU is stopped. */
339	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
340	/** @} */
341
342
343	/** The name of the raw-mode context VMM Core module. */
344	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
345	/** The name of the ring-0 context VMM Core module. */
346	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
347
348	/**
349	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
350	*/
351	#ifdef VBOX_WITH_RAW_MODE
352	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
353	#else
354	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
355	#endif
356
357
358	/** VM Forced Action Flags.
359	*
360	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
361	* action mask of a VM.
362	*
363	* Available VM bits:
364	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
365	*
366	*
367	* Available VMCPU bits:
368	* 14, 15, 34 to 63
369	*
370	* @todo If we run low on VMCPU, we may consider merging the SELM bits
371	*
372	* @{
373	*/
374	/** The virtual sync clock has been stopped, go to TM until it has been
375	* restarted... */
376	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
377	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
378	/** PDM Queues are pending. */
379	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
380	/** The bit number for VM_FF_PDM_QUEUES. */
381	#define VM_FF_PDM_QUEUES_BIT 3
382	/** PDM DMA transfers are pending. */
383	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
384	/** The bit number for VM_FF_PDM_DMA. */
385	#define VM_FF_PDM_DMA_BIT 4
386	/** This action forces the VM to call DBGF so DBGF can service debugger
387	* requests in the emulation thread.
388	* This action flag stays asserted till DBGF clears it.*/
389	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
390	/** The bit number for VM_FF_DBGF. */
391	#define VM_FF_DBGF_BIT 8
392	/** This action forces the VM to service pending requests from other
393	* thread or requests which must be executed in another context. */
394	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
395	#define VM_FF_REQUEST_BIT 9
396	/** Check for VM state changes and take appropriate action. */
397	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
398	/** The bit number for VM_FF_CHECK_VM_STATE. */
399	#define VM_FF_CHECK_VM_STATE_BIT 10
400	/** Reset the VM. (postponed) */
401	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
402	/** The bit number for VM_FF_RESET. */
403	#define VM_FF_RESET_BIT 11
404	/** EMT rendezvous in VMM. */
405	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
406	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
407	#define VM_FF_EMT_RENDEZVOUS_BIT 12
408
409	/** PGM needs to allocate handy pages. */
410	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
411	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
412	/** PGM is out of memory.
413	* Abandon all loops and code paths which can be resumed and get up to the EM
414	* loops. */
415	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
416	#define VM_FF_PGM_NO_MEMORY_BIT 19
417	/** PGM is about to perform a lightweight pool flush
418	* Guest SMP: all EMT threads should return to ring 3
419	*/
420	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
421	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
422	/** REM needs to be informed about handler changes. */
423	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
424	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
425	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
426	/** Suspend the VM - debug only. */
427	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
428	#define VM_FF_DEBUG_SUSPEND_BIT 31
429
430
431	/** This action forces the VM to check any pending interrupts on the APIC. */
432	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
433	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
434	/** This action forces the VM to check any pending interrups on the PIC. */
435	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
436	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
437	/** This action forces the VM to schedule and run pending timer (TM).
438	* @remarks Don't move - PATM compatibility. */
439	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
440	#define VMCPU_FF_TIMER_BIT 2
441	/** This action forces the VM to check any pending NMIs. */
442	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
443	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
444	/** This action forces the VM to check any pending SMIs. */
445	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
446	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
447	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
448	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
449	#define VMCPU_FF_PDM_CRITSECT_BIT 5
450	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
451	* the virtual CPU out of the next (/current) halted state. It is not processed
452	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
453	* is cleared the next time EM leaves the HALTED state. */
454	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
455	#define VMCPU_FF_UNHALT_BIT 6
456	/** Pending IEM action (mask). */
457	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
458	/** Pending IEM action (bit number). */
459	#define VMCPU_FF_IEM_BIT 7
460	/** Pending APIC action (bit number). */
461	#define VMCPU_FF_UPDATE_APIC_BIT 8
462	/** This action forces the VM to update APIC's asynchronously arrived
463	* interrupts as pending interrupts. */
464	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
465	/** This action forces the VM to service pending requests from other
466	* thread or requests which must be executed in another context. */
467	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
468	#define VMCPU_FF_REQUEST_BIT 9
469	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
470	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
471	/** The bit number for VMCPU_FF_DBGF. */
472	#define VMCPU_FF_DBGF_BIT 10
473	/** This action forces the VM to service any pending updates to CR3 (used only
474	* by HM). */
475	/** Hardware virtualized nested-guest interrupt pending. */
476	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
477	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
478	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
479	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
480	/** This action forces the VM to service any pending updates to PAE PDPEs (used
481	* only by HM). */
482	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
483	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
484	/** This action forces the VM to resync the page tables before going
485	* back to execute guest code. (GLOBAL FLUSH) */
486	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
487	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
488	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
489	* (NON-GLOBAL FLUSH) */
490	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
491	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
492	/** Check for pending TLB shootdown actions (deprecated)
493	* Reserved for furture HM re-use if necessary / safe.
494	* Consumer: HM */
495	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
496	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
497	/** Check for pending TLB flush action.
498	* Consumer: HM
499	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
500	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
501	/** The bit number for VMCPU_FF_TLB_FLUSH. */
502	#define VMCPU_FF_TLB_FLUSH_BIT 19
503	#ifdef VBOX_WITH_RAW_MODE
504	/** Check the interrupt and trap gates */
505	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_64(VMCPU_FF_TRPM_SYNC_IDT_BIT)
506	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
507	/** Check Guest's TSS ring 0 stack */
508	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_64(VMCPU_FF_SELM_SYNC_TSS_BIT)
509	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
510	/** Check Guest's GDT table */
511	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_64(VMCPU_FF_SELM_SYNC_GDT_BIT)
512	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
513	/** Check Guest's LDT table */
514	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_64(VMCPU_FF_SELM_SYNC_LDT_BIT)
515	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
516	#endif /* VBOX_WITH_RAW_MODE */
517	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
518	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
519	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
520	/** Block injection of non-maskable interrupts to the guest. */
521	#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
522	#define VMCPU_FF_BLOCK_NMIS_BIT 25
523	#ifdef VBOX_WITH_RAW_MODE
524	/** CSAM needs to scan the page that's being executed */
525	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_64(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
526	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
527	/** CSAM needs to do some homework. */
528	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_64(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
529	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
530	#endif /* VBOX_WITH_RAW_MODE */
531	/** Force return to Ring-3. */
532	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
533	#define VMCPU_FF_TO_R3_BIT 28
534	/** Force return to ring-3 to service pending I/O or MMIO write.
535	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
536	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
537	* status codes to be propagated at the same time without loss. */
538	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
539	#define VMCPU_FF_IOM_BIT 29
540	#ifdef VBOX_WITH_RAW_MODE
541	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
542	# define VMCPU_FF_CPUM RT_BIT_64(VMCPU_FF_CPUM_BIT)
543	/** The bit number for VMCPU_FF_CPUM. */
544	# define VMCPU_FF_CPUM_BIT 30
545	#endif /* VBOX_WITH_RAW_MODE */
546	/** VMX-preemption timer in effect. */
547	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
548	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
549	/** Pending MTF (Monitor Trap Flag) event. */
550	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
551	#define VMCPU_FF_VMX_MTF_BIT 32
552	/** VMX APIC-write emulation pending. */
553	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
554	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
555
556
557	/** Externally VM forced actions. Used to quit the idle/wait loop. */
558	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
559	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
560	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
561
562	/** Externally forced VM actions. Used to quit the idle/wait loop. */
563	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
564	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
565	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
566	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
567	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
568	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
569	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
570
571	/** High priority VM pre-execution actions. */
572	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
573	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
574	\| VM_FF_EMT_RENDEZVOUS )
575	/** High priority VMCPU pre-execution actions. */
576	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
577	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
578	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
579	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \
580	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
581	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
582
583	/** High priority VM pre raw-mode execution mask. */
584	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
585	/** High priority VMCPU pre raw-mode execution mask. */
586	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
587	\| VMCPU_FF_INHIBIT_INTERRUPTS \
588	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
589	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
590
591	/** High priority post-execution actions. */
592	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
593	/** High priority post-execution actions. */
594	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
595	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
596	\| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_IEM \| VMCPU_FF_IOM )
597
598	/** Normal priority VM post-execution actions. */
599	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
600	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
601	/** Normal priority VMCPU post-execution actions. */
602	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
603
604	/** Normal priority VM actions. */
605	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
606	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
607	/** Normal priority VMCPU actions. */
608	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
609
610	/** Flags to clear before resuming guest execution. */
611	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
612
613
614	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
615	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
616	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
617	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
618	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
619	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
620	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
621	#ifdef IN_RING3
622	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \
623	\| VMCPU_FF_VMX_MTF )
624	#else
625	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
626	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF )
627	#endif
628	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
629	* enabled. */
630	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
631	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
632	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
633	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
634	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
635	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
636	* disabled. */
637	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
638	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
639	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
640
641	/** VM Flags that cause the HM loops to go back to ring-3. */
642	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
643	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
644	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
645	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
646	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
647
648	/** High priority ring-0 VM pre HM-mode execution mask. */
649	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
650	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
651	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
652	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
653	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
654	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
655	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
656	\| VM_FF_PDM_DMA) )
657	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
658	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
659	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
660
661	/** All the forced VM flags. */
662	#define VM_FF_ALL_MASK (UINT32_MAX)
663	/** All the forced VMCPU flags. */
664	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
665
666	/** All the forced VM flags except those related to raw-mode and hardware
667	* assisted execution. */
668	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
669	/** All the forced VMCPU flags except those related to raw-mode and hardware
670	* assisted execution. */
671	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
672	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
673	/** @} */
674
675	/** @def VM_FF_SET
676	* Sets a single force action flag.
677	*
678	* @param pVM The cross context VM structure.
679	* @param fFlag The flag to set.
680	*/
681	#define VM_FF_SET(pVM, fFlag) do { \
682	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
683	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
684	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
685	} while (0)
686
687	/** @def VMCPU_FF_SET
688	* Sets a single force action flag for the given VCPU.
689	*
690	* @param pVCpu The cross context virtual CPU structure.
691	* @param fFlag The flag to set.
692	* @sa VMCPU_FF_SET_MASK
693	*/
694	#ifdef VMCPU_WITH_64_BIT_FFS
695	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
696	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
697	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
698	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
699	} while (0)
700	#else
701	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
702	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
703	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
704	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
705	} while (0)
706	#endif
707
708	/** @def VMCPU_FF_SET_MASK
709	* Sets a two or more force action flag for the given VCPU.
710	*
711	* @param pVCpu The cross context virtual CPU structure.
712	* @param fFlags The flags to set.
713	* @sa VMCPU_FF_SET
714	*/
715	#ifdef VMCPU_WITH_64_BIT_FFS
716	# if ARCH_BITS > 32
717	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
718	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
719	# else
720	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
721	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
722	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
723	} while (0)
724	# endif
725	#else
726	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
727	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
728	#endif
729
730	/** @def VM_FF_CLEAR
731	* Clears a single force action flag.
732	*
733	* @param pVM The cross context VM structure.
734	* @param fFlag The flag to clear.
735	*/
736	#define VM_FF_CLEAR(pVM, fFlag) do { \
737	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
738	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
739	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
740	} while (0)
741
742	/** @def VMCPU_FF_CLEAR
743	* Clears a single force action flag for the given VCPU.
744	*
745	* @param pVCpu The cross context virtual CPU structure.
746	* @param fFlag The flag to clear.
747	*/
748	#ifdef VMCPU_WITH_64_BIT_FFS
749	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
750	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
751	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
752	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
753	} while (0)
754	#else
755	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
756	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
757	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
758	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
759	} while (0)
760	#endif
761
762	/** @def VMCPU_FF_CLEAR_MASK
763	* Clears two or more force action flags for the given VCPU.
764	*
765	* @param pVCpu The cross context virtual CPU structure.
766	* @param fFlags The flags to clear.
767	*/
768	#ifdef VMCPU_WITH_64_BIT_FFS
769	# if ARCH_BITS > 32
770	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
771	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
772	# else
773	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
774	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
775	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
776	} while (0)
777	# endif
778	#else
779	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
780	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
781	#endif
782
783	/** @def VM_FF_IS_SET
784	* Checks if single a force action flag is set.
785	*
786	* @param pVM The cross context VM structure.
787	* @param fFlag The flag to check.
788	* @sa VM_FF_IS_ANY_SET
789	*/
790	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
791	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
792	#else
793	# define VM_FF_IS_SET(pVM, fFlag) \
794	([](PVM a_pVM) -> bool \
795	{ \
796	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
797	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
798	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
799	}(pVM))
800	#endif
801
802	/** @def VMCPU_FF_IS_SET
803	* Checks if a single force action flag is set for the given VCPU.
804	*
805	* @param pVCpu The cross context virtual CPU structure.
806	* @param fFlag The flag to check.
807	* @sa VMCPU_FF_IS_ANY_SET
808	*/
809	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
810	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
811	#else
812	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
813	([](PVMCPU a_pVCpu) -> bool \
814	{ \
815	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
816	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
817	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
818	}(pVCpu))
819	#endif
820
821	/** @def VM_FF_IS_ANY_SET
822	* Checks if one or more force action in the specified set is pending.
823	*
824	* @param pVM The cross context VM structure.
825	* @param fFlags The flags to check for.
826	* @sa VM_FF_IS_SET
827	*/
828	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
829
830	/** @def VMCPU_FF_IS_ANY_SET
831	* Checks if two or more force action flags in the specified set is set for the given VCPU.
832	*
833	* @param pVCpu The cross context virtual CPU structure.
834	* @param fFlags The flags to check for.
835	* @sa VMCPU_FF_IS_SET
836	*/
837	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
838
839	/** @def VM_FF_TEST_AND_CLEAR
840	* Checks if one (!) force action in the specified set is pending and clears it atomically
841	*
842	* @returns true if the bit was set.
843	* @returns false if the bit was clear.
844	* @param pVM The cross context VM structure.
845	* @param fFlag Flag constant to check and clear (_BIT is appended).
846	*/
847	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
848
849	/** @def VMCPU_FF_TEST_AND_CLEAR
850	* Checks if one (!) force action in the specified set is pending and clears it atomically
851	*
852	* @returns true if the bit was set.
853	* @returns false if the bit was clear.
854	* @param pVCpu The cross context virtual CPU structure.
855	* @param fFlag Flag constant to check and clear (_BIT is appended).
856	*/
857	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
858
859	/** @def VM_FF_IS_PENDING_EXCEPT
860	* Checks if one or more force action in the specified set is pending while one
861	* or more other ones are not.
862	*
863	* @param pVM The cross context VM structure.
864	* @param fFlags The flags to check for.
865	* @param fExcpt The flags that should not be set.
866	*/
867	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
868	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
869
870	/** @def VM_IS_EMT
871	* Checks if the current thread is the emulation thread (EMT).
872	*
873	* @remark The ring-0 variation will need attention if we expand the ring-0
874	* code to let threads other than EMT mess around with the VM.
875	*/
876	#ifdef IN_RC
877	# define VM_IS_EMT(pVM) true
878	#else
879	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
880	#endif
881
882	/** @def VMCPU_IS_EMT
883	* Checks if the current thread is the emulation thread (EMT) for the specified
884	* virtual CPU.
885	*/
886	#ifdef IN_RC
887	# define VMCPU_IS_EMT(pVCpu) true
888	#else
889	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
890	#endif
891
892	/** @def VM_ASSERT_EMT
893	* Asserts that the current thread IS the emulation thread (EMT).
894	*/
895	#ifdef IN_RC
896	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
897	#elif defined(IN_RING0)
898	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
899	#else
900	# define VM_ASSERT_EMT(pVM) \
901	AssertMsg(VM_IS_EMT(pVM), \
902	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
903	#endif
904
905	/** @def VMCPU_ASSERT_EMT
906	* Asserts that the current thread IS the emulation thread (EMT) of the
907	* specified virtual CPU.
908	*/
909	#ifdef IN_RC
910	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
911	#elif defined(IN_RING0)
912	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
913	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
914	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
915	(pVCpu) ? (pVCpu)->idCpu : 0))
916	#else
917	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
918	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
919	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
920	#endif
921
922	/** @def VM_ASSERT_EMT_RETURN
923	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
924	*/
925	#ifdef IN_RC
926	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
927	#elif defined(IN_RING0)
928	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
929	#else
930	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
931	AssertMsgReturn(VM_IS_EMT(pVM), \
932	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
933	(rc))
934	#endif
935
936	/** @def VMCPU_ASSERT_EMT_RETURN
937	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
938	*/
939	#ifdef IN_RC
940	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
941	#elif defined(IN_RING0)
942	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
943	#else
944	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
945	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
946	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
947	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
948	(rc))
949	#endif
950
951	/** @def VMCPU_ASSERT_EMT_OR_GURU
952	* Asserts that the current thread IS the emulation thread (EMT) of the
953	* specified virtual CPU.
954	*/
955	#if defined(IN_RC) \|\| defined(IN_RING0)
956	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
957	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
958	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
959	#else
960	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
961	AssertMsg( VMCPU_IS_EMT(pVCpu) \
962	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
963	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
964	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
965	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
966	#endif
967
968	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
969	* Asserts that the current thread IS the emulation thread (EMT) of the
970	* specified virtual CPU or the VM is not running.
971	*/
972	#if defined(IN_RC) \|\| defined(IN_RING0)
973	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
974	Assert( VMCPU_IS_EMT(pVCpu) \
975	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
976	#else
977	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
978	AssertMsg( VMCPU_IS_EMT(pVCpu) \
979	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
980	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
981	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
982	#endif
983
984	/** @def VMSTATE_IS_RUNNING
985	* Checks if the given state indicates a running VM.
986	*/
987	#define VMSTATE_IS_RUNNING(a_enmVMState) \
988	( (enmVMState) == VMSTATE_RUNNING \
989	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
990	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
991
992	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
993	* Checks if the VM is running.
994	* @note This is only for pure debug assertions. No AssertReturn or similar!
995	* @sa VMSTATE_IS_RUNNING
996	*/
997	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
998	( (pVM)->enmVMState == VMSTATE_RUNNING \
999	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
1000	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
1001
1002	/** @def VM_ASSERT_IS_NOT_RUNNING
1003	* Asserts that the VM is not running.
1004	*/
1005	#if defined(IN_RC) \|\| defined(IN_RING0)
1006	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1007	#else
1008	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1009	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1010	#endif
1011
1012	/** @def VM_ASSERT_EMT0
1013	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1014	*/
1015	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
1016
1017	/** @def VM_ASSERT_EMT0_RETURN
1018	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1019	* it isn't.
1020	*/
1021	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1022
1023
1024	/**
1025	* Asserts that the current thread is NOT the emulation thread.
1026	*/
1027	#define VM_ASSERT_OTHER_THREAD(pVM) \
1028	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1029
1030
1031	/** @def VM_ASSERT_STATE
1032	* Asserts a certain VM state.
1033	*/
1034	#define VM_ASSERT_STATE(pVM, _enmState) \
1035	AssertMsg((pVM)->enmVMState == (_enmState), \
1036	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1037
1038	/** @def VM_ASSERT_STATE_RETURN
1039	* Asserts a certain VM state and returns if it doesn't match.
1040	*/
1041	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1042	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1043	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1044	(rc))
1045
1046	/** @def VM_IS_VALID_EXT
1047	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1048	* or terminated. */
1049	#define VM_IS_VALID_EXT(pVM) \
1050	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1051	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1052	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1053	&& VM_IS_EMT(pVM))) )
1054
1055	/** @def VM_ASSERT_VALID_EXT_RETURN
1056	* Asserts a the VM handle is valid for external access, i.e. not being
1057	* destroy or terminated.
1058	*/
1059	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1060	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1061	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1062	? VMGetStateName(pVM->enmVMState) : ""), \
1063	(rc))
1064
1065	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1066	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1067	* destroy or terminated.
1068	*/
1069	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1070	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1071	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1072	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1073	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1074	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1075	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1076	(rc))
1077
1078	#endif /* !VBOX_FOR_DTRACE_LIB */
1079
1080
1081	/**
1082	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1083	*
1084	* ONLY HM and NEM MAY USE THIS!
1085	*
1086	* @param a_pVM The cross context VM structure.
1087	* @param a_bValue The new value.
1088	* @internal
1089	*/
1090	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1091	do { \
1092	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1093	ASMCompilerBarrier(); /* just to be on the safe side */ \
1094	} while (0)
1095
1096	/**
1097	* Checks whether raw-mode is used.
1098	*
1099	* @retval true if either is used.
1100	* @retval false if software virtualization (raw-mode) is used.
1101	*
1102	* @param a_pVM The cross context VM structure.
1103	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1104	* @internal
1105	*/
1106	#ifdef VBOX_WITH_RAW_MODE
1107	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1108	#else
1109	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1110	#endif
1111
1112	/**
1113	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1114	*
1115	* @retval true if either is used.
1116	* @retval false if software virtualization (raw-mode) is used.
1117	*
1118	* @param a_pVM The cross context VM structure.
1119	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1120	* @internal
1121	*/
1122	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1123
1124	/**
1125	* Checks whether HM is being used by this VM.
1126	*
1127	* @retval true if HM (VT-x/AMD-v) is used.
1128	* @retval false if not.
1129	*
1130	* @param a_pVM The cross context VM structure.
1131	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1132	* @internal
1133	*/
1134	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1135
1136	/**
1137	* Checks whether NEM is being used by this VM.
1138	*
1139	* @retval true if a native hypervisor API is used.
1140	* @retval false if not.
1141	*
1142	* @param a_pVM The cross context VM structure.
1143	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1144	* @internal
1145	*/
1146	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1147
1148
1149	/**
1150	* The cross context VM structure.
1151	*
1152	* It contains all the VM data which have to be available in all contexts.
1153	* Even if it contains all the data the idea is to use APIs not to modify all
1154	* the members all around the place. Therefore we make use of unions to hide
1155	* everything which isn't local to the current source module. This means we'll
1156	* have to pay a little bit of attention when adding new members to structures
1157	* in the unions and make sure to keep the padding sizes up to date.
1158	*
1159	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1160	*/
1161	typedef struct VM
1162	{
1163	/** The state of the VM.
1164	* This field is read only to everyone except the VM and EM. */
1165	VMSTATE volatile enmVMState;
1166	/** Forced action flags.
1167	* See the VM_FF_* \#defines. Updated atomically.
1168	*/
1169	volatile uint32_t fGlobalForcedActions;
1170	/** Pointer to the array of page descriptors for the VM structure allocation. */
1171	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1172	/** Session handle. For use when calling SUPR0 APIs. */
1173	PSUPDRVSESSION pSession;
1174	/** Pointer to the ring-3 VM structure. */
1175	PUVM pUVM;
1176	/** Ring-3 Host Context VM Pointer. */
1177	R3PTRTYPE(struct VM *) pVMR3;
1178	/** Ring-0 Host Context VM Pointer. */
1179	R0PTRTYPE(struct VM *) pVMR0;
1180	/** Raw-mode Context VM Pointer. */
1181	RCPTRTYPE(struct VM *) pVMRC;
1182
1183	/** The GVM VM handle. Only the GVM should modify this field. */
1184	uint32_t hSelf;
1185	/** Number of virtual CPUs. */
1186	uint32_t cCpus;
1187	/** CPU excution cap (1-100) */
1188	uint32_t uCpuExecutionCap;
1189
1190	/** Size of the VM structure including the VMCPU array. */
1191	uint32_t cbSelf;
1192
1193	/** Offset to the VMCPU array starting from beginning of this structure. */
1194	uint32_t offVMCPU;
1195
1196	/**
1197	* VMMSwitcher assembly entry point returning to host context.
1198	*
1199	* Depending on how the host handles the rc status given in @a eax, this may
1200	* return and let the caller resume whatever it was doing prior to the call.
1201	*
1202	*
1203	* @param eax The return code, register.
1204	* @remark Assume interrupts disabled.
1205	* @remark This method pointer lives here because TRPM needs it.
1206	*/
1207	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1208
1209	/**
1210	* VMMSwitcher assembly entry point returning to host context without saving the
1211	* raw-mode context (hyper) registers.
1212	*
1213	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1214	* expects the caller to save a RC context in CPUM where one might return if the
1215	* return code indicate that this is possible.
1216	*
1217	* This method pointer lives here because TRPM needs it.
1218	*
1219	* @param eax The return code, register.
1220	* @remark Assume interrupts disabled.
1221	* @remark This method pointer lives here because TRPM needs it.
1222	*/
1223	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1224
1225	/** @name Various items that are frequently accessed.
1226	* @{ */
1227	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1228	* This is set early during vmR3InitRing3 by HM or NEM. */
1229	uint8_t const bMainExecutionEngine;
1230
1231	/** Whether to recompile user mode code or run it raw/hm/nem.
1232	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1233	* to recompiler stuff. */
1234	bool fRecompileUser;
1235	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1236	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1237	* to recompiler stuff. */
1238	bool fRecompileSupervisor;
1239	/** Whether raw mode supports ring-1 code or not.
1240	* This will be cleared when not in raw-mode. */
1241	bool fRawRing1Enabled;
1242	/** PATM enabled flag.
1243	* This is placed here for performance reasons.
1244	* This will be cleared when not in raw-mode. */
1245	bool fPATMEnabled;
1246	/** CSAM enabled flag.
1247	* This is placed here for performance reasons.
1248	* This will be cleared when not in raw-mode. */
1249	bool fCSAMEnabled;
1250
1251	/** Hardware VM support is available and enabled.
1252	* Determined very early during init.
1253	* This is placed here for performance reasons.
1254	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1255	bool fHMEnabled;
1256	/** Hardware VM support requires a minimal raw-mode context.
1257	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1258	bool fHMNeedRawModeCtx;
1259
1260	/** Set when this VM is the master FT node.
1261	* @todo This doesn't need to be here, FTM should store it in it's own
1262	* structures instead. */
1263	bool fFaultTolerantMaster;
1264	/** Large page enabled flag.
1265	* @todo This doesn't need to be here, PGM should store it in it's own
1266	* structures instead. */
1267	bool fUseLargePages;
1268	/** @} */
1269
1270	/** Alignment padding. */
1271	uint8_t uPadding1[2];
1272
1273	/** @name Debugging
1274	* @{ */
1275	/** Raw-mode Context VM Pointer. */
1276	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1277	/** Ring-3 Host Context VM Pointer. */
1278	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1279	/** Ring-0 Host Context VM Pointer. */
1280	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1281	/** @} */
1282
1283	#if HC_ARCH_BITS == 32
1284	/** Alignment padding. */
1285	uint32_t uPadding2;
1286	#endif
1287
1288	/** @name Switcher statistics (remove)
1289	* @{ */
1290	/** Profiling the total time from Qemu to GC. */
1291	STAMPROFILEADV StatTotalQemuToGC;
1292	/** Profiling the total time from GC to Qemu. */
1293	STAMPROFILEADV StatTotalGCToQemu;
1294	/** Profiling the total time spent in GC. */
1295	STAMPROFILEADV StatTotalInGC;
1296	/** Profiling the total time spent not in Qemu. */
1297	STAMPROFILEADV StatTotalInQemu;
1298	/** Profiling the VMMSwitcher code for going to GC. */
1299	STAMPROFILEADV StatSwitcherToGC;
1300	/** Profiling the VMMSwitcher code for going to HC. */
1301	STAMPROFILEADV StatSwitcherToHC;
1302	STAMPROFILEADV StatSwitcherSaveRegs;
1303	STAMPROFILEADV StatSwitcherSysEnter;
1304	STAMPROFILEADV StatSwitcherDebug;
1305	STAMPROFILEADV StatSwitcherCR0;
1306	STAMPROFILEADV StatSwitcherCR4;
1307	STAMPROFILEADV StatSwitcherJmpCR3;
1308	STAMPROFILEADV StatSwitcherRstrRegs;
1309	STAMPROFILEADV StatSwitcherLgdt;
1310	STAMPROFILEADV StatSwitcherLidt;
1311	STAMPROFILEADV StatSwitcherLldt;
1312	STAMPROFILEADV StatSwitcherTSS;
1313	/** @} */
1314
1315	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1316	* must start at the same offset on both 64-bit and 32-bit hosts. */
1317	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1318
1319	/** CPUM part. */
1320	union
1321	{
1322	#ifdef ___CPUMInternal_h
1323	struct CPUM s;
1324	#endif
1325	#ifdef ___VBox_vmm_cpum_h
1326	/** Read only info exposed about the host and guest CPUs. */
1327	struct
1328	{
1329	/** Padding for hidden fields. */
1330	uint8_t abHidden0[64];
1331	/** Host CPU feature information. */
1332	CPUMFEATURES HostFeatures;
1333	/** Guest CPU feature information. */
1334	CPUMFEATURES GuestFeatures;
1335	} const ro;
1336	#endif
1337	uint8_t padding[1536]; /* multiple of 64 */
1338	} cpum;
1339
1340	/** VMM part. */
1341	union
1342	{
1343	#ifdef ___VMMInternal_h
1344	struct VMM s;
1345	#endif
1346	uint8_t padding[1600]; /* multiple of 64 */
1347	} vmm;
1348
1349	/** PGM part. */
1350	union
1351	{
1352	#ifdef ___PGMInternal_h
1353	struct PGM s;
1354	#endif
1355	uint8_t padding[40962+6080]; / multiple of 64 */
1356	} pgm;
1357
1358	/** HM part. */
1359	union
1360	{
1361	#ifdef ___HMInternal_h
1362	struct HM s;
1363	#endif
1364	uint8_t padding[5440]; /* multiple of 64 */
1365	} hm;
1366
1367	/** TRPM part. */
1368	union
1369	{
1370	#ifdef ___TRPMInternal_h
1371	struct TRPM s;
1372	#endif
1373	uint8_t padding[5248]; /* multiple of 64 */
1374	} trpm;
1375
1376	/** SELM part. */
1377	union
1378	{
1379	#ifdef ___SELMInternal_h
1380	struct SELM s;
1381	#endif
1382	uint8_t padding[768]; /* multiple of 64 */
1383	} selm;
1384
1385	/** MM part. */
1386	union
1387	{
1388	#ifdef ___MMInternal_h
1389	struct MM s;
1390	#endif
1391	uint8_t padding[192]; /* multiple of 64 */
1392	} mm;
1393
1394	/** PDM part. */
1395	union
1396	{
1397	#ifdef ___PDMInternal_h
1398	struct PDM s;
1399	#endif
1400	uint8_t padding[1920]; /* multiple of 64 */
1401	} pdm;
1402
1403	/** IOM part. */
1404	union
1405	{
1406	#ifdef ___IOMInternal_h
1407	struct IOM s;
1408	#endif
1409	uint8_t padding[896]; /* multiple of 64 */
1410	} iom;
1411
1412	/** EM part. */
1413	union
1414	{
1415	#ifdef ___EMInternal_h
1416	struct EM s;
1417	#endif
1418	uint8_t padding[256]; /* multiple of 64 */
1419	} em;
1420
1421	/** NEM part. */
1422	union
1423	{
1424	#ifdef ___NEMInternal_h
1425	struct NEM s;
1426	#endif
1427	uint8_t padding[128]; /* multiple of 64 */
1428	} nem;
1429
1430	/** TM part. */
1431	union
1432	{
1433	#ifdef ___TMInternal_h
1434	struct TM s;
1435	#endif
1436	uint8_t padding[2496]; /* multiple of 64 */
1437	} tm;
1438
1439	/** DBGF part. */
1440	union
1441	{
1442	#ifdef ___DBGFInternal_h
1443	struct DBGF s;
1444	#endif
1445	#ifdef ___VBox_vmm_dbgf_h
1446	/** Read only info exposed about interrupt breakpoints and selected events. */
1447	struct
1448	{
1449	/** Bitmap of enabled hardware interrupt breakpoints. */
1450	uint32_t bmHardIntBreakpoints[256 / 32];
1451	/** Bitmap of enabled software interrupt breakpoints. */
1452	uint32_t bmSoftIntBreakpoints[256 / 32];
1453	/** Bitmap of selected events.
1454	* This includes non-selectable events too for simplicity, we maintain the
1455	* state for some of these, as it may come in handy. */
1456	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1457	/** Enabled hardware interrupt breakpoints. */
1458	uint32_t cHardIntBreakpoints;
1459	/** Enabled software interrupt breakpoints. */
1460	uint32_t cSoftIntBreakpoints;
1461	/** The number of selected events. */
1462	uint32_t cSelectedEvents;
1463	/** The number of enabled hardware breakpoints. */
1464	uint8_t cEnabledHwBreakpoints;
1465	/** The number of enabled hardware I/O breakpoints. */
1466	uint8_t cEnabledHwIoBreakpoints;
1467	/** The number of enabled INT3 breakpoints. */
1468	uint8_t cEnabledInt3Breakpoints;
1469	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1470	} const ro;
1471	#endif
1472	uint8_t padding[2432]; /* multiple of 64 */
1473	} dbgf;
1474
1475	/** SSM part. */
1476	union
1477	{
1478	#ifdef ___SSMInternal_h
1479	struct SSM s;
1480	#endif
1481	uint8_t padding[128]; /* multiple of 64 */
1482	} ssm;
1483
1484	/** FTM part. */
1485	union
1486	{
1487	#ifdef ___FTMInternal_h
1488	struct FTM s;
1489	#endif
1490	uint8_t padding[512]; /* multiple of 64 */
1491	} ftm;
1492
1493	#ifdef VBOX_WITH_RAW_MODE
1494	/** PATM part. */
1495	union
1496	{
1497	# ifdef ___PATMInternal_h
1498	struct PATM s;
1499	# endif
1500	uint8_t padding[768]; /* multiple of 64 */
1501	} patm;
1502
1503	/** CSAM part. */
1504	union
1505	{
1506	# ifdef ___CSAMInternal_h
1507	struct CSAM s;
1508	# endif
1509	uint8_t padding[1088]; /* multiple of 64 */
1510	} csam;
1511	#endif
1512
1513	#ifdef VBOX_WITH_REM
1514	/** REM part. */
1515	union
1516	{
1517	# ifdef ___REMInternal_h
1518	struct REM s;
1519	# endif
1520	uint8_t padding[0x11100]; /* multiple of 64 */
1521	} rem;
1522	#endif
1523
1524	union
1525	{
1526	#ifdef ___GIMInternal_h
1527	struct GIM s;
1528	#endif
1529	uint8_t padding[448]; /* multiple of 64 */
1530	} gim;
1531
1532	union
1533	{
1534	#ifdef ___APICInternal_h
1535	struct APIC s;
1536	#endif
1537	uint8_t padding[128]; /* multiple of 8 */
1538	} apic;
1539
1540	/* ---- begin small stuff ---- */
1541
1542	/** VM part. */
1543	union
1544	{
1545	#ifdef ___VMInternal_h
1546	struct VMINT s;
1547	#endif
1548	uint8_t padding[32]; /* multiple of 8 */
1549	} vm;
1550
1551	/** CFGM part. */
1552	union
1553	{
1554	#ifdef ___CFGMInternal_h
1555	struct CFGM s;
1556	#endif
1557	uint8_t padding[8]; /* multiple of 8 */
1558	} cfgm;
1559
1560	/** Padding for aligning the cpu array on a page boundary. */
1561	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1562	uint8_t abAlignment2[3670];
1563	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1564	uint8_t abAlignment2[1430];
1565	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1566	uint8_t abAlignment2[3926];
1567	#else
1568	uint8_t abAlignment2[1686];
1569	#endif
1570
1571	/* ---- end small stuff ---- */
1572
1573	/** VMCPU array for the configured number of virtual CPUs.
1574	* Must be aligned on a page boundary for TLB hit reasons as well as
1575	* alignment of VMCPU members. */
1576	VMCPU aCpus[1];
1577	} VM;
1578
1579
1580	#ifdef IN_RC
1581	RT_C_DECLS_BEGIN
1582
1583	/** The VM structure.
1584	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1585	* globals which we should avoid using.
1586	*/
1587	extern DECLIMPORT(VM) g_VM;
1588
1589	RT_C_DECLS_END
1590	#endif
1591
1592	/** @} */
1593
1594	#endif
1595

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source: vbox/trunk/include/VBox/vmm/vm.h@ 76290

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