VirtualBox

source: vbox/trunk/include/VBox/x86.h@ 34801

Last change on this file since 34801 was 34328, checked in by vboxsync, 14 years ago

CPUM: updated the CPUID processor feature flags
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1/** @file
2 * X86 (and AMD64) Structures and Definitions (VMM,++).
3 *
4 * x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2009 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___VBox_x86_h
29#define ___VBox_x86_h
30
31#include <VBox/types.h>
32#include <iprt/assert.h>
33
34/* Workaround for Solaris sys/regset.h defining CS, DS */
35#ifdef RT_OS_SOLARIS
36# undef CS
37# undef DS
38#endif
39
40/** @defgroup grp_x86 x86 Types and Definitions
41 * @{
42 */
43
44/**
45 * EFLAGS Bits.
46 */
47typedef struct X86EFLAGSBITS
48{
49 /** Bit 0 - CF - Carry flag - Status flag. */
50 unsigned u1CF : 1;
51 /** Bit 1 - 1 - Reserved flag. */
52 unsigned u1Reserved0 : 1;
53 /** Bit 2 - PF - Parity flag - Status flag. */
54 unsigned u1PF : 1;
55 /** Bit 3 - 0 - Reserved flag. */
56 unsigned u1Reserved1 : 1;
57 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
58 unsigned u1AF : 1;
59 /** Bit 5 - 0 - Reserved flag. */
60 unsigned u1Reserved2 : 1;
61 /** Bit 6 - ZF - Zero flag - Status flag. */
62 unsigned u1ZF : 1;
63 /** Bit 7 - SF - Signed flag - Status flag. */
64 unsigned u1SF : 1;
65 /** Bit 8 - TF - Trap flag - System flag. */
66 unsigned u1TF : 1;
67 /** Bit 9 - IF - Interrupt flag - System flag. */
68 unsigned u1IF : 1;
69 /** Bit 10 - DF - Direction flag - Control flag. */
70 unsigned u1DF : 1;
71 /** Bit 11 - OF - Overflow flag - Status flag. */
72 unsigned u1OF : 1;
73 /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
74 unsigned u2IOPL : 2;
75 /** Bit 14 - NT - Nested task flag - System flag. */
76 unsigned u1NT : 1;
77 /** Bit 15 - 0 - Reserved flag. */
78 unsigned u1Reserved3 : 1;
79 /** Bit 16 - RF - Resume flag - System flag. */
80 unsigned u1RF : 1;
81 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
82 unsigned u1VM : 1;
83 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
84 unsigned u1AC : 1;
85 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
86 unsigned u1VIF : 1;
87 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
88 unsigned u1VIP : 1;
89 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
90 unsigned u1ID : 1;
91 /** Bit 22-31 - 0 - Reserved flag. */
92 unsigned u10Reserved4 : 10;
93} X86EFLAGSBITS;
94/** Pointer to EFLAGS bits. */
95typedef X86EFLAGSBITS *PX86EFLAGSBITS;
96/** Pointer to const EFLAGS bits. */
97typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
98
99/**
100 * EFLAGS.
101 */
102typedef union X86EFLAGS
103{
104 /** The plain unsigned view. */
105 uint32_t u;
106 /** The bitfield view. */
107 X86EFLAGSBITS Bits;
108 /** The 8-bit view. */
109 uint8_t au8[4];
110 /** The 16-bit view. */
111 uint16_t au16[2];
112 /** The 32-bit view. */
113 uint32_t au32[1];
114 /** The 32-bit view. */
115 uint32_t u32;
116} X86EFLAGS;
117/** Pointer to EFLAGS. */
118typedef X86EFLAGS *PX86EFLAGS;
119/** Pointer to const EFLAGS. */
120typedef const X86EFLAGS *PCX86EFLAGS;
121
122/**
123 * RFLAGS (32 upper bits are reserved).
124 */
125typedef union X86RFLAGS
126{
127 /** The plain unsigned view. */
128 uint64_t u;
129 /** The bitfield view. */
130 X86EFLAGSBITS Bits;
131 /** The 8-bit view. */
132 uint8_t au8[8];
133 /** The 16-bit view. */
134 uint16_t au16[4];
135 /** The 32-bit view. */
136 uint32_t au32[2];
137 /** The 64-bit view. */
138 uint64_t au64[1];
139 /** The 64-bit view. */
140 uint64_t u64;
141} X86RFLAGS;
142/** Pointer to RFLAGS. */
143typedef X86RFLAGS *PX86RFLAGS;
144/** Pointer to const RFLAGS. */
145typedef const X86RFLAGS *PCX86RFLAGS;
146
147
148/** @name EFLAGS
149 * @{
150 */
151/** Bit 0 - CF - Carry flag - Status flag. */
152#define X86_EFL_CF RT_BIT(0)
153/** Bit 2 - PF - Parity flag - Status flag. */
154#define X86_EFL_PF RT_BIT(2)
155/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
156#define X86_EFL_AF RT_BIT(4)
157/** Bit 6 - ZF - Zero flag - Status flag. */
158#define X86_EFL_ZF RT_BIT(6)
159/** Bit 7 - SF - Signed flag - Status flag. */
160#define X86_EFL_SF RT_BIT(7)
161/** Bit 8 - TF - Trap flag - System flag. */
162#define X86_EFL_TF RT_BIT(8)
163/** Bit 9 - IF - Interrupt flag - System flag. */
164#define X86_EFL_IF RT_BIT(9)
165/** Bit 10 - DF - Direction flag - Control flag. */
166#define X86_EFL_DF RT_BIT(10)
167/** Bit 11 - OF - Overflow flag - Status flag. */
168#define X86_EFL_OF RT_BIT(11)
169/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
170#define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
171/** Bit 14 - NT - Nested task flag - System flag. */
172#define X86_EFL_NT RT_BIT(14)
173/** Bit 16 - RF - Resume flag - System flag. */
174#define X86_EFL_RF RT_BIT(16)
175/** Bit 17 - VM - Virtual 8086 mode - System flag. */
176#define X86_EFL_VM RT_BIT(17)
177/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
178#define X86_EFL_AC RT_BIT(18)
179/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
180#define X86_EFL_VIF RT_BIT(19)
181/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
182#define X86_EFL_VIP RT_BIT(20)
183/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
184#define X86_EFL_ID RT_BIT(21)
185/** IOPL shift. */
186#define X86_EFL_IOPL_SHIFT 12
187/** The the IOPL level from the flags. */
188#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
189/** Bits restored by popf */
190#define X86_EFL_POPF_BITS (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID)
191/** @} */
192
193
194/** CPUID Feature information - ECX.
195 * CPUID query with EAX=1.
196 */
197typedef struct X86CPUIDFEATECX
198{
199 /** Bit 0 - SSE3 - Supports SSE3 or not. */
200 unsigned u1SSE3 : 1;
201 /** Bit 1 - PCLMULQDQ. */
202 unsigned u1PCLMULQDQ : 1;
203 /** Bit 2 - DS Area 64-bit layout. */
204 unsigned u1DTE64 : 1;
205 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
206 unsigned u1Monitor : 1;
207 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
208 unsigned u1CPLDS : 1;
209 /** Bit 5 - VMX - Virtual Machine Technology. */
210 unsigned u1VMX : 1;
211 /** Bit 6 - SMX: Safer Mode Extensions. */
212 unsigned u1SMX : 1;
213 /** Bit 7 - EST - Enh. SpeedStep Tech. */
214 unsigned u1EST : 1;
215 /** Bit 8 - TM2 - Terminal Monitor 2. */
216 unsigned u1TM2 : 1;
217 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
218 unsigned u1SSSE3 : 1;
219 /** Bit 10 - CNTX-ID - L1 Context ID. */
220 unsigned u1CNTXID : 1;
221 /** Bit 11 - Reserved. */
222 unsigned u1Reserved1 : 1;
223 /** Bit 12 - FMA. */
224 unsigned u1FMA : 1;
225 /** Bit 13 - CX16 - CMPXCHG16B. */
226 unsigned u1CX16 : 1;
227 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228 unsigned u1TPRUpdate : 1;
229 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
230 unsigned u1PDCM : 1;
231 /** Bit 16 - Reserved. */
232 unsigned u1Reserved2 : 1;
233 /** Bit 17 - PCID - Process-context identifiers. */
234 unsigned u1PCID : 1;
235 /** Bit 18 - Direct Cache Access. */
236 unsigned u1DCA : 1;
237 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
238 unsigned u1SSE4_1 : 1;
239 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
240 unsigned u1SSE4_2 : 1;
241 /** Bit 21 - x2APIC. */
242 unsigned u1x2APIC : 1;
243 /** Bit 22 - MOVBE - Supports MOVBE. */
244 unsigned u1MOVBE : 1;
245 /** Bit 23 - POPCNT - Supports POPCNT. */
246 unsigned u1POPCNT : 1;
247 /** Bit 24 - TSC-Deadline. */
248 unsigned u1TSCDEADLINE : 1;
249 /** Bit 25 - AES. */
250 unsigned u1AES : 1;
251 /** Bit 26 - XSAVE - Supports XSAVE. */
252 unsigned u1XSAVE : 1;
253 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
254 unsigned u1OSXSAVE : 1;
255 /** Bit 28 - AVX - Supports AVX instruction extensions. */
256 unsigned u1AVX : 1;
257 /** Bit 29 - 30 - Reserved */
258 unsigned u2Reserved3 : 2;
259 /** Reserved, always 0. */
260 unsigned u1Reserved4 : 1;
261} X86CPUIDFEATECX;
262/** Pointer to CPUID Feature Information - ECX. */
263typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
264/** Pointer to const CPUID Feature Information - ECX. */
265typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
266
267
268/** CPUID Feature Information - EDX.
269 * CPUID query with EAX=1.
270 */
271typedef struct X86CPUIDFEATEDX
272{
273 /** Bit 0 - FPU - x87 FPU on Chip. */
274 unsigned u1FPU : 1;
275 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
276 unsigned u1VME : 1;
277 /** Bit 2 - DE - Debugging extensions. */
278 unsigned u1DE : 1;
279 /** Bit 3 - PSE - Page Size Extension. */
280 unsigned u1PSE : 1;
281 /** Bit 4 - TSC - Time Stamp Counter. */
282 unsigned u1TSC : 1;
283 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
284 unsigned u1MSR : 1;
285 /** Bit 6 - PAE - Physical Address Extension. */
286 unsigned u1PAE : 1;
287 /** Bit 7 - MCE - Machine Check Exception. */
288 unsigned u1MCE : 1;
289 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
290 unsigned u1CX8 : 1;
291 /** Bit 9 - APIC - APIC On-Chip. */
292 unsigned u1APIC : 1;
293 /** Bit 10 - Reserved. */
294 unsigned u1Reserved1 : 1;
295 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
296 unsigned u1SEP : 1;
297 /** Bit 12 - MTRR - Memory Type Range Registers. */
298 unsigned u1MTRR : 1;
299 /** Bit 13 - PGE - PTE Global Bit. */
300 unsigned u1PGE : 1;
301 /** Bit 14 - MCA - Machine Check Architecture. */
302 unsigned u1MCA : 1;
303 /** Bit 15 - CMOV - Conditional Move Instructions. */
304 unsigned u1CMOV : 1;
305 /** Bit 16 - PAT - Page Attribute Table. */
306 unsigned u1PAT : 1;
307 /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
308 unsigned u1PSE36 : 1;
309 /** Bit 18 - PSN - Processor Serial Number. */
310 unsigned u1PSN : 1;
311 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
312 unsigned u1CLFSH : 1;
313 /** Bit 20 - Reserved. */
314 unsigned u1Reserved2 : 1;
315 /** Bit 21 - DS - Debug Store. */
316 unsigned u1DS : 1;
317 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
318 unsigned u1ACPI : 1;
319 /** Bit 23 - MMX - Intel MMX 'Technology'. */
320 unsigned u1MMX : 1;
321 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
322 unsigned u1FXSR : 1;
323 /** Bit 25 - SSE - SSE Support. */
324 unsigned u1SSE : 1;
325 /** Bit 26 - SSE2 - SSE2 Support. */
326 unsigned u1SSE2 : 1;
327 /** Bit 27 - SS - Self Snoop. */
328 unsigned u1SS : 1;
329 /** Bit 28 - HTT - Hyper-Threading Technology. */
330 unsigned u1HTT : 1;
331 /** Bit 29 - TM - Thermal Monitor. */
332 unsigned u1TM : 1;
333 /** Bit 30 - Reserved - . */
334 unsigned u1Reserved3 : 1;
335 /** Bit 31 - PBE - Pending Break Enabled. */
336 unsigned u1PBE : 1;
337} X86CPUIDFEATEDX;
338/** Pointer to CPUID Feature Information - EDX. */
339typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
340/** Pointer to const CPUID Feature Information - EDX. */
341typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
342
343/** @name CPUID Vendor information.
344 * CPUID query with EAX=0.
345 * @{
346 */
347#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
348#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
349#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
350
351#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
352#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
353#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
354/** @} */
355
356
357/** @name CPUID Feature information.
358 * CPUID query with EAX=1.
359 * @{
360 */
361/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
362#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
363/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
364#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
365/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
366#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
367/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
368#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
369/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
370#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
371/** ECX Bit 5 - VMX - Virtual Machine Technology. */
372#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
373/** ECX Bit 6 - SMX - Safer Mode Extensions. */
374#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
375/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
376#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
377/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
378#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
379/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
380#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
381/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
382#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
383/** ECX Bit 12 - FMA. */
384#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
385/** ECX Bit 13 - CX16 - CMPXCHG16B. */
386#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
387/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
388#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
389/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
390#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
391/** ECX Bit 17 - PCID - Process-context identifiers. */
392#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
393/** ECX Bit 18 - DCA - Direct Cache Access. */
394#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
395/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
396#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
397/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
398#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
399/** ECX Bit 21 - x2APIC support. */
400#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
401/** ECX Bit 22 - MOVBE instruction. */
402#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
403/** ECX Bit 23 - POPCNT instruction. */
404#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
405/** ECX Bir 24 - TSC-Deadline. */
406#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
407/** ECX Bit 25 - AES instructions. */
408#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
409/** ECX Bit 26 - XSAVE instruction. */
410#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
411/** ECX Bit 27 - OSXSAVE instruction. */
412#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
413/** ECX Bit 28 - AVX. */
414#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
415
416
417/** Bit 0 - FPU - x87 FPU on Chip. */
418#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
419/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
420#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
421/** Bit 2 - DE - Debugging extensions. */
422#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
423/** Bit 3 - PSE - Page Size Extension. */
424#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
425/** Bit 4 - TSC - Time Stamp Counter. */
426#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
427/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
428#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
429/** Bit 6 - PAE - Physical Address Extension. */
430#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
431/** Bit 7 - MCE - Machine Check Exception. */
432#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
433/** Bit 8 - CX8 - CMPXCHG8B instruction. */
434#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
435/** Bit 9 - APIC - APIC On-Chip. */
436#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
437/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
438#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
439/** Bit 12 - MTRR - Memory Type Range Registers. */
440#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
441/** Bit 13 - PGE - PTE Global Bit. */
442#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
443/** Bit 14 - MCA - Machine Check Architecture. */
444#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
445/** Bit 15 - CMOV - Conditional Move Instructions. */
446#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
447/** Bit 16 - PAT - Page Attribute Table. */
448#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
449/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
450#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
451/** Bit 18 - PSN - Processor Serial Number. */
452#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
453/** Bit 19 - CLFSH - CLFLUSH Instruction. */
454#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
455/** Bit 21 - DS - Debug Store. */
456#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
457/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
458#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
459/** Bit 23 - MMX - Intel MMX Technology. */
460#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
461/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
462#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
463/** Bit 25 - SSE - SSE Support. */
464#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
465/** Bit 26 - SSE2 - SSE2 Support. */
466#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
467/** Bit 27 - SS - Self Snoop. */
468#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
469/** Bit 28 - HTT - Hyper-Threading Technology. */
470#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
471/** Bit 29 - TM - Therm. Monitor. */
472#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
473/** Bit 31 - PBE - Pending Break Enabled. */
474#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
475/** @} */
476
477/** @name CPUID mwait/monitor information.
478 * CPUID query with EAX=5.
479 * @{
480 */
481/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
482#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
483/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
484#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
485/** @} */
486
487
488/** @name CPUID AMD Feature information.
489 * CPUID query with EAX=0x80000001.
490 * @{
491 */
492/** Bit 0 - FPU - x87 FPU on Chip. */
493#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
494/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
495#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
496/** Bit 2 - DE - Debugging extensions. */
497#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
498/** Bit 3 - PSE - Page Size Extension. */
499#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
500/** Bit 4 - TSC - Time Stamp Counter. */
501#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
502/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
503#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
504/** Bit 6 - PAE - Physical Address Extension. */
505#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
506/** Bit 7 - MCE - Machine Check Exception. */
507#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
508/** Bit 8 - CX8 - CMPXCHG8B instruction. */
509#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
510/** Bit 9 - APIC - APIC On-Chip. */
511#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
512/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
513#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
514/** Bit 12 - MTRR - Memory Type Range Registers. */
515#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
516/** Bit 13 - PGE - PTE Global Bit. */
517#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
518/** Bit 14 - MCA - Machine Check Architecture. */
519#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
520/** Bit 15 - CMOV - Conditional Move Instructions. */
521#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
522/** Bit 16 - PAT - Page Attribute Table. */
523#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
524/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
525#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
526/** Bit 20 - NX - AMD No-Execute Page Protection. */
527#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
528/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
529#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
530/** Bit 23 - MMX - Intel MMX Technology. */
531#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
532/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
533#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
534/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
535#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
536/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
537#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
538/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
539#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
540/** Bit 29 - LM - AMD Long Mode. */
541#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
542/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
543#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
544/** Bit 31 - 3DNOW - AMD 3DNow. */
545#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
546
547/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
548#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
549/** Bit 1 - CMPL - Core multi-processing legacy mode. */
550#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
551/** Bit 2 - SVM - AMD VM extensions. */
552#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
553/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
554#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
555/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
556#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
557/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
558#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
559/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
560#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
561/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
562#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
563/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
564#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
565/** Bit 9 - OSVW - AMD OS visible workaround. */
566#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
567/** Bit 10 - IBS - Instruct based sampling. */
568#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
569/** Bit 11 - SSE5 - SSE5 instruction support. */
570#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
571/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
572#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
573/** Bit 13 - WDT - AMD Watchdog timer support. */
574#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
575
576/** @} */
577
578
579/** @name CPUID AMD Feature information.
580 * CPUID query with EAX=0x80000007.
581 * @{
582 */
583/** Bit 0 - TS - Temperature Sensor. */
584#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
585/** Bit 1 - FID - Frequency ID Control. */
586#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
587/** Bit 2 - VID - Voltage ID Control. */
588#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
589/** Bit 3 - TTP - THERMTRIP. */
590#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
591/** Bit 4 - TM - Hardware Thermal Control. */
592#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
593/** Bit 5 - STC - Software Thermal Control. */
594#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
595/** Bit 6 - MC - 100 Mhz Multiplier Control. */
596#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
597/** Bit 7 - HWPSTATE - Hardware P-State Control. */
598#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
599/** Bit 8 - TSCINVAR - TSC Invariant. */
600#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
601/** @} */
602
603
604/** @name CR0
605 * @{ */
606/** Bit 0 - PE - Protection Enabled */
607#define X86_CR0_PE RT_BIT(0)
608#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
609/** Bit 1 - MP - Monitor Coprocessor */
610#define X86_CR0_MP RT_BIT(1)
611#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
612/** Bit 2 - EM - Emulation. */
613#define X86_CR0_EM RT_BIT(2)
614#define X86_CR0_EMULATE_FPU RT_BIT(2)
615/** Bit 3 - TS - Task Switch. */
616#define X86_CR0_TS RT_BIT(3)
617#define X86_CR0_TASK_SWITCH RT_BIT(3)
618/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
619#define X86_CR0_ET RT_BIT(4)
620#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
621/** Bit 5 - NE - Numeric error. */
622#define X86_CR0_NE RT_BIT(5)
623#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
624/** Bit 16 - WP - Write Protect. */
625#define X86_CR0_WP RT_BIT(16)
626#define X86_CR0_WRITE_PROTECT RT_BIT(16)
627/** Bit 18 - AM - Alignment Mask. */
628#define X86_CR0_AM RT_BIT(18)
629#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
630/** Bit 29 - NW - Not Write-though. */
631#define X86_CR0_NW RT_BIT(29)
632#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
633/** Bit 30 - WP - Cache Disable. */
634#define X86_CR0_CD RT_BIT(30)
635#define X86_CR0_CACHE_DISABLE RT_BIT(30)
636/** Bit 31 - PG - Paging. */
637#define X86_CR0_PG RT_BIT(31)
638#define X86_CR0_PAGING RT_BIT(31)
639/** @} */
640
641
642/** @name CR3
643 * @{ */
644/** Bit 3 - PWT - Page-level Writes Transparent. */
645#define X86_CR3_PWT RT_BIT(3)
646/** Bit 4 - PCD - Page-level Cache Disable. */
647#define X86_CR3_PCD RT_BIT(4)
648/** Bits 12-31 - - Page directory page number. */
649#define X86_CR3_PAGE_MASK (0xfffff000)
650/** Bits 5-31 - - PAE Page directory page number. */
651#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
652/** Bits 12-51 - - AMD64 Page directory page number. */
653#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
654/** @} */
655
656
657/** @name CR4
658 * @{ */
659/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
660#define X86_CR4_VME RT_BIT(0)
661/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
662#define X86_CR4_PVI RT_BIT(1)
663/** Bit 2 - TSD - Time Stamp Disable. */
664#define X86_CR4_TSD RT_BIT(2)
665/** Bit 3 - DE - Debugging Extensions. */
666#define X86_CR4_DE RT_BIT(3)
667/** Bit 4 - PSE - Page Size Extension. */
668#define X86_CR4_PSE RT_BIT(4)
669/** Bit 5 - PAE - Physical Address Extension. */
670#define X86_CR4_PAE RT_BIT(5)
671/** Bit 6 - MCE - Machine-Check Enable. */
672#define X86_CR4_MCE RT_BIT(6)
673/** Bit 7 - PGE - Page Global Enable. */
674#define X86_CR4_PGE RT_BIT(7)
675/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
676#define X86_CR4_PCE RT_BIT(8)
677/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
678#define X86_CR4_OSFSXR RT_BIT(9)
679/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
680#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
681/** Bit 13 - VMXE - VMX mode is enabled. */
682#define X86_CR4_VMXE RT_BIT(13)
683/** @} */
684
685
686/** @name DR6
687 * @{ */
688/** Bit 0 - B0 - Breakpoint 0 condition detected. */
689#define X86_DR6_B0 RT_BIT(0)
690/** Bit 1 - B1 - Breakpoint 1 condition detected. */
691#define X86_DR6_B1 RT_BIT(1)
692/** Bit 2 - B2 - Breakpoint 2 condition detected. */
693#define X86_DR6_B2 RT_BIT(2)
694/** Bit 3 - B3 - Breakpoint 3 condition detected. */
695#define X86_DR6_B3 RT_BIT(3)
696/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
697#define X86_DR6_BD RT_BIT(13)
698/** Bit 14 - BS - Single step */
699#define X86_DR6_BS RT_BIT(14)
700/** Bit 15 - BT - Task switch. (TSS T bit.) */
701#define X86_DR6_BT RT_BIT(15)
702/** Value of DR6 after powerup/reset. */
703#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
704/** @} */
705
706
707/** @name DR7
708 * @{ */
709/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
710#define X86_DR7_L0 RT_BIT(0)
711/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
712#define X86_DR7_G0 RT_BIT(1)
713/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
714#define X86_DR7_L1 RT_BIT(2)
715/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
716#define X86_DR7_G1 RT_BIT(3)
717/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
718#define X86_DR7_L2 RT_BIT(4)
719/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
720#define X86_DR7_G2 RT_BIT(5)
721/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
722#define X86_DR7_L3 RT_BIT(6)
723/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
724#define X86_DR7_G3 RT_BIT(7)
725/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
726#define X86_DR7_LE RT_BIT(8)
727/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
728#define X86_DR7_GE RT_BIT(9)
729
730/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
731 * any DR register is accessed. */
732#define X86_DR7_GD RT_BIT(13)
733/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
734#define X86_DR7_RW0_MASK (3 << 16)
735/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
736#define X86_DR7_LEN0_MASK (3 << 18)
737/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
738#define X86_DR7_RW1_MASK (3 << 20)
739/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
740#define X86_DR7_LEN1_MASK (3 << 22)
741/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
742#define X86_DR7_RW2_MASK (3 << 24)
743/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
744#define X86_DR7_LEN2_MASK (3 << 26)
745/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
746#define X86_DR7_RW3_MASK (3 << 28)
747/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
748#define X86_DR7_LEN3_MASK (3 << 30)
749
750/** Bits which must be 1s. */
751#define X86_DR7_MB1_MASK (RT_BIT(10))
752
753/** Calcs the L bit of Nth breakpoint.
754 * @param iBp The breakpoint number [0..3].
755 */
756#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
757
758/** Calcs the G bit of Nth breakpoint.
759 * @param iBp The breakpoint number [0..3].
760 */
761#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
762
763/** @name Read/Write values.
764 * @{ */
765/** Break on instruction fetch only. */
766#define X86_DR7_RW_EO 0U
767/** Break on write only. */
768#define X86_DR7_RW_WO 1U
769/** Break on I/O read/write. This is only defined if CR4.DE is set. */
770#define X86_DR7_RW_IO 2U
771/** Break on read or write (but not instruction fetches). */
772#define X86_DR7_RW_RW 3U
773/** @} */
774
775/** Shifts a X86_DR7_RW_* value to its right place.
776 * @param iBp The breakpoint number [0..3].
777 * @param fRw One of the X86_DR7_RW_* value.
778 */
779#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
780
781/** @name Length values.
782 * @{ */
783#define X86_DR7_LEN_BYTE 0U
784#define X86_DR7_LEN_WORD 1U
785#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
786#define X86_DR7_LEN_DWORD 3U
787/** @} */
788
789/** Shifts a X86_DR7_LEN_* value to its right place.
790 * @param iBp The breakpoint number [0..3].
791 * @param cb One of the X86_DR7_LEN_* values.
792 */
793#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
794
795/** Fetch the breakpoint length bits from the DR7 value.
796 * @param uDR7 DR7 value
797 * @param iBp The breakpoint number [0..3].
798 */
799#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
800
801/** Mask used to check if any breakpoints are enabled. */
802#define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
803
804/** Mask used to check if any io breakpoints are set. */
805#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
806
807/** Value of DR7 after powerup/reset. */
808#define X86_DR7_INIT_VAL 0x400
809/** @} */
810
811
812/** @name Machine Specific Registers
813 * @{
814 */
815
816/** Time Stamp Counter. */
817#define MSR_IA32_TSC 0x10
818
819#define MSR_IA32_PLATFORM_ID 0x17
820
821#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
822#define MSR_IA32_APICBASE 0x1b
823#endif
824
825/** CPU Feature control. */
826#define MSR_IA32_FEATURE_CONTROL 0x3A
827#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
828#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
829
830/** BIOS update trigger (microcode update). */
831#define MSR_IA32_BIOS_UPDT_TRIG 0x79
832
833/** BIOS update signature (microcode). */
834#define MSR_IA32_BIOS_SIGN_ID 0x8B
835
836/** General performance counter no. 0. */
837#define MSR_IA32_PMC0 0xC1
838/** General performance counter no. 1. */
839#define MSR_IA32_PMC1 0xC2
840/** General performance counter no. 2. */
841#define MSR_IA32_PMC2 0xC3
842/** General performance counter no. 3. */
843#define MSR_IA32_PMC3 0xC4
844
845/** Nehalem power control. */
846#define MSR_IA32_PLATFORM_INFO 0xCE
847
848/** Get FSB clock status (Intel-specific). */
849#define MSR_IA32_FSB_CLOCK_STS 0xCD
850
851/** MTRR Capabilities. */
852#define MSR_IA32_MTRR_CAP 0xFE
853
854
855#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
856/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
857 * R0 SS == CS + 8
858 * R3 CS == CS + 16
859 * R3 SS == CS + 24
860 */
861#define MSR_IA32_SYSENTER_CS 0x174
862/** SYSENTER_ESP - the R0 ESP. */
863#define MSR_IA32_SYSENTER_ESP 0x175
864/** SYSENTER_EIP - the R0 EIP. */
865#define MSR_IA32_SYSENTER_EIP 0x176
866#endif
867
868/** Machine Check Global Capabilities Register. */
869#define MSR_IA32_MCP_CAP 0x179
870/** Machine Check Global Status Register. */
871#define MSR_IA32_MCP_STATUS 0x17A
872/** Machine Check Global Control Register. */
873#define MSR_IA32_MCP_CTRL 0x17B
874
875/** Trace/Profile Resource Control (R/W) */
876#define MSR_IA32_DEBUGCTL 0x1D9
877
878/* Page Attribute Table. */
879#define MSR_IA32_CR_PAT 0x277
880
881/** Performance counter MSRs. (Intel only) */
882#define MSR_IA32_PERFEVTSEL0 0x186
883#define MSR_IA32_PERFEVTSEL1 0x187
884#define MSR_IA32_FLEX_RATIO 0x194
885#define MSR_IA32_PERF_STATUS 0x198
886#define MSR_IA32_PERF_CTL 0x199
887#define MSR_IA32_THERM_STATUS 0x19c
888
889/** Enable misc. processor features (R/W). */
890#define MSR_IA32_MISC_ENABLE 0x1A0
891
892/** MTRR Default Range. */
893#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
894
895#define MSR_IA32_MC0_CTL 0x400
896#define MSR_IA32_MC0_STATUS 0x401
897
898/** Basic VMX information. */
899#define MSR_IA32_VMX_BASIC_INFO 0x480
900/** Allowed settings for pin-based VM execution controls */
901#define MSR_IA32_VMX_PINBASED_CTLS 0x481
902/** Allowed settings for proc-based VM execution controls */
903#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
904/** Allowed settings for the VMX exit controls. */
905#define MSR_IA32_VMX_EXIT_CTLS 0x483
906/** Allowed settings for the VMX entry controls. */
907#define MSR_IA32_VMX_ENTRY_CTLS 0x484
908/** Misc VMX info. */
909#define MSR_IA32_VMX_MISC 0x485
910/** Fixed cleared bits in CR0. */
911#define MSR_IA32_VMX_CR0_FIXED0 0x486
912/** Fixed set bits in CR0. */
913#define MSR_IA32_VMX_CR0_FIXED1 0x487
914/** Fixed cleared bits in CR4. */
915#define MSR_IA32_VMX_CR4_FIXED0 0x488
916/** Fixed set bits in CR4. */
917#define MSR_IA32_VMX_CR4_FIXED1 0x489
918/** Information for enumerating fields in the VMCS. */
919#define MSR_IA32_VMX_VMCS_ENUM 0x48A
920/** Allowed settings for secondary proc-based VM execution controls */
921#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
922/** EPT capabilities. */
923#define MSR_IA32_VMX_EPT_CAPS 0x48C
924/** DS Save Area (R/W). */
925#define MSR_IA32_DS_AREA 0x600
926/** X2APIC MSR ranges. */
927#define MSR_IA32_APIC_START 0x800
928#define MSR_IA32_APIC_END 0x900
929
930/** K6 EFER - Extended Feature Enable Register. */
931#define MSR_K6_EFER 0xc0000080
932/** @todo document EFER */
933/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
934#define MSR_K6_EFER_SCE RT_BIT(0)
935/** Bit 8 - LME - Long mode enabled. (R/W) */
936#define MSR_K6_EFER_LME RT_BIT(8)
937/** Bit 10 - LMA - Long mode active. (R) */
938#define MSR_K6_EFER_LMA RT_BIT(10)
939/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
940#define MSR_K6_EFER_NXE RT_BIT(11)
941/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
942#define MSR_K6_EFER_SVME RT_BIT(12)
943/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
944#define MSR_K6_EFER_LMSLE RT_BIT(13)
945/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
946#define MSR_K6_EFER_FFXSR RT_BIT(14)
947/** K6 STAR - SYSCALL/RET targets. */
948#define MSR_K6_STAR 0xc0000081
949/** Shift value for getting the SYSRET CS and SS value. */
950#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
951/** Shift value for getting the SYSCALL CS and SS value. */
952#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
953/** Selector mask for use after shifting. */
954#define MSR_K6_STAR_SEL_MASK 0xffff
955/** The mask which give the SYSCALL EIP. */
956#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
957/** K6 WHCR - Write Handling Control Register. */
958#define MSR_K6_WHCR 0xc0000082
959/** K6 UWCCR - UC/WC Cacheability Control Register. */
960#define MSR_K6_UWCCR 0xc0000085
961/** K6 PSOR - Processor State Observability Register. */
962#define MSR_K6_PSOR 0xc0000087
963/** K6 PFIR - Page Flush/Invalidate Register. */
964#define MSR_K6_PFIR 0xc0000088
965
966/** Performance counter MSRs. (AMD only) */
967#define MSR_K7_EVNTSEL0 0xc0010000
968#define MSR_K7_EVNTSEL1 0xc0010001
969#define MSR_K7_EVNTSEL2 0xc0010002
970#define MSR_K7_EVNTSEL3 0xc0010003
971#define MSR_K7_PERFCTR0 0xc0010004
972#define MSR_K7_PERFCTR1 0xc0010005
973#define MSR_K7_PERFCTR2 0xc0010006
974#define MSR_K7_PERFCTR3 0xc0010007
975
976#define MSR_K8_HWCR 0xc0010015
977
978/** K8 LSTAR - Long mode SYSCALL target (RIP). */
979#define MSR_K8_LSTAR 0xc0000082
980/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
981#define MSR_K8_CSTAR 0xc0000083
982/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
983#define MSR_K8_SF_MASK 0xc0000084
984/** K8 FS.base - The 64-bit base FS register. */
985#define MSR_K8_FS_BASE 0xc0000100
986/** K8 GS.base - The 64-bit base GS register. */
987#define MSR_K8_GS_BASE 0xc0000101
988/** K8 KernelGSbase - Used with SWAPGS. */
989#define MSR_K8_KERNEL_GS_BASE 0xc0000102
990#define MSR_K8_TSC_AUX 0xc0000103
991#define MSR_K8_SYSCFG 0xc0010010
992#define MSR_K8_HWCR 0xc0010015
993#define MSR_K8_IORRBASE0 0xc0010016
994#define MSR_K8_IORRMASK0 0xc0010017
995#define MSR_K8_IORRBASE1 0xc0010018
996#define MSR_K8_IORRMASK1 0xc0010019
997#define MSR_K8_TOP_MEM1 0xc001001a
998#define MSR_K8_TOP_MEM2 0xc001001d
999#define MSR_K8_VM_CR 0xc0010114
1000#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1001
1002#define MSR_K8_IGNNE 0xc0010115
1003#define MSR_K8_SMM_CTL 0xc0010116
1004/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1005 * host state during world switch.
1006 */
1007#define MSR_K8_VM_HSAVE_PA 0xc0010117
1008
1009/** @} */
1010
1011
1012/** @name Page Table / Directory / Directory Pointers / L4.
1013 * @{
1014 */
1015
1016/** Page table/directory entry as an unsigned integer. */
1017typedef uint32_t X86PGUINT;
1018/** Pointer to a page table/directory table entry as an unsigned integer. */
1019typedef X86PGUINT *PX86PGUINT;
1020/** Pointer to an const page table/directory table entry as an unsigned integer. */
1021typedef X86PGUINT const *PCX86PGUINT;
1022
1023/** Number of entries in a 32-bit PT/PD. */
1024#define X86_PG_ENTRIES 1024
1025
1026
1027/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1028typedef uint64_t X86PGPAEUINT;
1029/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1030typedef X86PGPAEUINT *PX86PGPAEUINT;
1031/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1032typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1033
1034/** Number of entries in a PAE PT/PD. */
1035#define X86_PG_PAE_ENTRIES 512
1036/** Number of entries in a PAE PDPT. */
1037#define X86_PG_PAE_PDPE_ENTRIES 4
1038
1039/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1040#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1041/** Number of entries in an AMD64 PDPT.
1042 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1043#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1044
1045/** The size of a 4KB page. */
1046#define X86_PAGE_4K_SIZE _4K
1047/** The page shift of a 4KB page. */
1048#define X86_PAGE_4K_SHIFT 12
1049/** The 4KB page offset mask. */
1050#define X86_PAGE_4K_OFFSET_MASK 0xfff
1051/** The 4KB page base mask for virtual addresses. */
1052#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1053/** The 4KB page base mask for virtual addresses - 32bit version. */
1054#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1055
1056/** The size of a 2MB page. */
1057#define X86_PAGE_2M_SIZE _2M
1058/** The page shift of a 2MB page. */
1059#define X86_PAGE_2M_SHIFT 21
1060/** The 2MB page offset mask. */
1061#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1062/** The 2MB page base mask for virtual addresses. */
1063#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1064/** The 2MB page base mask for virtual addresses - 32bit version. */
1065#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1066
1067/** The size of a 4MB page. */
1068#define X86_PAGE_4M_SIZE _4M
1069/** The page shift of a 4MB page. */
1070#define X86_PAGE_4M_SHIFT 22
1071/** The 4MB page offset mask. */
1072#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1073/** The 4MB page base mask for virtual addresses. */
1074#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1075/** The 4MB page base mask for virtual addresses - 32bit version. */
1076#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1077
1078
1079
1080/** @name Page Table Entry
1081 * @{
1082 */
1083/** Bit 0 - P - Present bit. */
1084#define X86_PTE_BIT_P 0
1085/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1086#define X86_PTE_BIT_RW 1
1087/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1088#define X86_PTE_BIT_US 2
1089/** Bit 3 - PWT - Page level write thru bit. */
1090#define X86_PTE_BIT_PWT 3
1091/** Bit 4 - PCD - Page level cache disable bit. */
1092#define X86_PTE_BIT_PCD 4
1093/** Bit 5 - A - Access bit. */
1094#define X86_PTE_BIT_A 5
1095/** Bit 6 - D - Dirty bit. */
1096#define X86_PTE_BIT_D 6
1097/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1098#define X86_PTE_BIT_PAT 7
1099/** Bit 8 - G - Global flag. */
1100#define X86_PTE_BIT_G 8
1101
1102/** Bit 0 - P - Present bit mask. */
1103#define X86_PTE_P RT_BIT(0)
1104/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1105#define X86_PTE_RW RT_BIT(1)
1106/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1107#define X86_PTE_US RT_BIT(2)
1108/** Bit 3 - PWT - Page level write thru bit mask. */
1109#define X86_PTE_PWT RT_BIT(3)
1110/** Bit 4 - PCD - Page level cache disable bit mask. */
1111#define X86_PTE_PCD RT_BIT(4)
1112/** Bit 5 - A - Access bit mask. */
1113#define X86_PTE_A RT_BIT(5)
1114/** Bit 6 - D - Dirty bit mask. */
1115#define X86_PTE_D RT_BIT(6)
1116/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1117#define X86_PTE_PAT RT_BIT(7)
1118/** Bit 8 - G - Global bit mask. */
1119#define X86_PTE_G RT_BIT(8)
1120
1121/** Bits 9-11 - - Available for use to system software. */
1122#define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1123/** Bits 12-31 - - Physical Page number of the next level. */
1124#define X86_PTE_PG_MASK ( 0xfffff000 )
1125
1126/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1127#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1128/** Bits 63 - NX - PAE/LM - No execution flag. */
1129#define X86_PTE_PAE_NX RT_BIT_64(63)
1130/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1131#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1132/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1133#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1134/** No bits - - LM - MBZ bits when NX is active. */
1135#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1136/** Bits 63 - - LM - MBZ bits when no NX. */
1137#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1138
1139/**
1140 * Page table entry.
1141 */
1142typedef struct X86PTEBITS
1143{
1144 /** Flags whether(=1) or not the page is present. */
1145 unsigned u1Present : 1;
1146 /** Read(=0) / Write(=1) flag. */
1147 unsigned u1Write : 1;
1148 /** User(=1) / Supervisor (=0) flag. */
1149 unsigned u1User : 1;
1150 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1151 unsigned u1WriteThru : 1;
1152 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1153 unsigned u1CacheDisable : 1;
1154 /** Accessed flag.
1155 * Indicates that the page have been read or written to. */
1156 unsigned u1Accessed : 1;
1157 /** Dirty flag.
1158 * Indicates that the page has been written to. */
1159 unsigned u1Dirty : 1;
1160 /** Reserved / If PAT enabled, bit 2 of the index. */
1161 unsigned u1PAT : 1;
1162 /** Global flag. (Ignored in all but final level.) */
1163 unsigned u1Global : 1;
1164 /** Available for use to system software. */
1165 unsigned u3Available : 3;
1166 /** Physical Page number of the next level. */
1167 unsigned u20PageNo : 20;
1168} X86PTEBITS;
1169/** Pointer to a page table entry. */
1170typedef X86PTEBITS *PX86PTEBITS;
1171/** Pointer to a const page table entry. */
1172typedef const X86PTEBITS *PCX86PTEBITS;
1173
1174/**
1175 * Page table entry.
1176 */
1177typedef union X86PTE
1178{
1179 /** Unsigned integer view */
1180 X86PGUINT u;
1181 /** Bit field view. */
1182 X86PTEBITS n;
1183 /** 32-bit view. */
1184 uint32_t au32[1];
1185 /** 16-bit view. */
1186 uint16_t au16[2];
1187 /** 8-bit view. */
1188 uint8_t au8[4];
1189} X86PTE;
1190/** Pointer to a page table entry. */
1191typedef X86PTE *PX86PTE;
1192/** Pointer to a const page table entry. */
1193typedef const X86PTE *PCX86PTE;
1194
1195
1196/**
1197 * PAE page table entry.
1198 */
1199typedef struct X86PTEPAEBITS
1200{
1201 /** Flags whether(=1) or not the page is present. */
1202 uint32_t u1Present : 1;
1203 /** Read(=0) / Write(=1) flag. */
1204 uint32_t u1Write : 1;
1205 /** User(=1) / Supervisor(=0) flag. */
1206 uint32_t u1User : 1;
1207 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1208 uint32_t u1WriteThru : 1;
1209 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1210 uint32_t u1CacheDisable : 1;
1211 /** Accessed flag.
1212 * Indicates that the page have been read or written to. */
1213 uint32_t u1Accessed : 1;
1214 /** Dirty flag.
1215 * Indicates that the page has been written to. */
1216 uint32_t u1Dirty : 1;
1217 /** Reserved / If PAT enabled, bit 2 of the index. */
1218 uint32_t u1PAT : 1;
1219 /** Global flag. (Ignored in all but final level.) */
1220 uint32_t u1Global : 1;
1221 /** Available for use to system software. */
1222 uint32_t u3Available : 3;
1223 /** Physical Page number of the next level - Low Part. Don't use this. */
1224 uint32_t u20PageNoLow : 20;
1225 /** Physical Page number of the next level - High Part. Don't use this. */
1226 uint32_t u20PageNoHigh : 20;
1227 /** MBZ bits */
1228 uint32_t u11Reserved : 11;
1229 /** No Execute flag. */
1230 uint32_t u1NoExecute : 1;
1231} X86PTEPAEBITS;
1232/** Pointer to a page table entry. */
1233typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1234/** Pointer to a page table entry. */
1235typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1236
1237/**
1238 * PAE Page table entry.
1239 */
1240typedef union X86PTEPAE
1241{
1242 /** Unsigned integer view */
1243 X86PGPAEUINT u;
1244 /** Bit field view. */
1245 X86PTEPAEBITS n;
1246 /** 32-bit view. */
1247 uint32_t au32[2];
1248 /** 16-bit view. */
1249 uint16_t au16[4];
1250 /** 8-bit view. */
1251 uint8_t au8[8];
1252} X86PTEPAE;
1253/** Pointer to a PAE page table entry. */
1254typedef X86PTEPAE *PX86PTEPAE;
1255/** Pointer to a const PAE page table entry. */
1256typedef const X86PTEPAE *PCX86PTEPAE;
1257/** @} */
1258
1259/**
1260 * Page table.
1261 */
1262typedef struct X86PT
1263{
1264 /** PTE Array. */
1265 X86PTE a[X86_PG_ENTRIES];
1266} X86PT;
1267/** Pointer to a page table. */
1268typedef X86PT *PX86PT;
1269/** Pointer to a const page table. */
1270typedef const X86PT *PCX86PT;
1271
1272/** The page shift to get the PT index. */
1273#define X86_PT_SHIFT 12
1274/** The PT index mask (apply to a shifted page address). */
1275#define X86_PT_MASK 0x3ff
1276
1277
1278/**
1279 * Page directory.
1280 */
1281typedef struct X86PTPAE
1282{
1283 /** PTE Array. */
1284 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1285} X86PTPAE;
1286/** Pointer to a page table. */
1287typedef X86PTPAE *PX86PTPAE;
1288/** Pointer to a const page table. */
1289typedef const X86PTPAE *PCX86PTPAE;
1290
1291/** The page shift to get the PA PTE index. */
1292#define X86_PT_PAE_SHIFT 12
1293/** The PAE PT index mask (apply to a shifted page address). */
1294#define X86_PT_PAE_MASK 0x1ff
1295
1296
1297/** @name 4KB Page Directory Entry
1298 * @{
1299 */
1300/** Bit 0 - P - Present bit. */
1301#define X86_PDE_P RT_BIT(0)
1302/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1303#define X86_PDE_RW RT_BIT(1)
1304/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1305#define X86_PDE_US RT_BIT(2)
1306/** Bit 3 - PWT - Page level write thru bit. */
1307#define X86_PDE_PWT RT_BIT(3)
1308/** Bit 4 - PCD - Page level cache disable bit. */
1309#define X86_PDE_PCD RT_BIT(4)
1310/** Bit 5 - A - Access bit. */
1311#define X86_PDE_A RT_BIT(5)
1312/** Bit 7 - PS - Page size attribute.
1313 * Clear mean 4KB pages, set means large pages (2/4MB). */
1314#define X86_PDE_PS RT_BIT(7)
1315/** Bits 9-11 - - Available for use to system software. */
1316#define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1317/** Bits 12-31 - - Physical Page number of the next level. */
1318#define X86_PDE_PG_MASK ( 0xfffff000 )
1319
1320/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1321#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1322/** Bits 63 - NX - PAE/LM - No execution flag. */
1323#define X86_PDE_PAE_NX RT_BIT_64(63)
1324/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1325#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1326/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1327#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1328/** Bit 7 - - LM - MBZ bits when NX is active. */
1329#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1330/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1331#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1332
1333/**
1334 * Page directory entry.
1335 */
1336typedef struct X86PDEBITS
1337{
1338 /** Flags whether(=1) or not the page is present. */
1339 unsigned u1Present : 1;
1340 /** Read(=0) / Write(=1) flag. */
1341 unsigned u1Write : 1;
1342 /** User(=1) / Supervisor (=0) flag. */
1343 unsigned u1User : 1;
1344 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1345 unsigned u1WriteThru : 1;
1346 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1347 unsigned u1CacheDisable : 1;
1348 /** Accessed flag.
1349 * Indicates that the page has been read or written to. */
1350 unsigned u1Accessed : 1;
1351 /** Reserved / Ignored (dirty bit). */
1352 unsigned u1Reserved0 : 1;
1353 /** Size bit if PSE is enabled - in any event it's 0. */
1354 unsigned u1Size : 1;
1355 /** Reserved / Ignored (global bit). */
1356 unsigned u1Reserved1 : 1;
1357 /** Available for use to system software. */
1358 unsigned u3Available : 3;
1359 /** Physical Page number of the next level. */
1360 unsigned u20PageNo : 20;
1361} X86PDEBITS;
1362/** Pointer to a page directory entry. */
1363typedef X86PDEBITS *PX86PDEBITS;
1364/** Pointer to a const page directory entry. */
1365typedef const X86PDEBITS *PCX86PDEBITS;
1366
1367
1368/**
1369 * PAE page directory entry.
1370 */
1371typedef struct X86PDEPAEBITS
1372{
1373 /** Flags whether(=1) or not the page is present. */
1374 uint32_t u1Present : 1;
1375 /** Read(=0) / Write(=1) flag. */
1376 uint32_t u1Write : 1;
1377 /** User(=1) / Supervisor (=0) flag. */
1378 uint32_t u1User : 1;
1379 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1380 uint32_t u1WriteThru : 1;
1381 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1382 uint32_t u1CacheDisable : 1;
1383 /** Accessed flag.
1384 * Indicates that the page has been read or written to. */
1385 uint32_t u1Accessed : 1;
1386 /** Reserved / Ignored (dirty bit). */
1387 uint32_t u1Reserved0 : 1;
1388 /** Size bit if PSE is enabled - in any event it's 0. */
1389 uint32_t u1Size : 1;
1390 /** Reserved / Ignored (global bit). / */
1391 uint32_t u1Reserved1 : 1;
1392 /** Available for use to system software. */
1393 uint32_t u3Available : 3;
1394 /** Physical Page number of the next level - Low Part. Don't use! */
1395 uint32_t u20PageNoLow : 20;
1396 /** Physical Page number of the next level - High Part. Don't use! */
1397 uint32_t u20PageNoHigh : 20;
1398 /** MBZ bits */
1399 uint32_t u11Reserved : 11;
1400 /** No Execute flag. */
1401 uint32_t u1NoExecute : 1;
1402} X86PDEPAEBITS;
1403/** Pointer to a page directory entry. */
1404typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1405/** Pointer to a const page directory entry. */
1406typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1407
1408/** @} */
1409
1410
1411/** @name 2/4MB Page Directory Entry
1412 * @{
1413 */
1414/** Bit 0 - P - Present bit. */
1415#define X86_PDE4M_P RT_BIT(0)
1416/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1417#define X86_PDE4M_RW RT_BIT(1)
1418/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1419#define X86_PDE4M_US RT_BIT(2)
1420/** Bit 3 - PWT - Page level write thru bit. */
1421#define X86_PDE4M_PWT RT_BIT(3)
1422/** Bit 4 - PCD - Page level cache disable bit. */
1423#define X86_PDE4M_PCD RT_BIT(4)
1424/** Bit 5 - A - Access bit. */
1425#define X86_PDE4M_A RT_BIT(5)
1426/** Bit 6 - D - Dirty bit. */
1427#define X86_PDE4M_D RT_BIT(6)
1428/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1429#define X86_PDE4M_PS RT_BIT(7)
1430/** Bit 8 - G - Global flag. */
1431#define X86_PDE4M_G RT_BIT(8)
1432/** Bits 9-11 - AVL - Available for use to system software. */
1433#define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1434/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1435#define X86_PDE4M_PAT RT_BIT(12)
1436/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1437#define X86_PDE4M_PAT_SHIFT (12 - 7)
1438/** Bits 22-31 - - Physical Page number. */
1439#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1440/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1441#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1442/** The number of bits to the high part of the page number. */
1443#define X86_PDE4M_PG_HIGH_SHIFT 19
1444/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1445#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1446
1447/** Bits 21-51 - - PAE/LM - Physical Page number.
1448 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1449#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1450/** Bits 63 - NX - PAE/LM - No execution flag. */
1451#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1452/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1453#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1454/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1455#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1456/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1457#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1458/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1459#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1460
1461/**
1462 * 4MB page directory entry.
1463 */
1464typedef struct X86PDE4MBITS
1465{
1466 /** Flags whether(=1) or not the page is present. */
1467 unsigned u1Present : 1;
1468 /** Read(=0) / Write(=1) flag. */
1469 unsigned u1Write : 1;
1470 /** User(=1) / Supervisor (=0) flag. */
1471 unsigned u1User : 1;
1472 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1473 unsigned u1WriteThru : 1;
1474 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1475 unsigned u1CacheDisable : 1;
1476 /** Accessed flag.
1477 * Indicates that the page have been read or written to. */
1478 unsigned u1Accessed : 1;
1479 /** Dirty flag.
1480 * Indicates that the page has been written to. */
1481 unsigned u1Dirty : 1;
1482 /** Page size flag - always 1 for 4MB entries. */
1483 unsigned u1Size : 1;
1484 /** Global flag. */
1485 unsigned u1Global : 1;
1486 /** Available for use to system software. */
1487 unsigned u3Available : 3;
1488 /** Reserved / If PAT enabled, bit 2 of the index. */
1489 unsigned u1PAT : 1;
1490 /** Bits 32-39 of the page number on AMD64.
1491 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1492 unsigned u8PageNoHigh : 8;
1493 /** Reserved. */
1494 unsigned u1Reserved : 1;
1495 /** Physical Page number of the page. */
1496 unsigned u10PageNo : 10;
1497} X86PDE4MBITS;
1498/** Pointer to a page table entry. */
1499typedef X86PDE4MBITS *PX86PDE4MBITS;
1500/** Pointer to a const page table entry. */
1501typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1502
1503
1504/**
1505 * 2MB PAE page directory entry.
1506 */
1507typedef struct X86PDE2MPAEBITS
1508{
1509 /** Flags whether(=1) or not the page is present. */
1510 uint32_t u1Present : 1;
1511 /** Read(=0) / Write(=1) flag. */
1512 uint32_t u1Write : 1;
1513 /** User(=1) / Supervisor(=0) flag. */
1514 uint32_t u1User : 1;
1515 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1516 uint32_t u1WriteThru : 1;
1517 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1518 uint32_t u1CacheDisable : 1;
1519 /** Accessed flag.
1520 * Indicates that the page have been read or written to. */
1521 uint32_t u1Accessed : 1;
1522 /** Dirty flag.
1523 * Indicates that the page has been written to. */
1524 uint32_t u1Dirty : 1;
1525 /** Page size flag - always 1 for 2MB entries. */
1526 uint32_t u1Size : 1;
1527 /** Global flag. */
1528 uint32_t u1Global : 1;
1529 /** Available for use to system software. */
1530 uint32_t u3Available : 3;
1531 /** Reserved / If PAT enabled, bit 2 of the index. */
1532 uint32_t u1PAT : 1;
1533 /** Reserved. */
1534 uint32_t u9Reserved : 9;
1535 /** Physical Page number of the next level - Low part. Don't use! */
1536 uint32_t u10PageNoLow : 10;
1537 /** Physical Page number of the next level - High part. Don't use! */
1538 uint32_t u20PageNoHigh : 20;
1539 /** MBZ bits */
1540 uint32_t u11Reserved : 11;
1541 /** No Execute flag. */
1542 uint32_t u1NoExecute : 1;
1543} X86PDE2MPAEBITS;
1544/** Pointer to a 2MB PAE page table entry. */
1545typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1546/** Pointer to a 2MB PAE page table entry. */
1547typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1548
1549/** @} */
1550
1551/**
1552 * Page directory entry.
1553 */
1554typedef union X86PDE
1555{
1556 /** Unsigned integer view. */
1557 X86PGUINT u;
1558 /** Normal view. */
1559 X86PDEBITS n;
1560 /** 4MB view (big). */
1561 X86PDE4MBITS b;
1562 /** 8 bit unsigned integer view. */
1563 uint8_t au8[4];
1564 /** 16 bit unsigned integer view. */
1565 uint16_t au16[2];
1566 /** 32 bit unsigned integer view. */
1567 uint32_t au32[1];
1568} X86PDE;
1569/** Pointer to a page directory entry. */
1570typedef X86PDE *PX86PDE;
1571/** Pointer to a const page directory entry. */
1572typedef const X86PDE *PCX86PDE;
1573
1574/**
1575 * PAE page directory entry.
1576 */
1577typedef union X86PDEPAE
1578{
1579 /** Unsigned integer view. */
1580 X86PGPAEUINT u;
1581 /** Normal view. */
1582 X86PDEPAEBITS n;
1583 /** 2MB page view (big). */
1584 X86PDE2MPAEBITS b;
1585 /** 8 bit unsigned integer view. */
1586 uint8_t au8[8];
1587 /** 16 bit unsigned integer view. */
1588 uint16_t au16[4];
1589 /** 32 bit unsigned integer view. */
1590 uint32_t au32[2];
1591} X86PDEPAE;
1592/** Pointer to a page directory entry. */
1593typedef X86PDEPAE *PX86PDEPAE;
1594/** Pointer to a const page directory entry. */
1595typedef const X86PDEPAE *PCX86PDEPAE;
1596
1597/**
1598 * Page directory.
1599 */
1600typedef struct X86PD
1601{
1602 /** PDE Array. */
1603 X86PDE a[X86_PG_ENTRIES];
1604} X86PD;
1605/** Pointer to a page directory. */
1606typedef X86PD *PX86PD;
1607/** Pointer to a const page directory. */
1608typedef const X86PD *PCX86PD;
1609
1610/** The page shift to get the PD index. */
1611#define X86_PD_SHIFT 22
1612/** The PD index mask (apply to a shifted page address). */
1613#define X86_PD_MASK 0x3ff
1614
1615
1616/**
1617 * PAE page directory.
1618 */
1619typedef struct X86PDPAE
1620{
1621 /** PDE Array. */
1622 X86PDEPAE a[X86_PG_PAE_ENTRIES];
1623} X86PDPAE;
1624/** Pointer to a PAE page directory. */
1625typedef X86PDPAE *PX86PDPAE;
1626/** Pointer to a const PAE page directory. */
1627typedef const X86PDPAE *PCX86PDPAE;
1628
1629/** The page shift to get the PAE PD index. */
1630#define X86_PD_PAE_SHIFT 21
1631/** The PAE PD index mask (apply to a shifted page address). */
1632#define X86_PD_PAE_MASK 0x1ff
1633
1634
1635/** @name Page Directory Pointer Table Entry (PAE)
1636 * @{
1637 */
1638/** Bit 0 - P - Present bit. */
1639#define X86_PDPE_P RT_BIT(0)
1640/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1641#define X86_PDPE_RW RT_BIT(1)
1642/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1643#define X86_PDPE_US RT_BIT(2)
1644/** Bit 3 - PWT - Page level write thru bit. */
1645#define X86_PDPE_PWT RT_BIT(3)
1646/** Bit 4 - PCD - Page level cache disable bit. */
1647#define X86_PDPE_PCD RT_BIT(4)
1648/** Bit 5 - A - Access bit. Long Mode only. */
1649#define X86_PDPE_A RT_BIT(5)
1650/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1651#define X86_PDPE_LM_PS RT_BIT(7)
1652/** Bits 9-11 - - Available for use to system software. */
1653#define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1654/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1655#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1656/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1657#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1658/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1659#define X86_PDPE_LM_NX RT_BIT_64(63)
1660/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1661#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1662/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1663#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1664/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1665#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1666/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1667#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1668
1669
1670/**
1671 * Page directory pointer table entry.
1672 */
1673typedef struct X86PDPEBITS
1674{
1675 /** Flags whether(=1) or not the page is present. */
1676 uint32_t u1Present : 1;
1677 /** Chunk of reserved bits. */
1678 uint32_t u2Reserved : 2;
1679 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1680 uint32_t u1WriteThru : 1;
1681 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1682 uint32_t u1CacheDisable : 1;
1683 /** Chunk of reserved bits. */
1684 uint32_t u4Reserved : 4;
1685 /** Available for use to system software. */
1686 uint32_t u3Available : 3;
1687 /** Physical Page number of the next level - Low Part. Don't use! */
1688 uint32_t u20PageNoLow : 20;
1689 /** Physical Page number of the next level - High Part. Don't use! */
1690 uint32_t u20PageNoHigh : 20;
1691 /** MBZ bits */
1692 uint32_t u12Reserved : 12;
1693} X86PDPEBITS;
1694/** Pointer to a page directory pointer table entry. */
1695typedef X86PDPEBITS *PX86PTPEBITS;
1696/** Pointer to a const page directory pointer table entry. */
1697typedef const X86PDPEBITS *PCX86PTPEBITS;
1698
1699/**
1700 * Page directory pointer table entry. AMD64 version
1701 */
1702typedef struct X86PDPEAMD64BITS
1703{
1704 /** Flags whether(=1) or not the page is present. */
1705 uint32_t u1Present : 1;
1706 /** Read(=0) / Write(=1) flag. */
1707 uint32_t u1Write : 1;
1708 /** User(=1) / Supervisor (=0) flag. */
1709 uint32_t u1User : 1;
1710 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1711 uint32_t u1WriteThru : 1;
1712 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1713 uint32_t u1CacheDisable : 1;
1714 /** Accessed flag.
1715 * Indicates that the page have been read or written to. */
1716 uint32_t u1Accessed : 1;
1717 /** Chunk of reserved bits. */
1718 uint32_t u3Reserved : 3;
1719 /** Available for use to system software. */
1720 uint32_t u3Available : 3;
1721 /** Physical Page number of the next level - Low Part. Don't use! */
1722 uint32_t u20PageNoLow : 20;
1723 /** Physical Page number of the next level - High Part. Don't use! */
1724 uint32_t u20PageNoHigh : 20;
1725 /** MBZ bits */
1726 uint32_t u11Reserved : 11;
1727 /** No Execute flag. */
1728 uint32_t u1NoExecute : 1;
1729} X86PDPEAMD64BITS;
1730/** Pointer to a page directory pointer table entry. */
1731typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1732/** Pointer to a const page directory pointer table entry. */
1733typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1734
1735/**
1736 * Page directory pointer table entry.
1737 */
1738typedef union X86PDPE
1739{
1740 /** Unsigned integer view. */
1741 X86PGPAEUINT u;
1742 /** Normal view. */
1743 X86PDPEBITS n;
1744 /** AMD64 view. */
1745 X86PDPEAMD64BITS lm;
1746 /** 8 bit unsigned integer view. */
1747 uint8_t au8[8];
1748 /** 16 bit unsigned integer view. */
1749 uint16_t au16[4];
1750 /** 32 bit unsigned integer view. */
1751 uint32_t au32[2];
1752} X86PDPE;
1753/** Pointer to a page directory pointer table entry. */
1754typedef X86PDPE *PX86PDPE;
1755/** Pointer to a const page directory pointer table entry. */
1756typedef const X86PDPE *PCX86PDPE;
1757
1758
1759/**
1760 * Page directory pointer table.
1761 */
1762typedef struct X86PDPT
1763{
1764 /** PDE Array. */
1765 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1766} X86PDPT;
1767/** Pointer to a page directory pointer table. */
1768typedef X86PDPT *PX86PDPT;
1769/** Pointer to a const page directory pointer table. */
1770typedef const X86PDPT *PCX86PDPT;
1771
1772/** The page shift to get the PDPT index. */
1773#define X86_PDPT_SHIFT 30
1774/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1775#define X86_PDPT_MASK_PAE 0x3
1776/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1777#define X86_PDPT_MASK_AMD64 0x1ff
1778
1779/** @} */
1780
1781
1782/** @name Page Map Level-4 Entry (Long Mode PAE)
1783 * @{
1784 */
1785/** Bit 0 - P - Present bit. */
1786#define X86_PML4E_P RT_BIT(0)
1787/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1788#define X86_PML4E_RW RT_BIT(1)
1789/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1790#define X86_PML4E_US RT_BIT(2)
1791/** Bit 3 - PWT - Page level write thru bit. */
1792#define X86_PML4E_PWT RT_BIT(3)
1793/** Bit 4 - PCD - Page level cache disable bit. */
1794#define X86_PML4E_PCD RT_BIT(4)
1795/** Bit 5 - A - Access bit. */
1796#define X86_PML4E_A RT_BIT(5)
1797/** Bits 9-11 - - Available for use to system software. */
1798#define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1799/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1800#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1801/** Bits 8, 7 - - MBZ bits when NX is active. */
1802#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1803/** Bits 63, 7 - - MBZ bits when no NX. */
1804#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1805/** Bits 63 - NX - PAE - No execution flag. */
1806#define X86_PML4E_NX RT_BIT_64(63)
1807
1808/**
1809 * Page Map Level-4 Entry
1810 */
1811typedef struct X86PML4EBITS
1812{
1813 /** Flags whether(=1) or not the page is present. */
1814 uint32_t u1Present : 1;
1815 /** Read(=0) / Write(=1) flag. */
1816 uint32_t u1Write : 1;
1817 /** User(=1) / Supervisor (=0) flag. */
1818 uint32_t u1User : 1;
1819 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1820 uint32_t u1WriteThru : 1;
1821 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1822 uint32_t u1CacheDisable : 1;
1823 /** Accessed flag.
1824 * Indicates that the page have been read or written to. */
1825 uint32_t u1Accessed : 1;
1826 /** Chunk of reserved bits. */
1827 uint32_t u3Reserved : 3;
1828 /** Available for use to system software. */
1829 uint32_t u3Available : 3;
1830 /** Physical Page number of the next level - Low Part. Don't use! */
1831 uint32_t u20PageNoLow : 20;
1832 /** Physical Page number of the next level - High Part. Don't use! */
1833 uint32_t u20PageNoHigh : 20;
1834 /** MBZ bits */
1835 uint32_t u11Reserved : 11;
1836 /** No Execute flag. */
1837 uint32_t u1NoExecute : 1;
1838} X86PML4EBITS;
1839/** Pointer to a page map level-4 entry. */
1840typedef X86PML4EBITS *PX86PML4EBITS;
1841/** Pointer to a const page map level-4 entry. */
1842typedef const X86PML4EBITS *PCX86PML4EBITS;
1843
1844/**
1845 * Page Map Level-4 Entry.
1846 */
1847typedef union X86PML4E
1848{
1849 /** Unsigned integer view. */
1850 X86PGPAEUINT u;
1851 /** Normal view. */
1852 X86PML4EBITS n;
1853 /** 8 bit unsigned integer view. */
1854 uint8_t au8[8];
1855 /** 16 bit unsigned integer view. */
1856 uint16_t au16[4];
1857 /** 32 bit unsigned integer view. */
1858 uint32_t au32[2];
1859} X86PML4E;
1860/** Pointer to a page map level-4 entry. */
1861typedef X86PML4E *PX86PML4E;
1862/** Pointer to a const page map level-4 entry. */
1863typedef const X86PML4E *PCX86PML4E;
1864
1865
1866/**
1867 * Page Map Level-4.
1868 */
1869typedef struct X86PML4
1870{
1871 /** PDE Array. */
1872 X86PML4E a[X86_PG_PAE_ENTRIES];
1873} X86PML4;
1874/** Pointer to a page map level-4. */
1875typedef X86PML4 *PX86PML4;
1876/** Pointer to a const page map level-4. */
1877typedef const X86PML4 *PCX86PML4;
1878
1879/** The page shift to get the PML4 index. */
1880#define X86_PML4_SHIFT 39
1881/** The PML4 index mask (apply to a shifted page address). */
1882#define X86_PML4_MASK 0x1ff
1883
1884/** @} */
1885
1886/** @} */
1887
1888
1889/**
1890 * 80-bit MMX/FPU register type.
1891 */
1892typedef struct X86FPUMMX
1893{
1894 uint8_t reg[10];
1895} X86FPUMMX;
1896/** Pointer to a 80-bit MMX/FPU register type. */
1897typedef X86FPUMMX *PX86FPUMMX;
1898/** Pointer to a const 80-bit MMX/FPU register type. */
1899typedef const X86FPUMMX *PCX86FPUMMX;
1900
1901/**
1902 * FPU state (aka FSAVE/FRSTOR Memory Region).
1903 */
1904#pragma pack(1)
1905typedef struct X86FPUSTATE
1906{
1907 /** Control word. */
1908 uint16_t FCW;
1909 /** Alignment word */
1910 uint16_t Dummy1;
1911 /** Status word. */
1912 uint16_t FSW;
1913 /** Alignment word */
1914 uint16_t Dummy2;
1915 /** Tag word */
1916 uint16_t FTW;
1917 /** Alignment word */
1918 uint16_t Dummy3;
1919
1920 /** Instruction pointer. */
1921 uint32_t FPUIP;
1922 /** Code selector. */
1923 uint16_t CS;
1924 /** Opcode. */
1925 uint16_t FOP;
1926 /** FOO. */
1927 uint32_t FPUOO;
1928 /** FOS. */
1929 uint32_t FPUOS;
1930 /* - offset 32 - */
1931 union
1932 {
1933 /** MMX view. */
1934 uint64_t mmx;
1935 /** FPU view - todo. */
1936 X86FPUMMX fpu;
1937 /** 8-bit view. */
1938 uint8_t au8[16];
1939 /** 16-bit view. */
1940 uint16_t au16[8];
1941 /** 32-bit view. */
1942 uint32_t au32[4];
1943 /** 64-bit view. */
1944 uint64_t au64[2];
1945 /** 128-bit view. (yeah, very helpful) */
1946 uint128_t au128[1];
1947 } regs[8];
1948} X86FPUSTATE;
1949#pragma pack()
1950/** Pointer to a FPU state. */
1951typedef X86FPUSTATE *PX86FPUSTATE;
1952/** Pointer to a const FPU state. */
1953typedef const X86FPUSTATE *PCX86FPUSTATE;
1954
1955/**
1956 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1957 */
1958#pragma pack(1)
1959typedef struct X86FXSTATE
1960{
1961 /** Control word. */
1962 uint16_t FCW;
1963 /** Status word. */
1964 uint16_t FSW;
1965 /** Tag word. (The upper byte is always zero.) */
1966 uint16_t FTW;
1967 /** Opcode. */
1968 uint16_t FOP;
1969 /** Instruction pointer. */
1970 uint32_t FPUIP;
1971 /** Code selector. */
1972 uint16_t CS;
1973 uint16_t Rsvrd1;
1974 /* - offset 16 - */
1975 /** Data pointer. */
1976 uint32_t FPUDP;
1977 /** Data segment */
1978 uint16_t DS;
1979 uint16_t Rsrvd2;
1980 uint32_t MXCSR;
1981 uint32_t MXCSR_MASK;
1982 /* - offset 32 - */
1983 union
1984 {
1985 /** MMX view. */
1986 uint64_t mmx;
1987 /** FPU view - todo. */
1988 X86FPUMMX fpu;
1989 /** 8-bit view. */
1990 uint8_t au8[16];
1991 /** 16-bit view. */
1992 uint16_t au16[8];
1993 /** 32-bit view. */
1994 uint32_t au32[4];
1995 /** 64-bit view. */
1996 uint64_t au64[2];
1997 /** 128-bit view. (yeah, very helpful) */
1998 uint128_t au128[1];
1999 } aRegs[8];
2000 /* - offset 160 - */
2001 union
2002 {
2003 /** XMM Register view *. */
2004 uint128_t xmm;
2005 /** 8-bit view. */
2006 uint8_t au8[16];
2007 /** 16-bit view. */
2008 uint16_t au16[8];
2009 /** 32-bit view. */
2010 uint32_t au32[4];
2011 /** 64-bit view. */
2012 uint64_t au64[2];
2013 /** 128-bit view. (yeah, very helpful) */
2014 uint128_t au128[1];
2015 } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2016 /* - offset 416 - */
2017 uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2018} X86FXSTATE;
2019#pragma pack()
2020/** Pointer to a FPU Extended state. */
2021typedef X86FXSTATE *PX86FXSTATE;
2022/** Pointer to a const FPU Extended state. */
2023typedef const X86FXSTATE *PCX86FXSTATE;
2024
2025
2026/** @name Selector Descriptor
2027 * @{
2028 */
2029
2030/**
2031 * Descriptor attributes.
2032 */
2033typedef struct X86DESCATTRBITS
2034{
2035 /** 00 - Segment Type. */
2036 unsigned u4Type : 4;
2037 /** 04 - Descriptor Type. System(=0) or code/data selector */
2038 unsigned u1DescType : 1;
2039 /** 05 - Descriptor Privelege level. */
2040 unsigned u2Dpl : 2;
2041 /** 07 - Flags selector present(=1) or not. */
2042 unsigned u1Present : 1;
2043 /** 08 - Segment limit 16-19. */
2044 unsigned u4LimitHigh : 4;
2045 /** 0c - Available for system software. */
2046 unsigned u1Available : 1;
2047 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2048 unsigned u1Long : 1;
2049 /** 0e - This flags meaning depends on the segment type. Try make sense out
2050 * of the intel manual yourself. */
2051 unsigned u1DefBig : 1;
2052 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
2053 * clear byte. */
2054 unsigned u1Granularity : 1;
2055} X86DESCATTRBITS;
2056
2057
2058#pragma pack(1)
2059typedef union X86DESCATTR
2060{
2061 /** Unsigned integer view. */
2062 uint32_t u;
2063 /** Normal view. */
2064 X86DESCATTRBITS n;
2065} X86DESCATTR;
2066#pragma pack()
2067/** Pointer to descriptor attributes. */
2068typedef X86DESCATTR *PX86DESCATTR;
2069/** Pointer to const descriptor attributes. */
2070typedef const X86DESCATTR *PCX86DESCATTR;
2071
2072
2073/**
2074 * Generic descriptor table entry
2075 */
2076#pragma pack(1)
2077typedef struct X86DESCGENERIC
2078{
2079 /** Limit - Low word. */
2080 unsigned u16LimitLow : 16;
2081 /** Base address - lowe word.
2082 * Don't try set this to 24 because MSC is doing stupid things then. */
2083 unsigned u16BaseLow : 16;
2084 /** Base address - first 8 bits of high word. */
2085 unsigned u8BaseHigh1 : 8;
2086 /** Segment Type. */
2087 unsigned u4Type : 4;
2088 /** Descriptor Type. System(=0) or code/data selector */
2089 unsigned u1DescType : 1;
2090 /** Descriptor Privelege level. */
2091 unsigned u2Dpl : 2;
2092 /** Flags selector present(=1) or not. */
2093 unsigned u1Present : 1;
2094 /** Segment limit 16-19. */
2095 unsigned u4LimitHigh : 4;
2096 /** Available for system software. */
2097 unsigned u1Available : 1;
2098 /** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2099 unsigned u1Long : 1;
2100 /** This flags meaning depends on the segment type. Try make sense out
2101 * of the intel manual yourself. */
2102 unsigned u1DefBig : 1;
2103 /** Granularity of the limit. If set 4KB granularity is used, if
2104 * clear byte. */
2105 unsigned u1Granularity : 1;
2106 /** Base address - highest 8 bits. */
2107 unsigned u8BaseHigh2 : 8;
2108} X86DESCGENERIC;
2109#pragma pack()
2110/** Pointer to a generic descriptor entry. */
2111typedef X86DESCGENERIC *PX86DESCGENERIC;
2112/** Pointer to a const generic descriptor entry. */
2113typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2114
2115/**
2116 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2117 */
2118typedef struct X86DESCGATE
2119{
2120 /** 00 - Target code segment offset - Low word.
2121 * Ignored if task-gate. */
2122 unsigned u16OffsetLow : 16;
2123 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2124 * TSS selector if task-gate. */
2125 unsigned u16Sel : 16;
2126 /** 20 - Number of parameters for a call-gate.
2127 * Ignored if interrupt-, trap- or task-gate. */
2128 unsigned u4ParmCount : 4;
2129 /** 24 - Reserved / ignored. */
2130 unsigned u4Reserved : 4;
2131 /** 28 - Segment Type. */
2132 unsigned u4Type : 4;
2133 /** 2c - Descriptor Type (0 = system). */
2134 unsigned u1DescType : 1;
2135 /** 2d - Descriptor Privelege level. */
2136 unsigned u2Dpl : 2;
2137 /** 2f - Flags selector present(=1) or not. */
2138 unsigned u1Present : 1;
2139 /** 30 - Target code segment offset - High word.
2140 * Ignored if task-gate. */
2141 unsigned u16OffsetHigh : 16;
2142} X86DESCGATE;
2143AssertCompileSize(X86DESCGATE, 8);
2144/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2145typedef X86DESCGATE *PX86DESCGATE;
2146/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2147typedef const X86DESCGATE *PCX86DESCGATE;
2148
2149/**
2150 * Descriptor table entry.
2151 */
2152#pragma pack(1)
2153typedef union X86DESC
2154{
2155 /** Generic descriptor view. */
2156 X86DESCGENERIC Gen;
2157 /** Gate descriptor view. */
2158 X86DESCGATE Gate;
2159
2160 /** 8 bit unsigned integer view. */
2161 uint8_t au8[8];
2162 /** 16 bit unsigned integer view. */
2163 uint16_t au16[4];
2164 /** 32 bit unsigned integer view. */
2165 uint32_t au32[2];
2166} X86DESC;
2167AssertCompileSize(X86DESC, 8);
2168#pragma pack()
2169/** Pointer to descriptor table entry. */
2170typedef X86DESC *PX86DESC;
2171/** Pointer to const descriptor table entry. */
2172typedef const X86DESC *PCX86DESC;
2173
2174/** @def X86DESC_BASE
2175 * Return the base address of a descriptor.
2176 */
2177#define X86DESC_BASE(desc) /*ASM-NOINC*/ \
2178 ( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2179 | ( (desc).Gen.u8BaseHigh1 << 16) \
2180 | ( (desc).Gen.u16BaseLow ) )
2181
2182/** @def X86DESC_LIMIT
2183 * Return the limit of a descriptor.
2184 */
2185#define X86DESC_LIMIT(desc) /*ASM-NOINC*/ \
2186 ( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2187 | ( (desc).Gen.u16LimitLow ) )
2188
2189/**
2190 * 64 bits generic descriptor table entry
2191 * Note: most of these bits have no meaning in long mode.
2192 */
2193#pragma pack(1)
2194typedef struct X86DESC64GENERIC
2195{
2196 /** Limit - Low word - *IGNORED*. */
2197 unsigned u16LimitLow : 16;
2198 /** Base address - lowe word. - *IGNORED*
2199 * Don't try set this to 24 because MSC is doing stupid things then. */
2200 unsigned u16BaseLow : 16;
2201 /** Base address - first 8 bits of high word. - *IGNORED* */
2202 unsigned u8BaseHigh1 : 8;
2203 /** Segment Type. */
2204 unsigned u4Type : 4;
2205 /** Descriptor Type. System(=0) or code/data selector */
2206 unsigned u1DescType : 1;
2207 /** Descriptor Privelege level. */
2208 unsigned u2Dpl : 2;
2209 /** Flags selector present(=1) or not. */
2210 unsigned u1Present : 1;
2211 /** Segment limit 16-19. - *IGNORED* */
2212 unsigned u4LimitHigh : 4;
2213 /** Available for system software. - *IGNORED* */
2214 unsigned u1Available : 1;
2215 /** Long mode flag. */
2216 unsigned u1Long : 1;
2217 /** This flags meaning depends on the segment type. Try make sense out
2218 * of the intel manual yourself. */
2219 unsigned u1DefBig : 1;
2220 /** Granularity of the limit. If set 4KB granularity is used, if
2221 * clear byte. - *IGNORED* */
2222 unsigned u1Granularity : 1;
2223 /** Base address - highest 8 bits. - *IGNORED* */
2224 unsigned u8BaseHigh2 : 8;
2225 /** Base address - bits 63-32. */
2226 unsigned u32BaseHigh3 : 32;
2227 unsigned u8Reserved : 8;
2228 unsigned u5Zeros : 5;
2229 unsigned u19Reserved : 19;
2230} X86DESC64GENERIC;
2231#pragma pack()
2232/** Pointer to a generic descriptor entry. */
2233typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2234/** Pointer to a const generic descriptor entry. */
2235typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2236
2237/**
2238 * System descriptor table entry (64 bits)
2239 *
2240 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2241 */
2242#pragma pack(1)
2243typedef struct X86DESC64SYSTEM
2244{
2245 /** Limit - Low word. */
2246 unsigned u16LimitLow : 16;
2247 /** Base address - lowe word.
2248 * Don't try set this to 24 because MSC is doing stupid things then. */
2249 unsigned u16BaseLow : 16;
2250 /** Base address - first 8 bits of high word. */
2251 unsigned u8BaseHigh1 : 8;
2252 /** Segment Type. */
2253 unsigned u4Type : 4;
2254 /** Descriptor Type. System(=0) or code/data selector */
2255 unsigned u1DescType : 1;
2256 /** Descriptor Privelege level. */
2257 unsigned u2Dpl : 2;
2258 /** Flags selector present(=1) or not. */
2259 unsigned u1Present : 1;
2260 /** Segment limit 16-19. */
2261 unsigned u4LimitHigh : 4;
2262 /** Available for system software. */
2263 unsigned u1Available : 1;
2264 /** Reserved - 0. */
2265 unsigned u1Reserved : 1;
2266 /** This flags meaning depends on the segment type. Try make sense out
2267 * of the intel manual yourself. */
2268 unsigned u1DefBig : 1;
2269 /** Granularity of the limit. If set 4KB granularity is used, if
2270 * clear byte. */
2271 unsigned u1Granularity : 1;
2272 /** Base address - bits 31-24. */
2273 unsigned u8BaseHigh2 : 8;
2274 /** Base address - bits 63-32. */
2275 unsigned u32BaseHigh3 : 32;
2276 unsigned u8Reserved : 8;
2277 unsigned u5Zeros : 5;
2278 unsigned u19Reserved : 19;
2279} X86DESC64SYSTEM;
2280#pragma pack()
2281/** Pointer to a system descriptor entry. */
2282typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2283/** Pointer to a const system descriptor entry. */
2284typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2285
2286/**
2287 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2288 */
2289typedef struct X86DESC64GATE
2290{
2291 /** Target code segment offset - Low word. */
2292 unsigned u16OffsetLow : 16;
2293 /** Target code segment selector. */
2294 unsigned u16Sel : 16;
2295 /** Interrupt stack table for interrupt- and trap-gates.
2296 * Ignored by call-gates. */
2297 unsigned u3IST : 3;
2298 /** Reserved / ignored. */
2299 unsigned u5Reserved : 5;
2300 /** Segment Type. */
2301 unsigned u4Type : 4;
2302 /** Descriptor Type (0 = system). */
2303 unsigned u1DescType : 1;
2304 /** Descriptor Privelege level. */
2305 unsigned u2Dpl : 2;
2306 /** Flags selector present(=1) or not. */
2307 unsigned u1Present : 1;
2308 /** Target code segment offset - High word.
2309 * Ignored if task-gate. */
2310 unsigned u16OffsetHigh : 16;
2311 /** Target code segment offset - Top dword.
2312 * Ignored if task-gate. */
2313 unsigned u32OffsetTop : 32;
2314 /** Reserved / ignored / must be zero.
2315 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2316 unsigned u32Reserved : 32;
2317} X86DESC64GATE;
2318AssertCompileSize(X86DESC64GATE, 16);
2319/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2320typedef X86DESC64GATE *PX86DESC64GATE;
2321/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2322typedef const X86DESC64GATE *PCX86DESC64GATE;
2323
2324
2325/**
2326 * Descriptor table entry.
2327 */
2328#pragma pack(1)
2329typedef union X86DESC64
2330{
2331 /** Generic descriptor view. */
2332 X86DESC64GENERIC Gen;
2333 /** System descriptor view. */
2334 X86DESC64SYSTEM System;
2335 /** Gate descriptor view. */
2336 X86DESC64GATE Gate;
2337
2338 /** 8 bit unsigned integer view. */
2339 uint8_t au8[16];
2340 /** 16 bit unsigned integer view. */
2341 uint16_t au16[8];
2342 /** 32 bit unsigned integer view. */
2343 uint32_t au32[4];
2344 /** 64 bit unsigned integer view. */
2345 uint64_t au64[2];
2346} X86DESC64;
2347AssertCompileSize(X86DESC64, 16);
2348#pragma pack()
2349/** Pointer to descriptor table entry. */
2350typedef X86DESC64 *PX86DESC64;
2351/** Pointer to const descriptor table entry. */
2352typedef const X86DESC64 *PCX86DESC64;
2353
2354/** @def X86DESC64_BASE
2355 * Return the base of a 64-bit descriptor.
2356 */
2357#define X86DESC64_BASE(desc) /*ASM-NOINC*/ \
2358 ( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2359 | ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2360 | ( (desc).Gen.u8BaseHigh1 << 16) \
2361 | ( (desc).Gen.u16BaseLow ) )
2362
2363
2364
2365/** @name Host system descriptor table entry - Use with care!
2366 * @{ */
2367/** Host system descriptor table entry. */
2368#if HC_ARCH_BITS == 64
2369typedef X86DESC64 X86DESCHC;
2370#else
2371typedef X86DESC X86DESCHC;
2372#endif
2373/** Pointer to a host system descriptor table entry. */
2374#if HC_ARCH_BITS == 64
2375typedef PX86DESC64 PX86DESCHC;
2376#else
2377typedef PX86DESC PX86DESCHC;
2378#endif
2379/** Pointer to a const host system descriptor table entry. */
2380#if HC_ARCH_BITS == 64
2381typedef PCX86DESC64 PCX86DESCHC;
2382#else
2383typedef PCX86DESC PCX86DESCHC;
2384#endif
2385/** @} */
2386
2387
2388/** @name Selector Descriptor Types.
2389 * @{
2390 */
2391
2392/** @name Non-System Selector Types.
2393 * @{ */
2394/** Code(=set)/Data(=clear) bit. */
2395#define X86_SEL_TYPE_CODE 8
2396/** Memory(=set)/System(=clear) bit. */
2397#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2398/** Accessed bit. */
2399#define X86_SEL_TYPE_ACCESSED 1
2400/** Expand down bit (for data selectors only). */
2401#define X86_SEL_TYPE_DOWN 4
2402/** Conforming bit (for code selectors only). */
2403#define X86_SEL_TYPE_CONF 4
2404/** Write bit (for data selectors only). */
2405#define X86_SEL_TYPE_WRITE 2
2406/** Read bit (for code selectors only). */
2407#define X86_SEL_TYPE_READ 2
2408
2409/** Read only selector type. */
2410#define X86_SEL_TYPE_RO 0
2411/** Accessed read only selector type. */
2412#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
2413/** Read write selector type. */
2414#define X86_SEL_TYPE_RW 2
2415/** Accessed read write selector type. */
2416#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
2417/** Expand down read only selector type. */
2418#define X86_SEL_TYPE_RO_DOWN 4
2419/** Accessed expand down read only selector type. */
2420#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
2421/** Expand down read write selector type. */
2422#define X86_SEL_TYPE_RW_DOWN 6
2423/** Accessed expand down read write selector type. */
2424#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
2425/** Execute only selector type. */
2426#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
2427/** Accessed execute only selector type. */
2428#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2429/** Execute and read selector type. */
2430#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
2431/** Accessed execute and read selector type. */
2432#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2433/** Conforming execute only selector type. */
2434#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
2435/** Accessed Conforming execute only selector type. */
2436#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2437/** Conforming execute and write selector type. */
2438#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
2439/** Accessed Conforming execute and write selector type. */
2440#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2441/** @} */
2442
2443
2444/** @name System Selector Types.
2445 * @{ */
2446/** Undefined system selector type. */
2447#define X86_SEL_TYPE_SYS_UNDEFINED 0
2448/** 286 TSS selector. */
2449#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2450/** LDT selector. */
2451#define X86_SEL_TYPE_SYS_LDT 2
2452/** 286 TSS selector - Busy. */
2453#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2454/** 286 Callgate selector. */
2455#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2456/** Taskgate selector. */
2457#define X86_SEL_TYPE_SYS_TASK_GATE 5
2458/** 286 Interrupt gate selector. */
2459#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2460/** 286 Trapgate selector. */
2461#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2462/** Undefined system selector. */
2463#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2464/** 386 TSS selector. */
2465#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2466/** Undefined system selector. */
2467#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2468/** 386 TSS selector - Busy. */
2469#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2470/** 386 Callgate selector. */
2471#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2472/** Undefined system selector. */
2473#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2474/** 386 Interruptgate selector. */
2475#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2476/** 386 Trapgate selector. */
2477#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2478/** @} */
2479
2480/** @name AMD64 System Selector Types.
2481 * @{ */
2482/** LDT selector. */
2483#define AMD64_SEL_TYPE_SYS_LDT 2
2484/** TSS selector - Busy. */
2485#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2486/** TSS selector - Busy. */
2487#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2488/** Callgate selector. */
2489#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2490/** Interruptgate selector. */
2491#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2492/** Trapgate selector. */
2493#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2494/** @} */
2495
2496/** @} */
2497
2498
2499/** @name Descriptor Table Entry Flag Masks.
2500 * These are for the 2nd 32-bit word of a descriptor.
2501 * @{ */
2502/** Bits 8-11 - TYPE - Descriptor type mask. */
2503#define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
2504/** Bit 12 - S - System (=0) or Code/Data (=1). */
2505#define X86_DESC_S RT_BIT(12)
2506/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2507#define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
2508/** Bit 15 - P - Present. */
2509#define X86_DESC_P RT_BIT(15)
2510/** Bit 20 - AVL - Available for system software. */
2511#define X86_DESC_AVL RT_BIT(20)
2512/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2513#define X86_DESC_DB RT_BIT(22)
2514/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2515 * used, if clear byte. */
2516#define X86_DESC_G RT_BIT(23)
2517/** @} */
2518
2519/** @} */
2520
2521
2522/** @name Task Segments.
2523 * @{
2524 */
2525
2526/**
2527 * 16-bit Task Segment (TSS).
2528 */
2529#pragma pack(1)
2530typedef struct X86TSS16
2531{
2532 /** Back link to previous task. (static) */
2533 RTSEL selPrev;
2534 /** Ring-0 stack pointer. (static) */
2535 uint16_t sp0;
2536 /** Ring-0 stack segment. (static) */
2537 RTSEL ss0;
2538 /** Ring-1 stack pointer. (static) */
2539 uint16_t sp1;
2540 /** Ring-1 stack segment. (static) */
2541 RTSEL ss1;
2542 /** Ring-2 stack pointer. (static) */
2543 uint16_t sp2;
2544 /** Ring-2 stack segment. (static) */
2545 RTSEL ss2;
2546 /** IP before task switch. */
2547 uint16_t ip;
2548 /** FLAGS before task switch. */
2549 uint16_t flags;
2550 /** AX before task switch. */
2551 uint16_t ax;
2552 /** CX before task switch. */
2553 uint16_t cx;
2554 /** DX before task switch. */
2555 uint16_t dx;
2556 /** BX before task switch. */
2557 uint16_t bx;
2558 /** SP before task switch. */
2559 uint16_t sp;
2560 /** BP before task switch. */
2561 uint16_t bp;
2562 /** SI before task switch. */
2563 uint16_t si;
2564 /** DI before task switch. */
2565 uint16_t di;
2566 /** ES before task switch. */
2567 RTSEL es;
2568 /** CS before task switch. */
2569 RTSEL cs;
2570 /** SS before task switch. */
2571 RTSEL ss;
2572 /** DS before task switch. */
2573 RTSEL ds;
2574 /** LDTR before task switch. */
2575 RTSEL selLdt;
2576} X86TSS16;
2577AssertCompileSize(X86TSS16, 44);
2578#pragma pack()
2579/** Pointer to a 16-bit task segment. */
2580typedef X86TSS16 *PX86TSS16;
2581/** Pointer to a const 16-bit task segment. */
2582typedef const X86TSS16 *PCX86TSS16;
2583
2584
2585/**
2586 * 32-bit Task Segment (TSS).
2587 */
2588#pragma pack(1)
2589typedef struct X86TSS32
2590{
2591 /** Back link to previous task. (static) */
2592 RTSEL selPrev;
2593 uint16_t padding1;
2594 /** Ring-0 stack pointer. (static) */
2595 uint32_t esp0;
2596 /** Ring-0 stack segment. (static) */
2597 RTSEL ss0;
2598 uint16_t padding_ss0;
2599 /** Ring-1 stack pointer. (static) */
2600 uint32_t esp1;
2601 /** Ring-1 stack segment. (static) */
2602 RTSEL ss1;
2603 uint16_t padding_ss1;
2604 /** Ring-2 stack pointer. (static) */
2605 uint32_t esp2;
2606 /** Ring-2 stack segment. (static) */
2607 RTSEL ss2;
2608 uint16_t padding_ss2;
2609 /** Page directory for the task. (static) */
2610 uint32_t cr3;
2611 /** EIP before task switch. */
2612 uint32_t eip;
2613 /** EFLAGS before task switch. */
2614 uint32_t eflags;
2615 /** EAX before task switch. */
2616 uint32_t eax;
2617 /** ECX before task switch. */
2618 uint32_t ecx;
2619 /** EDX before task switch. */
2620 uint32_t edx;
2621 /** EBX before task switch. */
2622 uint32_t ebx;
2623 /** ESP before task switch. */
2624 uint32_t esp;
2625 /** EBP before task switch. */
2626 uint32_t ebp;
2627 /** ESI before task switch. */
2628 uint32_t esi;
2629 /** EDI before task switch. */
2630 uint32_t edi;
2631 /** ES before task switch. */
2632 RTSEL es;
2633 uint16_t padding_es;
2634 /** CS before task switch. */
2635 RTSEL cs;
2636 uint16_t padding_cs;
2637 /** SS before task switch. */
2638 RTSEL ss;
2639 uint16_t padding_ss;
2640 /** DS before task switch. */
2641 RTSEL ds;
2642 uint16_t padding_ds;
2643 /** FS before task switch. */
2644 RTSEL fs;
2645 uint16_t padding_fs;
2646 /** GS before task switch. */
2647 RTSEL gs;
2648 uint16_t padding_gs;
2649 /** LDTR before task switch. */
2650 RTSEL selLdt;
2651 uint16_t padding_ldt;
2652 /** Debug trap flag */
2653 uint16_t fDebugTrap;
2654 /** Offset relative to the TSS of the start of the I/O Bitmap
2655 * and the end of the interrupt redirection bitmap. */
2656 uint16_t offIoBitmap;
2657 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2658 uint8_t IntRedirBitmap[32];
2659} X86TSS32;
2660#pragma pack()
2661/** Pointer to task segment. */
2662typedef X86TSS32 *PX86TSS32;
2663/** Pointer to const task segment. */
2664typedef const X86TSS32 *PCX86TSS32;
2665
2666
2667/**
2668 * 64-bit Task segment.
2669 */
2670#pragma pack(1)
2671typedef struct X86TSS64
2672{
2673 /** Reserved. */
2674 uint32_t u32Reserved;
2675 /** Ring-0 stack pointer. (static) */
2676 uint64_t rsp0;
2677 /** Ring-1 stack pointer. (static) */
2678 uint64_t rsp1;
2679 /** Ring-2 stack pointer. (static) */
2680 uint64_t rsp2;
2681 /** Reserved. */
2682 uint32_t u32Reserved2[2];
2683 /* IST */
2684 uint64_t ist1;
2685 uint64_t ist2;
2686 uint64_t ist3;
2687 uint64_t ist4;
2688 uint64_t ist5;
2689 uint64_t ist6;
2690 uint64_t ist7;
2691 /* Reserved. */
2692 uint16_t u16Reserved[5];
2693 /** Offset relative to the TSS of the start of the I/O Bitmap
2694 * and the end of the interrupt redirection bitmap. */
2695 uint16_t offIoBitmap;
2696 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2697 uint8_t IntRedirBitmap[32];
2698} X86TSS64;
2699#pragma pack()
2700/** Pointer to a 64-bit task segment. */
2701typedef X86TSS64 *PX86TSS64;
2702/** Pointer to a const 64-bit task segment. */
2703typedef const X86TSS64 *PCX86TSS64;
2704AssertCompileSize(X86TSS64, 136);
2705
2706/** @} */
2707
2708
2709/** @name Selectors.
2710 * @{
2711 */
2712
2713/**
2714 * The shift used to convert a selector from and to index an index (C).
2715 */
2716#define X86_SEL_SHIFT 3
2717
2718/**
2719 * The mask used to mask off the table indicator and CPL of an selector.
2720 */
2721#define X86_SEL_MASK 0xfff8
2722
2723/**
2724 * The bit indicating that a selector is in the LDT and not in the GDT.
2725 */
2726#define X86_SEL_LDT 0x0004
2727/**
2728 * The bit mask for getting the RPL of a selector.
2729 */
2730#define X86_SEL_RPL 0x0003
2731
2732/** @} */
2733
2734
2735/**
2736 * x86 Exceptions/Faults/Traps.
2737 */
2738typedef enum X86XCPT
2739{
2740 /** \#DE - Divide error. */
2741 X86_XCPT_DE = 0x00,
2742 /** \#DB - Debug event (single step, DRx, ..) */
2743 X86_XCPT_DB = 0x01,
2744 /** NMI - Non-Maskable Interrupt */
2745 X86_XCPT_NMI = 0x02,
2746 /** \#BP - Breakpoint (INT3). */
2747 X86_XCPT_BP = 0x03,
2748 /** \#OF - Overflow (INTO). */
2749 X86_XCPT_OF = 0x04,
2750 /** \#BR - Bound range exceeded (BOUND). */
2751 X86_XCPT_BR = 0x05,
2752 /** \#UD - Undefined opcode. */
2753 X86_XCPT_UD = 0x06,
2754 /** \#NM - Device not available (math coprocessor device). */
2755 X86_XCPT_NM = 0x07,
2756 /** \#DF - Double fault. */
2757 X86_XCPT_DF = 0x08,
2758 /** ??? - Coprocessor segment overrun (obsolete). */
2759 X86_XCPT_CO_SEG_OVERRUN = 0x09,
2760 /** \#TS - Taskswitch (TSS). */
2761 X86_XCPT_TS = 0x0a,
2762 /** \#NP - Segment no present. */
2763 X86_XCPT_NP = 0x0b,
2764 /** \#SS - Stack segment fault. */
2765 X86_XCPT_SS = 0x0c,
2766 /** \#GP - General protection fault. */
2767 X86_XCPT_GP = 0x0d,
2768 /** \#PF - Page fault. */
2769 X86_XCPT_PF = 0x0e,
2770 /* 0x0f is reserved. */
2771 /** \#MF - Math fault (FPU). */
2772 X86_XCPT_MF = 0x10,
2773 /** \#AC - Alignment check. */
2774 X86_XCPT_AC = 0x11,
2775 /** \#MC - Machine check. */
2776 X86_XCPT_MC = 0x12,
2777 /** \#XF - SIMD Floating-Pointer Exception. */
2778 X86_XCPT_XF = 0x13
2779} X86XCPT;
2780/** Pointer to a x86 exception code. */
2781typedef X86XCPT *PX86XCPT;
2782/** Pointer to a const x86 exception code. */
2783typedef const X86XCPT *PCX86XCPT;
2784
2785
2786/** @name Trap Error Codes
2787 * @{
2788 */
2789/** External indicator. */
2790#define X86_TRAP_ERR_EXTERNAL 1
2791/** IDT indicator. */
2792#define X86_TRAP_ERR_IDT 2
2793/** Descriptor table indicator - If set LDT, if clear GDT. */
2794#define X86_TRAP_ERR_TI 4
2795/** Mask for getting the selector. */
2796#define X86_TRAP_ERR_SEL_MASK 0xfff8
2797/** Shift for getting the selector table index (C type index). */
2798#define X86_TRAP_ERR_SEL_SHIFT 3
2799/** @} */
2800
2801
2802/** @name \#PF Trap Error Codes
2803 * @{
2804 */
2805/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2806#define X86_TRAP_PF_P RT_BIT(0)
2807/** Bit 1 - R/W - Read (clear) or write (set) access. */
2808#define X86_TRAP_PF_RW RT_BIT(1)
2809/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2810#define X86_TRAP_PF_US RT_BIT(2)
2811/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2812#define X86_TRAP_PF_RSVD RT_BIT(3)
2813/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2814#define X86_TRAP_PF_ID RT_BIT(4)
2815/** @} */
2816
2817#pragma pack(1)
2818/**
2819 * 32-bit IDTR/GDTR.
2820 */
2821typedef struct X86XDTR32
2822{
2823 /** Size of the descriptor table. */
2824 uint16_t cb;
2825 /** Address of the descriptor table. */
2826 uint32_t uAddr;
2827} X86XDTR32, *PX86XDTR32;
2828#pragma pack()
2829
2830#pragma pack(1)
2831/**
2832 * 64-bit IDTR/GDTR.
2833 */
2834typedef struct X86XDTR64
2835{
2836 /** Size of the descriptor table. */
2837 uint16_t cb;
2838 /** Address of the descriptor table. */
2839 uint64_t uAddr;
2840} X86XDTR64, *PX86XDTR64;
2841#pragma pack()
2842
2843/** @} */
2844
2845#endif
2846
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