Changeset 34328 in vbox
- Timestamp:
- Nov 24, 2010 2:33:57 PM (14 years ago)
- svn:sync-xref-src-repo-rev:
- 68087
- Location:
- trunk
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/x86.h
r33971 r34328 199 199 /** Bit 0 - SSE3 - Supports SSE3 or not. */ 200 200 unsigned u1SSE3 : 1; 201 /** Reserved. */202 unsigned u1 Reserved1: 1;201 /** Bit 1 - PCLMULQDQ. */ 202 unsigned u1PCLMULQDQ : 1; 203 203 /** Bit 2 - DS Area 64-bit layout. */ 204 204 unsigned u1DTE64 : 1; … … 219 219 /** Bit 10 - CNTX-ID - L1 Context ID. */ 220 220 unsigned u1CNTXID : 1; 221 /** Bit 11 - FMA. */ 221 /** Bit 11 - Reserved. */ 222 unsigned u1Reserved1 : 1; 223 /** Bit 12 - FMA. */ 222 224 unsigned u1FMA : 1; 223 /** Bit 12 - Reserved. */224 unsigned u1Reserved2 : 1;225 225 /** Bit 13 - CX16 - CMPXCHG16B. */ 226 226 unsigned u1CX16 : 1; … … 229 229 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */ 230 230 unsigned u1PDCM : 1; 231 /** Reserved. */ 232 unsigned u2Reserved3 : 2; 231 /** Bit 16 - Reserved. */ 232 unsigned u1Reserved2 : 1; 233 /** Bit 17 - PCID - Process-context identifiers. */ 234 unsigned u1PCID : 1; 233 235 /** Bit 18 - Direct Cache Access. */ 234 236 unsigned u1DCA : 1; … … 243 245 /** Bit 23 - POPCNT - Supports POPCNT. */ 244 246 unsigned u1POPCNT : 1; 245 /** Bit 24 - Reserved. */246 unsigned u1 Reserved4: 1;247 /** Bit 24 - TSC-Deadline. */ 248 unsigned u1TSCDEADLINE : 1; 247 249 /** Bit 25 - AES. */ 248 250 unsigned u1AES : 1; … … 251 253 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */ 252 254 unsigned u1OSXSAVE : 1; 253 /** Reserved. */ 254 unsigned u4Reserved5 : 4; 255 /** Bit 28 - AVX - Supports AVX instruction extensions. */ 256 unsigned u1AVX : 1; 257 /** Bit 29 - 30 - Reserved */ 258 unsigned u2Reserved3 : 2; 259 /** Reserved, always 0. */ 260 unsigned u1Reserved4 : 1; 255 261 } X86CPUIDFEATECX; 256 262 /** Pointer to CPUID Feature Information - ECX. */ … … 383 389 /** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */ 384 390 #define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15) 391 /** ECX Bit 17 - PCID - Process-context identifiers. */ 392 #define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17) 385 393 /** ECX Bit 18 - DCA - Direct Cache Access. */ 386 394 #define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18) … … 395 403 /** ECX Bit 23 - POPCNT instruction. */ 396 404 #define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23) 405 /** ECX Bir 24 - TSC-Deadline. */ 406 #define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24) 397 407 /** ECX Bit 25 - AES instructions. */ 398 408 #define X86_CPUID_FEATURE_ECX_AES RT_BIT(25) -
trunk/src/VBox/VMM/CPUM.cpp
r34326 r34328 2956 2956 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM"); 2957 2957 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16"); 2958 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");2958 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID"); 2959 2959 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA"); 2960 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4 _1");2961 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4 _2");2960 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1"); 2961 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2"); 2962 2962 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC"); 2963 2963 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE"); 2964 2964 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT"); 2965 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");2965 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL"); 2966 2966 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES"); 2967 2967 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE"); … … 2993 2993 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8); 2994 2994 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC); 2995 pHlp->pfnPrintf(pHlp, " Reserved= %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);2995 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1); 2996 2996 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP); 2997 2997 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR); … … 3003 3003 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN); 3004 3004 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH); 3005 pHlp->pfnPrintf(pHlp, " Reserved= %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);3005 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2); 3006 3006 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS); 3007 3007 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI); … … 3016 3016 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE); 3017 3017 3018 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not= %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);3019 pHlp->pfnPrintf(pHlp, " Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);3018 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3); 3019 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ); 3020 3020 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64); 3021 3021 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor); … … 3025 3025 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST); 3026 3026 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2); 3027 pHlp->pfnPrintf(pHlp, "Supp orts Supplemental SSE3 or not= %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);3027 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3); 3028 3028 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID); 3029 pHlp->pfnPrintf(pHlp, " FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);3030 pHlp->pfnPrintf(pHlp, " Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);3031 pHlp->pfnPrintf(pHlp, "CMPXCHG16B 3029 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1); 3030 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA); 3031 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16); 3032 3032 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate); 3033 3033 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM); 3034 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3); 3035 pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA); 3036 pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1); 3037 pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2); 3034 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2); 3035 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID); 3036 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA); 3037 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1); 3038 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2); 3038 3039 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC); 3039 pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE); 3040 pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT); 3041 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4); 3042 pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE); 3040 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE); 3041 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT); 3042 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE); 3043 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES); 3044 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE); 3043 3045 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE); 3044 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5); 3046 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX); 3047 pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3); 3048 pHlp->pfnPrintf(pHlp, "31 - Reserved (always 0) = %d (%d)\n", EcxGuest.u1Reserved4, EcxHost.u1Reserved4); 3045 3049 } 3046 3050 }
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