x86.h@ 11052

Last change on this file since 11052 was 10817, checked in by vboxsync, 16 years ago
Started with EPT support.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 83.6 KB

Line
1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	/*
31	* x86.mac is generated from this file using:
32	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33	*/
34
35	#ifndef ___VBox_x86_h
36	#define ___VBox_x86_h
37
38	#include <VBox/types.h>
39
40	/* Workaround for Solaris sys/regset.h defining CS, DS */
41	#if defined(RT_OS_SOLARIS)
42	# undef CS
43	# undef DS
44	#endif
45
46	/** @defgroup grp_x86 x86 Types and Definitions
47	* @{
48	*/
49
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104
105	/**
106	* EFLAGS.
107	*/
108	typedef union X86EFLAGS
109	{
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	/** The plain unsigned view. */
121	uint32_t u;
122	} X86EFLAGS;
123	/** Pointer to EFLAGS. */
124	typedef X86EFLAGS *PX86EFLAGS;
125	/** Pointer to const EFLAGS. */
126	typedef const X86EFLAGS *PCX86EFLAGS;
127
128	/**
129	* RFLAGS (32 upper bits are reserved).
130	*/
131	typedef union X86RFLAGS
132	{
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	/** The plain unsigned view. */
146	uint64_t u;
147	} X86RFLAGS;
148	/** Pointer to RFLAGS. */
149	typedef X86RFLAGS *PX86RFLAGS;
150	/** Pointer to const RFLAGS. */
151	typedef const X86RFLAGS *PCX86RFLAGS;
152
153
154	/** @name EFLAGS
155	* @{
156	*/
157	/** Bit 0 - CF - Carry flag - Status flag. */
158	#define X86_EFL_CF RT_BIT(0)
159	/** Bit 2 - PF - Parity flag - Status flag. */
160	#define X86_EFL_PF RT_BIT(2)
161	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
162	#define X86_EFL_AF RT_BIT(4)
163	/** Bit 6 - ZF - Zero flag - Status flag. */
164	#define X86_EFL_ZF RT_BIT(6)
165	/** Bit 7 - SF - Signed flag - Status flag. */
166	#define X86_EFL_SF RT_BIT(7)
167	/** Bit 8 - TF - Trap flag - System flag. */
168	#define X86_EFL_TF RT_BIT(8)
169	/** Bit 9 - IF - Interrupt flag - System flag. */
170	#define X86_EFL_IF RT_BIT(9)
171	/** Bit 10 - DF - Direction flag - Control flag. */
172	#define X86_EFL_DF RT_BIT(10)
173	/** Bit 11 - OF - Overflow flag - Status flag. */
174	#define X86_EFL_OF RT_BIT(11)
175	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
176	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
177	/** Bit 14 - NT - Nested task flag - System flag. */
178	#define X86_EFL_NT RT_BIT(14)
179	/** Bit 16 - RF - Resume flag - System flag. */
180	#define X86_EFL_RF RT_BIT(16)
181	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
182	#define X86_EFL_VM RT_BIT(17)
183	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
184	#define X86_EFL_AC RT_BIT(18)
185	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
186	#define X86_EFL_VIF RT_BIT(19)
187	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
188	#define X86_EFL_VIP RT_BIT(20)
189	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
190	#define X86_EFL_ID RT_BIT(21)
191	/** IOPL shift. */
192	#define X86_EFL_IOPL_SHIFT 12
193	/** The the IOPL level from the flags. */
194	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u2Reserved1 : 2;
207	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208	unsigned u1Monitor : 1;
209	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210	unsigned u1CPLDS : 1;
211	/** Bit 5 - VMX - Virtual Machine Technology. */
212	unsigned u1VMX : 1;
213	/** Reserved. */
214	unsigned u1Reserved2 : 1;
215	/** Bit 7 - EST - Enh. SpeedStep Tech. */
216	unsigned u1EST : 1;
217	/** Bit 8 - TM2 - Terminal Monitor 2. */
218	unsigned u1TM2 : 1;
219	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220	unsigned u1SSSE3 : 1;
221	/** Bit 10 - CNTX-ID - L1 Context ID. */
222	unsigned u1CNTXID : 1;
223	/** Reserved. */
224	unsigned u2Reserved4 : 2;
225	/** Bit 13 - CX16 - CMPXCHG16B. */
226	unsigned u1CX16 : 1;
227	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228	unsigned u1TPRUpdate : 1;
229	/** Reserved. */
230	unsigned u17Reserved5 : 17;
231
232	} X86CPUIDFEATECX;
233	/** Pointer to CPUID Feature Information - ECX. */
234	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235	/** Pointer to const CPUID Feature Information - ECX. */
236	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239	/** CPUID Feature Information - EDX.
240	* CPUID query with EAX=1.
241	*/
242	typedef struct X86CPUIDFEATEDX
243	{
244	/** Bit 0 - FPU - x87 FPU on Chip. */
245	unsigned u1FPU : 1;
246	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247	unsigned u1VME : 1;
248	/** Bit 2 - DE - Debugging extensions. */
249	unsigned u1DE : 1;
250	/** Bit 3 - PSE - Page Size Extension. */
251	unsigned u1PSE : 1;
252	/** Bit 4 - TSC - Time Stamp Counter. */
253	unsigned u1TSC : 1;
254	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255	unsigned u1MSR : 1;
256	/** Bit 6 - PAE - Physical Address Extension. */
257	unsigned u1PAE : 1;
258	/** Bit 7 - MCE - Machine Check Exception. */
259	unsigned u1MCE : 1;
260	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
261	unsigned u1CX8 : 1;
262	/** Bit 9 - APIC - APIC On-Chip. */
263	unsigned u1APIC : 1;
264	/** Bit 10 - Reserved. */
265	unsigned u1Reserved1 : 1;
266	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267	unsigned u1SEP : 1;
268	/** Bit 12 - MTRR - Memory Type Range Registers. */
269	unsigned u1MTRR : 1;
270	/** Bit 13 - PGE - PTE Global Bit. */
271	unsigned u1PGE : 1;
272	/** Bit 14 - MCA - Machine Check Architecture. */
273	unsigned u1MCA : 1;
274	/** Bit 15 - CMOV - Conditional Move Instructions. */
275	unsigned u1CMOV : 1;
276	/** Bit 16 - PAT - Page Attribute Table. */
277	unsigned u1PAT : 1;
278	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279	unsigned u1PSE36 : 1;
280	/** Bit 18 - PSN - Processor Serial Number. */
281	unsigned u1PSN : 1;
282	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
283	unsigned u1CLFSH : 1;
284	/** Bit 20 - Reserved. */
285	unsigned u1Reserved2 : 1;
286	/** Bit 21 - DS - Debug Store. */
287	unsigned u1DS : 1;
288	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289	unsigned u1ACPI : 1;
290	/** Bit 23 - MMX - Intel MMX 'Technology'. */
291	unsigned u1MMX : 1;
292	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293	unsigned u1FXSR : 1;
294	/** Bit 25 - SSE - SSE Support. */
295	unsigned u1SSE : 1;
296	/** Bit 26 - SSE2 - SSE2 Support. */
297	unsigned u1SSE2 : 1;
298	/** Bit 27 - SS - Self Snoop. */
299	unsigned u1SS : 1;
300	/** Bit 28 - HTT - Hyper-Threading Technology. */
301	unsigned u1HTT : 1;
302	/** Bit 29 - TM - Thermal Monitor. */
303	unsigned u1TM : 1;
304	/** Bit 30 - Reserved - . */
305	unsigned u1Reserved3 : 1;
306	/** Bit 31 - PBE - Pending Break Enabled. */
307	unsigned u1PBE : 1;
308	} X86CPUIDFEATEDX;
309	/** Pointer to CPUID Feature Information - EDX. */
310	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311	/** Pointer to const CPUID Feature Information - EDX. */
312	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314	/** @name CPUID Vendor information.
315	* CPUID query with EAX=0.
316	* @{
317	*/
318	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325	/** @} */
326
327
328	/** @name CPUID Feature information.
329	* CPUID query with EAX=1.
330	* @{
331	*/
332	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352	/** ECX Bit 23 - POPCOUNT instruction. */
353	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
354
355
356	/** Bit 0 - FPU - x87 FPU on Chip. */
357	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
358	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
359	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
360	/** Bit 2 - DE - Debugging extensions. */
361	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
362	/** Bit 3 - PSE - Page Size Extension. */
363	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
364	/** Bit 4 - TSC - Time Stamp Counter. */
365	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
366	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
367	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
368	/** Bit 6 - PAE - Physical Address Extension. */
369	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
370	/** Bit 7 - MCE - Machine Check Exception. */
371	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
372	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
373	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
374	/** Bit 9 - APIC - APIC On-Chip. */
375	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
376	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
377	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
378	/** Bit 12 - MTRR - Memory Type Range Registers. */
379	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
380	/** Bit 13 - PGE - PTE Global Bit. */
381	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
382	/** Bit 14 - MCA - Machine Check Architecture. */
383	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
384	/** Bit 15 - CMOV - Conditional Move Instructions. */
385	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
386	/** Bit 16 - PAT - Page Attribute Table. */
387	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
388	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
389	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
390	/** Bit 18 - PSN - Processor Serial Number. */
391	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
392	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
393	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
394	/** Bit 21 - DS - Debug Store. */
395	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
396	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
397	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
398	/** Bit 23 - MMX - Intel MMX Technology. */
399	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
400	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
401	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
402	/** Bit 25 - SSE - SSE Support. */
403	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
404	/** Bit 26 - SSE2 - SSE2 Support. */
405	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
406	/** Bit 27 - SS - Self Snoop. */
407	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
408	/** Bit 28 - HTT - Hyper-Threading Technology. */
409	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
410	/** Bit 29 - TM - Therm. Monitor. */
411	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
412	/** Bit 31 - PBE - Pending Break Enabled. */
413	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
414	/** @} */
415
416
417	/** @name CPUID AMD Feature information.
418	* CPUID query with EAX=0x80000001.
419	* @{
420	*/
421	/** Bit 0 - FPU - x87 FPU on Chip. */
422	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
423	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
424	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
425	/** Bit 2 - DE - Debugging extensions. */
426	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
427	/** Bit 3 - PSE - Page Size Extension. */
428	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
429	/** Bit 4 - TSC - Time Stamp Counter. */
430	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
431	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
432	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
433	/** Bit 6 - PAE - Physical Address Extension. */
434	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
435	/** Bit 7 - MCE - Machine Check Exception. */
436	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
437	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
438	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
439	/** Bit 9 - APIC - APIC On-Chip. */
440	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
441	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
442	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
443	/** Bit 12 - MTRR - Memory Type Range Registers. */
444	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
445	/** Bit 13 - PGE - PTE Global Bit. */
446	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
447	/** Bit 14 - MCA - Machine Check Architecture. */
448	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
449	/** Bit 15 - CMOV - Conditional Move Instructions. */
450	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
451	/** Bit 16 - PAT - Page Attribute Table. */
452	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
453	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
454	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
455	/** Bit 20 - NX - AMD No-Execute Page Protection. */
456	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
457	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
458	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
459	/** Bit 23 - MMX - Intel MMX Technology. */
460	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
461	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
462	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
463	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
464	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
465	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
466	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
467	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
468	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
469	/** Bit 29 - LM - AMD Long Mode. */
470	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
471	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
472	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
473	/** Bit 31 - 3DNOW - AMD 3DNow. */
474	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
475
476	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
477	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
478	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
479	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
480	/** Bit 2 - SVM - AMD VM extensions. */
481	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
482	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
483	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
484	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
485	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
486	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
487	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
488	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
490	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
491	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
492	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
493	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
494	/** Bit 9 - OSVW - AMD OS visible workaround. */
495	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
496	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
497	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
498	/** Bit 13 - WDT - AMD Watchdog timer support. */
499	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
500
501	/** @} */
502
503
504	/** @name CPUID AMD Feature information.
505	* CPUID query with EAX=0x80000007.
506	* @{
507	*/
508	/** Bit 0 - TS - Temperature Sensor. */
509	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
510	/** Bit 1 - FID - Frequency ID Control. */
511	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
512	/** Bit 2 - VID - Voltage ID Control. */
513	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
514	/** Bit 3 - TTP - THERMTRIP. */
515	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
516	/** Bit 4 - TM - Hardware Thermal Control. */
517	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
518	/** Bit 5 - STC - Software Thermal Control. */
519	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
520	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
521	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
522	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
523	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
524	/** Bit 8 - TSCINVAR - TSC Invariant. */
525	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
526	/** @} */
527
528
529	/** @name CR0
530	* @{ */
531	/** Bit 0 - PE - Protection Enabled */
532	#define X86_CR0_PE RT_BIT(0)
533	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
534	/** Bit 1 - MP - Monitor Coprocessor */
535	#define X86_CR0_MP RT_BIT(1)
536	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
537	/** Bit 2 - EM - Emulation. */
538	#define X86_CR0_EM RT_BIT(2)
539	#define X86_CR0_EMULATE_FPU RT_BIT(2)
540	/** Bit 3 - TS - Task Switch. */
541	#define X86_CR0_TS RT_BIT(3)
542	#define X86_CR0_TASK_SWITCH RT_BIT(3)
543	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
544	#define X86_CR0_ET RT_BIT(4)
545	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
546	/** Bit 5 - NE - Numeric error. */
547	#define X86_CR0_NE RT_BIT(5)
548	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
549	/** Bit 16 - WP - Write Protect. */
550	#define X86_CR0_WP RT_BIT(16)
551	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
552	/** Bit 18 - AM - Alignment Mask. */
553	#define X86_CR0_AM RT_BIT(18)
554	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
555	/** Bit 29 - NW - Not Write-though. */
556	#define X86_CR0_NW RT_BIT(29)
557	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
558	/** Bit 30 - WP - Cache Disable. */
559	#define X86_CR0_CD RT_BIT(30)
560	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
561	/** Bit 31 - PG - Paging. */
562	#define X86_CR0_PG RT_BIT(31)
563	#define X86_CR0_PAGING RT_BIT(31)
564	/** @} */
565
566
567	/** @name CR3
568	* @{ */
569	/** Bit 3 - PWT - Page-level Writes Transparent. */
570	#define X86_CR3_PWT RT_BIT(3)
571	/** Bit 4 - PCD - Page-level Cache Disable. */
572	#define X86_CR3_PCD RT_BIT(4)
573	/** Bits 12-31 - - Page directory page number. */
574	#define X86_CR3_PAGE_MASK (0xfffff000)
575	/** Bits 5-31 - - PAE Page directory page number. */
576	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
577	/** Bits 12-51 - - AMD64 Page directory page number. */
578	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
579	/** @} */
580
581
582	/** @name CR4
583	* @{ */
584	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
585	#define X86_CR4_VME RT_BIT(0)
586	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
587	#define X86_CR4_PVI RT_BIT(1)
588	/** Bit 2 - TSD - Time Stamp Disable. */
589	#define X86_CR4_TSD RT_BIT(2)
590	/** Bit 3 - DE - Debugging Extensions. */
591	#define X86_CR4_DE RT_BIT(3)
592	/** Bit 4 - PSE - Page Size Extension. */
593	#define X86_CR4_PSE RT_BIT(4)
594	/** Bit 5 - PAE - Physical Address Extension. */
595	#define X86_CR4_PAE RT_BIT(5)
596	/** Bit 6 - MCE - Machine-Check Enable. */
597	#define X86_CR4_MCE RT_BIT(6)
598	/** Bit 7 - PGE - Page Global Enable. */
599	#define X86_CR4_PGE RT_BIT(7)
600	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
601	#define X86_CR4_PCE RT_BIT(8)
602	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
603	#define X86_CR4_OSFSXR RT_BIT(9)
604	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
605	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
606	/** Bit 13 - VMXE - VMX mode is enabled. */
607	#define X86_CR4_VMXE RT_BIT(13)
608	/** @} */
609
610
611	/** @name DR6
612	* @{ */
613	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
614	#define X86_DR6_B0 RT_BIT(0)
615	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
616	#define X86_DR6_B1 RT_BIT(1)
617	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
618	#define X86_DR6_B2 RT_BIT(2)
619	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
620	#define X86_DR6_B3 RT_BIT(3)
621	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
622	#define X86_DR6_BD RT_BIT(13)
623	/** Bit 14 - BS - Single step */
624	#define X86_DR6_BS RT_BIT(14)
625	/** Bit 15 - BT - Task switch. (TSS T bit.) */
626	#define X86_DR6_BT RT_BIT(15)
627	/** @} */
628
629
630	/** @name DR7
631	* @{ */
632	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
633	#define X86_DR7_L0 RT_BIT(0)
634	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
635	#define X86_DR7_G0 RT_BIT(1)
636	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
637	#define X86_DR7_L1 RT_BIT(2)
638	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
639	#define X86_DR7_G1 RT_BIT(3)
640	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
641	#define X86_DR7_L2 RT_BIT(4)
642	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
643	#define X86_DR7_G2 RT_BIT(5)
644	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
645	#define X86_DR7_L3 RT_BIT(6)
646	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
647	#define X86_DR7_G3 RT_BIT(7)
648	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
649	#define X86_DR7_LE RT_BIT(8)
650	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
651	#define X86_DR7_GE RT_BIT(9)
652
653	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
654	* any DR register is accessed. */
655	#define X86_DR7_GD RT_BIT(13)
656	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
657	#define X86_DR7_RW0_MASK (3 << 16)
658	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
659	#define X86_DR7_LEN0_MASK (3 << 18)
660	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
661	#define X86_DR7_RW1_MASK (3 << 20)
662	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
663	#define X86_DR7_LEN1_MASK (3 << 22)
664	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
665	#define X86_DR7_RW2_MASK (3 << 24)
666	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
667	#define X86_DR7_LEN2_MASK (3 << 26)
668	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
669	#define X86_DR7_RW3_MASK (3 << 28)
670	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
671	#define X86_DR7_LEN3_MASK (3 << 30)
672
673	/** Bits which must be 1s. */
674	#define X86_DR7_MB1_MASK (RT_BIT(10))
675
676	/** Calcs the L bit of Nth breakpoint.
677	* @param iBp The breakpoint number [0..3].
678	*/
679	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
680
681	/** Calcs the G bit of Nth breakpoint.
682	* @param iBp The breakpoint number [0..3].
683	*/
684	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
685
686	/** @name Read/Write values.
687	* @{ */
688	/** Break on instruction fetch only. */
689	#define X86_DR7_RW_EO 0
690	/** Break on write only. */
691	#define X86_DR7_RW_WO 1
692	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
693	#define X86_DR7_RW_IO 2
694	/** Break on read or write (but not instruction fetches). */
695	#define X86_DR7_RW_RW 3
696	/** @} */
697
698	/** Shifts a X86_DR7_RW_* value to its right place.
699	* @param iBp The breakpoint number [0..3].
700	* @param fRw One of the X86_DR7_RW_* value.
701	*/
702	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
703
704	/** @name Length values.
705	* @{ */
706	#define X86_DR7_LEN_BYTE 0
707	#define X86_DR7_LEN_WORD 1
708	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
709	#define X86_DR7_LEN_DWORD 3
710	/** @} */
711
712	/** Shifts a X86_DR7_LEN_* value to its right place.
713	* @param iBp The breakpoint number [0..3].
714	* @param cb One of the X86_DR7_LEN_* values.
715	*/
716	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
717
718	/** Mask used to check if any breakpoints are enabled. */
719	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
720
721	/** @} */
722
723
724	/** @name Machine Specific Registers
725	* @{
726	*/
727
728	/** Time Stamp Counter. */
729	#define MSR_IA32_TSC 0x10
730
731	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
732	#define MSR_IA32_APICBASE 0x1b
733	#endif
734
735	/** CPU Feature control. */
736	#define MSR_IA32_FEATURE_CONTROL 0x3A
737	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
738	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
739
740	/** MTRR Capabilities. */
741	#define MSR_IA32_MTRR_CAP 0xFE
742
743
744	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
745	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
746	* R0 SS == CS + 8
747	* R3 CS == CS + 16
748	* R3 SS == CS + 24
749	*/
750	#define MSR_IA32_SYSENTER_CS 0x174
751	/** SYSENTER_ESP - the R0 ESP. */
752	#define MSR_IA32_SYSENTER_ESP 0x175
753	/** SYSENTER_EIP - the R0 EIP. */
754	#define MSR_IA32_SYSENTER_EIP 0x176
755	#endif
756
757	/** Machine Check Global Capabilities Register. */
758	#define MSR_IA32_MCP_CAP 0x179
759	/** Machine Check Global Status Register. */
760	#define MSR_IA32_MCP_STATUS 0x17A
761	/** Machine Check Global Control Register. */
762	#define MSR_IA32_MCP_CTRL 0x17B
763
764	/* Page Attribute Table. */
765	#define MSR_IA32_CR_PAT 0x277
766
767	/** MTRR Default Range. */
768	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
769
770	/** Basic VMX information. */
771	#define MSR_IA32_VMX_BASIC_INFO 0x480
772	/** Allowed settings for pin-based VM execution controls */
773	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
774	/** Allowed settings for proc-based VM execution controls */
775	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
776	/** Allowed settings for the VMX exit controls. */
777	#define MSR_IA32_VMX_EXIT_CTLS 0x483
778	/** Allowed settings for the VMX entry controls. */
779	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
780	/** Misc VMX info. */
781	#define MSR_IA32_VMX_MISC 0x485
782	/** Fixed cleared bits in CR0. */
783	#define MSR_IA32_VMX_CR0_FIXED0 0x486
784	/** Fixed set bits in CR0. */
785	#define MSR_IA32_VMX_CR0_FIXED1 0x487
786	/** Fixed cleared bits in CR4. */
787	#define MSR_IA32_VMX_CR4_FIXED0 0x488
788	/** Fixed set bits in CR4. */
789	#define MSR_IA32_VMX_CR4_FIXED1 0x489
790	/** Information for enumerating fields in the VMCS. */
791	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
792	/** Allowed settings for secondary proc-based VM execution controls */
793	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
794	/** EPT capabilities. */
795	#define MSR_IA32_VMX_EPT_CAPS 0x48C
796
797	/** K6 EFER - Extended Feature Enable Register. */
798	#define MSR_K6_EFER 0xc0000080
799	/** @todo document EFER */
800	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
801	#define MSR_K6_EFER_SCE RT_BIT(0)
802	/** Bit 8 - LME - Long mode enabled. (R/W) */
803	#define MSR_K6_EFER_LME RT_BIT(8)
804	/** Bit 10 - LMA - Long mode active. (R) */
805	#define MSR_K6_EFER_LMA RT_BIT(10)
806	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
807	#define MSR_K6_EFER_NXE RT_BIT(11)
808	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
809	#define MSR_K6_EFER_SVME RT_BIT(12)
810	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
811	#define MSR_K6_EFER_LMSLE RT_BIT(13)
812	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
813	#define MSR_K6_EFER_FFXSR RT_BIT(14)
814	/** K6 STAR - SYSCALL/RET targets. */
815	#define MSR_K6_STAR 0xc0000081
816	/** Shift value for getting the SYSRET CS and SS value. */
817	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
818	/** Shift value for getting the SYSCALL CS and SS value. */
819	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
820	/** Selector mask for use after shifting. */
821	#define MSR_K6_STAR_SEL_MASK 0xffff
822	/** The mask which give the SYSCALL EIP. */
823	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
824	/** K6 WHCR - Write Handling Control Register. */
825	#define MSR_K6_WHCR 0xc0000082
826	/** K6 UWCCR - UC/WC Cacheability Control Register. */
827	#define MSR_K6_UWCCR 0xc0000085
828	/** K6 PSOR - Processor State Observability Register. */
829	#define MSR_K6_PSOR 0xc0000087
830	/** K6 PFIR - Page Flush/Invalidate Register. */
831	#define MSR_K6_PFIR 0xc0000088
832
833	#define MSR_K7_EVNTSEL0 0xc0010000
834	#define MSR_K7_EVNTSEL1 0xc0010001
835	#define MSR_K7_EVNTSEL2 0xc0010002
836	#define MSR_K7_EVNTSEL3 0xc0010003
837	#define MSR_K7_PERFCTR0 0xc0010004
838	#define MSR_K7_PERFCTR1 0xc0010005
839	#define MSR_K7_PERFCTR2 0xc0010006
840	#define MSR_K7_PERFCTR3 0xc0010007
841
842	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
843	#define MSR_K8_LSTAR 0xc0000082
844	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
845	#define MSR_K8_CSTAR 0xc0000083
846	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
847	#define MSR_K8_SF_MASK 0xc0000084
848	/** K8 FS.base - The 64-bit base FS register. */
849	#define MSR_K8_FS_BASE 0xc0000100
850	/** K8 GS.base - The 64-bit base GS register. */
851	#define MSR_K8_GS_BASE 0xc0000101
852	/** K8 KernelGSbase - Used with SWAPGS. */
853	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
854	#define MSR_K8_TSC_AUX 0xc0000103
855	#define MSR_K8_SYSCFG 0xc0010010
856	#define MSR_K8_HWCR 0xc0010015
857	#define MSR_K8_IORRBASE0 0xc0010016
858	#define MSR_K8_IORRMASK0 0xc0010017
859	#define MSR_K8_IORRBASE1 0xc0010018
860	#define MSR_K8_IORRMASK1 0xc0010019
861	#define MSR_K8_TOP_MEM1 0xc001001a
862	#define MSR_K8_TOP_MEM2 0xc001001d
863	#define MSR_K8_VM_CR 0xc0010114
864	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
865
866	#define MSR_K8_IGNNE 0xc0010115
867	#define MSR_K8_SMM_CTL 0xc0010116
868	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
869	* host state during world switch.
870	*/
871	#define MSR_K8_VM_HSAVE_PA 0xc0010117
872
873	/** @} */
874
875
876	/** @name Page Table / Directory / Directory Pointers / L4.
877	* @{
878	*/
879
880	/** Page table/directory entry as an unsigned integer. */
881	typedef uint32_t X86PGUINT;
882	/** Pointer to a page table/directory table entry as an unsigned integer. */
883	typedef X86PGUINT *PX86PGUINT;
884
885	/** Number of entries in a 32-bit PT/PD. */
886	#define X86_PG_ENTRIES 1024
887
888
889	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
890	typedef uint64_t X86PGPAEUINT;
891	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
892	typedef X86PGPAEUINT *PX86PGPAEUINT;
893
894	/** Number of entries in a PAE PT/PD. */
895	#define X86_PG_PAE_ENTRIES 512
896	/** Number of entries in a PAE PDPT. */
897	#define X86_PG_PAE_PDPE_ENTRIES 4
898
899	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
900	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
901	/** Number of entries in an AMD64 PDPT.
902	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
903	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
904
905	/** The size of a 4KB page. */
906	#define X86_PAGE_4K_SIZE _4K
907	/** The page shift of a 4KB page. */
908	#define X86_PAGE_4K_SHIFT 12
909	/** The 4KB page offset mask. */
910	#define X86_PAGE_4K_OFFSET_MASK 0xfff
911	/** The 4KB page base mask for virtual addresses. */
912	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
913	/** The 4KB page base mask for virtual addresses - 32bit version. */
914	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
915
916	/** The size of a 2MB page. */
917	#define X86_PAGE_2M_SIZE _2M
918	/** The page shift of a 2MB page. */
919	#define X86_PAGE_2M_SHIFT 21
920	/** The 2MB page offset mask. */
921	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
922	/** The 2MB page base mask for virtual addresses. */
923	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
924	/** The 2MB page base mask for virtual addresses - 32bit version. */
925	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
926
927	/** The size of a 4MB page. */
928	#define X86_PAGE_4M_SIZE _4M
929	/** The page shift of a 4MB page. */
930	#define X86_PAGE_4M_SHIFT 22
931	/** The 4MB page offset mask. */
932	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
933	/** The 4MB page base mask for virtual addresses. */
934	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
935	/** The 4MB page base mask for virtual addresses - 32bit version. */
936	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
937
938
939
940	/** @name Page Table Entry
941	* @{
942	*/
943	/** Bit 0 - P - Present bit. */
944	#define X86_PTE_P RT_BIT(0)
945	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
946	#define X86_PTE_RW RT_BIT(1)
947	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
948	#define X86_PTE_US RT_BIT(2)
949	/** Bit 3 - PWT - Page level write thru bit. */
950	#define X86_PTE_PWT RT_BIT(3)
951	/** Bit 4 - PCD - Page level cache disable bit. */
952	#define X86_PTE_PCD RT_BIT(4)
953	/** Bit 5 - A - Access bit. */
954	#define X86_PTE_A RT_BIT(5)
955	/** Bit 6 - D - Dirty bit. */
956	#define X86_PTE_D RT_BIT(6)
957	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
958	#define X86_PTE_PAT RT_BIT(7)
959	/** Bit 8 - G - Global flag. */
960	#define X86_PTE_G RT_BIT(8)
961	/** Bits 9-11 - - Available for use to system software. */
962	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
963	/** Bits 12-31 - - Physical Page number of the next level. */
964	#define X86_PTE_PG_MASK ( 0xfffff000 )
965
966	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
967	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
968	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
969	/** @todo Get rid of the above hack; makes code unreadable. */
970	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
971	#else
972	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
973	#endif
974	/** Bits 63 - NX - PAE - No execution flag. */
975	#define X86_PTE_PAE_NX RT_BIT_64(63)
976
977	/**
978	* Page table entry.
979	*/
980	typedef struct X86PTEBITS
981	{
982	/** Flags whether(=1) or not the page is present. */
983	unsigned u1Present : 1;
984	/** Read(=0) / Write(=1) flag. */
985	unsigned u1Write : 1;
986	/** User(=1) / Supervisor (=0) flag. */
987	unsigned u1User : 1;
988	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
989	unsigned u1WriteThru : 1;
990	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
991	unsigned u1CacheDisable : 1;
992	/** Accessed flag.
993	* Indicates that the page have been read or written to. */
994	unsigned u1Accessed : 1;
995	/** Dirty flag.
996	* Indicates that the page have been written to. */
997	unsigned u1Dirty : 1;
998	/** Reserved / If PAT enabled, bit 2 of the index. */
999	unsigned u1PAT : 1;
1000	/** Global flag. (Ignored in all but final level.) */
1001	unsigned u1Global : 1;
1002	/** Available for use to system software. */
1003	unsigned u3Available : 3;
1004	/** Physical Page number of the next level. */
1005	unsigned u20PageNo : 20;
1006	} X86PTEBITS;
1007	/** Pointer to a page table entry. */
1008	typedef X86PTEBITS *PX86PTEBITS;
1009	/** Pointer to a const page table entry. */
1010	typedef const X86PTEBITS *PCX86PTEBITS;
1011
1012	/**
1013	* Page table entry.
1014	*/
1015	typedef union X86PTE
1016	{
1017	/** Bit field view. */
1018	X86PTEBITS n;
1019	/** Unsigned integer view */
1020	X86PGUINT u;
1021	/** 32-bit view. */
1022	uint32_t au32[1];
1023	/** 16-bit view. */
1024	uint16_t au16[2];
1025	/** 8-bit view. */
1026	uint8_t au8[4];
1027	} X86PTE;
1028	/** Pointer to a page table entry. */
1029	typedef X86PTE *PX86PTE;
1030	/** Pointer to a const page table entry. */
1031	typedef const X86PTE *PCX86PTE;
1032
1033
1034	/**
1035	* PAE page table entry.
1036	*/
1037	typedef struct X86PTEPAEBITS
1038	{
1039	/** Flags whether(=1) or not the page is present. */
1040	uint32_t u1Present : 1;
1041	/** Read(=0) / Write(=1) flag. */
1042	uint32_t u1Write : 1;
1043	/** User(=1) / Supervisor(=0) flag. */
1044	uint32_t u1User : 1;
1045	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1046	uint32_t u1WriteThru : 1;
1047	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1048	uint32_t u1CacheDisable : 1;
1049	/** Accessed flag.
1050	* Indicates that the page have been read or written to. */
1051	uint32_t u1Accessed : 1;
1052	/** Dirty flag.
1053	* Indicates that the page have been written to. */
1054	uint32_t u1Dirty : 1;
1055	/** Reserved / If PAT enabled, bit 2 of the index. */
1056	uint32_t u1PAT : 1;
1057	/** Global flag. (Ignored in all but final level.) */
1058	uint32_t u1Global : 1;
1059	/** Available for use to system software. */
1060	uint32_t u3Available : 3;
1061	/** Physical Page number of the next level - Low Part. Don't use this. */
1062	uint32_t u20PageNoLow : 20;
1063	/** Physical Page number of the next level - High Part. Don't use this. */
1064	uint32_t u20PageNoHigh : 20;
1065	/** MBZ bits */
1066	uint32_t u11Reserved : 11;
1067	/** No Execute flag. */
1068	uint32_t u1NoExecute : 1;
1069	} X86PTEPAEBITS;
1070	/** Pointer to a page table entry. */
1071	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1072	/** Pointer to a page table entry. */
1073	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1074
1075	/**
1076	* PAE Page table entry.
1077	*/
1078	typedef union X86PTEPAE
1079	{
1080	/** Bit field view. */
1081	X86PTEPAEBITS n;
1082	/** Unsigned integer view */
1083	X86PGPAEUINT u;
1084	/** 32-bit view. */
1085	uint32_t au32[2];
1086	/** 16-bit view. */
1087	uint16_t au16[4];
1088	/** 8-bit view. */
1089	uint8_t au8[8];
1090	} X86PTEPAE;
1091	/** Pointer to a PAE page table entry. */
1092	typedef X86PTEPAE *PX86PTEPAE;
1093	/** Pointer to a const PAE page table entry. */
1094	typedef const X86PTEPAE *PCX86PTEPAE;
1095	/** @} */
1096
1097	/**
1098	* Page table.
1099	*/
1100	typedef struct X86PT
1101	{
1102	/** PTE Array. */
1103	X86PTE a[X86_PG_ENTRIES];
1104	} X86PT;
1105	/** Pointer to a page table. */
1106	typedef X86PT *PX86PT;
1107	/** Pointer to a const page table. */
1108	typedef const X86PT *PCX86PT;
1109
1110	/** The page shift to get the PT index. */
1111	#define X86_PT_SHIFT 12
1112	/** The PT index mask (apply to a shifted page address). */
1113	#define X86_PT_MASK 0x3ff
1114
1115
1116	/**
1117	* Page directory.
1118	*/
1119	typedef struct X86PTPAE
1120	{
1121	/** PTE Array. */
1122	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1123	} X86PTPAE;
1124	/** Pointer to a page table. */
1125	typedef X86PTPAE *PX86PTPAE;
1126	/** Pointer to a const page table. */
1127	typedef const X86PTPAE *PCX86PTPAE;
1128
1129	/** The page shift to get the PA PTE index. */
1130	#define X86_PT_PAE_SHIFT 12
1131	/** The PAE PT index mask (apply to a shifted page address). */
1132	#define X86_PT_PAE_MASK 0x1ff
1133
1134
1135	/** @name 4KB Page Directory Entry
1136	* @{
1137	*/
1138	/** Bit 0 - P - Present bit. */
1139	#define X86_PDE_P RT_BIT(0)
1140	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1141	#define X86_PDE_RW RT_BIT(1)
1142	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1143	#define X86_PDE_US RT_BIT(2)
1144	/** Bit 3 - PWT - Page level write thru bit. */
1145	#define X86_PDE_PWT RT_BIT(3)
1146	/** Bit 4 - PCD - Page level cache disable bit. */
1147	#define X86_PDE_PCD RT_BIT(4)
1148	/** Bit 5 - A - Access bit. */
1149	#define X86_PDE_A RT_BIT(5)
1150	/** Bit 7 - PS - Page size attribute.
1151	* Clear mean 4KB pages, set means large pages (2/4MB). */
1152	#define X86_PDE_PS RT_BIT(7)
1153	/** Bits 9-11 - - Available for use to system software. */
1154	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1155	/** Bits 12-31 - - Physical Page number of the next level. */
1156	#define X86_PDE_PG_MASK ( 0xfffff000 )
1157
1158	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1159	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1160	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1161	* we partly or that part into shadow page table entries. Will be corrected
1162	* soon.
1163	*/
1164	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1165	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1166	#else
1167	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1168	#endif
1169	/** Bits 63 - NX - PAE - No execution flag. */
1170	#define X86_PDE_PAE_NX RT_BIT_64(63)
1171
1172	/**
1173	* Page directory entry.
1174	*/
1175	typedef struct X86PDEBITS
1176	{
1177	/** Flags whether(=1) or not the page is present. */
1178	unsigned u1Present : 1;
1179	/** Read(=0) / Write(=1) flag. */
1180	unsigned u1Write : 1;
1181	/** User(=1) / Supervisor (=0) flag. */
1182	unsigned u1User : 1;
1183	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1184	unsigned u1WriteThru : 1;
1185	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1186	unsigned u1CacheDisable : 1;
1187	/** Accessed flag.
1188	* Indicates that the page have been read or written to. */
1189	unsigned u1Accessed : 1;
1190	/** Reserved / Ignored (dirty bit). */
1191	unsigned u1Reserved0 : 1;
1192	/** Size bit if PSE is enabled - in any event it's 0. */
1193	unsigned u1Size : 1;
1194	/** Reserved / Ignored (global bit). */
1195	unsigned u1Reserved1 : 1;
1196	/** Available for use to system software. */
1197	unsigned u3Available : 3;
1198	/** Physical Page number of the next level. */
1199	unsigned u20PageNo : 20;
1200	} X86PDEBITS;
1201	/** Pointer to a page directory entry. */
1202	typedef X86PDEBITS *PX86PDEBITS;
1203	/** Pointer to a const page directory entry. */
1204	typedef const X86PDEBITS *PCX86PDEBITS;
1205
1206
1207	/**
1208	* PAE page directory entry.
1209	*/
1210	typedef struct X86PDEPAEBITS
1211	{
1212	/** Flags whether(=1) or not the page is present. */
1213	uint32_t u1Present : 1;
1214	/** Read(=0) / Write(=1) flag. */
1215	uint32_t u1Write : 1;
1216	/** User(=1) / Supervisor (=0) flag. */
1217	uint32_t u1User : 1;
1218	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1219	uint32_t u1WriteThru : 1;
1220	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1221	uint32_t u1CacheDisable : 1;
1222	/** Accessed flag.
1223	* Indicates that the page have been read or written to. */
1224	uint32_t u1Accessed : 1;
1225	/** Reserved / Ignored (dirty bit). */
1226	uint32_t u1Reserved0 : 1;
1227	/** Size bit if PSE is enabled - in any event it's 0. */
1228	uint32_t u1Size : 1;
1229	/** Reserved / Ignored (global bit). / */
1230	uint32_t u1Reserved1 : 1;
1231	/** Available for use to system software. */
1232	uint32_t u3Available : 3;
1233	/** Physical Page number of the next level - Low Part. Don't use! */
1234	uint32_t u20PageNoLow : 20;
1235	/** Physical Page number of the next level - High Part. Don't use! */
1236	uint32_t u20PageNoHigh : 20;
1237	/** MBZ bits */
1238	uint32_t u11Reserved : 11;
1239	/** No Execute flag. */
1240	uint32_t u1NoExecute : 1;
1241	} X86PDEPAEBITS;
1242	/** Pointer to a page directory entry. */
1243	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1244	/** Pointer to a const page directory entry. */
1245	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1246
1247	/** @} */
1248
1249
1250	/** @name 2/4MB Page Directory Entry
1251	* @{
1252	*/
1253	/** Bit 0 - P - Present bit. */
1254	#define X86_PDE4M_P RT_BIT(0)
1255	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1256	#define X86_PDE4M_RW RT_BIT(1)
1257	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1258	#define X86_PDE4M_US RT_BIT(2)
1259	/** Bit 3 - PWT - Page level write thru bit. */
1260	#define X86_PDE4M_PWT RT_BIT(3)
1261	/** Bit 4 - PCD - Page level cache disable bit. */
1262	#define X86_PDE4M_PCD RT_BIT(4)
1263	/** Bit 5 - A - Access bit. */
1264	#define X86_PDE4M_A RT_BIT(5)
1265	/** Bit 6 - D - Dirty bit. */
1266	#define X86_PDE4M_D RT_BIT(6)
1267	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1268	#define X86_PDE4M_PS RT_BIT(7)
1269	/** Bit 8 - G - Global flag. */
1270	#define X86_PDE4M_G RT_BIT(8)
1271	/** Bits 9-11 - AVL - Available for use to system software. */
1272	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1273	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1274	#define X86_PDE4M_PAT RT_BIT(12)
1275	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1276	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1277	/** Bits 22-31 - - Physical Page number. */
1278	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1279	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1280	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1281	/** The number of bits to the high part of the page number. */
1282	#define X86_PDE4M_PG_HIGH_SHIFT 19
1283
1284	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1285	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1286	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1287	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1288	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1289
1290	/**
1291	* 4MB page directory entry.
1292	*/
1293	typedef struct X86PDE4MBITS
1294	{
1295	/** Flags whether(=1) or not the page is present. */
1296	unsigned u1Present : 1;
1297	/** Read(=0) / Write(=1) flag. */
1298	unsigned u1Write : 1;
1299	/** User(=1) / Supervisor (=0) flag. */
1300	unsigned u1User : 1;
1301	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1302	unsigned u1WriteThru : 1;
1303	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1304	unsigned u1CacheDisable : 1;
1305	/** Accessed flag.
1306	* Indicates that the page have been read or written to. */
1307	unsigned u1Accessed : 1;
1308	/** Dirty flag.
1309	* Indicates that the page have been written to. */
1310	unsigned u1Dirty : 1;
1311	/** Page size flag - always 1 for 4MB entries. */
1312	unsigned u1Size : 1;
1313	/** Global flag. */
1314	unsigned u1Global : 1;
1315	/** Available for use to system software. */
1316	unsigned u3Available : 3;
1317	/** Reserved / If PAT enabled, bit 2 of the index. */
1318	unsigned u1PAT : 1;
1319	/** Bits 32-39 of the page number on AMD64.
1320	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1321	unsigned u8PageNoHigh : 8;
1322	/** Reserved. */
1323	unsigned u1Reserved : 1;
1324	/** Physical Page number of the page. */
1325	unsigned u10PageNo : 10;
1326	} X86PDE4MBITS;
1327	/** Pointer to a page table entry. */
1328	typedef X86PDE4MBITS *PX86PDE4MBITS;
1329	/** Pointer to a const page table entry. */
1330	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1331
1332
1333	/**
1334	* 2MB PAE page directory entry.
1335	*/
1336	typedef struct X86PDE2MPAEBITS
1337	{
1338	/** Flags whether(=1) or not the page is present. */
1339	uint32_t u1Present : 1;
1340	/** Read(=0) / Write(=1) flag. */
1341	uint32_t u1Write : 1;
1342	/** User(=1) / Supervisor(=0) flag. */
1343	uint32_t u1User : 1;
1344	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1345	uint32_t u1WriteThru : 1;
1346	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1347	uint32_t u1CacheDisable : 1;
1348	/** Accessed flag.
1349	* Indicates that the page have been read or written to. */
1350	uint32_t u1Accessed : 1;
1351	/** Dirty flag.
1352	* Indicates that the page have been written to. */
1353	uint32_t u1Dirty : 1;
1354	/** Page size flag - always 1 for 2MB entries. */
1355	uint32_t u1Size : 1;
1356	/** Global flag. */
1357	uint32_t u1Global : 1;
1358	/** Available for use to system software. */
1359	uint32_t u3Available : 3;
1360	/** Reserved / If PAT enabled, bit 2 of the index. */
1361	uint32_t u1PAT : 1;
1362	/** Reserved. */
1363	uint32_t u9Reserved : 9;
1364	/** Physical Page number of the next level - Low part. Don't use! */
1365	uint32_t u10PageNoLow : 10;
1366	/** Physical Page number of the next level - High part. Don't use! */
1367	uint32_t u20PageNoHigh : 20;
1368	/** MBZ bits */
1369	uint32_t u11Reserved : 11;
1370	/** No Execute flag. */
1371	uint32_t u1NoExecute : 1;
1372	} X86PDE2MPAEBITS;
1373	/** Pointer to a 4MB PAE page table entry. */
1374	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1375	/** Pointer to a 4MB PAE page table entry. */
1376	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1377
1378	/** @} */
1379
1380	/**
1381	* Page directory entry.
1382	*/
1383	typedef union X86PDE
1384	{
1385	/** Normal view. */
1386	X86PDEBITS n;
1387	/** 4MB view (big). */
1388	X86PDE4MBITS b;
1389	/** Unsigned integer view. */
1390	X86PGUINT u;
1391	/** 8 bit unsigned integer view. */
1392	uint8_t au8[4];
1393	/** 16 bit unsigned integer view. */
1394	uint16_t au16[2];
1395	/** 32 bit unsigned integer view. */
1396	uint32_t au32[1];
1397	} X86PDE;
1398	/** Pointer to a page directory entry. */
1399	typedef X86PDE *PX86PDE;
1400	/** Pointer to a const page directory entry. */
1401	typedef const X86PDE *PCX86PDE;
1402
1403	/**
1404	* PAE page directory entry.
1405	*/
1406	typedef union X86PDEPAE
1407	{
1408	/** Normal view. */
1409	X86PDEPAEBITS n;
1410	/** 2MB page view (big). */
1411	X86PDE2MPAEBITS b;
1412	/** Unsigned integer view. */
1413	X86PGPAEUINT u;
1414	/** 8 bit unsigned integer view. */
1415	uint8_t au8[8];
1416	/** 16 bit unsigned integer view. */
1417	uint16_t au16[4];
1418	/** 32 bit unsigned integer view. */
1419	uint32_t au32[2];
1420	} X86PDEPAE;
1421	/** Pointer to a page directory entry. */
1422	typedef X86PDEPAE *PX86PDEPAE;
1423	/** Pointer to a const page directory entry. */
1424	typedef const X86PDEPAE *PCX86PDEPAE;
1425
1426	/**
1427	* Page directory.
1428	*/
1429	typedef struct X86PD
1430	{
1431	/** PDE Array. */
1432	X86PDE a[X86_PG_ENTRIES];
1433	} X86PD;
1434	/** Pointer to a page directory. */
1435	typedef X86PD *PX86PD;
1436	/** Pointer to a const page directory. */
1437	typedef const X86PD *PCX86PD;
1438
1439	/** The page shift to get the PD index. */
1440	#define X86_PD_SHIFT 22
1441	/** The PD index mask (apply to a shifted page address). */
1442	#define X86_PD_MASK 0x3ff
1443
1444
1445	/**
1446	* PAE page directory.
1447	*/
1448	typedef struct X86PDPAE
1449	{
1450	/** PDE Array. */
1451	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1452	} X86PDPAE;
1453	/** Pointer to a PAE page directory. */
1454	typedef X86PDPAE *PX86PDPAE;
1455	/** Pointer to a const PAE page directory. */
1456	typedef const X86PDPAE *PCX86PDPAE;
1457
1458	/** The page shift to get the PAE PD index. */
1459	#define X86_PD_PAE_SHIFT 21
1460	/** The PAE PD index mask (apply to a shifted page address). */
1461	#define X86_PD_PAE_MASK 0x1ff
1462
1463
1464	/** @name Page Directory Pointer Table Entry (PAE)
1465	* @{
1466	*/
1467	/** Bit 0 - P - Present bit. */
1468	#define X86_PDPE_P RT_BIT(0)
1469	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1470	#define X86_PDPE_RW RT_BIT(1)
1471	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1472	#define X86_PDPE_US RT_BIT(2)
1473	/** Bit 3 - PWT - Page level write thru bit. */
1474	#define X86_PDPE_PWT RT_BIT(3)
1475	/** Bit 4 - PCD - Page level cache disable bit. */
1476	#define X86_PDPE_PCD RT_BIT(4)
1477	/** Bit 5 - A - Access bit. Long Mode only. */
1478	#define X86_PDPE_A RT_BIT(5)
1479	/** Bits 9-11 - - Available for use to system software. */
1480	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1481	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1482	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1483	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1484	/** @todo Get rid of the above hack; makes code unreadable. */
1485	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1486	#else
1487	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1488	#endif
1489	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1490	#define X86_PDPE_NX RT_BIT_64(63)
1491
1492	/**
1493	* Page directory pointer table entry.
1494	*/
1495	typedef struct X86PDPEBITS
1496	{
1497	/** Flags whether(=1) or not the page is present. */
1498	uint32_t u1Present : 1;
1499	/** Chunk of reserved bits. */
1500	uint32_t u2Reserved : 2;
1501	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1502	uint32_t u1WriteThru : 1;
1503	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1504	uint32_t u1CacheDisable : 1;
1505	/** Chunk of reserved bits. */
1506	uint32_t u4Reserved : 4;
1507	/** Available for use to system software. */
1508	uint32_t u3Available : 3;
1509	/** Physical Page number of the next level - Low Part. Don't use! */
1510	uint32_t u20PageNoLow : 20;
1511	/** Physical Page number of the next level - High Part. Don't use! */
1512	uint32_t u20PageNoHigh : 20;
1513	/** MBZ bits */
1514	uint32_t u12Reserved : 12;
1515	} X86PDPEBITS;
1516	/** Pointer to a page directory pointer table entry. */
1517	typedef X86PDPEBITS *PX86PTPEBITS;
1518	/** Pointer to a const page directory pointer table entry. */
1519	typedef const X86PDPEBITS *PCX86PTPEBITS;
1520
1521	/**
1522	* Page directory pointer table entry. AMD64 version
1523	*/
1524	typedef struct X86PDPEAMD64BITS
1525	{
1526	/** Flags whether(=1) or not the page is present. */
1527	uint32_t u1Present : 1;
1528	/** Read(=0) / Write(=1) flag. */
1529	uint32_t u1Write : 1;
1530	/** User(=1) / Supervisor (=0) flag. */
1531	uint32_t u1User : 1;
1532	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1533	uint32_t u1WriteThru : 1;
1534	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1535	uint32_t u1CacheDisable : 1;
1536	/** Accessed flag.
1537	* Indicates that the page have been read or written to. */
1538	uint32_t u1Accessed : 1;
1539	/** Chunk of reserved bits. */
1540	uint32_t u3Reserved : 3;
1541	/** Available for use to system software. */
1542	uint32_t u3Available : 3;
1543	/** Physical Page number of the next level - Low Part. Don't use! */
1544	uint32_t u20PageNoLow : 20;
1545	/** Physical Page number of the next level - High Part. Don't use! */
1546	uint32_t u20PageNoHigh : 20;
1547	/** MBZ bits */
1548	uint32_t u11Reserved : 11;
1549	/** No Execute flag. */
1550	uint32_t u1NoExecute : 1;
1551	} X86PDPEAMD64BITS;
1552	/** Pointer to a page directory pointer table entry. */
1553	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1554	/** Pointer to a const page directory pointer table entry. */
1555	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1556
1557	/**
1558	* Page directory pointer table entry.
1559	*/
1560	typedef union X86PDPE
1561	{
1562	/** Normal view. */
1563	X86PDPEBITS n;
1564	/** AMD64 view. */
1565	X86PDPEAMD64BITS lm;
1566	/** Unsigned integer view. */
1567	X86PGPAEUINT u;
1568	/** 8 bit unsigned integer view. */
1569	uint8_t au8[8];
1570	/** 16 bit unsigned integer view. */
1571	uint16_t au16[4];
1572	/** 32 bit unsigned integer view. */
1573	uint32_t au32[2];
1574	} X86PDPE;
1575	/** Pointer to a page directory pointer table entry. */
1576	typedef X86PDPE *PX86PDPE;
1577	/** Pointer to a const page directory pointer table entry. */
1578	typedef const X86PDPE *PCX86PDPE;
1579
1580
1581	/**
1582	* Page directory pointer table.
1583	*/
1584	typedef struct X86PDPT
1585	{
1586	/** PDE Array. */
1587	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1588	} X86PDPT;
1589	/** Pointer to a page directory pointer table. */
1590	typedef X86PDPT *PX86PDPT;
1591	/** Pointer to a const page directory pointer table. */
1592	typedef const X86PDPT *PCX86PDPT;
1593
1594	/** The page shift to get the PDPT index. */
1595	#define X86_PDPT_SHIFT 30
1596	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1597	#define X86_PDPT_MASK_PAE 0x3
1598	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1599	#define X86_PDPT_MASK_AMD64 0x1ff
1600
1601	/** @} */
1602
1603
1604	/** @name Page Map Level-4 Entry (Long Mode PAE)
1605	* @{
1606	*/
1607	/** Bit 0 - P - Present bit. */
1608	#define X86_PML4E_P RT_BIT(0)
1609	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1610	#define X86_PML4E_RW RT_BIT(1)
1611	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1612	#define X86_PML4E_US RT_BIT(2)
1613	/** Bit 3 - PWT - Page level write thru bit. */
1614	#define X86_PML4E_PWT RT_BIT(3)
1615	/** Bit 4 - PCD - Page level cache disable bit. */
1616	#define X86_PML4E_PCD RT_BIT(4)
1617	/** Bit 5 - A - Access bit. */
1618	#define X86_PML4E_A RT_BIT(5)
1619	/** Bits 9-11 - - Available for use to system software. */
1620	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1621	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1622	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1623	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1624	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1625	#else
1626	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1627	#endif
1628	/** Bits 63 - NX - PAE - No execution flag. */
1629	#define X86_PML4E_NX RT_BIT_64(63)
1630
1631	/**
1632	* Page Map Level-4 Entry
1633	*/
1634	typedef struct X86PML4EBITS
1635	{
1636	/** Flags whether(=1) or not the page is present. */
1637	uint32_t u1Present : 1;
1638	/** Read(=0) / Write(=1) flag. */
1639	uint32_t u1Write : 1;
1640	/** User(=1) / Supervisor (=0) flag. */
1641	uint32_t u1User : 1;
1642	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1643	uint32_t u1WriteThru : 1;
1644	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1645	uint32_t u1CacheDisable : 1;
1646	/** Accessed flag.
1647	* Indicates that the page have been read or written to. */
1648	uint32_t u1Accessed : 1;
1649	/** Chunk of reserved bits. */
1650	uint32_t u3Reserved : 3;
1651	/** Available for use to system software. */
1652	uint32_t u3Available : 3;
1653	/** Physical Page number of the next level - Low Part. Don't use! */
1654	uint32_t u20PageNoLow : 20;
1655	/** Physical Page number of the next level - High Part. Don't use! */
1656	uint32_t u20PageNoHigh : 20;
1657	/** MBZ bits */
1658	uint32_t u11Reserved : 11;
1659	/** No Execute flag. */
1660	uint32_t u1NoExecute : 1;
1661	} X86PML4EBITS;
1662	/** Pointer to a page map level-4 entry. */
1663	typedef X86PML4EBITS *PX86PML4EBITS;
1664	/** Pointer to a const page map level-4 entry. */
1665	typedef const X86PML4EBITS *PCX86PML4EBITS;
1666
1667	/**
1668	* Page Map Level-4 Entry.
1669	*/
1670	typedef union X86PML4E
1671	{
1672	/** Normal view. */
1673	X86PML4EBITS n;
1674	/** Unsigned integer view. */
1675	X86PGPAEUINT u;
1676	/** 8 bit unsigned integer view. */
1677	uint8_t au8[8];
1678	/** 16 bit unsigned integer view. */
1679	uint16_t au16[4];
1680	/** 32 bit unsigned integer view. */
1681	uint32_t au32[2];
1682	} X86PML4E;
1683	/** Pointer to a page map level-4 entry. */
1684	typedef X86PML4E *PX86PML4E;
1685	/** Pointer to a const page map level-4 entry. */
1686	typedef const X86PML4E *PCX86PML4E;
1687
1688
1689	/**
1690	* Page Map Level-4.
1691	*/
1692	typedef struct X86PML4
1693	{
1694	/** PDE Array. */
1695	X86PML4E a[X86_PG_PAE_ENTRIES];
1696	} X86PML4;
1697	/** Pointer to a page map level-4. */
1698	typedef X86PML4 *PX86PML4;
1699	/** Pointer to a const page map level-4. */
1700	typedef const X86PML4 *PCX86PML4;
1701
1702	/** The page shift to get the PML4 index. */
1703	#define X86_PML4_SHIFT 39
1704	/** The PML4 index mask (apply to a shifted page address). */
1705	#define X86_PML4_MASK 0x1ff
1706
1707	/** @} */
1708
1709	/** @} */
1710
1711
1712	/**
1713	* 80-bit MMX/FPU register type.
1714	*/
1715	typedef struct X86FPUMMX
1716	{
1717	uint8_t reg[10];
1718	} X86FPUMMX;
1719	/** Pointer to a 80-bit MMX/FPU register type. */
1720	typedef X86FPUMMX *PX86FPUMMX;
1721	/** Pointer to a const 80-bit MMX/FPU register type. */
1722	typedef const X86FPUMMX *PCX86FPUMMX;
1723
1724	/**
1725	* FPU state (aka FSAVE/FRSTOR Memory Region).
1726	*/
1727	#pragma pack(1)
1728	typedef struct X86FPUSTATE
1729	{
1730	/** Control word. */
1731	uint16_t FCW;
1732	/** Alignment word */
1733	uint16_t Dummy1;
1734	/** Status word. */
1735	uint16_t FSW;
1736	/** Alignment word */
1737	uint16_t Dummy2;
1738	/** Tag word */
1739	uint16_t FTW;
1740	/** Alignment word */
1741	uint16_t Dummy3;
1742
1743	/** Instruction pointer. */
1744	uint32_t FPUIP;
1745	/** Code selector. */
1746	uint16_t CS;
1747	/** Opcode. */
1748	uint16_t FOP;
1749	/** FOO. */
1750	uint32_t FPUOO;
1751	/** FOS. */
1752	uint32_t FPUOS;
1753	/** FPU view - todo. */
1754	X86FPUMMX regs[8];
1755	} X86FPUSTATE;
1756	#pragma pack()
1757	/** Pointer to a FPU state. */
1758	typedef X86FPUSTATE *PX86FPUSTATE;
1759	/** Pointer to a const FPU state. */
1760	typedef const X86FPUSTATE *PCX86FPUSTATE;
1761
1762	/**
1763	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1764	*/
1765	#pragma pack(1)
1766	typedef struct X86FXSTATE
1767	{
1768	/** Control word. */
1769	uint16_t FCW;
1770	/** Status word. */
1771	uint16_t FSW;
1772	/** Tag word (it's a byte actually). */
1773	uint8_t FTW;
1774	uint8_t huh1;
1775	/** Opcode. */
1776	uint16_t FOP;
1777	/** Instruction pointer. */
1778	uint32_t FPUIP;
1779	/** Code selector. */
1780	uint16_t CS;
1781	uint16_t Rsvrd1;
1782	/* - offset 16 - */
1783	/** Data pointer. */
1784	uint32_t FPUDP;
1785	/** Data segment */
1786	uint16_t DS;
1787	uint16_t Rsrvd2;
1788	uint32_t MXCSR;
1789	uint32_t MXCSR_MASK;
1790	/* - offset 32 - */
1791	union
1792	{
1793	/** MMX view. */
1794	uint64_t mmx;
1795	/** FPU view - todo. */
1796	X86FPUMMX fpu;
1797	/** 8-bit view. */
1798	uint8_t au8[16];
1799	/** 16-bit view. */
1800	uint16_t au16[8];
1801	/** 32-bit view. */
1802	uint32_t au32[4];
1803	/** 64-bit view. */
1804	uint64_t au64[2];
1805	/** 128-bit view. (yeah, very helpful) */
1806	uint128_t au128[1];
1807	} aRegs[8];
1808	/* - offset 160 - */
1809	union
1810	{
1811	/** XMM Register view . /
1812	uint128_t xmm;
1813	/** 8-bit view. */
1814	uint8_t au8[16];
1815	/** 16-bit view. */
1816	uint16_t au16[8];
1817	/** 32-bit view. */
1818	uint32_t au32[4];
1819	/** 64-bit view. */
1820	uint64_t au64[2];
1821	/** 128-bit view. (yeah, very helpful) */
1822	uint128_t au128[1];
1823	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1824	/* - offset 416 - */
1825	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1826	} X86FXSTATE;
1827	#pragma pack()
1828	/** Pointer to a FPU Extended state. */
1829	typedef X86FXSTATE *PX86FXSTATE;
1830	/** Pointer to a const FPU Extended state. */
1831	typedef const X86FXSTATE *PCX86FXSTATE;
1832
1833
1834	/** @name Selector Descriptor
1835	* @{
1836	*/
1837
1838	/**
1839	* Generic descriptor table entry
1840	*/
1841	#pragma pack(1)
1842	typedef struct X86DESCGENERIC
1843	{
1844	/** Limit - Low word. */
1845	unsigned u16LimitLow : 16;
1846	/** Base address - lowe word.
1847	* Don't try set this to 24 because MSC is doing studing things then. */
1848	unsigned u16BaseLow : 16;
1849	/** Base address - first 8 bits of high word. */
1850	unsigned u8BaseHigh1 : 8;
1851	/** Segment Type. */
1852	unsigned u4Type : 4;
1853	/** Descriptor Type. System(=0) or code/data selector */
1854	unsigned u1DescType : 1;
1855	/** Descriptor Privelege level. */
1856	unsigned u2Dpl : 2;
1857	/** Flags selector present(=1) or not. */
1858	unsigned u1Present : 1;
1859	/** Segment limit 16-19. */
1860	unsigned u4LimitHigh : 4;
1861	/** Available for system software. */
1862	unsigned u1Available : 1;
1863	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1864	unsigned u1Long : 1;
1865	/** This flags meaning depends on the segment type. Try make sense out
1866	* of the intel manual yourself. */
1867	unsigned u1DefBig : 1;
1868	/** Granularity of the limit. If set 4KB granularity is used, if
1869	* clear byte. */
1870	unsigned u1Granularity : 1;
1871	/** Base address - highest 8 bits. */
1872	unsigned u8BaseHigh2 : 8;
1873	} X86DESCGENERIC;
1874	#pragma pack()
1875	/** Pointer to a generic descriptor entry. */
1876	typedef X86DESCGENERIC *PX86DESCGENERIC;
1877	/** Pointer to a const generic descriptor entry. */
1878	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1879
1880
1881	/**
1882	* Descriptor attributes.
1883	*/
1884	typedef struct X86DESCATTRBITS
1885	{
1886	/** Segment Type. */
1887	unsigned u4Type : 4;
1888	/** Descriptor Type. System(=0) or code/data selector */
1889	unsigned u1DescType : 1;
1890	/** Descriptor Privelege level. */
1891	unsigned u2Dpl : 2;
1892	/** Flags selector present(=1) or not. */
1893	unsigned u1Present : 1;
1894	/** Segment limit 16-19. */
1895	unsigned u4LimitHigh : 4;
1896	/** Available for system software. */
1897	unsigned u1Available : 1;
1898	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1899	unsigned u1Long : 1;
1900	/** This flags meaning depends on the segment type. Try make sense out
1901	* of the intel manual yourself. */
1902	unsigned u1DefBig : 1;
1903	/** Granularity of the limit. If set 4KB granularity is used, if
1904	* clear byte. */
1905	unsigned u1Granularity : 1;
1906	} X86DESCATTRBITS;
1907
1908
1909	#pragma pack(1)
1910	typedef union X86DESCATTR
1911	{
1912	/** Normal view. */
1913	X86DESCATTRBITS n;
1914	/** Unsigned integer view. */
1915	uint32_t u;
1916	} X86DESCATTR;
1917	#pragma pack()
1918
1919	/** Pointer to descriptor attributes. */
1920	typedef X86DESCATTR *PX86DESCATTR;
1921	/** Pointer to const descriptor attributes. */
1922	typedef const X86DESCATTR *PCX86DESCATTR;
1923
1924
1925	/**
1926	* Descriptor table entry.
1927	*/
1928	#pragma pack(1)
1929	typedef union X86DESC
1930	{
1931	/** Generic descriptor view. */
1932	X86DESCGENERIC Gen;
1933	#if 0
1934	/** IDT view. */
1935	VBOXIDTE Idt;
1936	#endif
1937
1938	/** 8 bit unsigned interger view. */
1939	uint8_t au8[8];
1940	/** 16 bit unsigned interger view. */
1941	uint16_t au16[4];
1942	/** 32 bit unsigned interger view. */
1943	uint32_t au32[2];
1944	} X86DESC;
1945	#pragma pack()
1946	/** Pointer to descriptor table entry. */
1947	typedef X86DESC *PX86DESC;
1948	/** Pointer to const descriptor table entry. */
1949	typedef const X86DESC *PCX86DESC;
1950
1951
1952	/** @def X86DESC_BASE
1953	* Return the base address of a descriptor.
1954	*/
1955	#define X86DESC_BASE(desc) \
1956	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
1957	\| ( (desc).Gen.u8BaseHigh1 << 16) \
1958	\| ( (desc).Gen.u16BaseLow ) )
1959
1960	/** @def X86DESC_LIMIT
1961	* Return the limit of a descriptor.
1962	*/
1963	#define X86DESC_LIMIT(desc) \
1964	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
1965	\| ( (desc).Gen.u16LimitLow ) )
1966
1967	/**
1968	* 64 bits generic descriptor table entry
1969	* Note: most of these bits have no meaning in long mode.
1970	*/
1971	#pragma pack(1)
1972	typedef struct X86DESC64GENERIC
1973	{
1974	/** Limit - Low word - IGNORED. */
1975	unsigned u16LimitLow : 16;
1976	/** Base address - lowe word. - IGNORED
1977	* Don't try set this to 24 because MSC is doing studing things then. */
1978	unsigned u16BaseLow : 16;
1979	/** Base address - first 8 bits of high word. - IGNORED */
1980	unsigned u8BaseHigh1 : 8;
1981	/** Segment Type. */
1982	unsigned u4Type : 4;
1983	/** Descriptor Type. System(=0) or code/data selector */
1984	unsigned u1DescType : 1;
1985	/** Descriptor Privelege level. */
1986	unsigned u2Dpl : 2;
1987	/** Flags selector present(=1) or not. */
1988	unsigned u1Present : 1;
1989	/** Segment limit 16-19. - IGNORED */
1990	unsigned u4LimitHigh : 4;
1991	/** Available for system software. - IGNORED */
1992	unsigned u1Available : 1;
1993	/** Long mode flag. */
1994	unsigned u1Long : 1;
1995	/** This flags meaning depends on the segment type. Try make sense out
1996	* of the intel manual yourself. */
1997	unsigned u1DefBig : 1;
1998	/** Granularity of the limit. If set 4KB granularity is used, if
1999	* clear byte. - IGNORED */
2000	unsigned u1Granularity : 1;
2001	/** Base address - highest 8 bits. - IGNORED */
2002	unsigned u8BaseHigh2 : 8;
2003	/** Base address - bits 63-32. */
2004	unsigned u32BaseHigh3 : 32;
2005	unsigned u8Reserved : 8;
2006	unsigned u5Zeros : 5;
2007	unsigned u19Reserved : 19;
2008	} X86DESC64GENERIC;
2009	#pragma pack()
2010	/** Pointer to a generic descriptor entry. */
2011	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2012	/** Pointer to a const generic descriptor entry. */
2013	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2014
2015	/**
2016	* System descriptor table entry (64 bits)
2017	*/
2018	#pragma pack(1)
2019	typedef struct X86DESC64SYSTEM
2020	{
2021	/** Limit - Low word. */
2022	unsigned u16LimitLow : 16;
2023	/** Base address - lowe word.
2024	* Don't try set this to 24 because MSC is doing studing things then. */
2025	unsigned u16BaseLow : 16;
2026	/** Base address - first 8 bits of high word. */
2027	unsigned u8BaseHigh1 : 8;
2028	/** Segment Type. */
2029	unsigned u4Type : 4;
2030	/** Descriptor Type. System(=0) or code/data selector */
2031	unsigned u1DescType : 1;
2032	/** Descriptor Privelege level. */
2033	unsigned u2Dpl : 2;
2034	/** Flags selector present(=1) or not. */
2035	unsigned u1Present : 1;
2036	/** Segment limit 16-19. */
2037	unsigned u4LimitHigh : 4;
2038	/** Available for system software. */
2039	unsigned u1Available : 1;
2040	/** Reserved - 0. */
2041	unsigned u1Reserved : 1;
2042	/** This flags meaning depends on the segment type. Try make sense out
2043	* of the intel manual yourself. */
2044	unsigned u1DefBig : 1;
2045	/** Granularity of the limit. If set 4KB granularity is used, if
2046	* clear byte. */
2047	unsigned u1Granularity : 1;
2048	/** Base address - bits 31-24. */
2049	unsigned u8BaseHigh2 : 8;
2050	/** Base address - bits 63-32. */
2051	unsigned u32BaseHigh3 : 32;
2052	unsigned u8Reserved : 8;
2053	unsigned u5Zeros : 5;
2054	unsigned u19Reserved : 19;
2055	} X86DESC64SYSTEM;
2056	#pragma pack()
2057	/** Pointer to a generic descriptor entry. */
2058	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2059	/** Pointer to a const generic descriptor entry. */
2060	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2061
2062
2063	/**
2064	* Descriptor table entry.
2065	*/
2066	#pragma pack(1)
2067	typedef union X86DESC64
2068	{
2069	/** Generic descriptor view. */
2070	X86DESC64GENERIC Gen;
2071	/** System descriptor view. */
2072	X86DESC64SYSTEM System;
2073	#if 0
2074	X86DESC64GATE Gate;
2075	#endif
2076
2077	/** 8 bit unsigned interger view. */
2078	uint8_t au8[16];
2079	/** 16 bit unsigned interger view. */
2080	uint16_t au16[8];
2081	/** 32 bit unsigned interger view. */
2082	uint32_t au32[4];
2083	/** 64 bit unsigned interger view. */
2084	uint64_t au64[2];
2085	} X86DESC64;
2086	#pragma pack()
2087	/** Pointer to descriptor table entry. */
2088	typedef X86DESC64 *PX86DESC64;
2089	/** Pointer to const descriptor table entry. */
2090	typedef const X86DESC64 *PCX86DESC64;
2091
2092	#if HC_ARCH_BITS == 64
2093	typedef X86DESC64 X86DESCHC;
2094	typedef X86DESC64 *PX86DESCHC;
2095	#else
2096	typedef X86DESC X86DESCHC;
2097	typedef X86DESC *PX86DESCHC;
2098	#endif
2099
2100	/** @def X86DESC_LIMIT
2101	* Return the base of a 64-bit descriptor.
2102	*/
2103	#define X86DESC64_BASE(desc) \
2104	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2105	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2106	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2107	\| ( (desc).Gen.u16BaseLow ) )
2108
2109
2110	/** @name Selector Descriptor Types.
2111	* @{
2112	*/
2113
2114	/** @name Non-System Selector Types.
2115	* @{ */
2116	/** Code(=set)/Data(=clear) bit. */
2117	#define X86_SEL_TYPE_CODE 8
2118	/** Memory(=set)/System(=clear) bit. */
2119	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2120	/** Accessed bit. */
2121	#define X86_SEL_TYPE_ACCESSED 1
2122	/** Expand down bit (for data selectors only). */
2123	#define X86_SEL_TYPE_DOWN 4
2124	/** Conforming bit (for code selectors only). */
2125	#define X86_SEL_TYPE_CONF 4
2126	/** Write bit (for data selectors only). */
2127	#define X86_SEL_TYPE_WRITE 2
2128	/** Read bit (for code selectors only). */
2129	#define X86_SEL_TYPE_READ 2
2130
2131	/** Read only selector type. */
2132	#define X86_SEL_TYPE_RO 0
2133	/** Accessed read only selector type. */
2134	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2135	/** Read write selector type. */
2136	#define X86_SEL_TYPE_RW 2
2137	/** Accessed read write selector type. */
2138	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2139	/** Expand down read only selector type. */
2140	#define X86_SEL_TYPE_RO_DOWN 4
2141	/** Accessed expand down read only selector type. */
2142	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2143	/** Expand down read write selector type. */
2144	#define X86_SEL_TYPE_RW_DOWN 6
2145	/** Accessed expand down read write selector type. */
2146	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2147	/** Execute only selector type. */
2148	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2149	/** Accessed execute only selector type. */
2150	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2151	/** Execute and read selector type. */
2152	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2153	/** Accessed execute and read selector type. */
2154	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2155	/** Conforming execute only selector type. */
2156	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2157	/** Accessed Conforming execute only selector type. */
2158	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2159	/** Conforming execute and write selector type. */
2160	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2161	/** Accessed Conforming execute and write selector type. */
2162	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2163	/** @} */
2164
2165
2166	/** @name System Selector Types.
2167	* @{ */
2168	/** Undefined system selector type. */
2169	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2170	/** 286 TSS selector. */
2171	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2172	/** LDT selector. */
2173	#define X86_SEL_TYPE_SYS_LDT 2
2174	/** 286 TSS selector - Busy. */
2175	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2176	/** 286 Callgate selector. */
2177	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2178	/** Taskgate selector. */
2179	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2180	/** 286 Interrupt gate selector. */
2181	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2182	/** 286 Trapgate selector. */
2183	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2184	/** Undefined system selector. */
2185	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2186	/** 386 TSS selector. */
2187	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2188	/** Undefined system selector. */
2189	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2190	/** 386 TSS selector - Busy. */
2191	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2192	/** 386 Callgate selector. */
2193	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2194	/** Undefined system selector. */
2195	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2196	/** 386 Interruptgate selector. */
2197	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2198	/** 386 Trapgate selector. */
2199	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2200	/** @} */
2201
2202	/** @name AMD64 System Selector Types.
2203	* @{ */
2204	#define AMD64_SEL_TYPE_SYS_LDT 2
2205	/** 286 TSS selector - Busy. */
2206	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2207	/** 386 TSS selector - Busy. */
2208	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2209	/** 386 Callgate selector. */
2210	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2211	/** 386 Interruptgate selector. */
2212	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2213	/** 386 Trapgate selector. */
2214	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2215	/** @} */
2216
2217	/** @} */
2218
2219
2220	/** @name Descriptor Table Entry Flag Masks.
2221	* These are for the 2nd 32-bit word of a descriptor.
2222	* @{ */
2223	/** Bits 8-11 - TYPE - Descriptor type mask. */
2224	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2225	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2226	#define X86_DESC_S RT_BIT(12)
2227	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2228	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2229	/** Bit 15 - P - Present. */
2230	#define X86_DESC_P RT_BIT(15)
2231	/** Bit 20 - AVL - Available for system software. */
2232	#define X86_DESC_AVL RT_BIT(20)
2233	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2234	#define X86_DESC_DB RT_BIT(22)
2235	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2236	* used, if clear byte. */
2237	#define X86_DESC_G RT_BIT(23)
2238	/** @} */
2239
2240	/** @} */
2241
2242
2243	/** @name Selectors.
2244	* @{
2245	*/
2246
2247	/**
2248	* The shift used to convert a selector from and to index an index (C).
2249	*/
2250	#define X86_SEL_SHIFT 3
2251
2252	/**
2253	* The shift used to convert a selector from and to index an index (C).
2254	*/
2255	#define AMD64_SEL_SHIFT 4
2256
2257	#if HC_ARCH_BITS == 64
2258	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2259	#else
2260	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2261	#endif
2262
2263	/**
2264	* The mask used to mask off the table indicator and CPL of an selector.
2265	*/
2266	#define X86_SEL_MASK 0xfff8
2267
2268	/**
2269	* The bit indicating that a selector is in the LDT and not in the GDT.
2270	*/
2271	#define X86_SEL_LDT 0x0004
2272	/**
2273	* The bit mask for getting the RPL of a selector.
2274	*/
2275	#define X86_SEL_RPL 0x0003
2276
2277	/** @} */
2278
2279
2280	/**
2281	* x86 Exceptions/Faults/Traps.
2282	*/
2283	typedef enum X86XCPT
2284	{
2285	/** \#DE - Divide error. */
2286	X86_XCPT_DE = 0x00,
2287	/** \#DB - Debug event (single step, DRx, ..) */
2288	X86_XCPT_DB = 0x01,
2289	/** NMI - Non-Maskable Interrupt */
2290	X86_XCPT_NMI = 0x02,
2291	/** \#BP - Breakpoint (INT3). */
2292	X86_XCPT_BP = 0x03,
2293	/** \#OF - Overflow (INTO). */
2294	X86_XCPT_OF = 0x04,
2295	/** \#BR - Bound range exceeded (BOUND). */
2296	X86_XCPT_BR = 0x05,
2297	/** \#UD - Undefined opcode. */
2298	X86_XCPT_UD = 0x06,
2299	/** \#NM - Device not available (math coprocessor device). */
2300	X86_XCPT_NM = 0x07,
2301	/** \#DF - Double fault. */
2302	X86_XCPT_DF = 0x08,
2303	/** ??? - Coprocessor segment overrun (obsolete). */
2304	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2305	/** \#TS - Taskswitch (TSS). */
2306	X86_XCPT_TS = 0x0a,
2307	/** \#NP - Segment no present. */
2308	X86_XCPT_NP = 0x0b,
2309	/** \#SS - Stack segment fault. */
2310	X86_XCPT_SS = 0x0c,
2311	/** \#GP - General protection fault. */
2312	X86_XCPT_GP = 0x0d,
2313	/** \#PF - Page fault. */
2314	X86_XCPT_PF = 0x0e,
2315	/* 0x0f is reserved. */
2316	/** \#MF - Math fault (FPU). */
2317	X86_XCPT_MF = 0x10,
2318	/** \#AC - Alignment check. */
2319	X86_XCPT_AC = 0x11,
2320	/** \#MC - Machine check. */
2321	X86_XCPT_MC = 0x12,
2322	/** \#XF - SIMD Floating-Pointer Exception. */
2323	X86_XCPT_XF = 0x13
2324	} X86XCPT;
2325	/** Pointer to a x86 exception code. */
2326	typedef X86XCPT *PX86XCPT;
2327	/** Pointer to a const x86 exception code. */
2328	typedef const X86XCPT *PCX86XCPT;
2329
2330
2331	/** @name Trap Error Codes
2332	* @{
2333	*/
2334	/** External indicator. */
2335	#define X86_TRAP_ERR_EXTERNAL 1
2336	/** IDT indicator. */
2337	#define X86_TRAP_ERR_IDT 2
2338	/** Descriptor table indicator - If set LDT, if clear GDT. */
2339	#define X86_TRAP_ERR_TI 4
2340	/** Mask for getting the selector. */
2341	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2342	/** Shift for getting the selector table index (C type index). */
2343	#define X86_TRAP_ERR_SEL_SHIFT 3
2344	/** @} */
2345
2346
2347	/** @name \#PF Trap Error Codes
2348	* @{
2349	*/
2350	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2351	#define X86_TRAP_PF_P RT_BIT(0)
2352	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2353	#define X86_TRAP_PF_RW RT_BIT(1)
2354	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2355	#define X86_TRAP_PF_US RT_BIT(2)
2356	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2357	#define X86_TRAP_PF_RSVD RT_BIT(3)
2358	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2359	#define X86_TRAP_PF_ID RT_BIT(4)
2360	/** @} */
2361
2362	#pragma pack(1)
2363	/**
2364	* 32-bit IDTR/GDTR.
2365	*/
2366	typedef struct X86XDTR32
2367	{
2368	/** Size of the descriptor table. */
2369	uint16_t cb;
2370	/** Address of the descriptor table. */
2371	uint32_t uAddr;
2372	} X86XDTR32, *PX86XDTR32;
2373	#pragma pack()
2374
2375	#pragma pack(1)
2376	/**
2377	* 64-bit IDTR/GDTR.
2378	*/
2379	typedef struct X86XDTR64
2380	{
2381	/** Size of the descriptor table. */
2382	uint16_t cb;
2383	/** Address of the descriptor table. */
2384	uint64_t uAddr;
2385	} X86XDTR64, *PX86XDTR64;
2386	#pragma pack()
2387
2388	/** @} */
2389
2390	#endif
2391

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/x86.h@ 11052

Download in other formats: