Changeset 10817 in vbox
- Timestamp:
- Jul 22, 2008 3:03:14 PM (16 years ago)
- Location:
- trunk
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/hwacc_vmx.h
r10463 r10817 40 40 * @{ 41 41 */ 42 43 /** 44 * Extended Page Directory Pointer. Bit view. 45 */ 46 #pragma pack(1) 47 typedef struct VTXEPTPBITS 48 { 49 /** EPT Table Memory Type. */ 50 uint64_t u3ETMT : 3; 51 /** Guest Address Width. */ 52 uint64_t u3GAW : 3; 53 /** Reserved. */ 54 uint64_t u6Reserved : 6; 55 /** Address Space Root; page frame address of the first level EPT page. Actual width depends on the maximum physical address width of the CPU. */ 56 uint64_t u52ASR : 52; 57 } VTXEPTPBITS; 58 #pragma pack() 59 /** Pointer to an extended page directory pointer. */ 60 typedef VTXEPTPBITS *PVTXEPTPBITS; 61 /** Pointer to a const extended page directory pointer. */ 62 typedef const VTXEPTPBITS *PCVTXEPTPBITS; 63 64 /** 65 * Extended Page Directory Pointer. 66 */ 67 #pragma pack(1) 68 typedef union VTXEPTP 69 { 70 VTXEPTPBITS n; 71 /** 64 bit unsigned integer view. */ 72 uint64_t au64[1]; 73 } VTXEPTP; 74 #pragma pack() 75 /** Pointer to an extended page directory pointer. */ 76 typedef VTXEPTP *PVTXEPTP; 77 /** Pointer to a const extended page directory pointer. */ 78 typedef const VTXEPTP *PCVTXEPTP; 79 80 81 /** 82 * Extended Page Directory Table Entry. Bit view. 83 */ 84 #pragma pack(1) 85 typedef union VTXEPTEBITS 86 { 87 /** Readable bit. */ 88 uint64_t u1Readable : 1; 89 /** Writable bit. */ 90 uint64_t u1Writable : 1; 91 /** Executable bit. */ 92 uint64_t u1Executable : 1; 93 /** EPT Table Memory Type. MBZ for non-leaf nodes. */ 94 uint64_t u3EMT : 3; 95 /** IGMT (Ignore Guest Memory Type) (leaf nodes). MBZ for non-leaf nodes. */ 96 uint64_t u1IGMT : 1; 97 /** Super page (non-leaf) / available (leaf). */ 98 uint64_t u1SP : 1; 99 /** Available for software. */ 100 uint64_t u4Available : 4; 101 /** Physical address of next leaf/super page. Restricted by maximum physical address width of the cpu. */ 102 uint64_t u45PhysAddr : 45; 103 /** Reserved (MBZ). */ 104 uint64_t u5Reserved : 5; 105 /** Availabe for software. */ 106 uint64_t u2Available : 2; 107 } VTXEPTEBITS; 108 #pragma pack() 109 /** Pointer to an extended page table entry. */ 110 typedef VTXEPTEBITS *PVTXEPTEBITS; 111 /** Pointer to a const extended table entry. */ 112 typedef const VTXEPTEBITS *PCVTXEPTEBITS; 113 114 /** 115 * Extended Page Directory Table Entry. 116 */ 117 #pragma pack(1) 118 typedef union VTXEPTE 119 { 120 VTXEPTEBITS n; 121 /** 64 bit unsigned integer view. */ 122 uint64_t au64[1]; 123 } VTXEPTE; 124 #pragma pack() 125 /** Pointer to an extended page table entry. */ 126 typedef VTXEPTE *PVTXEPTE; 127 /** Pointer to a const extended table entry. */ 128 typedef const VTXEPTE *PCVTXEPTE; 42 129 43 130 /** VMX Basic Exit Reasons. … … 234 321 /** @} */ 235 322 323 324 /** MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR 325 * @{ 326 */ 327 #define MSRVAL_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0) 328 #define MSRVAL_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1) 329 #define MSRVAL_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2) 330 #define MSRVAL_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3) 331 #define MSRVAL_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4) 332 #define MSRVAL_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5) 333 #define MSRVAL_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6) 334 #define MSRVAL_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7) 335 #define MSRVAL_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8) 336 #define MSRVAL_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9) 337 #define MSRVAL_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12) 338 #define MSRVAL_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13) 339 #define MSRVAL_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14) 340 #define MSRVAL_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16) 341 #define MSRVAL_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17) 342 #define MSRVAL_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18) 343 #define MSRVAL_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19) 344 #define MSRVAL_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20) 345 #define MSRVAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24) 346 #define MSRVAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25) 347 #define MSRVAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26) 348 #define MSRVAL_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32) 349 #define MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40) 350 #define MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41) 351 #define MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42) 352 #define MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43) 353 354 /** @} */ 355 236 356 /** @} */ 237 357 … … 244 364 * @{ 245 365 */ 366 #define VMX_VMCS_GUEST_FIELD_VPID 0x0 246 367 #define VMX_VMCS_GUEST_FIELD_ES 0x800 247 368 #define VMX_VMCS_GUEST_FIELD_CS 0x802 … … 266 387 /** @} */ 267 388 389 /** 64 bits host fields 390 * @{ 391 */ 392 #define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00 393 #define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01 394 #define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02 395 #define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03 396 #define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /* MSR IA32_PERF_GLOBAL_CTRL */ 397 #define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /* MSR IA32_PERF_GLOBAL_CTRL */ 398 /** @} */ 399 400 268 401 /** 64 Bits control fields 269 402 * @{ … … 295 428 #define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012 296 429 #define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013 430 431 /** Extended page table pointer. */ 432 #define VMX_VMCS_CTRL_EPTP_FULL 0x201a 433 #define VMX_VMCS_CTRL_EPTP_HIGH 0x201b 434 435 /** VM-exit phyiscal address. */ 436 #define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400 437 #define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401 297 438 /** @} */ 298 439 … … 303 444 #define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800 304 445 #define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801 305 #define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /* MSR IA32_DEBUGCTL */ 306 #define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /* MSR IA32_DEBUGCTL */ 446 #define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /* MSR IA32_DEBUGCTL */ 447 #define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /* MSR IA32_DEBUGCTL */ 448 #define VMX_VMCS_GUEST_PAT_FULL 0x2804 449 #define VMX_VMCS_GUEST_PAT_HIGH 0x2805 450 #define VMX_VMCS_GUEST_EFER_FULL 0x2806 451 #define VMX_VMCS_GUEST_EFER_HIGH 0x2807 452 #define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /* MSR IA32_PERF_GLOBAL_CTRL */ 453 #define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /* MSR IA32_PERF_GLOBAL_CTRL */ 454 #define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A 455 #define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B 456 #define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C 457 #define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D 458 #define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E 459 #define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F 460 #define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810 461 #define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811 307 462 /** @} */ 308 463 … … 325 480 #define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018 326 481 #define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A 327 /* Optional*/482 /** This field exists only on processors that support the 1-setting of the use TPR shadow VM-execution control. */ 328 483 #define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C 484 /** This field exists only on processors that support the 1-setting of the activate secondary controls VM-execution control. */ 485 #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E 329 486 /** @} */ 330 487 … … 339 496 /* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */ 340 497 /** @} */ 341 342 498 343 499 /** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS … … 376 532 /* VM Exit when executing the PAUSE instruction. */ 377 533 #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30) 534 /* Determines whether the secondary processor based VM-execution controls are used. */ 535 #define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31) 536 /** @} */ 537 538 /** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 539 * @{ 540 */ 541 /** EPT supported/enabled. */ 542 #define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1) 543 /** VPID supported/enabled. */ 544 #define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5) 378 545 /** @} */ 379 546 … … 518 685 #define VMX_VMCS_RO_IO_RDI 0x6406 519 686 #define VMX_VMCS_RO_IO_RIP 0x6408 520 #define VMX_VMCS_ GUEST_LINEAR_ADDR0x640A687 #define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A 521 688 /** @} */ 522 689 -
trunk/include/VBox/x86.h
r10707 r10817 790 790 /** Information for enumerating fields in the VMCS. */ 791 791 #define MSR_IA32_VMX_VMCS_ENUM 0x48A 792 792 /** Allowed settings for secondary proc-based VM execution controls */ 793 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B 794 /** EPT capabilities. */ 795 #define MSR_IA32_VMX_EPT_CAPS 0x48C 793 796 794 797 /** K6 EFER - Extended Feature Enable Register. */ -
trunk/src/VBox/VMM/HWACCM.cpp
r10730 r10817 350 350 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT) 351 351 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n")); 352 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) 353 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n")); 352 354 353 355 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0; … … 384 386 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT) 385 387 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n")); 388 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) 389 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n")); 390 391 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) 392 { 393 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u)); 394 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1; 395 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT) 396 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n")); 397 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID) 398 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n")); 399 400 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0; 401 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT) 402 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n")); 403 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID) 404 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n")); 405 } 386 406 387 407 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u)); … … 412 432 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ) 413 433 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n")); 434 435 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps) 436 { 437 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps)); 438 439 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_RWX_X_ONLY) 440 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n")); 441 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_RWX_W_ONLY) 442 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n")); 443 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_RWX_WX_ONLY) 444 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n")); 445 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_GAW_21_BITS) 446 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_GAW_21_BITS\n")); 447 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_GAW_30_BITS) 448 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_GAW_30_BITS\n")); 449 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_GAW_39_BITS) 450 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_GAW_39_BITS\n")); 451 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_GAW_48_BITS) 452 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_GAW_48_BITS\n")); 453 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_GAW_57_BITS) 454 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_GAW_57_BITS\n")); 455 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_EMT_UC) 456 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_EMT_UC\n")); 457 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_EMT_WC) 458 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_EMT_WC\n")); 459 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_EMT_WT) 460 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_EMT_WT\n")); 461 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_EMT_WP) 462 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_EMT_WP\n")); 463 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_EMT_WB) 464 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_EMT_WB\n")); 465 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_SP_21_BITS) 466 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_SP_21_BITS\n")); 467 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_SP_30_BITS) 468 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_SP_30_BITS\n")); 469 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_SP_39_BITS) 470 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_SP_39_BITS\n")); 471 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_SP_48_BITS) 472 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_SP_48_BITS\n")); 473 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_INVEPT) 474 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_INVEPT\n")); 475 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV) 476 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n")); 477 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT) 478 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n")); 479 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL) 480 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n")); 481 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_INVVPID) 482 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_INVVPID\n")); 483 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV) 484 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n")); 485 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT) 486 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n")); 487 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL) 488 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n")); 489 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL) 490 LogRel(("HWACCM: MSRVAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n")); 491 } 414 492 415 493 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc)); -
trunk/src/VBox/VMM/HWACCMInternal.h
r10691 r10817 240 240 VMX_CAPABILITY vmx_pin_ctls; 241 241 VMX_CAPABILITY vmx_proc_ctls; 242 VMX_CAPABILITY vmx_proc_ctls2; 242 243 VMX_CAPABILITY vmx_exit; 243 244 VMX_CAPABILITY vmx_entry; … … 248 249 uint64_t vmx_cr4_fixed1; 249 250 uint64_t vmx_vmcs_enum; 251 uint64_t vmx_eptcaps; 250 252 } msr; 251 253 -
trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp
r10687 r10817 89 89 VMX_CAPABILITY vmx_pin_ctls; 90 90 VMX_CAPABILITY vmx_proc_ctls; 91 VMX_CAPABILITY vmx_proc_ctls2; 91 92 VMX_CAPABILITY vmx_exit; 92 93 VMX_CAPABILITY vmx_entry; … … 97 98 uint64_t vmx_cr4_fixed1; 98 99 uint64_t vmx_vmcs_enum; 100 uint64_t vmx_eptcaps; 99 101 } msr; 100 102 /* Last instruction error */ … … 222 224 HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1); 223 225 HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM); 226 227 if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) 228 { 229 HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2); 230 if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT|VMX_VMCS_CTRL_PROC_EXEC2_VPID)) 231 HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS); 232 } 233 224 234 HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4(); 225 235 … … 655 665 pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls; 656 666 pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls; 667 pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2; 657 668 pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit; 658 669 pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry; … … 663 674 pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1; 664 675 pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum; 676 pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps; 665 677 pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev; 666 678 pVM->hwaccm.s.svm.u32MaxASID = HWACCMR0Globals.svm.u32MaxASID;
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