armv8.h@ 99577

Last change on this file since 99577 was 99577, checked in by vboxsync, 2 years ago
include/iprt/armv8.h: Some paging related definitions, bugref:10388
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 57.8 KB

Line
1	/** @file
2	* IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef IPRT_INCLUDED_armv8_h
37	#define IPRT_INCLUDED_armv8_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# include <iprt/types.h>
44	# include <iprt/assert.h>
45	#else
46	# pragma D depends_on library vbox-types.d
47	#endif
48
49	/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
50	* @ingroup grp_rt
51	* @{
52	*/
53
54	/** @name The AArch64 register encoding.
55	* @{ */
56	#define ARMV8_AARCH64_REG_X0 0
57	#define ARMV8_AARCH64_REG_W0 ARMV8_AARCH64_REG_X0
58	#define ARMV8_AARCH64_REG_X1 1
59	#define ARMV8_AARCH64_REG_W1 ARMV8_AARCH64_REG_X1
60	#define ARMV8_AARCH64_REG_X2 2
61	#define ARMV8_AARCH64_REG_W2 ARMV8_AARCH64_REG_X2
62	#define ARMV8_AARCH64_REG_X3 3
63	#define ARMV8_AARCH64_REG_W3 ARMV8_AARCH64_REG_X3
64	#define ARMV8_AARCH64_REG_X4 4
65	#define ARMV8_AARCH64_REG_W4 ARMV8_AARCH64_REG_X4
66	#define ARMV8_AARCH64_REG_X5 5
67	#define ARMV8_AARCH64_REG_W5 ARMV8_AARCH64_REG_X5
68	#define ARMV8_AARCH64_REG_X6 6
69	#define ARMV8_AARCH64_REG_W6 ARMV8_AARCH64_REG_X6
70	#define ARMV8_AARCH64_REG_X7 7
71	#define ARMV8_AARCH64_REG_W7 ARMV8_AARCH64_REG_X7
72	#define ARMV8_AARCH64_REG_X8 8
73	#define ARMV8_AARCH64_REG_W8 ARMV8_AARCH64_REG_X8
74	#define ARMV8_AARCH64_REG_X9 9
75	#define ARMV8_AARCH64_REG_W9 ARMV8_AARCH64_REG_X9
76	#define ARMV8_AARCH64_REG_X10 10
77	#define ARMV8_AARCH64_REG_W10 ARMV8_AARCH64_REG_X10
78	#define ARMV8_AARCH64_REG_X11 11
79	#define ARMV8_AARCH64_REG_W11 ARMV8_AARCH64_REG_X11
80	#define ARMV8_AARCH64_REG_X12 12
81	#define ARMV8_AARCH64_REG_W12 ARMV8_AARCH64_REG_X12
82	#define ARMV8_AARCH64_REG_X13 13
83	#define ARMV8_AARCH64_REG_W13 ARMV8_AARCH64_REG_X13
84	#define ARMV8_AARCH64_REG_X14 14
85	#define ARMV8_AARCH64_REG_W14 ARMV8_AARCH64_REG_X14
86	#define ARMV8_AARCH64_REG_X15 15
87	#define ARMV8_AARCH64_REG_W15 ARMV8_AARCH64_REG_X15
88	#define ARMV8_AARCH64_REG_X16 16
89	#define ARMV8_AARCH64_REG_W16 ARMV8_AARCH64_REG_X16
90	#define ARMV8_AARCH64_REG_X17 17
91	#define ARMV8_AARCH64_REG_W17 ARMV8_AARCH64_REG_X17
92	#define ARMV8_AARCH64_REG_X18 18
93	#define ARMV8_AARCH64_REG_W18 ARMV8_AARCH64_REG_X18
94	#define ARMV8_AARCH64_REG_X19 19
95	#define ARMV8_AARCH64_REG_W19 ARMV8_AARCH64_REG_X19
96	#define ARMV8_AARCH64_REG_X20 20
97	#define ARMV8_AARCH64_REG_W20 ARMV8_AARCH64_REG_X20
98	#define ARMV8_AARCH64_REG_X21 21
99	#define ARMV8_AARCH64_REG_W21 ARMV8_AARCH64_REG_X21
100	#define ARMV8_AARCH64_REG_X22 22
101	#define ARMV8_AARCH64_REG_W22 ARMV8_AARCH64_REG_X22
102	#define ARMV8_AARCH64_REG_X23 23
103	#define ARMV8_AARCH64_REG_W23 ARMV8_AARCH64_REG_X23
104	#define ARMV8_AARCH64_REG_X24 24
105	#define ARMV8_AARCH64_REG_W24 ARMV8_AARCH64_REG_X24
106	#define ARMV8_AARCH64_REG_X25 25
107	#define ARMV8_AARCH64_REG_W25 ARMV8_AARCH64_REG_X25
108	#define ARMV8_AARCH64_REG_X26 26
109	#define ARMV8_AARCH64_REG_W26 ARMV8_AARCH64_REG_X26
110	#define ARMV8_AARCH64_REG_X27 27
111	#define ARMV8_AARCH64_REG_W27 ARMV8_AARCH64_REG_X27
112	#define ARMV8_AARCH64_REG_X28 28
113	#define ARMV8_AARCH64_REG_W28 ARMV8_AARCH64_REG_X28
114	#define ARMV8_AARCH64_REG_X29 29
115	#define ARMV8_AARCH64_REG_W29 ARMV8_AARCH64_REG_X29
116	#define ARMV8_AARCH64_REG_X30 30
117	#define ARMV8_AARCH64_REG_W30 ARMV8_AARCH64_REG_X30
118	/** The zero register. */
119	#define ARMV8_AARCH64_REG_ZR 31
120	/** @} */
121
122
123	/** @name System register encoding.
124	* @{
125	*/
126	/** Mask for the op0 part of an MSR/MRS instruction */
127	#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) \| RT_BIT_32(20))
128	/** Shift for the op0 part of an MSR/MRS instruction */
129	#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
130	/** Returns the op0 part of the given MRS/MSR instruction. */
131	#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
132	/** Mask for the op1 part of an MSR/MRS instruction */
133	#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18))
134	/** Shift for the op1 part of an MSR/MRS instruction */
135	#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
136	/** Returns the op1 part of the given MRS/MSR instruction. */
137	#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
138	/** Mask for the CRn part of an MSR/MRS instruction */
139	#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \
140	\| RT_BIT_32(15) )
141	/** Shift for the CRn part of an MSR/MRS instruction */
142	#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
143	/** Returns the CRn part of the given MRS/MSR instruction. */
144	#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
145	/** Mask for the CRm part of an MSR/MRS instruction */
146	#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \
147	\| RT_BIT_32(11) )
148	/** Shift for the CRm part of an MSR/MRS instruction */
149	#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
150	/** Returns the CRn part of the given MRS/MSR instruction. */
151	#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
152	/** Mask for the op2 part of an MSR/MRS instruction */
153	#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7))
154	/** Shift for the op2 part of an MSR/MRS instruction */
155	#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
156	/** Returns the op2 part of the given MRS/MSR instruction. */
157	#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
158	/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
159	#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK \| ARMV8_AARCH64_SYSREG_OP1_MASK \
160	\| ARMV8_AARCH64_SYSREG_CRN_MASK \| ARMV8_AARCH64_SYSREG_CRN_MASK \
161	\| ARMV8_AARCH64_SYSREG_OP2_MASK)
162
163	/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
164	* IPRT specific and not part of the ARMv8 specification. */
165	#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
166	UINT16_C( (((a_Op0) & 0x3) << 14) \
167	\| (((a_Op1) & 0x7) << 11) \
168	\| (((a_CRn) & 0xf) << 7) \
169	\| (((a_CRm) & 0xf) << 3) \
170	\| ((a_Op2) & 0x7))
171	/** Returns the internal system register ID from the given MRS/MSR instruction. */
172	#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
173	ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
174	ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
175	ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
176	ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
177	ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
178	/** Encodes the given system register ID in the given MSR/MRS instruction. */
179	#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
180	((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) \| (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
181	/** @} */
182
183
184	/** @name System register IDs.
185	* @{ */
186	/** OSLAR_EL1 register - RW. */
187	#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
188	/** OSLSR_EL1 register - RW. */
189	#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
190	/** OSDLR_EL1 register - RW. */
191	#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
192
193	/** MIDR_EL1 register - RO. */
194	#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
195	/** MIPDR_EL1 register - RO. */
196	#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
197	/** REVIDR_EL1 register - RO. */
198	#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
199	/** ID_PFR0_EL1 register - RO. */
200	#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
201	/** ID_PFR1_EL1 register - RO. */
202	#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
203	/** ID_DFR0_EL1 register - RO. */
204	#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
205	/** ID_AFR0_EL1 register - RO. */
206	#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
207	/** ID_MMFR0_EL1 register - RO. */
208	#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
209	/** ID_MMFR1_EL1 register - RO. */
210	#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
211	/** ID_MMFR2_EL1 register - RO. */
212	#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
213	/** ID_MMFR3_EL1 register - RO. */
214	#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
215
216	/** ID_ISAR0_EL1 register - RO. */
217	#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
218	/** ID_ISAR1_EL1 register - RO. */
219	#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
220	/** ID_ISAR2_EL1 register - RO. */
221	#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
222	/** ID_ISAR3_EL1 register - RO. */
223	#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
224	/** ID_ISAR4_EL1 register - RO. */
225	#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
226	/** ID_ISAR5_EL1 register - RO. */
227	#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
228	/** ID_MMFR4_EL1 register - RO. */
229	#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
230	/** ID_ISAR6_EL1 register - RO. */
231	#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
232
233	/** MVFR0_EL1 register - RO. */
234	#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
235	/** MVFR1_EL1 register - RO. */
236	#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
237	/** MVFR2_EL1 register - RO. */
238	#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
239	/** ID_PFR2_EL1 register - RO. */
240	#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
241	/** ID_DFR1_EL1 register - RO. */
242	#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
243	/** ID_MMFR5_EL1 register - RO. */
244	#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
245
246	/** ID_AA64PFR0_EL1 register - RO. */
247	#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
248	/** ID_AA64PFR0_EL1 register - RO. */
249	#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
250	/** ID_AA64ZFR0_EL1 register - RO. */
251	#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
252	/** ID_AA64SMFR0_EL1 register - RO. */
253	#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
254
255	/** ID_AA64DFR0_EL1 register - RO. */
256	#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
257	/** ID_AA64DFR0_EL1 register - RO. */
258	#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
259	/** ID_AA64AFR0_EL1 register - RO. */
260	#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
261	/** ID_AA64AFR1_EL1 register - RO. */
262	#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
263
264	/** ID_AA64ISAR0_EL1 register - RO. */
265	#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
266	/** ID_AA64ISAR1_EL1 register - RO. */
267	#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
268	/** ID_AA64ISAR2_EL1 register - RO. */
269	#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
270
271	/** ID_AA64MMFR0_EL1 register - RO. */
272	#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
273	/** ID_AA64MMFR1_EL1 register - RO. */
274	#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
275	/** ID_AA64MMFR2_EL1 register - RO. */
276	#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
277
278	/** SCTRL_EL1 register - RW. */
279	#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
280	/** ACTRL_EL1 register - RW. */
281	#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
282	/** CPACR_EL1 register - RW. */
283	#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
284	/** RGSR_EL1 register - RW. */
285	#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
286	/** GCR_EL1 register - RW. */
287	#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
288
289	/** ZCR_EL1 register - RW. */
290	#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
291	/** TRFCR_EL1 register - RW. */
292	#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
293	/** SMPRI_EL1 register - RW. */
294	#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
295	/** SMCR_EL1 register - RW. */
296	#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
297
298	/** TTBR0_EL1 register - RW. */
299	#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
300	/** TTBR1_EL1 register - RW. */
301	#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
302	/** TCR_EL1 register - RW. */
303	#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
304
305	/** @todo APIA,APIB,APDA,APDB,APGA registers. */
306
307	/** SPSR_EL1 register - RW. */
308	#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
309	/** ELR_EL1 register - RW. */
310	#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
311
312	/** SP_EL0 register - RW. */
313	#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
314
315	/** PSTATE.SPSel value. */
316	#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
317	/** PSTATE.CurrentEL value. */
318	#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
319	/** PSTATE.PAN value. */
320	#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
321	/** PSTATE.UAO value. */
322	#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
323
324	/** PSTATE.ALLINT value. */
325	#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
326
327	/** ICC_PMR_EL1 register - RW. */
328	#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
329
330	/** AFSR0_EL1 register - RW. */
331	#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
332	/** AFSR1_EL1 register - RW. */
333	#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
334
335	/** ESR_EL1 register - RW. */
336	#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
337
338	/** ERRIDR_EL1 register - RO. */
339	#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
340	/** ERRSELR_EL1 register - RW. */
341	#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
342
343	/** ICC_IAR0_EL1 register - RO. */
344	#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
345	/** ICC_EOIR0_EL1 register - WO. */
346	#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
347	/** ICC_HPPIR0_EL1 register - WO. */
348	#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
349	/** ICC_BPR0_EL1 register - RW. */
350	#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
351	/** ICC_AP0R0_EL1 register - RW. */
352	#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
353	/** ICC_AP0R1_EL1 register - RW. */
354	#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
355	/** ICC_AP0R2_EL1 register - RW. */
356	#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
357	/** ICC_AP0R3_EL1 register - RW. */
358	#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
359
360	/** ICC_AP1R0_EL1 register - RW. */
361	#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
362	/** ICC_AP1R1_EL1 register - RW. */
363	#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
364	/** ICC_AP1R2_EL1 register - RW. */
365	#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
366	/** ICC_AP1R3_EL1 register - RW. */
367	#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
368	/** ICC_NMIAR1_EL1 register - RO. */
369	#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
370
371	/** ICC_DIR_EL1 register - WO. */
372	#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
373	/** ICC_RPR_EL1 register - RO. */
374	#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
375	/** ICC_SGI1R_EL1 register - WO. */
376	#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
377	/** ICC_ASGI1R_EL1 register - WO. */
378	#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
379	/** ICC_SGI0R_EL1 register - WO. */
380	#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
381
382	/** ICC_IAR1_EL1 register - RO. */
383	#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
384	/** ICC_EOIR1_EL1 register - WO. */
385	#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
386	/** ICC_HPPIR1_EL1 register - RO. */
387	#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
388	/** ICC_BPR1_EL1 register - RW. */
389	#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
390	/** ICC_CTLR_EL1 register - RW. */
391	#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
392	/** ICC_SRE_EL1 register - RW. */
393	#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
394	/** ICC_IGRPEN0_EL1 register - RW. */
395	#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
396	/** ICC_IGRPEN1_EL1 register - RW. */
397	#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
398	/** @} */
399
400	/** @} */
401
402
403	/**
404	* SPSR_EL2 (according to chapter C5.2.19)
405	*/
406	typedef union ARMV8SPSREL2
407	{
408	/** The plain unsigned view. */
409	uint64_t u;
410	/** The 8-bit view. */
411	uint8_t au8[8];
412	/** The 16-bit view. */
413	uint16_t au16[4];
414	/** The 32-bit view. */
415	uint32_t au32[2];
416	/** The 64-bit view. */
417	uint64_t u64;
418	} ARMV8SPSREL2;
419	/** Pointer to SPSR_EL2. */
420	typedef ARMV8SPSREL2 *PARMV8SPSREL2;
421	/** Pointer to const SPSR_EL2. */
422	typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
423
424
425	/** @name SPSR_EL2 (When exception is taken from AArch64 state)
426	* @{
427	*/
428	/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
429	#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \| RT_BIT_64(3))
430	#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
431	/** Bit 0 - SP - Selected stack pointer. */
432	#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
433	#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
434	/** Bit 1 - Reserved (read as zero). */
435	#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
436	/** Bit 2 - 3 - EL - Exception level. */
437	#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) \| RT_BIT_64(3))
438	#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
439	#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
440	#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
441	/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
442	#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
443	#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
444	/** Bit 5 - Reserved (read as zero). */
445	#define ARMV8_SPSR_EL2_AARCH64_RSVD_5 RT_BIT_64(5)
446	/** Bit 6 - I - FIQ interrupt mask. */
447	#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
448	#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
449	/** Bit 7 - I - IRQ interrupt mask. */
450	#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
451	#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
452	/** Bit 8 - A - SError interrupt mask. */
453	#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
454	#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
455	/** Bit 9 - D - Debug Exception mask. */
456	#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
457	#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
458	/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
459	#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) \| RT_BIT_64(11))
460	#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
461	#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
462	/** Bit 12 - SSBS - Speculative Store Bypass. */
463	#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
464	#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
465	/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
466	#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
467	#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
468	/** Bit 14 - 19 - Reserved (read as zero). */
469	#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) \| RT_BIT_64(15) \| RT_BIT_64(16) \
470	\| RT_BIT_64(17) \| RT_BIT_64(18) \| RT_BIT_64(19))
471	/** Bit 20 - IL - Illegal Execution State flag. */
472	#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
473	#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
474	/** Bit 21 - SS - Software Step flag. */
475	#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
476	#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
477	/** Bit 22 - PAN - Privileged Access Never flag. */
478	#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
479	#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
480	/** Bit 23 - UAO - User Access Override flag. */
481	#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
482	#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
483	/** Bit 24 - DIT - Data Independent Timing flag. */
484	#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
485	#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
486	/** Bit 25 - TCO - Tag Check Override flag. */
487	#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
488	#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
489	/** Bit 26 - 27 - Reserved (read as zero). */
490	#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) \| RT_BIT_64(27))
491	/** Bit 28 - V - Overflow condition flag. */
492	#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
493	#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
494	/** Bit 29 - C - Carry condition flag. */
495	#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
496	#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
497	/** Bit 30 - Z - Zero condition flag. */
498	#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
499	#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
500	/** Bit 31 - N - Negative condition flag. */
501	#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
502	#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
503	/** Bit 32 - 63 - Reserved (read as zero). */
504	#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
505	/** Checks whether the given SPSR value contains a AARCH64 execution state. */
506	#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
507	/** @} */
508
509	/** @name Aarch64 Exception levels
510	* @{ */
511	/** Exception Level 0 - User mode. */
512	#define ARMV8_AARCH64_EL_0 0
513	/** Exception Level 1 - Supervisor mode. */
514	#define ARMV8_AARCH64_EL_1 1
515	/** Exception Level 2 - Hypervisor mode. */
516	#define ARMV8_AARCH64_EL_2 2
517	/** @} */
518
519
520	/** @name ESR_EL2 (Exception Syndrome Register, EL2)
521	* @{
522	*/
523	/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
524	#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
525	#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
526	/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
527	#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
528	#define ARMV8_ESR_EL2_IL_BIT 25
529	#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
530	#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
531	/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
532	#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) \| RT_BIT_64(27) \| RT_BIT_64(28) \
533	\| RT_BIT_64(29) \| RT_BIT_64(30) \| RT_BIT_64(31))
534	#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
535	/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
536	#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34) \
537	\| RT_BIT_64(35) \| RT_BIT_64(36))
538	#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
539	/+ @} /
540
541
542	/** @name ESR_EL2 Exception Classes (EC)
543	* @{ */
544	/** Unknown exception reason. */
545	#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
546	/** Trapped WF* instruction. */
547	#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
548	/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
549	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
550	/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
551	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
552	/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
553	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
554	/** AArch32 - Trapped LDC or STC access. */
555	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
556	/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
557	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
558	/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
559	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
560	/** AArch32 - Trapped pointer authentication instruction. */
561	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
562	/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
563	#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
564	/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
565	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
566	/** FEAT_BTI - Branch Target Exception. */
567	#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
568	/** Illegal Execution State. */
569	#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
570	/** AArch32 - SVC instruction execution. */
571	#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
572	/** AArch32 - HVC instruction execution. */
573	#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
574	/** AArch32 - SMC instruction execution. */
575	#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
576	/** AArch64 - SVC instruction execution. */
577	#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
578	/** AArch64 - HVC instruction execution. */
579	#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
580	/** AArch64 - SMC instruction execution. */
581	#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
582	/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
583	#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
584	/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
585	#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
586	/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
587	#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
588	/** FEAT_TME - Exception from TSTART instruction. */
589	#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
590	/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
591	#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
592	/** FEAT_SME - Access to SME functionality trapped. */
593	#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
594	/** FEAT_RME - Exception from Granule Protection Check. */
595	#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
596	/** Instruction Abort from a lower Exception level. */
597	#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
598	/** Instruction Abort from the same Exception level. */
599	#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
600	/** PC alignment fault exception. */
601	#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
602	/** Data Abort from a lower Exception level. */
603	#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
604	/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
605	#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
606	/** SP alignment fault exception. */
607	#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
608	/** FEAT_MOPS - Memory Operation Exception. */
609	#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
610	/** AArch32 - Trapped floating point exception. */
611	#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
612	/** AArch64 - Trapped floating point exception. */
613	#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
614	/** SError interrupt. */
615	#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
616	/** Breakpoint Exception from a lower Exception level. */
617	#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
618	/** Breakpoint Exception from the same Exception level. */
619	#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
620	/** Software Step Exception from a lower Exception level. */
621	#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
622	/** Software Step Exception from the same Exception level. */
623	#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
624	/** Watchpoint Exception from a lower Exception level. */
625	#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
626	/** Watchpoint Exception from the same Exception level. */
627	#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
628	/** AArch32 - BKPT instruction execution. */
629	#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
630	/** AArch32 - Vector Catch exception. */
631	#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
632	/** AArch64 - BRK instruction execution. */
633	#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
634	/** @} */
635
636
637	/** @name ISS encoding for Data Abort exceptions.
638	* @{ */
639	/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
640	#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) \| RT_BIT_32(1) \| RT_BIT_32(2) \
641	\| RT_BIT_32(3) \| RT_BIT_32(4) \| RT_BIT_32(5))
642	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
643	/** Bit 6 - WnR - Write not Read. */
644	#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
645	#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
646	/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
647	#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
648	#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
649	/** Bit 8 - CM - Cache maintenance instruction. */
650	#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
651	#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
652	/** Bit 9 - EA - External abort type. */
653	#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
654	#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
655	/** Bit 10 - FnV - FAR not Valid. */
656	#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
657	#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
658	/** Bit 11 - 12 - LST - Load/Store Type. */
659	#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) \| RT_BIT_32(12))
660	#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
661	/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
662	#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
663	#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
664	/** Bit 14 - AR - Acquire/Release semantics. */
665	#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
666	#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
667	/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
668	#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
669	#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
670	/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
671	#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18) \
672	\| RT_BIT_32(19) \| RT_BIT_32(20))
673	#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
674	/** Bit 21 - SSE - Syndrome Sign Extend. */
675	#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
676	#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
677	/** Bit 22 - 23 - SAS - Syndrome Access Size. */
678	#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) \| RT_BIT_32(23))
679	#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
680	/** Bit 24 - ISV - Instruction Syndrome Valid. */
681	#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
682	#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
683
684
685	/** @name Data Fault Status Code (DFSC).
686	* @{ */
687	/** Address size fault, level 0 of translation or translation table base register. */
688	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
689	/** Address size fault, level 1. */
690	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
691	/** Address size fault, level 2. */
692	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
693	/** Address size fault, level 3. */
694	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
695	/** Translation fault, level 0. */
696	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
697	/** Translation fault, level 1. */
698	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
699	/** Translation fault, level 2. */
700	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
701	/** Translation fault, level 3. */
702	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
703	/** FEAT_LPA2 - Access flag fault, level 0. */
704	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
705	/** Access flag fault, level 1. */
706	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
707	/** Access flag fault, level 2. */
708	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
709	/** Access flag fault, level 3. */
710	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
711	/** FEAT_LPA2 - Permission fault, level 0. */
712	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
713	/** Permission fault, level 1. */
714	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
715	/** Permission fault, level 2. */
716	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
717	/** Permission fault, level 3. */
718	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
719	/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
720	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
721	/** FEAT_MTE2 - Synchronous Tag Check Fault. */
722	#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
723	/** @todo Do the rest (lazy developer). */
724	/** @} */
725
726
727	/** @name SAS encoding. */
728	/** Byte access. */
729	#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
730	/** Halfword access (uint16_t). */
731	#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
732	/** Word access (uint32_t). */
733	#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
734	/** Doubleword access (uint64_t). */
735	#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
736	/** @} */
737
738	/** @} */
739
740
741	/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
742	* @{ */
743	/** Bit 0 - Direction flag. */
744	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
745	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
746	/** Bit 1 - 4 - CRm value from the instruction. */
747	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) \| RT_BIT_32(2) \| RT_BIT_32(3) \
748	\| RT_BIT_32(4))
749	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
750	/** Bit 5 - 9 - Rt value from the instruction. */
751	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7) \
752	\| RT_BIT_32(8) \| RT_BIT_32(9))
753	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
754	/** Bit 10 - 13 - CRn value from the instruction. */
755	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \
756	\| RT_BIT_32(13))
757	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
758	/** Bit 14 - 16 - Op2 value from the instruction. */
759	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(16))
760	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
761	/** Bit 17 - 19 - Op2 value from the instruction. */
762	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) \| RT_BIT_32(18) \| RT_BIT_32(19))
763	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
764	/** Bit 20 - 21 - Op0 value from the instruction. */
765	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) \| RT_BIT_32(21))
766	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
767	/** Bit 22 - 24 - Reserved. */
768	#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24))
769	/** @} */
770
771
772	/** @name ISS encoding for trapped HVC instruction exceptions.
773	* @{ */
774	/** Bit 0 - 15 - imm16 value of the instruction. */
775	#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
776	#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
777	/** @} */
778
779
780	/** @name TCR_EL1 - Translation Control Register (EL1)
781	* @{
782	*/
783	/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
784	#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) \| RT_BIT_64(1) \| RT_BIT_64(2) \
785	\| RT_BIT_64(3) \| RT_BIT_64(4) \| RT_BIT_64(5))
786	#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
787	/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
788	#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
789	#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
790	/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
791	#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) \| RT_BIT_64(9))
792	#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
793	/** Non cacheable. */
794	# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
795	/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
796	# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
797	/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
798	# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
799	/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
800	# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
801	/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
802	#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) \| RT_BIT_64(11))
803	#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
804	/** Non cacheable. */
805	# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
806	/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
807	# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
808	/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
809	# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
810	/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
811	# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
812	/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
813	#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) \| RT_BIT_64(13))
814	#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
815	/** Non shareable. */
816	# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
817	/** Invalid value. */
818	# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
819	/** Outer Shareable. */
820	# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
821	/** Inner Shareable. */
822	# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
823	/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
824	#define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) \| RT_BIT_64(15))
825	#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
826	/** Invalid granule size. */
827	# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
828	/** 16KiB granule size. */
829	# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
830	/** 4KiB granule size. */
831	# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
832	/** 64KiB granule size. */
833	# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
834	/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
835	#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) \| RT_BIT_64(17) \| RT_BIT_64(18) \
836	\| RT_BIT_64(19) \| RT_BIT_64(20) \| RT_BIT_64(21))
837	#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
838	/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
839	#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
840	#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
841	/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
842	#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
843	#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
844	/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
845	#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) \| RT_BIT_64(25))
846	#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
847	/** Non cacheable. */
848	# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
849	/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
850	# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
851	/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
852	# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
853	/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
854	# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
855	/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
856	#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) \| RT_BIT_64(27))
857	#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
858	/** Non cacheable. */
859	# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
860	/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
861	# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
862	/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
863	# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
864	/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
865	# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
866	/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
867	#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) \| RT_BIT_64(29))
868	#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
869	/** Non shareable. */
870	# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
871	/** Invalid value. */
872	# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
873	/** Outer Shareable. */
874	# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
875	/** Inner Shareable. */
876	# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
877	/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
878	#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) \| RT_BIT_64(31))
879	#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
880	/** Invalid granule size. */
881	# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
882	/** 16KiB granule size. */
883	# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
884	/** 4KiB granule size. */
885	# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
886	/** 64KiB granule size. */
887	# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
888	/** Bit 32 - 34 - Intermediate Physical Address Size. */
889	#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) \| RT_BIT_64(33) \| RT_BIT_64(34))
890	#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
891	/** IPA - 32 bits, 4GiB. */
892	# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
893	/** IPA - 36 bits, 64GiB. */
894	# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
895	/** IPA - 40 bits, 1TiB. */
896	# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
897	/** IPA - 42 bits, 4TiB. */
898	# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
899	/** IPA - 44 bits, 16TiB. */
900	# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
901	/** IPA - 48 bits, 256TiB. */
902	# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
903	/** IPA - 52 bits, 4PiB. */
904	# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
905	/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
906	#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
907	#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
908	/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
909	#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
910	#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
911	/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
912	#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
913	#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
914	/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
915	#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
916	#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
917	/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
918	#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
919	#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
920	/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
921	#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
922	#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
923	/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
924	#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
925	#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
926	/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
927	#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
928	#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
929	/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
930	#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
931	#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
932	/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
933	#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
934	#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
935	/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
936	#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
937	#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
938	/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
939	#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
940	#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
941	/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
942	#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
943	#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
944	/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
945	#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
946	#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
947	/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
948	#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
949	#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
950	/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
951	#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
952	#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
953	/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
954	#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
955	#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
956	/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
957	#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
958	#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
959	/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
960	#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
961	#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
962	/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
963	#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
964	#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
965	/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
966	#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
967	#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
968	/** Bit 57 - TCMA0 */
969	#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
970	#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
971	/** Bit 58 - TCMA1 */
972	#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
973	#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
974	/** Bit 59 - Data Sharing(?). */
975	#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
976	#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
977	/** @} */
978
979
980	/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
981	* @{
982	*/
983	/** Bit 0 - Common not Private (FEAT_TTCNP). */
984	#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
985	#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
986	/** Bit 1 - 47 - Translation table base address. */
987	#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
988	#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR) >> 1)
989	/** Bit 48 - 63 - ASID. */
990	#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
991	#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
992	/** @} */
993
994	/** @} */
995
996	#endif /* !IPRT_INCLUDED_armv8_h */
997

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/iprt/armv8.h@ 99577

Download in other formats: