x86.h@ 54878

Last change on this file since 54878 was 54862, checked in by vboxsync, 10 years ago
Corrected x86.h/mac typo.
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2014 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** The status bits commonly updated by arithmetic instructions. */
215	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
216	/** @} */
217
218
219	/** CPUID Feature information - ECX.
220	* CPUID query with EAX=1.
221	*/
222	#ifndef VBOX_FOR_DTRACE_LIB
223	typedef struct X86CPUIDFEATECX
224	{
225	/** Bit 0 - SSE3 - Supports SSE3 or not. */
226	unsigned u1SSE3 : 1;
227	/** Bit 1 - PCLMULQDQ. */
228	unsigned u1PCLMULQDQ : 1;
229	/** Bit 2 - DS Area 64-bit layout. */
230	unsigned u1DTE64 : 1;
231	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
232	unsigned u1Monitor : 1;
233	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
234	unsigned u1CPLDS : 1;
235	/** Bit 5 - VMX - Virtual Machine Technology. */
236	unsigned u1VMX : 1;
237	/** Bit 6 - SMX: Safer Mode Extensions. */
238	unsigned u1SMX : 1;
239	/** Bit 7 - EST - Enh. SpeedStep Tech. */
240	unsigned u1EST : 1;
241	/** Bit 8 - TM2 - Terminal Monitor 2. */
242	unsigned u1TM2 : 1;
243	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
244	unsigned u1SSSE3 : 1;
245	/** Bit 10 - CNTX-ID - L1 Context ID. */
246	unsigned u1CNTXID : 1;
247	/** Bit 11 - Reserved. */
248	unsigned u1Reserved1 : 1;
249	/** Bit 12 - FMA. */
250	unsigned u1FMA : 1;
251	/** Bit 13 - CX16 - CMPXCHG16B. */
252	unsigned u1CX16 : 1;
253	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
254	unsigned u1TPRUpdate : 1;
255	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
256	unsigned u1PDCM : 1;
257	/** Bit 16 - Reserved. */
258	unsigned u1Reserved2 : 1;
259	/** Bit 17 - PCID - Process-context identifiers. */
260	unsigned u1PCID : 1;
261	/** Bit 18 - Direct Cache Access. */
262	unsigned u1DCA : 1;
263	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
264	unsigned u1SSE4_1 : 1;
265	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
266	unsigned u1SSE4_2 : 1;
267	/** Bit 21 - x2APIC. */
268	unsigned u1x2APIC : 1;
269	/** Bit 22 - MOVBE - Supports MOVBE. */
270	unsigned u1MOVBE : 1;
271	/** Bit 23 - POPCNT - Supports POPCNT. */
272	unsigned u1POPCNT : 1;
273	/** Bit 24 - TSC-Deadline. */
274	unsigned u1TSCDEADLINE : 1;
275	/** Bit 25 - AES. */
276	unsigned u1AES : 1;
277	/** Bit 26 - XSAVE - Supports XSAVE. */
278	unsigned u1XSAVE : 1;
279	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
280	unsigned u1OSXSAVE : 1;
281	/** Bit 28 - AVX - Supports AVX instruction extensions. */
282	unsigned u1AVX : 1;
283	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
284	unsigned u1F16C : 1;
285	/** Bit 30 - RDRAND - Supports RDRAND. */
286	unsigned u1RDRAND : 1;
287	/** Bit 31 - Hypervisor present (we're a guest). */
288	unsigned u1HVP : 1;
289	} X86CPUIDFEATECX;
290	#else /* VBOX_FOR_DTRACE_LIB */
291	typedef uint32_t X86CPUIDFEATECX;
292	#endif /* VBOX_FOR_DTRACE_LIB */
293	/** Pointer to CPUID Feature Information - ECX. */
294	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
295	/** Pointer to const CPUID Feature Information - ECX. */
296	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
297
298
299	/** CPUID Feature Information - EDX.
300	* CPUID query with EAX=1.
301	*/
302	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
303	typedef struct X86CPUIDFEATEDX
304	{
305	/** Bit 0 - FPU - x87 FPU on Chip. */
306	unsigned u1FPU : 1;
307	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
308	unsigned u1VME : 1;
309	/** Bit 2 - DE - Debugging extensions. */
310	unsigned u1DE : 1;
311	/** Bit 3 - PSE - Page Size Extension. */
312	unsigned u1PSE : 1;
313	/** Bit 4 - TSC - Time Stamp Counter. */
314	unsigned u1TSC : 1;
315	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
316	unsigned u1MSR : 1;
317	/** Bit 6 - PAE - Physical Address Extension. */
318	unsigned u1PAE : 1;
319	/** Bit 7 - MCE - Machine Check Exception. */
320	unsigned u1MCE : 1;
321	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
322	unsigned u1CX8 : 1;
323	/** Bit 9 - APIC - APIC On-Chip. */
324	unsigned u1APIC : 1;
325	/** Bit 10 - Reserved. */
326	unsigned u1Reserved1 : 1;
327	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
328	unsigned u1SEP : 1;
329	/** Bit 12 - MTRR - Memory Type Range Registers. */
330	unsigned u1MTRR : 1;
331	/** Bit 13 - PGE - PTE Global Bit. */
332	unsigned u1PGE : 1;
333	/** Bit 14 - MCA - Machine Check Architecture. */
334	unsigned u1MCA : 1;
335	/** Bit 15 - CMOV - Conditional Move Instructions. */
336	unsigned u1CMOV : 1;
337	/** Bit 16 - PAT - Page Attribute Table. */
338	unsigned u1PAT : 1;
339	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
340	unsigned u1PSE36 : 1;
341	/** Bit 18 - PSN - Processor Serial Number. */
342	unsigned u1PSN : 1;
343	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
344	unsigned u1CLFSH : 1;
345	/** Bit 20 - Reserved. */
346	unsigned u1Reserved2 : 1;
347	/** Bit 21 - DS - Debug Store. */
348	unsigned u1DS : 1;
349	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
350	unsigned u1ACPI : 1;
351	/** Bit 23 - MMX - Intel MMX 'Technology'. */
352	unsigned u1MMX : 1;
353	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
354	unsigned u1FXSR : 1;
355	/** Bit 25 - SSE - SSE Support. */
356	unsigned u1SSE : 1;
357	/** Bit 26 - SSE2 - SSE2 Support. */
358	unsigned u1SSE2 : 1;
359	/** Bit 27 - SS - Self Snoop. */
360	unsigned u1SS : 1;
361	/** Bit 28 - HTT - Hyper-Threading Technology. */
362	unsigned u1HTT : 1;
363	/** Bit 29 - TM - Thermal Monitor. */
364	unsigned u1TM : 1;
365	/** Bit 30 - Reserved - . */
366	unsigned u1Reserved3 : 1;
367	/** Bit 31 - PBE - Pending Break Enabled. */
368	unsigned u1PBE : 1;
369	} X86CPUIDFEATEDX;
370	#else /* VBOX_FOR_DTRACE_LIB */
371	typedef uint32_t X86CPUIDFEATEDX;
372	#endif /* VBOX_FOR_DTRACE_LIB */
373	/** Pointer to CPUID Feature Information - EDX. */
374	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
375	/** Pointer to const CPUID Feature Information - EDX. */
376	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
377
378	/** @name CPUID Vendor information.
379	* CPUID query with EAX=0.
380	* @{
381	*/
382	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
383	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
384	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
385
386	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
387	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
388	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
389
390	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
391	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
392	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
393	/** @} */
394
395
396	/** @name CPUID Feature information.
397	* CPUID query with EAX=1.
398	* @{
399	*/
400	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
401	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
402	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
403	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
404	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
405	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
406	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
407	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
408	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
409	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
410	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
411	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
412	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
413	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
414	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
415	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
416	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
417	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
418	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
419	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
420	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
421	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
422	/** ECX Bit 12 - FMA. */
423	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
424	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
425	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
426	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
427	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
428	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
429	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
430	/** ECX Bit 17 - PCID - Process-context identifiers. */
431	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
432	/** ECX Bit 18 - DCA - Direct Cache Access. */
433	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
434	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
435	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
436	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
437	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
438	/** ECX Bit 21 - x2APIC support. */
439	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
440	/** ECX Bit 22 - MOVBE instruction. */
441	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
442	/** ECX Bit 23 - POPCNT instruction. */
443	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
444	/** ECX Bir 24 - TSC-Deadline. */
445	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
446	/** ECX Bit 25 - AES instructions. */
447	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
448	/** ECX Bit 26 - XSAVE instruction. */
449	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
450	/** ECX Bit 27 - OSXSAVE instruction. */
451	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
452	/** ECX Bit 28 - AVX. */
453	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
454	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
455	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT(29)
456	/** ECX Bit 30 - RDRAND instruction. */
457	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT(30)
458	/** ECX Bit 31 - Hypervisor Present (software only). */
459	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
460
461
462	/** Bit 0 - FPU - x87 FPU on Chip. */
463	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
464	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
465	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
466	/** Bit 2 - DE - Debugging extensions. */
467	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
468	/** Bit 3 - PSE - Page Size Extension. */
469	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
470	/** Bit 4 - TSC - Time Stamp Counter. */
471	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
472	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
473	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
474	/** Bit 6 - PAE - Physical Address Extension. */
475	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
476	/** Bit 7 - MCE - Machine Check Exception. */
477	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
478	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
479	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
480	/** Bit 9 - APIC - APIC On-Chip. */
481	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
482	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
483	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
484	/** Bit 12 - MTRR - Memory Type Range Registers. */
485	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
486	/** Bit 13 - PGE - PTE Global Bit. */
487	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
488	/** Bit 14 - MCA - Machine Check Architecture. */
489	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
490	/** Bit 15 - CMOV - Conditional Move Instructions. */
491	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
492	/** Bit 16 - PAT - Page Attribute Table. */
493	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
494	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
495	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
496	/** Bit 18 - PSN - Processor Serial Number. */
497	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
498	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
499	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
500	/** Bit 21 - DS - Debug Store. */
501	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
502	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
503	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
504	/** Bit 23 - MMX - Intel MMX Technology. */
505	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
506	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
507	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
508	/** Bit 25 - SSE - SSE Support. */
509	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
510	/** Bit 26 - SSE2 - SSE2 Support. */
511	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
512	/** Bit 27 - SS - Self Snoop. */
513	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
514	/** Bit 28 - HTT - Hyper-Threading Technology. */
515	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
516	/** Bit 29 - TM - Therm. Monitor. */
517	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
518	/** Bit 31 - PBE - Pending Break Enabled. */
519	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
520	/** @} */
521
522	/** @name CPUID mwait/monitor information.
523	* CPUID query with EAX=5.
524	* @{
525	*/
526	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
527	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
528	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
529	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
530	/** @} */
531
532
533	/** @name CPUID Structured Extended Feature information.
534	* CPUID query with EAX=7.
535	* @{
536	*/
537	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
538	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
539	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
540	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
541	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
542	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
543	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
544	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
545	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
546	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT(5)
547	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
548	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
549	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
550	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
551	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
552	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
553	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
554	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
555	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
556	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
557	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
558	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
559	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
560	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT(13)
561	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
562	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
563	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
564	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
565	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
566	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
567	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
568	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT(18)
569	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
570	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
571	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
572	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
573	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
574	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT(23)
575	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
576	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
577	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
578	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
579	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
580	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
581	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
582	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
583	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
584	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
585
586	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
587	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT(0)
588	/** @} */
589
590
591	/** @name CPUID Extended Feature information.
592	* CPUID query with EAX=0x80000001.
593	* @{
594	*/
595	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
596	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
597
598	/** EDX Bit 11 - SYSCALL/SYSRET. */
599	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
600	/** EDX Bit 20 - No-Execute/Execute-Disable. */
601	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
602	/** EDX Bit 26 - 1 GB large page. */
603	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
604	/** EDX Bit 27 - RDTSCP. */
605	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
606	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
607	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
608	/** @}*/
609
610	/** @name CPUID AMD Feature information.
611	* CPUID query with EAX=0x80000001.
612	* @{
613	*/
614	/** Bit 0 - FPU - x87 FPU on Chip. */
615	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
616	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
617	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
618	/** Bit 2 - DE - Debugging extensions. */
619	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
620	/** Bit 3 - PSE - Page Size Extension. */
621	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
622	/** Bit 4 - TSC - Time Stamp Counter. */
623	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
624	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
625	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
626	/** Bit 6 - PAE - Physical Address Extension. */
627	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
628	/** Bit 7 - MCE - Machine Check Exception. */
629	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
630	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
631	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
632	/** Bit 9 - APIC - APIC On-Chip. */
633	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
634	/** Bit 12 - MTRR - Memory Type Range Registers. */
635	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
636	/** Bit 13 - PGE - PTE Global Bit. */
637	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
638	/** Bit 14 - MCA - Machine Check Architecture. */
639	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
640	/** Bit 15 - CMOV - Conditional Move Instructions. */
641	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
642	/** Bit 16 - PAT - Page Attribute Table. */
643	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
644	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
645	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
646	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
647	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
648	/** Bit 23 - MMX - Intel MMX Technology. */
649	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
650	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
651	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
652	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
653	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
654	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
655	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
656	/** Bit 31 - 3DNOW - AMD 3DNow. */
657	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
658
659	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
660	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
661	/** Bit 2 - SVM - AMD VM extensions. */
662	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
663	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
664	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
665	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
666	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
667	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
668	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
669	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
670	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
671	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
672	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
673	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
674	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
675	/** Bit 9 - OSVW - AMD OS visible workaround. */
676	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
677	/** Bit 10 - IBS - Instruct based sampling. */
678	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
679	/** Bit 11 - SSE5 - SSE5 instruction support. */
680	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
681	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
682	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
683	/** Bit 13 - WDT - AMD Watchdog timer support. */
684	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
685	/** Bit 15 - LWP - Lightweight profiling support. */
686	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT(15)
687	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
688	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT(16)
689	/** Bit 19 - NodeId - Indicates support for
690	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
691	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT(19)
692	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
693	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT(21)
694	/** Bit 22 - TopologyExtensions - . */
695	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT(22)
696	/** @} */
697
698
699	/** @name CPUID AMD Feature information.
700	* CPUID query with EAX=0x80000007.
701	* @{
702	*/
703	/** Bit 0 - TS - Temperature Sensor. */
704	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
705	/** Bit 1 - FID - Frequency ID Control. */
706	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
707	/** Bit 2 - VID - Voltage ID Control. */
708	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
709	/** Bit 3 - TTP - THERMTRIP. */
710	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
711	/** Bit 4 - TM - Hardware Thermal Control. */
712	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
713	/** Bit 5 - STC - Software Thermal Control. */
714	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
715	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
716	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
717	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
718	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
719	/** Bit 8 - TSCINVAR - TSC Invariant. */
720	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
721	/** Bit 9 - CPB - TSC Invariant. */
722	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
723	/** Bit 10 - EffFreqRO - MPERF/APERF. */
724	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
725	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
726	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
727	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
728	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
729	/** @} */
730
731
732	/** @name CR0
733	* @{ */
734	/** Bit 0 - PE - Protection Enabled */
735	#define X86_CR0_PE RT_BIT(0)
736	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
737	/** Bit 1 - MP - Monitor Coprocessor */
738	#define X86_CR0_MP RT_BIT(1)
739	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
740	/** Bit 2 - EM - Emulation. */
741	#define X86_CR0_EM RT_BIT(2)
742	#define X86_CR0_EMULATE_FPU RT_BIT(2)
743	/** Bit 3 - TS - Task Switch. */
744	#define X86_CR0_TS RT_BIT(3)
745	#define X86_CR0_TASK_SWITCH RT_BIT(3)
746	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
747	#define X86_CR0_ET RT_BIT(4)
748	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
749	/** Bit 5 - NE - Numeric error. */
750	#define X86_CR0_NE RT_BIT(5)
751	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
752	/** Bit 16 - WP - Write Protect. */
753	#define X86_CR0_WP RT_BIT(16)
754	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
755	/** Bit 18 - AM - Alignment Mask. */
756	#define X86_CR0_AM RT_BIT(18)
757	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
758	/** Bit 29 - NW - Not Write-though. */
759	#define X86_CR0_NW RT_BIT(29)
760	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
761	/** Bit 30 - WP - Cache Disable. */
762	#define X86_CR0_CD RT_BIT(30)
763	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
764	/** Bit 31 - PG - Paging. */
765	#define X86_CR0_PG RT_BIT(31)
766	#define X86_CR0_PAGING RT_BIT(31)
767	/** @} */
768
769
770	/** @name CR3
771	* @{ */
772	/** Bit 3 - PWT - Page-level Writes Transparent. */
773	#define X86_CR3_PWT RT_BIT(3)
774	/** Bit 4 - PCD - Page-level Cache Disable. */
775	#define X86_CR3_PCD RT_BIT(4)
776	/** Bits 12-31 - - Page directory page number. */
777	#define X86_CR3_PAGE_MASK (0xfffff000)
778	/** Bits 5-31 - - PAE Page directory page number. */
779	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
780	/** Bits 12-51 - - AMD64 Page directory page number. */
781	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
782	/** @} */
783
784
785	/** @name CR4
786	* @{ */
787	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
788	#define X86_CR4_VME RT_BIT(0)
789	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
790	#define X86_CR4_PVI RT_BIT(1)
791	/** Bit 2 - TSD - Time Stamp Disable. */
792	#define X86_CR4_TSD RT_BIT(2)
793	/** Bit 3 - DE - Debugging Extensions. */
794	#define X86_CR4_DE RT_BIT(3)
795	/** Bit 4 - PSE - Page Size Extension. */
796	#define X86_CR4_PSE RT_BIT(4)
797	/** Bit 5 - PAE - Physical Address Extension. */
798	#define X86_CR4_PAE RT_BIT(5)
799	/** Bit 6 - MCE - Machine-Check Enable. */
800	#define X86_CR4_MCE RT_BIT(6)
801	/** Bit 7 - PGE - Page Global Enable. */
802	#define X86_CR4_PGE RT_BIT(7)
803	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
804	#define X86_CR4_PCE RT_BIT(8)
805	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
806	#define X86_CR4_OSFXSR RT_BIT(9)
807	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
808	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
809	/** Bit 13 - VMXE - VMX mode is enabled. */
810	#define X86_CR4_VMXE RT_BIT(13)
811	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
812	#define X86_CR4_SMXE RT_BIT(14)
813	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
814	#define X86_CR4_PCIDE RT_BIT(17)
815	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
816	* extended states. */
817	#define X86_CR4_OSXSAVE RT_BIT(18)
818	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
819	#define X86_CR4_SMEP RT_BIT(20)
820	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
821	#define X86_CR4_SMAP RT_BIT(21)
822	/** @} */
823
824
825	/** @name DR6
826	* @{ */
827	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
828	#define X86_DR6_B0 RT_BIT(0)
829	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
830	#define X86_DR6_B1 RT_BIT(1)
831	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
832	#define X86_DR6_B2 RT_BIT(2)
833	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
834	#define X86_DR6_B3 RT_BIT(3)
835	/** Mask of all the Bx bits. */
836	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
837	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
838	#define X86_DR6_BD RT_BIT(13)
839	/** Bit 14 - BS - Single step */
840	#define X86_DR6_BS RT_BIT(14)
841	/** Bit 15 - BT - Task switch. (TSS T bit.) */
842	#define X86_DR6_BT RT_BIT(15)
843	/** Value of DR6 after powerup/reset. */
844	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
845	/** Bits which must be 1s in DR6. */
846	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
847	/** Bits which must be 0s in DR6. */
848	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
849	/** Bits which must be 0s on writes to DR6. */
850	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
851	/** @} */
852
853	/** Get the DR6.Bx bit for a the given breakpoint. */
854	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
855
856
857	/** @name DR7
858	* @{ */
859	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
860	#define X86_DR7_L0 RT_BIT(0)
861	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
862	#define X86_DR7_G0 RT_BIT(1)
863	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
864	#define X86_DR7_L1 RT_BIT(2)
865	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
866	#define X86_DR7_G1 RT_BIT(3)
867	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
868	#define X86_DR7_L2 RT_BIT(4)
869	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
870	#define X86_DR7_G2 RT_BIT(5)
871	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
872	#define X86_DR7_L3 RT_BIT(6)
873	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
874	#define X86_DR7_G3 RT_BIT(7)
875	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
876	#define X86_DR7_LE RT_BIT(8)
877	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
878	#define X86_DR7_GE RT_BIT(9)
879
880	/** L0, L1, L2, and L3. */
881	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
882	/** L0, L1, L2, and L3. */
883	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
884
885	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
886	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
887	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
888	* instruction is executed.
889	* @see http://www.rcollins.org/secrets/DR7.html */
890	#define X86_DR7_ICE_IR RT_BIT(12)
891	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
892	* any DR register is accessed. */
893	#define X86_DR7_GD RT_BIT(13)
894	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
895	* Pentium. */
896	#define X86_DR7_ICE_TR1 RT_BIT(14)
897	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
898	#define X86_DR7_ICE_TR2 RT_BIT(15)
899	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
900	#define X86_DR7_RW0_MASK (3 << 16)
901	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
902	#define X86_DR7_LEN0_MASK (3 << 18)
903	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
904	#define X86_DR7_RW1_MASK (3 << 20)
905	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
906	#define X86_DR7_LEN1_MASK (3 << 22)
907	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
908	#define X86_DR7_RW2_MASK (3 << 24)
909	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
910	#define X86_DR7_LEN2_MASK (3 << 26)
911	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
912	#define X86_DR7_RW3_MASK (3 << 28)
913	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
914	#define X86_DR7_LEN3_MASK (3 << 30)
915
916	/** Bits which reads as 1s. */
917	#define X86_DR7_RA1_MASK (RT_BIT(10))
918	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
919	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
920	/** Bits which must be 0s when writing to DR7. */
921	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
922
923	/** Calcs the L bit of Nth breakpoint.
924	* @param iBp The breakpoint number [0..3].
925	*/
926	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
927
928	/** Calcs the G bit of Nth breakpoint.
929	* @param iBp The breakpoint number [0..3].
930	*/
931	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
932
933	/** Calcs the L and G bits of Nth breakpoint.
934	* @param iBp The breakpoint number [0..3].
935	*/
936	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
937
938	/** @name Read/Write values.
939	* @{ */
940	/** Break on instruction fetch only. */
941	#define X86_DR7_RW_EO 0U
942	/** Break on write only. */
943	#define X86_DR7_RW_WO 1U
944	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
945	#define X86_DR7_RW_IO 2U
946	/** Break on read or write (but not instruction fetches). */
947	#define X86_DR7_RW_RW 3U
948	/** @} */
949
950	/** Shifts a X86_DR7_RW_* value to its right place.
951	* @param iBp The breakpoint number [0..3].
952	* @param fRw One of the X86_DR7_RW_* value.
953	*/
954	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
955
956	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
957	* one of the X86_DR7_RW_XXX constants).
958	*
959	* @returns X86_DR7_RW_XXX
960	* @param uDR7 DR7 value
961	* @param iBp The breakpoint number [0..3].
962	*/
963	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
964
965	/** R/W0, R/W1, R/W2, and R/W3. */
966	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
967
968	#ifndef VBOX_FOR_DTRACE_LIB
969	/** Checks if there are any I/O breakpoint types configured in the RW
970	* registers. Does NOT check if these are enabled, sorry. */
971	# define X86_DR7_ANY_RW_IO(uDR7) \
972	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
973	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
974	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
975	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
976	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
977	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
978	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
979	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
980	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
981	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
982	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
983	#endif /* !VBOX_FOR_DTRACE_LIB */
984
985	/** @name Length values.
986	* @{ */
987	#define X86_DR7_LEN_BYTE 0U
988	#define X86_DR7_LEN_WORD 1U
989	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
990	#define X86_DR7_LEN_DWORD 3U
991	/** @} */
992
993	/** Shifts a X86_DR7_LEN_* value to its right place.
994	* @param iBp The breakpoint number [0..3].
995	* @param cb One of the X86_DR7_LEN_* values.
996	*/
997	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
998
999	/** Fetch the breakpoint length bits from the DR7 value.
1000	* @param uDR7 DR7 value
1001	* @param iBp The breakpoint number [0..3].
1002	*/
1003	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1004
1005	/** Mask used to check if any breakpoints are enabled. */
1006	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1007
1008	/** LEN0, LEN1, LEN2, and LEN3. */
1009	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1010	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1011	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1012
1013	/** Value of DR7 after powerup/reset. */
1014	#define X86_DR7_INIT_VAL 0x400
1015	/** @} */
1016
1017
1018	/** @name Machine Specific Registers
1019	* @{
1020	*/
1021	/** Machine check address register (P5). */
1022	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1023	/** Machine check type register (P5). */
1024	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1025	/** Time Stamp Counter. */
1026	#define MSR_IA32_TSC 0x10
1027	#define MSR_IA32_CESR UINT32_C(0x00000011)
1028	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1029	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1030
1031	#define MSR_IA32_PLATFORM_ID 0x17
1032
1033	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1034	# define MSR_IA32_APICBASE 0x1b
1035	/** Local APIC enabled. */
1036	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1037	/** X2APIC enabled (requires the EN bit to be set). */
1038	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1039	/** The processor is the boot strap processor (BSP). */
1040	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1041	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1042	* width. */
1043	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1044	#endif
1045
1046	/** Undocumented intel MSR for reporting thread and core counts.
1047	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1048	* first 16 bits is the thread count. The next 16 bits the core count, except
1049	* on Westmere where it seems it's only the next 4 bits for some reason. */
1050	#define MSR_CORE_THREAD_COUNT 0x35
1051
1052	/** CPU Feature control. */
1053	#define MSR_IA32_FEATURE_CONTROL 0x3A
1054	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
1055	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT(1)
1056	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
1057
1058	/** Per-processor TSC adjust MSR. */
1059	#define MSR_IA32_TSC_ADJUST 0x3B
1060
1061	/** BIOS update trigger (microcode update). */
1062	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1063
1064	/** BIOS update signature (microcode). */
1065	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1066
1067	/** General performance counter no. 0. */
1068	#define MSR_IA32_PMC0 0xC1
1069	/** General performance counter no. 1. */
1070	#define MSR_IA32_PMC1 0xC2
1071	/** General performance counter no. 2. */
1072	#define MSR_IA32_PMC2 0xC3
1073	/** General performance counter no. 3. */
1074	#define MSR_IA32_PMC3 0xC4
1075
1076	/** Nehalem power control. */
1077	#define MSR_IA32_PLATFORM_INFO 0xCE
1078
1079	/** Get FSB clock status (Intel-specific). */
1080	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1081
1082	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1083	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1084
1085	/** C0 Maximum Frequency Clock Count */
1086	#define MSR_IA32_MPERF 0xE7
1087	/** C0 Actual Frequency Clock Count */
1088	#define MSR_IA32_APERF 0xE8
1089
1090	/** MTRR Capabilities. */
1091	#define MSR_IA32_MTRR_CAP 0xFE
1092
1093	/** Cache control/info. */
1094	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1095
1096	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1097	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1098	* R0 SS == CS + 8
1099	* R3 CS == CS + 16
1100	* R3 SS == CS + 24
1101	*/
1102	#define MSR_IA32_SYSENTER_CS 0x174
1103	/** SYSENTER_ESP - the R0 ESP. */
1104	#define MSR_IA32_SYSENTER_ESP 0x175
1105	/** SYSENTER_EIP - the R0 EIP. */
1106	#define MSR_IA32_SYSENTER_EIP 0x176
1107	#endif
1108
1109	/** Machine Check Global Capabilities Register. */
1110	#define MSR_IA32_MCG_CAP 0x179
1111	/** Machine Check Global Status Register. */
1112	#define MSR_IA32_MCG_STATUS 0x17A
1113	/** Machine Check Global Control Register. */
1114	#define MSR_IA32_MCG_CTRL 0x17B
1115
1116	/** Page Attribute Table. */
1117	#define MSR_IA32_CR_PAT 0x277
1118
1119	/** Performance counter MSRs. (Intel only) */
1120	#define MSR_IA32_PERFEVTSEL0 0x186
1121	#define MSR_IA32_PERFEVTSEL1 0x187
1122	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1123	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1124	* holds a ratio that Apple takes for TSC granularity.
1125	*
1126	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1127	#define MSR_FLEX_RATIO 0x194
1128	/** Performance state value and starting with Intel core more.
1129	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1130	#define MSR_IA32_PERF_STATUS 0x198
1131	#define MSR_IA32_PERF_CTL 0x199
1132	#define MSR_IA32_THERM_STATUS 0x19c
1133
1134	/** Enable misc. processor features (R/W). */
1135	#define MSR_IA32_MISC_ENABLE 0x1A0
1136	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1137	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1138	/** Automatic Thermal Control Circuit Enable (R/W). */
1139	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1140	/** Performance Monitoring Available (R). */
1141	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1142	/** Branch Trace Storage Unavailable (R/O). */
1143	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1144	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1145	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1146	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1147	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1148	/** If MONITOR/MWAIT is supported (R/W). */
1149	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1150	/** Limit CPUID Maxval to 3 leafs (R/W). */
1151	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1152	/** When set to 1, xTPR messages are disabled (R/W). */
1153	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1154	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1155	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1156
1157	/** Trace/Profile Resource Control (R/W) */
1158	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1159	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1160	* related Xeons. */
1161	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1162	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1163	* @{ */
1164	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1165	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1166	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1167	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1168	/** @} */
1169
1170
1171	#define IA32_MTRR_PHYSBASE0 0x200
1172	#define IA32_MTRR_PHYSMASK0 0x201
1173	#define IA32_MTRR_PHYSBASE1 0x202
1174	#define IA32_MTRR_PHYSMASK1 0x203
1175	#define IA32_MTRR_PHYSBASE2 0x204
1176	#define IA32_MTRR_PHYSMASK2 0x205
1177	#define IA32_MTRR_PHYSBASE3 0x206
1178	#define IA32_MTRR_PHYSMASK3 0x207
1179	#define IA32_MTRR_PHYSBASE4 0x208
1180	#define IA32_MTRR_PHYSMASK4 0x209
1181	#define IA32_MTRR_PHYSBASE5 0x20a
1182	#define IA32_MTRR_PHYSMASK5 0x20b
1183	#define IA32_MTRR_PHYSBASE6 0x20c
1184	#define IA32_MTRR_PHYSMASK6 0x20d
1185	#define IA32_MTRR_PHYSBASE7 0x20e
1186	#define IA32_MTRR_PHYSMASK7 0x20f
1187	#define IA32_MTRR_PHYSBASE8 0x210
1188	#define IA32_MTRR_PHYSMASK8 0x211
1189	#define IA32_MTRR_PHYSBASE9 0x212
1190	#define IA32_MTRR_PHYSMASK9 0x213
1191
1192	/** Fixed range MTRRs.
1193	* @{ */
1194	#define IA32_MTRR_FIX64K_00000 0x250
1195	#define IA32_MTRR_FIX16K_80000 0x258
1196	#define IA32_MTRR_FIX16K_A0000 0x259
1197	#define IA32_MTRR_FIX4K_C0000 0x268
1198	#define IA32_MTRR_FIX4K_C8000 0x269
1199	#define IA32_MTRR_FIX4K_D0000 0x26a
1200	#define IA32_MTRR_FIX4K_D8000 0x26b
1201	#define IA32_MTRR_FIX4K_E0000 0x26c
1202	#define IA32_MTRR_FIX4K_E8000 0x26d
1203	#define IA32_MTRR_FIX4K_F0000 0x26e
1204	#define IA32_MTRR_FIX4K_F8000 0x26f
1205	/** @} */
1206
1207	/** MTRR Default Range. */
1208	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1209
1210	#define MSR_IA32_MC0_CTL 0x400
1211	#define MSR_IA32_MC0_STATUS 0x401
1212
1213	/** Basic VMX information. */
1214	#define MSR_IA32_VMX_BASIC_INFO 0x480
1215	/** Allowed settings for pin-based VM execution controls */
1216	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1217	/** Allowed settings for proc-based VM execution controls */
1218	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1219	/** Allowed settings for the VMX exit controls. */
1220	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1221	/** Allowed settings for the VMX entry controls. */
1222	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1223	/** Misc VMX info. */
1224	#define MSR_IA32_VMX_MISC 0x485
1225	/** Fixed cleared bits in CR0. */
1226	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1227	/** Fixed set bits in CR0. */
1228	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1229	/** Fixed cleared bits in CR4. */
1230	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1231	/** Fixed set bits in CR4. */
1232	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1233	/** Information for enumerating fields in the VMCS. */
1234	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1235	/** Allowed settings for the VM-functions controls. */
1236	#define MSR_IA32_VMX_VMFUNC 0x491
1237	/** Allowed settings for secondary proc-based VM execution controls */
1238	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1239	/** EPT capabilities. */
1240	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1241	/** DS Save Area (R/W). */
1242	#define MSR_IA32_DS_AREA 0x600
1243	/** Running Average Power Limit (RAPL) power units. */
1244	#define MSR_RAPL_POWER_UNIT 0x606
1245	/** X2APIC MSR ranges. */
1246	#define MSR_IA32_X2APIC_START 0x800
1247	#define MSR_IA32_X2APIC_TPR 0x808
1248	#define MSR_IA32_X2APIC_END 0xBFF
1249
1250	/** K6 EFER - Extended Feature Enable Register. */
1251	#define MSR_K6_EFER UINT32_C(0xc0000080)
1252	/** @todo document EFER */
1253	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1254	#define MSR_K6_EFER_SCE RT_BIT(0)
1255	/** Bit 8 - LME - Long mode enabled. (R/W) */
1256	#define MSR_K6_EFER_LME RT_BIT(8)
1257	/** Bit 10 - LMA - Long mode active. (R) */
1258	#define MSR_K6_EFER_LMA RT_BIT(10)
1259	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1260	#define MSR_K6_EFER_NXE RT_BIT(11)
1261	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1262	#define MSR_K6_EFER_SVME RT_BIT(12)
1263	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1264	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1265	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1266	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1267	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1268	#define MSR_K6_EFER_TCE RT_BIT(15)
1269	/** K6 STAR - SYSCALL/RET targets. */
1270	#define MSR_K6_STAR UINT32_C(0xc0000081)
1271	/** Shift value for getting the SYSRET CS and SS value. */
1272	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1273	/** Shift value for getting the SYSCALL CS and SS value. */
1274	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1275	/** Selector mask for use after shifting. */
1276	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1277	/** The mask which give the SYSCALL EIP. */
1278	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1279	/** K6 WHCR - Write Handling Control Register. */
1280	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1281	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1282	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1283	/** K6 PSOR - Processor State Observability Register. */
1284	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1285	/** K6 PFIR - Page Flush/Invalidate Register. */
1286	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1287
1288	/** Performance counter MSRs. (AMD only) */
1289	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1290	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1291	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1292	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1293	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1294	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1295	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1296	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1297
1298	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1299	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1300	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1301	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1302	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1303	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1304	/** K8 FS.base - The 64-bit base FS register. */
1305	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1306	/** K8 GS.base - The 64-bit base GS register. */
1307	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1308	/** K8 KernelGSbase - Used with SWAPGS. */
1309	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1310	/** K8 TSC_AUX - Used with RDTSCP. */
1311	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1312	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1313	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1314	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1315	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1316	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1317	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1318	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1319	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1320	/** North bridge config? See BIOS & Kernel dev guides for
1321	* details. */
1322	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1323
1324	/** Hypertransport interrupt pending register.
1325	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1326	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1327	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1328	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1329
1330	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1331	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1332	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1333	* host state during world switch. */
1334	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1335
1336	/** @} */
1337
1338
1339	/** @name Page Table / Directory / Directory Pointers / L4.
1340	* @{
1341	*/
1342
1343	/** Page table/directory entry as an unsigned integer. */
1344	typedef uint32_t X86PGUINT;
1345	/** Pointer to a page table/directory table entry as an unsigned integer. */
1346	typedef X86PGUINT *PX86PGUINT;
1347	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1348	typedef X86PGUINT const *PCX86PGUINT;
1349
1350	/** Number of entries in a 32-bit PT/PD. */
1351	#define X86_PG_ENTRIES 1024
1352
1353
1354	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1355	typedef uint64_t X86PGPAEUINT;
1356	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1357	typedef X86PGPAEUINT *PX86PGPAEUINT;
1358	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1359	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1360
1361	/** Number of entries in a PAE PT/PD. */
1362	#define X86_PG_PAE_ENTRIES 512
1363	/** Number of entries in a PAE PDPT. */
1364	#define X86_PG_PAE_PDPE_ENTRIES 4
1365
1366	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1367	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1368	/** Number of entries in an AMD64 PDPT.
1369	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1370	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1371
1372	/** The size of a 4KB page. */
1373	#define X86_PAGE_4K_SIZE _4K
1374	/** The page shift of a 4KB page. */
1375	#define X86_PAGE_4K_SHIFT 12
1376	/** The 4KB page offset mask. */
1377	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1378	/** The 4KB page base mask for virtual addresses. */
1379	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1380	/** The 4KB page base mask for virtual addresses - 32bit version. */
1381	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1382
1383	/** The size of a 2MB page. */
1384	#define X86_PAGE_2M_SIZE _2M
1385	/** The page shift of a 2MB page. */
1386	#define X86_PAGE_2M_SHIFT 21
1387	/** The 2MB page offset mask. */
1388	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1389	/** The 2MB page base mask for virtual addresses. */
1390	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1391	/** The 2MB page base mask for virtual addresses - 32bit version. */
1392	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1393
1394	/** The size of a 4MB page. */
1395	#define X86_PAGE_4M_SIZE _4M
1396	/** The page shift of a 4MB page. */
1397	#define X86_PAGE_4M_SHIFT 22
1398	/** The 4MB page offset mask. */
1399	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1400	/** The 4MB page base mask for virtual addresses. */
1401	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1402	/** The 4MB page base mask for virtual addresses - 32bit version. */
1403	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1404
1405	/**
1406	* Check if the given address is canonical.
1407	*/
1408	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1409
1410
1411	/** @name Page Table Entry
1412	* @{
1413	*/
1414	/** Bit 0 - P - Present bit. */
1415	#define X86_PTE_BIT_P 0
1416	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1417	#define X86_PTE_BIT_RW 1
1418	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1419	#define X86_PTE_BIT_US 2
1420	/** Bit 3 - PWT - Page level write thru bit. */
1421	#define X86_PTE_BIT_PWT 3
1422	/** Bit 4 - PCD - Page level cache disable bit. */
1423	#define X86_PTE_BIT_PCD 4
1424	/** Bit 5 - A - Access bit. */
1425	#define X86_PTE_BIT_A 5
1426	/** Bit 6 - D - Dirty bit. */
1427	#define X86_PTE_BIT_D 6
1428	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1429	#define X86_PTE_BIT_PAT 7
1430	/** Bit 8 - G - Global flag. */
1431	#define X86_PTE_BIT_G 8
1432
1433	/** Bit 0 - P - Present bit mask. */
1434	#define X86_PTE_P RT_BIT(0)
1435	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1436	#define X86_PTE_RW RT_BIT(1)
1437	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1438	#define X86_PTE_US RT_BIT(2)
1439	/** Bit 3 - PWT - Page level write thru bit mask. */
1440	#define X86_PTE_PWT RT_BIT(3)
1441	/** Bit 4 - PCD - Page level cache disable bit mask. */
1442	#define X86_PTE_PCD RT_BIT(4)
1443	/** Bit 5 - A - Access bit mask. */
1444	#define X86_PTE_A RT_BIT(5)
1445	/** Bit 6 - D - Dirty bit mask. */
1446	#define X86_PTE_D RT_BIT(6)
1447	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1448	#define X86_PTE_PAT RT_BIT(7)
1449	/** Bit 8 - G - Global bit mask. */
1450	#define X86_PTE_G RT_BIT(8)
1451
1452	/** Bits 9-11 - - Available for use to system software. */
1453	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1454	/** Bits 12-31 - - Physical Page number of the next level. */
1455	#define X86_PTE_PG_MASK ( 0xfffff000 )
1456
1457	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1458	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1459	/** Bits 63 - NX - PAE/LM - No execution flag. */
1460	#define X86_PTE_PAE_NX RT_BIT_64(63)
1461	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1462	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1463	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1464	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1465	/** No bits - - LM - MBZ bits when NX is active. */
1466	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1467	/** Bits 63 - - LM - MBZ bits when no NX. */
1468	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1469
1470	/**
1471	* Page table entry.
1472	*/
1473	typedef struct X86PTEBITS
1474	{
1475	/** Flags whether(=1) or not the page is present. */
1476	unsigned u1Present : 1;
1477	/** Read(=0) / Write(=1) flag. */
1478	unsigned u1Write : 1;
1479	/** User(=1) / Supervisor (=0) flag. */
1480	unsigned u1User : 1;
1481	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1482	unsigned u1WriteThru : 1;
1483	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1484	unsigned u1CacheDisable : 1;
1485	/** Accessed flag.
1486	* Indicates that the page have been read or written to. */
1487	unsigned u1Accessed : 1;
1488	/** Dirty flag.
1489	* Indicates that the page has been written to. */
1490	unsigned u1Dirty : 1;
1491	/** Reserved / If PAT enabled, bit 2 of the index. */
1492	unsigned u1PAT : 1;
1493	/** Global flag. (Ignored in all but final level.) */
1494	unsigned u1Global : 1;
1495	/** Available for use to system software. */
1496	unsigned u3Available : 3;
1497	/** Physical Page number of the next level. */
1498	unsigned u20PageNo : 20;
1499	} X86PTEBITS;
1500	/** Pointer to a page table entry. */
1501	typedef X86PTEBITS *PX86PTEBITS;
1502	/** Pointer to a const page table entry. */
1503	typedef const X86PTEBITS *PCX86PTEBITS;
1504
1505	/**
1506	* Page table entry.
1507	*/
1508	typedef union X86PTE
1509	{
1510	/** Unsigned integer view */
1511	X86PGUINT u;
1512	/** Bit field view. */
1513	X86PTEBITS n;
1514	/** 32-bit view. */
1515	uint32_t au32[1];
1516	/** 16-bit view. */
1517	uint16_t au16[2];
1518	/** 8-bit view. */
1519	uint8_t au8[4];
1520	} X86PTE;
1521	/** Pointer to a page table entry. */
1522	typedef X86PTE *PX86PTE;
1523	/** Pointer to a const page table entry. */
1524	typedef const X86PTE *PCX86PTE;
1525
1526
1527	/**
1528	* PAE page table entry.
1529	*/
1530	typedef struct X86PTEPAEBITS
1531	{
1532	/** Flags whether(=1) or not the page is present. */
1533	uint32_t u1Present : 1;
1534	/** Read(=0) / Write(=1) flag. */
1535	uint32_t u1Write : 1;
1536	/** User(=1) / Supervisor(=0) flag. */
1537	uint32_t u1User : 1;
1538	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1539	uint32_t u1WriteThru : 1;
1540	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1541	uint32_t u1CacheDisable : 1;
1542	/** Accessed flag.
1543	* Indicates that the page have been read or written to. */
1544	uint32_t u1Accessed : 1;
1545	/** Dirty flag.
1546	* Indicates that the page has been written to. */
1547	uint32_t u1Dirty : 1;
1548	/** Reserved / If PAT enabled, bit 2 of the index. */
1549	uint32_t u1PAT : 1;
1550	/** Global flag. (Ignored in all but final level.) */
1551	uint32_t u1Global : 1;
1552	/** Available for use to system software. */
1553	uint32_t u3Available : 3;
1554	/** Physical Page number of the next level - Low Part. Don't use this. */
1555	uint32_t u20PageNoLow : 20;
1556	/** Physical Page number of the next level - High Part. Don't use this. */
1557	uint32_t u20PageNoHigh : 20;
1558	/** MBZ bits */
1559	uint32_t u11Reserved : 11;
1560	/** No Execute flag. */
1561	uint32_t u1NoExecute : 1;
1562	} X86PTEPAEBITS;
1563	/** Pointer to a page table entry. */
1564	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1565	/** Pointer to a page table entry. */
1566	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1567
1568	/**
1569	* PAE Page table entry.
1570	*/
1571	typedef union X86PTEPAE
1572	{
1573	/** Unsigned integer view */
1574	X86PGPAEUINT u;
1575	/** Bit field view. */
1576	X86PTEPAEBITS n;
1577	/** 32-bit view. */
1578	uint32_t au32[2];
1579	/** 16-bit view. */
1580	uint16_t au16[4];
1581	/** 8-bit view. */
1582	uint8_t au8[8];
1583	} X86PTEPAE;
1584	/** Pointer to a PAE page table entry. */
1585	typedef X86PTEPAE *PX86PTEPAE;
1586	/** Pointer to a const PAE page table entry. */
1587	typedef const X86PTEPAE *PCX86PTEPAE;
1588	/** @} */
1589
1590	/**
1591	* Page table.
1592	*/
1593	typedef struct X86PT
1594	{
1595	/** PTE Array. */
1596	X86PTE a[X86_PG_ENTRIES];
1597	} X86PT;
1598	/** Pointer to a page table. */
1599	typedef X86PT *PX86PT;
1600	/** Pointer to a const page table. */
1601	typedef const X86PT *PCX86PT;
1602
1603	/** The page shift to get the PT index. */
1604	#define X86_PT_SHIFT 12
1605	/** The PT index mask (apply to a shifted page address). */
1606	#define X86_PT_MASK 0x3ff
1607
1608
1609	/**
1610	* Page directory.
1611	*/
1612	typedef struct X86PTPAE
1613	{
1614	/** PTE Array. */
1615	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1616	} X86PTPAE;
1617	/** Pointer to a page table. */
1618	typedef X86PTPAE *PX86PTPAE;
1619	/** Pointer to a const page table. */
1620	typedef const X86PTPAE *PCX86PTPAE;
1621
1622	/** The page shift to get the PA PTE index. */
1623	#define X86_PT_PAE_SHIFT 12
1624	/** The PAE PT index mask (apply to a shifted page address). */
1625	#define X86_PT_PAE_MASK 0x1ff
1626
1627
1628	/** @name 4KB Page Directory Entry
1629	* @{
1630	*/
1631	/** Bit 0 - P - Present bit. */
1632	#define X86_PDE_P RT_BIT(0)
1633	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1634	#define X86_PDE_RW RT_BIT(1)
1635	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1636	#define X86_PDE_US RT_BIT(2)
1637	/** Bit 3 - PWT - Page level write thru bit. */
1638	#define X86_PDE_PWT RT_BIT(3)
1639	/** Bit 4 - PCD - Page level cache disable bit. */
1640	#define X86_PDE_PCD RT_BIT(4)
1641	/** Bit 5 - A - Access bit. */
1642	#define X86_PDE_A RT_BIT(5)
1643	/** Bit 7 - PS - Page size attribute.
1644	* Clear mean 4KB pages, set means large pages (2/4MB). */
1645	#define X86_PDE_PS RT_BIT(7)
1646	/** Bits 9-11 - - Available for use to system software. */
1647	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1648	/** Bits 12-31 - - Physical Page number of the next level. */
1649	#define X86_PDE_PG_MASK ( 0xfffff000 )
1650
1651	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1652	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1653	/** Bits 63 - NX - PAE/LM - No execution flag. */
1654	#define X86_PDE_PAE_NX RT_BIT_64(63)
1655	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1656	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1657	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1658	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1659	/** Bit 7 - - LM - MBZ bits when NX is active. */
1660	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1661	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1662	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1663
1664	/**
1665	* Page directory entry.
1666	*/
1667	typedef struct X86PDEBITS
1668	{
1669	/** Flags whether(=1) or not the page is present. */
1670	unsigned u1Present : 1;
1671	/** Read(=0) / Write(=1) flag. */
1672	unsigned u1Write : 1;
1673	/** User(=1) / Supervisor (=0) flag. */
1674	unsigned u1User : 1;
1675	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1676	unsigned u1WriteThru : 1;
1677	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1678	unsigned u1CacheDisable : 1;
1679	/** Accessed flag.
1680	* Indicates that the page has been read or written to. */
1681	unsigned u1Accessed : 1;
1682	/** Reserved / Ignored (dirty bit). */
1683	unsigned u1Reserved0 : 1;
1684	/** Size bit if PSE is enabled - in any event it's 0. */
1685	unsigned u1Size : 1;
1686	/** Reserved / Ignored (global bit). */
1687	unsigned u1Reserved1 : 1;
1688	/** Available for use to system software. */
1689	unsigned u3Available : 3;
1690	/** Physical Page number of the next level. */
1691	unsigned u20PageNo : 20;
1692	} X86PDEBITS;
1693	/** Pointer to a page directory entry. */
1694	typedef X86PDEBITS *PX86PDEBITS;
1695	/** Pointer to a const page directory entry. */
1696	typedef const X86PDEBITS *PCX86PDEBITS;
1697
1698
1699	/**
1700	* PAE page directory entry.
1701	*/
1702	typedef struct X86PDEPAEBITS
1703	{
1704	/** Flags whether(=1) or not the page is present. */
1705	uint32_t u1Present : 1;
1706	/** Read(=0) / Write(=1) flag. */
1707	uint32_t u1Write : 1;
1708	/** User(=1) / Supervisor (=0) flag. */
1709	uint32_t u1User : 1;
1710	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1711	uint32_t u1WriteThru : 1;
1712	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1713	uint32_t u1CacheDisable : 1;
1714	/** Accessed flag.
1715	* Indicates that the page has been read or written to. */
1716	uint32_t u1Accessed : 1;
1717	/** Reserved / Ignored (dirty bit). */
1718	uint32_t u1Reserved0 : 1;
1719	/** Size bit if PSE is enabled - in any event it's 0. */
1720	uint32_t u1Size : 1;
1721	/** Reserved / Ignored (global bit). / */
1722	uint32_t u1Reserved1 : 1;
1723	/** Available for use to system software. */
1724	uint32_t u3Available : 3;
1725	/** Physical Page number of the next level - Low Part. Don't use! */
1726	uint32_t u20PageNoLow : 20;
1727	/** Physical Page number of the next level - High Part. Don't use! */
1728	uint32_t u20PageNoHigh : 20;
1729	/** MBZ bits */
1730	uint32_t u11Reserved : 11;
1731	/** No Execute flag. */
1732	uint32_t u1NoExecute : 1;
1733	} X86PDEPAEBITS;
1734	/** Pointer to a page directory entry. */
1735	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1736	/** Pointer to a const page directory entry. */
1737	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1738
1739	/** @} */
1740
1741
1742	/** @name 2/4MB Page Directory Entry
1743	* @{
1744	*/
1745	/** Bit 0 - P - Present bit. */
1746	#define X86_PDE4M_P RT_BIT(0)
1747	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1748	#define X86_PDE4M_RW RT_BIT(1)
1749	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1750	#define X86_PDE4M_US RT_BIT(2)
1751	/** Bit 3 - PWT - Page level write thru bit. */
1752	#define X86_PDE4M_PWT RT_BIT(3)
1753	/** Bit 4 - PCD - Page level cache disable bit. */
1754	#define X86_PDE4M_PCD RT_BIT(4)
1755	/** Bit 5 - A - Access bit. */
1756	#define X86_PDE4M_A RT_BIT(5)
1757	/** Bit 6 - D - Dirty bit. */
1758	#define X86_PDE4M_D RT_BIT(6)
1759	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1760	#define X86_PDE4M_PS RT_BIT(7)
1761	/** Bit 8 - G - Global flag. */
1762	#define X86_PDE4M_G RT_BIT(8)
1763	/** Bits 9-11 - AVL - Available for use to system software. */
1764	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1765	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1766	#define X86_PDE4M_PAT RT_BIT(12)
1767	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1768	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1769	/** Bits 22-31 - - Physical Page number. */
1770	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1771	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1772	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1773	/** The number of bits to the high part of the page number. */
1774	#define X86_PDE4M_PG_HIGH_SHIFT 19
1775	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1776	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1777
1778	/** Bits 21-51 - - PAE/LM - Physical Page number.
1779	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1780	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1781	/** Bits 63 - NX - PAE/LM - No execution flag. */
1782	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1783	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1784	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1785	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1786	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1787	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1788	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1789	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1790	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1791
1792	/**
1793	* 4MB page directory entry.
1794	*/
1795	typedef struct X86PDE4MBITS
1796	{
1797	/** Flags whether(=1) or not the page is present. */
1798	unsigned u1Present : 1;
1799	/** Read(=0) / Write(=1) flag. */
1800	unsigned u1Write : 1;
1801	/** User(=1) / Supervisor (=0) flag. */
1802	unsigned u1User : 1;
1803	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1804	unsigned u1WriteThru : 1;
1805	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1806	unsigned u1CacheDisable : 1;
1807	/** Accessed flag.
1808	* Indicates that the page have been read or written to. */
1809	unsigned u1Accessed : 1;
1810	/** Dirty flag.
1811	* Indicates that the page has been written to. */
1812	unsigned u1Dirty : 1;
1813	/** Page size flag - always 1 for 4MB entries. */
1814	unsigned u1Size : 1;
1815	/** Global flag. */
1816	unsigned u1Global : 1;
1817	/** Available for use to system software. */
1818	unsigned u3Available : 3;
1819	/** Reserved / If PAT enabled, bit 2 of the index. */
1820	unsigned u1PAT : 1;
1821	/** Bits 32-39 of the page number on AMD64.
1822	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1823	unsigned u8PageNoHigh : 8;
1824	/** Reserved. */
1825	unsigned u1Reserved : 1;
1826	/** Physical Page number of the page. */
1827	unsigned u10PageNo : 10;
1828	} X86PDE4MBITS;
1829	/** Pointer to a page table entry. */
1830	typedef X86PDE4MBITS *PX86PDE4MBITS;
1831	/** Pointer to a const page table entry. */
1832	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1833
1834
1835	/**
1836	* 2MB PAE page directory entry.
1837	*/
1838	typedef struct X86PDE2MPAEBITS
1839	{
1840	/** Flags whether(=1) or not the page is present. */
1841	uint32_t u1Present : 1;
1842	/** Read(=0) / Write(=1) flag. */
1843	uint32_t u1Write : 1;
1844	/** User(=1) / Supervisor(=0) flag. */
1845	uint32_t u1User : 1;
1846	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1847	uint32_t u1WriteThru : 1;
1848	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1849	uint32_t u1CacheDisable : 1;
1850	/** Accessed flag.
1851	* Indicates that the page have been read or written to. */
1852	uint32_t u1Accessed : 1;
1853	/** Dirty flag.
1854	* Indicates that the page has been written to. */
1855	uint32_t u1Dirty : 1;
1856	/** Page size flag - always 1 for 2MB entries. */
1857	uint32_t u1Size : 1;
1858	/** Global flag. */
1859	uint32_t u1Global : 1;
1860	/** Available for use to system software. */
1861	uint32_t u3Available : 3;
1862	/** Reserved / If PAT enabled, bit 2 of the index. */
1863	uint32_t u1PAT : 1;
1864	/** Reserved. */
1865	uint32_t u9Reserved : 9;
1866	/** Physical Page number of the next level - Low part. Don't use! */
1867	uint32_t u10PageNoLow : 10;
1868	/** Physical Page number of the next level - High part. Don't use! */
1869	uint32_t u20PageNoHigh : 20;
1870	/** MBZ bits */
1871	uint32_t u11Reserved : 11;
1872	/** No Execute flag. */
1873	uint32_t u1NoExecute : 1;
1874	} X86PDE2MPAEBITS;
1875	/** Pointer to a 2MB PAE page table entry. */
1876	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1877	/** Pointer to a 2MB PAE page table entry. */
1878	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1879
1880	/** @} */
1881
1882	/**
1883	* Page directory entry.
1884	*/
1885	typedef union X86PDE
1886	{
1887	/** Unsigned integer view. */
1888	X86PGUINT u;
1889	/** Normal view. */
1890	X86PDEBITS n;
1891	/** 4MB view (big). */
1892	X86PDE4MBITS b;
1893	/** 8 bit unsigned integer view. */
1894	uint8_t au8[4];
1895	/** 16 bit unsigned integer view. */
1896	uint16_t au16[2];
1897	/** 32 bit unsigned integer view. */
1898	uint32_t au32[1];
1899	} X86PDE;
1900	/** Pointer to a page directory entry. */
1901	typedef X86PDE *PX86PDE;
1902	/** Pointer to a const page directory entry. */
1903	typedef const X86PDE *PCX86PDE;
1904
1905	/**
1906	* PAE page directory entry.
1907	*/
1908	typedef union X86PDEPAE
1909	{
1910	/** Unsigned integer view. */
1911	X86PGPAEUINT u;
1912	/** Normal view. */
1913	X86PDEPAEBITS n;
1914	/** 2MB page view (big). */
1915	X86PDE2MPAEBITS b;
1916	/** 8 bit unsigned integer view. */
1917	uint8_t au8[8];
1918	/** 16 bit unsigned integer view. */
1919	uint16_t au16[4];
1920	/** 32 bit unsigned integer view. */
1921	uint32_t au32[2];
1922	} X86PDEPAE;
1923	/** Pointer to a page directory entry. */
1924	typedef X86PDEPAE *PX86PDEPAE;
1925	/** Pointer to a const page directory entry. */
1926	typedef const X86PDEPAE *PCX86PDEPAE;
1927
1928	/**
1929	* Page directory.
1930	*/
1931	typedef struct X86PD
1932	{
1933	/** PDE Array. */
1934	X86PDE a[X86_PG_ENTRIES];
1935	} X86PD;
1936	/** Pointer to a page directory. */
1937	typedef X86PD *PX86PD;
1938	/** Pointer to a const page directory. */
1939	typedef const X86PD *PCX86PD;
1940
1941	/** The page shift to get the PD index. */
1942	#define X86_PD_SHIFT 22
1943	/** The PD index mask (apply to a shifted page address). */
1944	#define X86_PD_MASK 0x3ff
1945
1946
1947	/**
1948	* PAE page directory.
1949	*/
1950	typedef struct X86PDPAE
1951	{
1952	/** PDE Array. */
1953	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1954	} X86PDPAE;
1955	/** Pointer to a PAE page directory. */
1956	typedef X86PDPAE *PX86PDPAE;
1957	/** Pointer to a const PAE page directory. */
1958	typedef const X86PDPAE *PCX86PDPAE;
1959
1960	/** The page shift to get the PAE PD index. */
1961	#define X86_PD_PAE_SHIFT 21
1962	/** The PAE PD index mask (apply to a shifted page address). */
1963	#define X86_PD_PAE_MASK 0x1ff
1964
1965
1966	/** @name Page Directory Pointer Table Entry (PAE)
1967	* @{
1968	*/
1969	/** Bit 0 - P - Present bit. */
1970	#define X86_PDPE_P RT_BIT(0)
1971	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1972	#define X86_PDPE_RW RT_BIT(1)
1973	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1974	#define X86_PDPE_US RT_BIT(2)
1975	/** Bit 3 - PWT - Page level write thru bit. */
1976	#define X86_PDPE_PWT RT_BIT(3)
1977	/** Bit 4 - PCD - Page level cache disable bit. */
1978	#define X86_PDPE_PCD RT_BIT(4)
1979	/** Bit 5 - A - Access bit. Long Mode only. */
1980	#define X86_PDPE_A RT_BIT(5)
1981	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1982	#define X86_PDPE_LM_PS RT_BIT(7)
1983	/** Bits 9-11 - - Available for use to system software. */
1984	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1985	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1986	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1987	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1988	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1989	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1990	#define X86_PDPE_LM_NX RT_BIT_64(63)
1991	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1992	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1993	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1994	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1995	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1996	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1997	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1998	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1999
2000
2001	/**
2002	* Page directory pointer table entry.
2003	*/
2004	typedef struct X86PDPEBITS
2005	{
2006	/** Flags whether(=1) or not the page is present. */
2007	uint32_t u1Present : 1;
2008	/** Chunk of reserved bits. */
2009	uint32_t u2Reserved : 2;
2010	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2011	uint32_t u1WriteThru : 1;
2012	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2013	uint32_t u1CacheDisable : 1;
2014	/** Chunk of reserved bits. */
2015	uint32_t u4Reserved : 4;
2016	/** Available for use to system software. */
2017	uint32_t u3Available : 3;
2018	/** Physical Page number of the next level - Low Part. Don't use! */
2019	uint32_t u20PageNoLow : 20;
2020	/** Physical Page number of the next level - High Part. Don't use! */
2021	uint32_t u20PageNoHigh : 20;
2022	/** MBZ bits */
2023	uint32_t u12Reserved : 12;
2024	} X86PDPEBITS;
2025	/** Pointer to a page directory pointer table entry. */
2026	typedef X86PDPEBITS *PX86PTPEBITS;
2027	/** Pointer to a const page directory pointer table entry. */
2028	typedef const X86PDPEBITS *PCX86PTPEBITS;
2029
2030	/**
2031	* Page directory pointer table entry. AMD64 version
2032	*/
2033	typedef struct X86PDPEAMD64BITS
2034	{
2035	/** Flags whether(=1) or not the page is present. */
2036	uint32_t u1Present : 1;
2037	/** Read(=0) / Write(=1) flag. */
2038	uint32_t u1Write : 1;
2039	/** User(=1) / Supervisor (=0) flag. */
2040	uint32_t u1User : 1;
2041	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2042	uint32_t u1WriteThru : 1;
2043	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2044	uint32_t u1CacheDisable : 1;
2045	/** Accessed flag.
2046	* Indicates that the page have been read or written to. */
2047	uint32_t u1Accessed : 1;
2048	/** Chunk of reserved bits. */
2049	uint32_t u3Reserved : 3;
2050	/** Available for use to system software. */
2051	uint32_t u3Available : 3;
2052	/** Physical Page number of the next level - Low Part. Don't use! */
2053	uint32_t u20PageNoLow : 20;
2054	/** Physical Page number of the next level - High Part. Don't use! */
2055	uint32_t u20PageNoHigh : 20;
2056	/** MBZ bits */
2057	uint32_t u11Reserved : 11;
2058	/** No Execute flag. */
2059	uint32_t u1NoExecute : 1;
2060	} X86PDPEAMD64BITS;
2061	/** Pointer to a page directory pointer table entry. */
2062	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2063	/** Pointer to a const page directory pointer table entry. */
2064	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2065
2066	/**
2067	* Page directory pointer table entry.
2068	*/
2069	typedef union X86PDPE
2070	{
2071	/** Unsigned integer view. */
2072	X86PGPAEUINT u;
2073	/** Normal view. */
2074	X86PDPEBITS n;
2075	/** AMD64 view. */
2076	X86PDPEAMD64BITS lm;
2077	/** 8 bit unsigned integer view. */
2078	uint8_t au8[8];
2079	/** 16 bit unsigned integer view. */
2080	uint16_t au16[4];
2081	/** 32 bit unsigned integer view. */
2082	uint32_t au32[2];
2083	} X86PDPE;
2084	/** Pointer to a page directory pointer table entry. */
2085	typedef X86PDPE *PX86PDPE;
2086	/** Pointer to a const page directory pointer table entry. */
2087	typedef const X86PDPE *PCX86PDPE;
2088
2089
2090	/**
2091	* Page directory pointer table.
2092	*/
2093	typedef struct X86PDPT
2094	{
2095	/** PDE Array. */
2096	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2097	} X86PDPT;
2098	/** Pointer to a page directory pointer table. */
2099	typedef X86PDPT *PX86PDPT;
2100	/** Pointer to a const page directory pointer table. */
2101	typedef const X86PDPT *PCX86PDPT;
2102
2103	/** The page shift to get the PDPT index. */
2104	#define X86_PDPT_SHIFT 30
2105	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2106	#define X86_PDPT_MASK_PAE 0x3
2107	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2108	#define X86_PDPT_MASK_AMD64 0x1ff
2109
2110	/** @} */
2111
2112
2113	/** @name Page Map Level-4 Entry (Long Mode PAE)
2114	* @{
2115	*/
2116	/** Bit 0 - P - Present bit. */
2117	#define X86_PML4E_P RT_BIT(0)
2118	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2119	#define X86_PML4E_RW RT_BIT(1)
2120	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2121	#define X86_PML4E_US RT_BIT(2)
2122	/** Bit 3 - PWT - Page level write thru bit. */
2123	#define X86_PML4E_PWT RT_BIT(3)
2124	/** Bit 4 - PCD - Page level cache disable bit. */
2125	#define X86_PML4E_PCD RT_BIT(4)
2126	/** Bit 5 - A - Access bit. */
2127	#define X86_PML4E_A RT_BIT(5)
2128	/** Bits 9-11 - - Available for use to system software. */
2129	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2130	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2131	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2132	/** Bits 8, 7 - - MBZ bits when NX is active. */
2133	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2134	/** Bits 63, 7 - - MBZ bits when no NX. */
2135	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2136	/** Bits 63 - NX - PAE - No execution flag. */
2137	#define X86_PML4E_NX RT_BIT_64(63)
2138
2139	/**
2140	* Page Map Level-4 Entry
2141	*/
2142	typedef struct X86PML4EBITS
2143	{
2144	/** Flags whether(=1) or not the page is present. */
2145	uint32_t u1Present : 1;
2146	/** Read(=0) / Write(=1) flag. */
2147	uint32_t u1Write : 1;
2148	/** User(=1) / Supervisor (=0) flag. */
2149	uint32_t u1User : 1;
2150	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2151	uint32_t u1WriteThru : 1;
2152	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2153	uint32_t u1CacheDisable : 1;
2154	/** Accessed flag.
2155	* Indicates that the page have been read or written to. */
2156	uint32_t u1Accessed : 1;
2157	/** Chunk of reserved bits. */
2158	uint32_t u3Reserved : 3;
2159	/** Available for use to system software. */
2160	uint32_t u3Available : 3;
2161	/** Physical Page number of the next level - Low Part. Don't use! */
2162	uint32_t u20PageNoLow : 20;
2163	/** Physical Page number of the next level - High Part. Don't use! */
2164	uint32_t u20PageNoHigh : 20;
2165	/** MBZ bits */
2166	uint32_t u11Reserved : 11;
2167	/** No Execute flag. */
2168	uint32_t u1NoExecute : 1;
2169	} X86PML4EBITS;
2170	/** Pointer to a page map level-4 entry. */
2171	typedef X86PML4EBITS *PX86PML4EBITS;
2172	/** Pointer to a const page map level-4 entry. */
2173	typedef const X86PML4EBITS *PCX86PML4EBITS;
2174
2175	/**
2176	* Page Map Level-4 Entry.
2177	*/
2178	typedef union X86PML4E
2179	{
2180	/** Unsigned integer view. */
2181	X86PGPAEUINT u;
2182	/** Normal view. */
2183	X86PML4EBITS n;
2184	/** 8 bit unsigned integer view. */
2185	uint8_t au8[8];
2186	/** 16 bit unsigned integer view. */
2187	uint16_t au16[4];
2188	/** 32 bit unsigned integer view. */
2189	uint32_t au32[2];
2190	} X86PML4E;
2191	/** Pointer to a page map level-4 entry. */
2192	typedef X86PML4E *PX86PML4E;
2193	/** Pointer to a const page map level-4 entry. */
2194	typedef const X86PML4E *PCX86PML4E;
2195
2196
2197	/**
2198	* Page Map Level-4.
2199	*/
2200	typedef struct X86PML4
2201	{
2202	/** PDE Array. */
2203	X86PML4E a[X86_PG_PAE_ENTRIES];
2204	} X86PML4;
2205	/** Pointer to a page map level-4. */
2206	typedef X86PML4 *PX86PML4;
2207	/** Pointer to a const page map level-4. */
2208	typedef const X86PML4 *PCX86PML4;
2209
2210	/** The page shift to get the PML4 index. */
2211	#define X86_PML4_SHIFT 39
2212	/** The PML4 index mask (apply to a shifted page address). */
2213	#define X86_PML4_MASK 0x1ff
2214
2215	/** @} */
2216
2217	/** @} */
2218
2219	/**
2220	* 32-bit protected mode FSTENV image.
2221	*/
2222	typedef struct X86FSTENV32P
2223	{
2224	uint16_t FCW;
2225	uint16_t padding1;
2226	uint16_t FSW;
2227	uint16_t padding2;
2228	uint16_t FTW;
2229	uint16_t padding3;
2230	uint32_t FPUIP;
2231	uint16_t FPUCS;
2232	uint16_t FOP;
2233	uint32_t FPUDP;
2234	uint16_t FPUDS;
2235	uint16_t padding4;
2236	} X86FSTENV32P;
2237	/** Pointer to a 32-bit protected mode FSTENV image. */
2238	typedef X86FSTENV32P *PX86FSTENV32P;
2239	/** Pointer to a const 32-bit protected mode FSTENV image. */
2240	typedef X86FSTENV32P const *PCX86FSTENV32P;
2241
2242
2243	/**
2244	* 80-bit MMX/FPU register type.
2245	*/
2246	typedef struct X86FPUMMX
2247	{
2248	uint8_t reg[10];
2249	} X86FPUMMX;
2250	/** Pointer to a 80-bit MMX/FPU register type. */
2251	typedef X86FPUMMX *PX86FPUMMX;
2252	/** Pointer to a const 80-bit MMX/FPU register type. */
2253	typedef const X86FPUMMX *PCX86FPUMMX;
2254
2255	/**
2256	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2257	* @todo verify this...
2258	*/
2259	#pragma pack(1)
2260	typedef struct X86FPUSTATE
2261	{
2262	/** 0x00 - Control word. */
2263	uint16_t FCW;
2264	/** 0x02 - Alignment word */
2265	uint16_t Dummy1;
2266	/** 0x04 - Status word. */
2267	uint16_t FSW;
2268	/** 0x06 - Alignment word */
2269	uint16_t Dummy2;
2270	/** 0x08 - Tag word */
2271	uint16_t FTW;
2272	/** 0x0a - Alignment word */
2273	uint16_t Dummy3;
2274
2275	/** 0x0c - Instruction pointer. */
2276	uint32_t FPUIP;
2277	/** 0x10 - Code selector. */
2278	uint16_t CS;
2279	/** 0x12 - Opcode. */
2280	uint16_t FOP;
2281	/** 0x14 - FOO. */
2282	uint32_t FPUOO;
2283	/** 0x18 - FOS. */
2284	uint32_t FPUOS;
2285	/** 0x1c */
2286	union
2287	{
2288	/** MMX view. */
2289	uint64_t mmx;
2290	/** FPU view - todo. */
2291	X86FPUMMX fpu;
2292	/** Extended precision floating point view. */
2293	RTFLOAT80U r80;
2294	/** Extended precision floating point view v2. */
2295	RTFLOAT80U2 r80Ex;
2296	/** 8-bit view. */
2297	uint8_t au8[16];
2298	/** 16-bit view. */
2299	uint16_t au16[8];
2300	/** 32-bit view. */
2301	uint32_t au32[4];
2302	/** 64-bit view. */
2303	uint64_t au64[2];
2304	/** 128-bit view. (yeah, very helpful) */
2305	uint128_t au128[1];
2306	} regs[8];
2307	} X86FPUSTATE;
2308	#pragma pack()
2309	/** Pointer to a FPU state. */
2310	typedef X86FPUSTATE *PX86FPUSTATE;
2311	/** Pointer to a const FPU state. */
2312	typedef const X86FPUSTATE *PCX86FPUSTATE;
2313
2314	/**
2315	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2316	*/
2317	#pragma pack(1)
2318	typedef struct X86FXSTATE
2319	{
2320	/** 0x00 - Control word. */
2321	uint16_t FCW;
2322	/** 0x02 - Status word. */
2323	uint16_t FSW;
2324	/** 0x04 - Tag word. (The upper byte is always zero.) */
2325	uint16_t FTW;
2326	/** 0x06 - Opcode. */
2327	uint16_t FOP;
2328	/** 0x08 - Instruction pointer. */
2329	uint32_t FPUIP;
2330	/** 0x0c - Code selector. */
2331	uint16_t CS;
2332	uint16_t Rsrvd1;
2333	/** 0x10 - Data pointer. */
2334	uint32_t FPUDP;
2335	/** 0x14 - Data segment */
2336	uint16_t DS;
2337	/** 0x16 */
2338	uint16_t Rsrvd2;
2339	/** 0x18 */
2340	uint32_t MXCSR;
2341	/** 0x1c */
2342	uint32_t MXCSR_MASK;
2343	/** 0x20 */
2344	union
2345	{
2346	/** MMX view. */
2347	uint64_t mmx;
2348	/** FPU view - todo. */
2349	X86FPUMMX fpu;
2350	/** Extended precision floating point view. */
2351	RTFLOAT80U r80;
2352	/** Extended precision floating point view v2 */
2353	RTFLOAT80U2 r80Ex;
2354	/** 8-bit view. */
2355	uint8_t au8[16];
2356	/** 16-bit view. */
2357	uint16_t au16[8];
2358	/** 32-bit view. */
2359	uint32_t au32[4];
2360	/** 64-bit view. */
2361	uint64_t au64[2];
2362	/** 128-bit view. (yeah, very helpful) */
2363	uint128_t au128[1];
2364	} aRegs[8];
2365	/* - offset 160 - */
2366	union
2367	{
2368	/** XMM Register view . /
2369	uint128_t xmm;
2370	/** 8-bit view. */
2371	uint8_t au8[16];
2372	/** 16-bit view. */
2373	uint16_t au16[8];
2374	/** 32-bit view. */
2375	uint32_t au32[4];
2376	/** 64-bit view. */
2377	uint64_t au64[2];
2378	/** 128-bit view. (yeah, very helpful) */
2379	uint128_t au128[1];
2380	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2381	/* - offset 416 - */
2382	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2383	/* - offset 464 - Software usable reserved bits. */
2384	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2385	} X86FXSTATE;
2386	#pragma pack()
2387	/** Pointer to a FPU Extended state. */
2388	typedef X86FXSTATE *PX86FXSTATE;
2389	/** Pointer to a const FPU Extended state. */
2390	typedef const X86FXSTATE *PCX86FXSTATE;
2391
2392	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2393	* magic. Don't forget to update x86.mac if you change this! */
2394	#define X86_OFF_FXSTATE_RSVD 0x1d0
2395	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2396	* forget to update x86.mac if you change this! */
2397	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2398	#ifndef VBOX_FOR_DTRACE_LIB
2399	AssertCompileSize(X86FXSTATE, 512);
2400	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2401	#endif
2402
2403	/** @name FPU status word flags.
2404	* @{ */
2405	/** Exception Flag: Invalid operation. */
2406	#define X86_FSW_IE RT_BIT(0)
2407	/** Exception Flag: Denormalized operand. */
2408	#define X86_FSW_DE RT_BIT(1)
2409	/** Exception Flag: Zero divide. */
2410	#define X86_FSW_ZE RT_BIT(2)
2411	/** Exception Flag: Overflow. */
2412	#define X86_FSW_OE RT_BIT(3)
2413	/** Exception Flag: Underflow. */
2414	#define X86_FSW_UE RT_BIT(4)
2415	/** Exception Flag: Precision. */
2416	#define X86_FSW_PE RT_BIT(5)
2417	/** Stack fault. */
2418	#define X86_FSW_SF RT_BIT(6)
2419	/** Error summary status. */
2420	#define X86_FSW_ES RT_BIT(7)
2421	/** Mask of exceptions flags, excluding the summary bit. */
2422	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2423	/** Mask of exceptions flags, including the summary bit. */
2424	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2425	/** Condition code 0. */
2426	#define X86_FSW_C0 RT_BIT(8)
2427	/** Condition code 1. */
2428	#define X86_FSW_C1 RT_BIT(9)
2429	/** Condition code 2. */
2430	#define X86_FSW_C2 RT_BIT(10)
2431	/** Top of the stack mask. */
2432	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2433	/** TOP shift value. */
2434	#define X86_FSW_TOP_SHIFT 11
2435	/** Mask for getting TOP value after shifting it right. */
2436	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2437	/** Get the TOP value. */
2438	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2439	/** Condition code 3. */
2440	#define X86_FSW_C3 RT_BIT(14)
2441	/** Mask of exceptions flags, including the summary bit. */
2442	#define X86_FSW_C_MASK UINT16_C(0x4700)
2443	/** FPU busy. */
2444	#define X86_FSW_B RT_BIT(15)
2445	/** @} */
2446
2447
2448	/** @name FPU control word flags.
2449	* @{ */
2450	/** Exception Mask: Invalid operation. */
2451	#define X86_FCW_IM RT_BIT(0)
2452	/** Exception Mask: Denormalized operand. */
2453	#define X86_FCW_DM RT_BIT(1)
2454	/** Exception Mask: Zero divide. */
2455	#define X86_FCW_ZM RT_BIT(2)
2456	/** Exception Mask: Overflow. */
2457	#define X86_FCW_OM RT_BIT(3)
2458	/** Exception Mask: Underflow. */
2459	#define X86_FCW_UM RT_BIT(4)
2460	/** Exception Mask: Precision. */
2461	#define X86_FCW_PM RT_BIT(5)
2462	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2463	* @remarks This includes reserved bit 6. */
2464	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2465	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2466	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2467	/** Precision control mask. */
2468	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2469	/** Precision control: 24-bit. */
2470	#define X86_FCW_PC_24 UINT16_C(0x0000)
2471	/** Precision control: Reserved. */
2472	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2473	/** Precision control: 53-bit. */
2474	#define X86_FCW_PC_53 UINT16_C(0x0200)
2475	/** Precision control: 64-bit. */
2476	#define X86_FCW_PC_64 UINT16_C(0x0300)
2477	/** Rounding control mask. */
2478	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2479	/** Rounding control: To nearest. */
2480	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2481	/** Rounding control: Down. */
2482	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2483	/** Rounding control: Up. */
2484	#define X86_FCW_RC_UP UINT16_C(0x0800)
2485	/** Rounding control: Towards zero. */
2486	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2487	/** Bits which should be zero, apparently. */
2488	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2489	/** @} */
2490
2491	/** @name SSE MXCSR
2492	* @{ */
2493	/** Exception Flag: Invalid operation. */
2494	#define X86_MSXCR_IE RT_BIT(0)
2495	/** Exception Flag: Denormalized operand. */
2496	#define X86_MSXCR_DE RT_BIT(1)
2497	/** Exception Flag: Zero divide. */
2498	#define X86_MSXCR_ZE RT_BIT(2)
2499	/** Exception Flag: Overflow. */
2500	#define X86_MSXCR_OE RT_BIT(3)
2501	/** Exception Flag: Underflow. */
2502	#define X86_MSXCR_UE RT_BIT(4)
2503	/** Exception Flag: Precision. */
2504	#define X86_MSXCR_PE RT_BIT(5)
2505
2506	/** Denormals are zero. */
2507	#define X86_MSXCR_DAZ RT_BIT(6)
2508
2509	/** Exception Mask: Invalid operation. */
2510	#define X86_MSXCR_IM RT_BIT(7)
2511	/** Exception Mask: Denormalized operand. */
2512	#define X86_MSXCR_DM RT_BIT(8)
2513	/** Exception Mask: Zero divide. */
2514	#define X86_MSXCR_ZM RT_BIT(9)
2515	/** Exception Mask: Overflow. */
2516	#define X86_MSXCR_OM RT_BIT(10)
2517	/** Exception Mask: Underflow. */
2518	#define X86_MSXCR_UM RT_BIT(11)
2519	/** Exception Mask: Precision. */
2520	#define X86_MSXCR_PM RT_BIT(12)
2521
2522	/** Rounding control mask. */
2523	#define X86_MSXCR_RC_MASK UINT16_C(0x6000)
2524	/** Rounding control: To nearest. */
2525	#define X86_MSXCR_RC_NEAREST UINT16_C(0x0000)
2526	/** Rounding control: Down. */
2527	#define X86_MSXCR_RC_DOWN UINT16_C(0x2000)
2528	/** Rounding control: Up. */
2529	#define X86_MSXCR_RC_UP UINT16_C(0x4000)
2530	/** Rounding control: Towards zero. */
2531	#define X86_MSXCR_RC_ZERO UINT16_C(0x6000)
2532
2533	/** Flush-to-zero for masked underflow. */
2534	#define X86_MSXCR_FZ RT_BIT(15)
2535
2536	/** Misaligned Exception Mask. */
2537	#define X86_MSXCR_MM RT_BIT(16)
2538	/** @} */
2539
2540
2541	/** @name Selector Descriptor
2542	* @{
2543	*/
2544
2545	#ifndef VBOX_FOR_DTRACE_LIB
2546	/**
2547	* Descriptor attributes (as seen by VT-x).
2548	*/
2549	typedef struct X86DESCATTRBITS
2550	{
2551	/** 00 - Segment Type. */
2552	unsigned u4Type : 4;
2553	/** 04 - Descriptor Type. System(=0) or code/data selector */
2554	unsigned u1DescType : 1;
2555	/** 05 - Descriptor Privilege level. */
2556	unsigned u2Dpl : 2;
2557	/** 07 - Flags selector present(=1) or not. */
2558	unsigned u1Present : 1;
2559	/** 08 - Segment limit 16-19. */
2560	unsigned u4LimitHigh : 4;
2561	/** 0c - Available for system software. */
2562	unsigned u1Available : 1;
2563	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2564	unsigned u1Long : 1;
2565	/** 0e - This flags meaning depends on the segment type. Try make sense out
2566	* of the intel manual yourself. */
2567	unsigned u1DefBig : 1;
2568	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2569	* clear byte. */
2570	unsigned u1Granularity : 1;
2571	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2572	unsigned u1Unusable : 1;
2573	} X86DESCATTRBITS;
2574	#endif /* !VBOX_FOR_DTRACE_LIB */
2575
2576	/** @name X86DESCATTR masks
2577	* @{ */
2578	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2579	#define X86DESCATTR_DT UINT32_C(0x00000010)
2580	#define X86DESCATTR_DPL UINT32_C(0x00000060)
2581	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
2582	#define X86DESCATTR_P UINT32_C(0x00000080)
2583	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2584	#define X86DESCATTR_AVL UINT32_C(0x00001000)
2585	#define X86DESCATTR_L UINT32_C(0x00002000)
2586	#define X86DESCATTR_D UINT32_C(0x00004000)
2587	#define X86DESCATTR_G UINT32_C(0x00008000)
2588	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2589	/** @} */
2590
2591	#pragma pack(1)
2592	typedef union X86DESCATTR
2593	{
2594	/** Unsigned integer view. */
2595	uint32_t u;
2596	#ifndef VBOX_FOR_DTRACE_LIB
2597	/** Normal view. */
2598	X86DESCATTRBITS n;
2599	#endif
2600	} X86DESCATTR;
2601	#pragma pack()
2602	/** Pointer to descriptor attributes. */
2603	typedef X86DESCATTR *PX86DESCATTR;
2604	/** Pointer to const descriptor attributes. */
2605	typedef const X86DESCATTR *PCX86DESCATTR;
2606
2607	#ifndef VBOX_FOR_DTRACE_LIB
2608
2609	/**
2610	* Generic descriptor table entry
2611	*/
2612	#pragma pack(1)
2613	typedef struct X86DESCGENERIC
2614	{
2615	/** 00 - Limit - Low word. */
2616	unsigned u16LimitLow : 16;
2617	/** 10 - Base address - lowe word.
2618	* Don't try set this to 24 because MSC is doing stupid things then. */
2619	unsigned u16BaseLow : 16;
2620	/** 20 - Base address - first 8 bits of high word. */
2621	unsigned u8BaseHigh1 : 8;
2622	/** 28 - Segment Type. */
2623	unsigned u4Type : 4;
2624	/** 2c - Descriptor Type. System(=0) or code/data selector */
2625	unsigned u1DescType : 1;
2626	/** 2d - Descriptor Privilege level. */
2627	unsigned u2Dpl : 2;
2628	/** 2f - Flags selector present(=1) or not. */
2629	unsigned u1Present : 1;
2630	/** 30 - Segment limit 16-19. */
2631	unsigned u4LimitHigh : 4;
2632	/** 34 - Available for system software. */
2633	unsigned u1Available : 1;
2634	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2635	unsigned u1Long : 1;
2636	/** 36 - This flags meaning depends on the segment type. Try make sense out
2637	* of the intel manual yourself. */
2638	unsigned u1DefBig : 1;
2639	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
2640	* clear byte. */
2641	unsigned u1Granularity : 1;
2642	/** 38 - Base address - highest 8 bits. */
2643	unsigned u8BaseHigh2 : 8;
2644	} X86DESCGENERIC;
2645	#pragma pack()
2646	/** Pointer to a generic descriptor entry. */
2647	typedef X86DESCGENERIC *PX86DESCGENERIC;
2648	/** Pointer to a const generic descriptor entry. */
2649	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2650
2651	/** @name Bit offsets of X86DESCGENERIC members.
2652	* @{*/
2653	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
2654	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
2655	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
2656	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
2657	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
2658	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
2659	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
2660	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
2661	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
2662	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
2663	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
2664	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
2665	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
2666	/** @} */
2667
2668	/**
2669	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2670	*/
2671	typedef struct X86DESCGATE
2672	{
2673	/** 00 - Target code segment offset - Low word.
2674	* Ignored if task-gate. */
2675	unsigned u16OffsetLow : 16;
2676	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2677	* TSS selector if task-gate. */
2678	unsigned u16Sel : 16;
2679	/** 20 - Number of parameters for a call-gate.
2680	* Ignored if interrupt-, trap- or task-gate. */
2681	unsigned u4ParmCount : 4;
2682	/** 24 - Reserved / ignored. */
2683	unsigned u4Reserved : 4;
2684	/** 28 - Segment Type. */
2685	unsigned u4Type : 4;
2686	/** 2c - Descriptor Type (0 = system). */
2687	unsigned u1DescType : 1;
2688	/** 2d - Descriptor Privilege level. */
2689	unsigned u2Dpl : 2;
2690	/** 2f - Flags selector present(=1) or not. */
2691	unsigned u1Present : 1;
2692	/** 30 - Target code segment offset - High word.
2693	* Ignored if task-gate. */
2694	unsigned u16OffsetHigh : 16;
2695	} X86DESCGATE;
2696	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2697	typedef X86DESCGATE *PX86DESCGATE;
2698	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2699	typedef const X86DESCGATE *PCX86DESCGATE;
2700
2701	#endif /* VBOX_FOR_DTRACE_LIB */
2702
2703	/**
2704	* Descriptor table entry.
2705	*/
2706	#pragma pack(1)
2707	typedef union X86DESC
2708	{
2709	#ifndef VBOX_FOR_DTRACE_LIB
2710	/** Generic descriptor view. */
2711	X86DESCGENERIC Gen;
2712	/** Gate descriptor view. */
2713	X86DESCGATE Gate;
2714	#endif
2715
2716	/** 8 bit unsigned integer view. */
2717	uint8_t au8[8];
2718	/** 16 bit unsigned integer view. */
2719	uint16_t au16[4];
2720	/** 32 bit unsigned integer view. */
2721	uint32_t au32[2];
2722	/** 64 bit unsigned integer view. */
2723	uint64_t au64[1];
2724	/** Unsigned integer view. */
2725	uint64_t u;
2726	} X86DESC;
2727	#ifndef VBOX_FOR_DTRACE_LIB
2728	AssertCompileSize(X86DESC, 8);
2729	#endif
2730	#pragma pack()
2731	/** Pointer to descriptor table entry. */
2732	typedef X86DESC *PX86DESC;
2733	/** Pointer to const descriptor table entry. */
2734	typedef const X86DESC *PCX86DESC;
2735
2736	/** @def X86DESC_BASE
2737	* Return the base address of a descriptor.
2738	*/
2739	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
2740	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2741	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2742	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2743
2744	/** @def X86DESC_LIMIT
2745	* Return the limit of a descriptor.
2746	*/
2747	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
2748	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2749	\| ( (a_pDesc)->Gen.u16LimitLow ) )
2750
2751	/** @def X86DESC_LIMIT_G
2752	* Return the limit of a descriptor with the granularity bit taken into account.
2753	* @returns Selector limit (uint32_t).
2754	* @param a_pDesc Pointer to the descriptor.
2755	*/
2756	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
2757	( (a_pDesc)->Gen.u1Granularity \
2758	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
2759	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
2760	)
2761
2762	/** @def X86DESC_GET_HID_ATTR
2763	* Get the descriptor attributes for the hidden register.
2764	*/
2765	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
2766	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2767
2768	#ifndef VBOX_FOR_DTRACE_LIB
2769
2770	/**
2771	* 64 bits generic descriptor table entry
2772	* Note: most of these bits have no meaning in long mode.
2773	*/
2774	#pragma pack(1)
2775	typedef struct X86DESC64GENERIC
2776	{
2777	/** Limit - Low word - IGNORED. */
2778	unsigned u16LimitLow : 16;
2779	/** Base address - low word. - IGNORED
2780	* Don't try set this to 24 because MSC is doing stupid things then. */
2781	unsigned u16BaseLow : 16;
2782	/** Base address - first 8 bits of high word. - IGNORED */
2783	unsigned u8BaseHigh1 : 8;
2784	/** Segment Type. */
2785	unsigned u4Type : 4;
2786	/** Descriptor Type. System(=0) or code/data selector */
2787	unsigned u1DescType : 1;
2788	/** Descriptor Privilege level. */
2789	unsigned u2Dpl : 2;
2790	/** Flags selector present(=1) or not. */
2791	unsigned u1Present : 1;
2792	/** Segment limit 16-19. - IGNORED */
2793	unsigned u4LimitHigh : 4;
2794	/** Available for system software. - IGNORED */
2795	unsigned u1Available : 1;
2796	/** Long mode flag. */
2797	unsigned u1Long : 1;
2798	/** This flags meaning depends on the segment type. Try make sense out
2799	* of the intel manual yourself. */
2800	unsigned u1DefBig : 1;
2801	/** Granularity of the limit. If set 4KB granularity is used, if
2802	* clear byte. - IGNORED */
2803	unsigned u1Granularity : 1;
2804	/** Base address - highest 8 bits. - IGNORED */
2805	unsigned u8BaseHigh2 : 8;
2806	/** Base address - bits 63-32. */
2807	unsigned u32BaseHigh3 : 32;
2808	unsigned u8Reserved : 8;
2809	unsigned u5Zeros : 5;
2810	unsigned u19Reserved : 19;
2811	} X86DESC64GENERIC;
2812	#pragma pack()
2813	/** Pointer to a generic descriptor entry. */
2814	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2815	/** Pointer to a const generic descriptor entry. */
2816	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2817
2818	/**
2819	* System descriptor table entry (64 bits)
2820	*
2821	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2822	*/
2823	#pragma pack(1)
2824	typedef struct X86DESC64SYSTEM
2825	{
2826	/** Limit - Low word. */
2827	unsigned u16LimitLow : 16;
2828	/** Base address - lowe word.
2829	* Don't try set this to 24 because MSC is doing stupid things then. */
2830	unsigned u16BaseLow : 16;
2831	/** Base address - first 8 bits of high word. */
2832	unsigned u8BaseHigh1 : 8;
2833	/** Segment Type. */
2834	unsigned u4Type : 4;
2835	/** Descriptor Type. System(=0) or code/data selector */
2836	unsigned u1DescType : 1;
2837	/** Descriptor Privilege level. */
2838	unsigned u2Dpl : 2;
2839	/** Flags selector present(=1) or not. */
2840	unsigned u1Present : 1;
2841	/** Segment limit 16-19. */
2842	unsigned u4LimitHigh : 4;
2843	/** Available for system software. */
2844	unsigned u1Available : 1;
2845	/** Reserved - 0. */
2846	unsigned u1Reserved : 1;
2847	/** This flags meaning depends on the segment type. Try make sense out
2848	* of the intel manual yourself. */
2849	unsigned u1DefBig : 1;
2850	/** Granularity of the limit. If set 4KB granularity is used, if
2851	* clear byte. */
2852	unsigned u1Granularity : 1;
2853	/** Base address - bits 31-24. */
2854	unsigned u8BaseHigh2 : 8;
2855	/** Base address - bits 63-32. */
2856	unsigned u32BaseHigh3 : 32;
2857	unsigned u8Reserved : 8;
2858	unsigned u5Zeros : 5;
2859	unsigned u19Reserved : 19;
2860	} X86DESC64SYSTEM;
2861	#pragma pack()
2862	/** Pointer to a system descriptor entry. */
2863	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2864	/** Pointer to a const system descriptor entry. */
2865	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2866
2867	/**
2868	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2869	*/
2870	typedef struct X86DESC64GATE
2871	{
2872	/** Target code segment offset - Low word. */
2873	unsigned u16OffsetLow : 16;
2874	/** Target code segment selector. */
2875	unsigned u16Sel : 16;
2876	/** Interrupt stack table for interrupt- and trap-gates.
2877	* Ignored by call-gates. */
2878	unsigned u3IST : 3;
2879	/** Reserved / ignored. */
2880	unsigned u5Reserved : 5;
2881	/** Segment Type. */
2882	unsigned u4Type : 4;
2883	/** Descriptor Type (0 = system). */
2884	unsigned u1DescType : 1;
2885	/** Descriptor Privilege level. */
2886	unsigned u2Dpl : 2;
2887	/** Flags selector present(=1) or not. */
2888	unsigned u1Present : 1;
2889	/** Target code segment offset - High word.
2890	* Ignored if task-gate. */
2891	unsigned u16OffsetHigh : 16;
2892	/** Target code segment offset - Top dword.
2893	* Ignored if task-gate. */
2894	unsigned u32OffsetTop : 32;
2895	/** Reserved / ignored / must be zero.
2896	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2897	unsigned u32Reserved : 32;
2898	} X86DESC64GATE;
2899	AssertCompileSize(X86DESC64GATE, 16);
2900	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2901	typedef X86DESC64GATE *PX86DESC64GATE;
2902	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2903	typedef const X86DESC64GATE *PCX86DESC64GATE;
2904
2905	#endif /* VBOX_FOR_DTRACE_LIB */
2906
2907	/**
2908	* Descriptor table entry.
2909	*/
2910	#pragma pack(1)
2911	typedef union X86DESC64
2912	{
2913	#ifndef VBOX_FOR_DTRACE_LIB
2914	/** Generic descriptor view. */
2915	X86DESC64GENERIC Gen;
2916	/** System descriptor view. */
2917	X86DESC64SYSTEM System;
2918	/** Gate descriptor view. */
2919	X86DESC64GATE Gate;
2920	#endif
2921
2922	/** 8 bit unsigned integer view. */
2923	uint8_t au8[16];
2924	/** 16 bit unsigned integer view. */
2925	uint16_t au16[8];
2926	/** 32 bit unsigned integer view. */
2927	uint32_t au32[4];
2928	/** 64 bit unsigned integer view. */
2929	uint64_t au64[2];
2930	} X86DESC64;
2931	#ifndef VBOX_FOR_DTRACE_LIB
2932	AssertCompileSize(X86DESC64, 16);
2933	#endif
2934	#pragma pack()
2935	/** Pointer to descriptor table entry. */
2936	typedef X86DESC64 *PX86DESC64;
2937	/** Pointer to const descriptor table entry. */
2938	typedef const X86DESC64 *PCX86DESC64;
2939
2940	/** @def X86DESC64_BASE
2941	* Return the base of a 64-bit descriptor.
2942	*/
2943	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
2944	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2945	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2946	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2947	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2948
2949
2950
2951	/** @name Host system descriptor table entry - Use with care!
2952	* @{ */
2953	/** Host system descriptor table entry. */
2954	#if HC_ARCH_BITS == 64
2955	typedef X86DESC64 X86DESCHC;
2956	#else
2957	typedef X86DESC X86DESCHC;
2958	#endif
2959	/** Pointer to a host system descriptor table entry. */
2960	#if HC_ARCH_BITS == 64
2961	typedef PX86DESC64 PX86DESCHC;
2962	#else
2963	typedef PX86DESC PX86DESCHC;
2964	#endif
2965	/** Pointer to a const host system descriptor table entry. */
2966	#if HC_ARCH_BITS == 64
2967	typedef PCX86DESC64 PCX86DESCHC;
2968	#else
2969	typedef PCX86DESC PCX86DESCHC;
2970	#endif
2971	/** @} */
2972
2973
2974	/** @name Selector Descriptor Types.
2975	* @{
2976	*/
2977
2978	/** @name Non-System Selector Types.
2979	* @{ */
2980	/** Code(=set)/Data(=clear) bit. */
2981	#define X86_SEL_TYPE_CODE 8
2982	/** Memory(=set)/System(=clear) bit. */
2983	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2984	/** Accessed bit. */
2985	#define X86_SEL_TYPE_ACCESSED 1
2986	/** Expand down bit (for data selectors only). */
2987	#define X86_SEL_TYPE_DOWN 4
2988	/** Conforming bit (for code selectors only). */
2989	#define X86_SEL_TYPE_CONF 4
2990	/** Write bit (for data selectors only). */
2991	#define X86_SEL_TYPE_WRITE 2
2992	/** Read bit (for code selectors only). */
2993	#define X86_SEL_TYPE_READ 2
2994	/** The bit number of the code segment read bit (relative to u4Type). */
2995	#define X86_SEL_TYPE_READ_BIT 1
2996
2997	/** Read only selector type. */
2998	#define X86_SEL_TYPE_RO 0
2999	/** Accessed read only selector type. */
3000	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
3001	/** Read write selector type. */
3002	#define X86_SEL_TYPE_RW 2
3003	/** Accessed read write selector type. */
3004	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
3005	/** Expand down read only selector type. */
3006	#define X86_SEL_TYPE_RO_DOWN 4
3007	/** Accessed expand down read only selector type. */
3008	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
3009	/** Expand down read write selector type. */
3010	#define X86_SEL_TYPE_RW_DOWN 6
3011	/** Accessed expand down read write selector type. */
3012	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
3013	/** Execute only selector type. */
3014	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
3015	/** Accessed execute only selector type. */
3016	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3017	/** Execute and read selector type. */
3018	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
3019	/** Accessed execute and read selector type. */
3020	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3021	/** Conforming execute only selector type. */
3022	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3023	/** Accessed Conforming execute only selector type. */
3024	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3025	/** Conforming execute and write selector type. */
3026	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3027	/** Accessed Conforming execute and write selector type. */
3028	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3029	/** @} */
3030
3031
3032	/** @name System Selector Types.
3033	* @{ */
3034	/** The TSS busy bit mask. */
3035	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3036
3037	/** Undefined system selector type. */
3038	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3039	/** 286 TSS selector. */
3040	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3041	/** LDT selector. */
3042	#define X86_SEL_TYPE_SYS_LDT 2
3043	/** 286 TSS selector - Busy. */
3044	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3045	/** 286 Callgate selector. */
3046	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3047	/** Taskgate selector. */
3048	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3049	/** 286 Interrupt gate selector. */
3050	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3051	/** 286 Trapgate selector. */
3052	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3053	/** Undefined system selector. */
3054	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3055	/** 386 TSS selector. */
3056	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3057	/** Undefined system selector. */
3058	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3059	/** 386 TSS selector - Busy. */
3060	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3061	/** 386 Callgate selector. */
3062	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3063	/** Undefined system selector. */
3064	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3065	/** 386 Interruptgate selector. */
3066	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3067	/** 386 Trapgate selector. */
3068	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3069	/** @} */
3070
3071	/** @name AMD64 System Selector Types.
3072	* @{ */
3073	/** LDT selector. */
3074	#define AMD64_SEL_TYPE_SYS_LDT 2
3075	/** TSS selector - Busy. */
3076	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3077	/** TSS selector - Busy. */
3078	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3079	/** Callgate selector. */
3080	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3081	/** Interruptgate selector. */
3082	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3083	/** Trapgate selector. */
3084	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3085	/** @} */
3086
3087	/** @} */
3088
3089
3090	/** @name Descriptor Table Entry Flag Masks.
3091	* These are for the 2nd 32-bit word of a descriptor.
3092	* @{ */
3093	/** Bits 8-11 - TYPE - Descriptor type mask. */
3094	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
3095	/** Bit 12 - S - System (=0) or Code/Data (=1). */
3096	#define X86_DESC_S RT_BIT(12)
3097	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3098	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
3099	/** Bit 15 - P - Present. */
3100	#define X86_DESC_P RT_BIT(15)
3101	/** Bit 20 - AVL - Available for system software. */
3102	#define X86_DESC_AVL RT_BIT(20)
3103	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3104	#define X86_DESC_DB RT_BIT(22)
3105	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3106	* used, if clear byte. */
3107	#define X86_DESC_G RT_BIT(23)
3108	/** @} */
3109
3110	/** @} */
3111
3112
3113	/** @name Task Segments.
3114	* @{
3115	*/
3116
3117	/**
3118	* The minimum TSS descriptor limit for 286 tasks.
3119	*/
3120	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3121
3122	/**
3123	* The minimum TSS descriptor segment limit for 386 tasks.
3124	*/
3125	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3126
3127	/**
3128	* 16-bit Task Segment (TSS).
3129	*/
3130	#pragma pack(1)
3131	typedef struct X86TSS16
3132	{
3133	/** Back link to previous task. (static) */
3134	RTSEL selPrev;
3135	/** Ring-0 stack pointer. (static) */
3136	uint16_t sp0;
3137	/** Ring-0 stack segment. (static) */
3138	RTSEL ss0;
3139	/** Ring-1 stack pointer. (static) */
3140	uint16_t sp1;
3141	/** Ring-1 stack segment. (static) */
3142	RTSEL ss1;
3143	/** Ring-2 stack pointer. (static) */
3144	uint16_t sp2;
3145	/** Ring-2 stack segment. (static) */
3146	RTSEL ss2;
3147	/** IP before task switch. */
3148	uint16_t ip;
3149	/** FLAGS before task switch. */
3150	uint16_t flags;
3151	/** AX before task switch. */
3152	uint16_t ax;
3153	/** CX before task switch. */
3154	uint16_t cx;
3155	/** DX before task switch. */
3156	uint16_t dx;
3157	/** BX before task switch. */
3158	uint16_t bx;
3159	/** SP before task switch. */
3160	uint16_t sp;
3161	/** BP before task switch. */
3162	uint16_t bp;
3163	/** SI before task switch. */
3164	uint16_t si;
3165	/** DI before task switch. */
3166	uint16_t di;
3167	/** ES before task switch. */
3168	RTSEL es;
3169	/** CS before task switch. */
3170	RTSEL cs;
3171	/** SS before task switch. */
3172	RTSEL ss;
3173	/** DS before task switch. */
3174	RTSEL ds;
3175	/** LDTR before task switch. */
3176	RTSEL selLdt;
3177	} X86TSS16;
3178	#ifndef VBOX_FOR_DTRACE_LIB
3179	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3180	#endif
3181	#pragma pack()
3182	/** Pointer to a 16-bit task segment. */
3183	typedef X86TSS16 *PX86TSS16;
3184	/** Pointer to a const 16-bit task segment. */
3185	typedef const X86TSS16 *PCX86TSS16;
3186
3187
3188	/**
3189	* 32-bit Task Segment (TSS).
3190	*/
3191	#pragma pack(1)
3192	typedef struct X86TSS32
3193	{
3194	/** Back link to previous task. (static) */
3195	RTSEL selPrev;
3196	uint16_t padding1;
3197	/** Ring-0 stack pointer. (static) */
3198	uint32_t esp0;
3199	/** Ring-0 stack segment. (static) */
3200	RTSEL ss0;
3201	uint16_t padding_ss0;
3202	/** Ring-1 stack pointer. (static) */
3203	uint32_t esp1;
3204	/** Ring-1 stack segment. (static) */
3205	RTSEL ss1;
3206	uint16_t padding_ss1;
3207	/** Ring-2 stack pointer. (static) */
3208	uint32_t esp2;
3209	/** Ring-2 stack segment. (static) */
3210	RTSEL ss2;
3211	uint16_t padding_ss2;
3212	/** Page directory for the task. (static) */
3213	uint32_t cr3;
3214	/** EIP before task switch. */
3215	uint32_t eip;
3216	/** EFLAGS before task switch. */
3217	uint32_t eflags;
3218	/** EAX before task switch. */
3219	uint32_t eax;
3220	/** ECX before task switch. */
3221	uint32_t ecx;
3222	/** EDX before task switch. */
3223	uint32_t edx;
3224	/** EBX before task switch. */
3225	uint32_t ebx;
3226	/** ESP before task switch. */
3227	uint32_t esp;
3228	/** EBP before task switch. */
3229	uint32_t ebp;
3230	/** ESI before task switch. */
3231	uint32_t esi;
3232	/** EDI before task switch. */
3233	uint32_t edi;
3234	/** ES before task switch. */
3235	RTSEL es;
3236	uint16_t padding_es;
3237	/** CS before task switch. */
3238	RTSEL cs;
3239	uint16_t padding_cs;
3240	/** SS before task switch. */
3241	RTSEL ss;
3242	uint16_t padding_ss;
3243	/** DS before task switch. */
3244	RTSEL ds;
3245	uint16_t padding_ds;
3246	/** FS before task switch. */
3247	RTSEL fs;
3248	uint16_t padding_fs;
3249	/** GS before task switch. */
3250	RTSEL gs;
3251	uint16_t padding_gs;
3252	/** LDTR before task switch. */
3253	RTSEL selLdt;
3254	uint16_t padding_ldt;
3255	/** Debug trap flag */
3256	uint16_t fDebugTrap;
3257	/** Offset relative to the TSS of the start of the I/O Bitmap
3258	* and the end of the interrupt redirection bitmap. */
3259	uint16_t offIoBitmap;
3260	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3261	uint8_t IntRedirBitmap[32];
3262	} X86TSS32;
3263	#pragma pack()
3264	/** Pointer to task segment. */
3265	typedef X86TSS32 *PX86TSS32;
3266	/** Pointer to const task segment. */
3267	typedef const X86TSS32 *PCX86TSS32;
3268
3269	/**
3270	* 64-bit Task segment.
3271	*/
3272	#pragma pack(1)
3273	typedef struct X86TSS64
3274	{
3275	/** Reserved. */
3276	uint32_t u32Reserved;
3277	/** Ring-0 stack pointer. (static) */
3278	uint64_t rsp0;
3279	/** Ring-1 stack pointer. (static) */
3280	uint64_t rsp1;
3281	/** Ring-2 stack pointer. (static) */
3282	uint64_t rsp2;
3283	/** Reserved. */
3284	uint32_t u32Reserved2[2];
3285	/* IST */
3286	uint64_t ist1;
3287	uint64_t ist2;
3288	uint64_t ist3;
3289	uint64_t ist4;
3290	uint64_t ist5;
3291	uint64_t ist6;
3292	uint64_t ist7;
3293	/* Reserved. */
3294	uint16_t u16Reserved[5];
3295	/** Offset relative to the TSS of the start of the I/O Bitmap
3296	* and the end of the interrupt redirection bitmap. */
3297	uint16_t offIoBitmap;
3298	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3299	uint8_t IntRedirBitmap[32];
3300	} X86TSS64;
3301	#pragma pack()
3302	/** Pointer to a 64-bit task segment. */
3303	typedef X86TSS64 *PX86TSS64;
3304	/** Pointer to a const 64-bit task segment. */
3305	typedef const X86TSS64 *PCX86TSS64;
3306	#ifndef VBOX_FOR_DTRACE_LIB
3307	AssertCompileSize(X86TSS64, 136);
3308	#endif
3309
3310	/** @} */
3311
3312
3313	/** @name Selectors.
3314	* @{
3315	*/
3316
3317	/**
3318	* The shift used to convert a selector from and to index an index (C).
3319	*/
3320	#define X86_SEL_SHIFT 3
3321
3322	/**
3323	* The mask used to mask off the table indicator and RPL of an selector.
3324	*/
3325	#define X86_SEL_MASK 0xfff8U
3326
3327	/**
3328	* The mask used to mask off the RPL of an selector.
3329	* This is suitable for checking for NULL selectors.
3330	*/
3331	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3332
3333	/**
3334	* The bit indicating that a selector is in the LDT and not in the GDT.
3335	*/
3336	#define X86_SEL_LDT 0x0004U
3337
3338	/**
3339	* The bit mask for getting the RPL of a selector.
3340	*/
3341	#define X86_SEL_RPL 0x0003U
3342
3343	/**
3344	* The mask covering both RPL and LDT.
3345	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3346	* checks.
3347	*/
3348	#define X86_SEL_RPL_LDT 0x0007U
3349
3350	/** @} */
3351
3352
3353	/**
3354	* x86 Exceptions/Faults/Traps.
3355	*/
3356	typedef enum X86XCPT
3357	{
3358	/** \#DE - Divide error. */
3359	X86_XCPT_DE = 0x00,
3360	/** \#DB - Debug event (single step, DRx, ..) */
3361	X86_XCPT_DB = 0x01,
3362	/** NMI - Non-Maskable Interrupt */
3363	X86_XCPT_NMI = 0x02,
3364	/** \#BP - Breakpoint (INT3). */
3365	X86_XCPT_BP = 0x03,
3366	/** \#OF - Overflow (INTO). */
3367	X86_XCPT_OF = 0x04,
3368	/** \#BR - Bound range exceeded (BOUND). */
3369	X86_XCPT_BR = 0x05,
3370	/** \#UD - Undefined opcode. */
3371	X86_XCPT_UD = 0x06,
3372	/** \#NM - Device not available (math coprocessor device). */
3373	X86_XCPT_NM = 0x07,
3374	/** \#DF - Double fault. */
3375	X86_XCPT_DF = 0x08,
3376	/** ??? - Coprocessor segment overrun (obsolete). */
3377	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3378	/** \#TS - Taskswitch (TSS). */
3379	X86_XCPT_TS = 0x0a,
3380	/** \#NP - Segment no present. */
3381	X86_XCPT_NP = 0x0b,
3382	/** \#SS - Stack segment fault. */
3383	X86_XCPT_SS = 0x0c,
3384	/** \#GP - General protection fault. */
3385	X86_XCPT_GP = 0x0d,
3386	/** \#PF - Page fault. */
3387	X86_XCPT_PF = 0x0e,
3388	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3389	/** \#MF - Math fault (FPU). */
3390	X86_XCPT_MF = 0x10,
3391	/** \#AC - Alignment check. */
3392	X86_XCPT_AC = 0x11,
3393	/** \#MC - Machine check. */
3394	X86_XCPT_MC = 0x12,
3395	/** \#XF - SIMD Floating-Pointer Exception. */
3396	X86_XCPT_XF = 0x13,
3397	/** \#VE - Virtualization Exception. */
3398	X86_XCPT_VE = 0x14,
3399	/** \#SX - Security Exception. */
3400	X86_XCPT_SX = 0x1f
3401	} X86XCPT;
3402	/** Pointer to a x86 exception code. */
3403	typedef X86XCPT *PX86XCPT;
3404	/** Pointer to a const x86 exception code. */
3405	typedef const X86XCPT *PCX86XCPT;
3406	/** The maximum exception value. */
3407	#define X86_XCPT_MAX (X86_XCPT_SX)
3408
3409
3410	/** @name Trap Error Codes
3411	* @{
3412	*/
3413	/** External indicator. */
3414	#define X86_TRAP_ERR_EXTERNAL 1
3415	/** IDT indicator. */
3416	#define X86_TRAP_ERR_IDT 2
3417	/** Descriptor table indicator - If set LDT, if clear GDT. */
3418	#define X86_TRAP_ERR_TI 4
3419	/** Mask for getting the selector. */
3420	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3421	/** Shift for getting the selector table index (C type index). */
3422	#define X86_TRAP_ERR_SEL_SHIFT 3
3423	/** @} */
3424
3425
3426	/** @name \#PF Trap Error Codes
3427	* @{
3428	*/
3429	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3430	#define X86_TRAP_PF_P RT_BIT(0)
3431	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3432	#define X86_TRAP_PF_RW RT_BIT(1)
3433	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3434	#define X86_TRAP_PF_US RT_BIT(2)
3435	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3436	#define X86_TRAP_PF_RSVD RT_BIT(3)
3437	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3438	#define X86_TRAP_PF_ID RT_BIT(4)
3439	/** @} */
3440
3441	#pragma pack(1)
3442	/**
3443	* 16-bit IDTR.
3444	*/
3445	typedef struct X86IDTR16
3446	{
3447	/** Offset. */
3448	uint16_t offSel;
3449	/** Selector. */
3450	uint16_t uSel;
3451	} X86IDTR16, *PX86IDTR16;
3452	#pragma pack()
3453
3454	#pragma pack(1)
3455	/**
3456	* 32-bit IDTR/GDTR.
3457	*/
3458	typedef struct X86XDTR32
3459	{
3460	/** Size of the descriptor table. */
3461	uint16_t cb;
3462	/** Address of the descriptor table. */
3463	#ifndef VBOX_FOR_DTRACE_LIB
3464	uint32_t uAddr;
3465	#else
3466	uint16_t au16Addr[2];
3467	#endif
3468	} X86XDTR32, *PX86XDTR32;
3469	#pragma pack()
3470
3471	#pragma pack(1)
3472	/**
3473	* 64-bit IDTR/GDTR.
3474	*/
3475	typedef struct X86XDTR64
3476	{
3477	/** Size of the descriptor table. */
3478	uint16_t cb;
3479	/** Address of the descriptor table. */
3480	#ifndef VBOX_FOR_DTRACE_LIB
3481	uint64_t uAddr;
3482	#else
3483	uint16_t au16Addr[4];
3484	#endif
3485	} X86XDTR64, *PX86XDTR64;
3486	#pragma pack()
3487
3488
3489	/** @name ModR/M
3490	* @{ */
3491	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3492	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3493	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3494	#define X86_MODRM_REG_SHIFT 3
3495	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3496	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3497	#define X86_MODRM_MOD_SHIFT 6
3498	#ifndef VBOX_FOR_DTRACE_LIB
3499	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3500	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3501	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3502	#endif
3503	/** @} */
3504
3505	/** @name SIB
3506	* @{ */
3507	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3508	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3509	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3510	#define X86_SIB_INDEX_SHIFT 3
3511	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3512	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3513	#define X86_SIB_SCALE_SHIFT 6
3514	#ifndef VBOX_FOR_DTRACE_LIB
3515	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3516	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3517	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3518	#endif
3519	/** @} */
3520
3521	/** @name General register indexes
3522	* @{ */
3523	#define X86_GREG_xAX 0
3524	#define X86_GREG_xCX 1
3525	#define X86_GREG_xDX 2
3526	#define X86_GREG_xBX 3
3527	#define X86_GREG_xSP 4
3528	#define X86_GREG_xBP 5
3529	#define X86_GREG_xSI 6
3530	#define X86_GREG_xDI 7
3531	#define X86_GREG_x8 8
3532	#define X86_GREG_x9 9
3533	#define X86_GREG_x10 10
3534	#define X86_GREG_x11 11
3535	#define X86_GREG_x12 12
3536	#define X86_GREG_x13 13
3537	#define X86_GREG_x14 14
3538	#define X86_GREG_x15 15
3539	/** @} */
3540
3541	/** @name X86_SREG_XXX - Segment register indexes.
3542	* @{ */
3543	#define X86_SREG_ES 0
3544	#define X86_SREG_CS 1
3545	#define X86_SREG_SS 2
3546	#define X86_SREG_DS 3
3547	#define X86_SREG_FS 4
3548	#define X86_SREG_GS 5
3549	/** @} */
3550	/** Segment register count. */
3551	#define X86_SREG_COUNT 6
3552
3553
3554	/** @name X86_OP_XXX - Prefixes
3555	* @{ */
3556	#define X86_OP_PRF_CS UINT8_C(0x2e)
3557	#define X86_OP_PRF_SS UINT8_C(0x36)
3558	#define X86_OP_PRF_DS UINT8_C(0x3e)
3559	#define X86_OP_PRF_ES UINT8_C(0x26)
3560	#define X86_OP_PRF_FS UINT8_C(0x64)
3561	#define X86_OP_PRF_GS UINT8_C(0x65)
3562	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3563	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3564	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3565	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3566	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3567	#define X86_OP_REX_B UINT8_C(0x41)
3568	#define X86_OP_REX_X UINT8_C(0x42)
3569	#define X86_OP_REX_R UINT8_C(0x44)
3570	#define X86_OP_REX_W UINT8_C(0x48)
3571	/** @} */
3572
3573
3574	/** @} */
3575
3576	#endif
3577

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source: vbox/trunk/include/iprt/x86.h@ 54878

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