x86.h@ 54924

Last change on this file since 54924 was 54898, checked in by vboxsync, 10 years ago
CPUMCTX,CPUMHOST: Replaced the fpu (X86FXSAVE) member with an XState (X86XSAVEAREA) member.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 138.8 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2014 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** The status bits commonly updated by arithmetic instructions. */
215	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
216	/** @} */
217
218
219	/** CPUID Feature information - ECX.
220	* CPUID query with EAX=1.
221	*/
222	#ifndef VBOX_FOR_DTRACE_LIB
223	typedef struct X86CPUIDFEATECX
224	{
225	/** Bit 0 - SSE3 - Supports SSE3 or not. */
226	unsigned u1SSE3 : 1;
227	/** Bit 1 - PCLMULQDQ. */
228	unsigned u1PCLMULQDQ : 1;
229	/** Bit 2 - DS Area 64-bit layout. */
230	unsigned u1DTE64 : 1;
231	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
232	unsigned u1Monitor : 1;
233	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
234	unsigned u1CPLDS : 1;
235	/** Bit 5 - VMX - Virtual Machine Technology. */
236	unsigned u1VMX : 1;
237	/** Bit 6 - SMX: Safer Mode Extensions. */
238	unsigned u1SMX : 1;
239	/** Bit 7 - EST - Enh. SpeedStep Tech. */
240	unsigned u1EST : 1;
241	/** Bit 8 - TM2 - Terminal Monitor 2. */
242	unsigned u1TM2 : 1;
243	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
244	unsigned u1SSSE3 : 1;
245	/** Bit 10 - CNTX-ID - L1 Context ID. */
246	unsigned u1CNTXID : 1;
247	/** Bit 11 - Reserved. */
248	unsigned u1Reserved1 : 1;
249	/** Bit 12 - FMA. */
250	unsigned u1FMA : 1;
251	/** Bit 13 - CX16 - CMPXCHG16B. */
252	unsigned u1CX16 : 1;
253	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
254	unsigned u1TPRUpdate : 1;
255	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
256	unsigned u1PDCM : 1;
257	/** Bit 16 - Reserved. */
258	unsigned u1Reserved2 : 1;
259	/** Bit 17 - PCID - Process-context identifiers. */
260	unsigned u1PCID : 1;
261	/** Bit 18 - Direct Cache Access. */
262	unsigned u1DCA : 1;
263	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
264	unsigned u1SSE4_1 : 1;
265	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
266	unsigned u1SSE4_2 : 1;
267	/** Bit 21 - x2APIC. */
268	unsigned u1x2APIC : 1;
269	/** Bit 22 - MOVBE - Supports MOVBE. */
270	unsigned u1MOVBE : 1;
271	/** Bit 23 - POPCNT - Supports POPCNT. */
272	unsigned u1POPCNT : 1;
273	/** Bit 24 - TSC-Deadline. */
274	unsigned u1TSCDEADLINE : 1;
275	/** Bit 25 - AES. */
276	unsigned u1AES : 1;
277	/** Bit 26 - XSAVE - Supports XSAVE. */
278	unsigned u1XSAVE : 1;
279	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
280	unsigned u1OSXSAVE : 1;
281	/** Bit 28 - AVX - Supports AVX instruction extensions. */
282	unsigned u1AVX : 1;
283	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
284	unsigned u1F16C : 1;
285	/** Bit 30 - RDRAND - Supports RDRAND. */
286	unsigned u1RDRAND : 1;
287	/** Bit 31 - Hypervisor present (we're a guest). */
288	unsigned u1HVP : 1;
289	} X86CPUIDFEATECX;
290	#else /* VBOX_FOR_DTRACE_LIB */
291	typedef uint32_t X86CPUIDFEATECX;
292	#endif /* VBOX_FOR_DTRACE_LIB */
293	/** Pointer to CPUID Feature Information - ECX. */
294	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
295	/** Pointer to const CPUID Feature Information - ECX. */
296	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
297
298
299	/** CPUID Feature Information - EDX.
300	* CPUID query with EAX=1.
301	*/
302	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
303	typedef struct X86CPUIDFEATEDX
304	{
305	/** Bit 0 - FPU - x87 FPU on Chip. */
306	unsigned u1FPU : 1;
307	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
308	unsigned u1VME : 1;
309	/** Bit 2 - DE - Debugging extensions. */
310	unsigned u1DE : 1;
311	/** Bit 3 - PSE - Page Size Extension. */
312	unsigned u1PSE : 1;
313	/** Bit 4 - TSC - Time Stamp Counter. */
314	unsigned u1TSC : 1;
315	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
316	unsigned u1MSR : 1;
317	/** Bit 6 - PAE - Physical Address Extension. */
318	unsigned u1PAE : 1;
319	/** Bit 7 - MCE - Machine Check Exception. */
320	unsigned u1MCE : 1;
321	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
322	unsigned u1CX8 : 1;
323	/** Bit 9 - APIC - APIC On-Chip. */
324	unsigned u1APIC : 1;
325	/** Bit 10 - Reserved. */
326	unsigned u1Reserved1 : 1;
327	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
328	unsigned u1SEP : 1;
329	/** Bit 12 - MTRR - Memory Type Range Registers. */
330	unsigned u1MTRR : 1;
331	/** Bit 13 - PGE - PTE Global Bit. */
332	unsigned u1PGE : 1;
333	/** Bit 14 - MCA - Machine Check Architecture. */
334	unsigned u1MCA : 1;
335	/** Bit 15 - CMOV - Conditional Move Instructions. */
336	unsigned u1CMOV : 1;
337	/** Bit 16 - PAT - Page Attribute Table. */
338	unsigned u1PAT : 1;
339	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
340	unsigned u1PSE36 : 1;
341	/** Bit 18 - PSN - Processor Serial Number. */
342	unsigned u1PSN : 1;
343	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
344	unsigned u1CLFSH : 1;
345	/** Bit 20 - Reserved. */
346	unsigned u1Reserved2 : 1;
347	/** Bit 21 - DS - Debug Store. */
348	unsigned u1DS : 1;
349	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
350	unsigned u1ACPI : 1;
351	/** Bit 23 - MMX - Intel MMX 'Technology'. */
352	unsigned u1MMX : 1;
353	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
354	unsigned u1FXSR : 1;
355	/** Bit 25 - SSE - SSE Support. */
356	unsigned u1SSE : 1;
357	/** Bit 26 - SSE2 - SSE2 Support. */
358	unsigned u1SSE2 : 1;
359	/** Bit 27 - SS - Self Snoop. */
360	unsigned u1SS : 1;
361	/** Bit 28 - HTT - Hyper-Threading Technology. */
362	unsigned u1HTT : 1;
363	/** Bit 29 - TM - Thermal Monitor. */
364	unsigned u1TM : 1;
365	/** Bit 30 - Reserved - . */
366	unsigned u1Reserved3 : 1;
367	/** Bit 31 - PBE - Pending Break Enabled. */
368	unsigned u1PBE : 1;
369	} X86CPUIDFEATEDX;
370	#else /* VBOX_FOR_DTRACE_LIB */
371	typedef uint32_t X86CPUIDFEATEDX;
372	#endif /* VBOX_FOR_DTRACE_LIB */
373	/** Pointer to CPUID Feature Information - EDX. */
374	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
375	/** Pointer to const CPUID Feature Information - EDX. */
376	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
377
378	/** @name CPUID Vendor information.
379	* CPUID query with EAX=0.
380	* @{
381	*/
382	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
383	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
384	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
385
386	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
387	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
388	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
389
390	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
391	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
392	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
393	/** @} */
394
395
396	/** @name CPUID Feature information.
397	* CPUID query with EAX=1.
398	* @{
399	*/
400	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
401	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
402	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
403	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
404	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
405	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
406	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
407	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
408	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
409	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
410	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
411	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
412	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
413	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
414	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
415	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
416	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
417	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
418	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
419	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
420	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
421	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
422	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
423	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
424	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT(11)
425	/** ECX Bit 12 - FMA. */
426	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
427	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
428	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
429	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
430	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
431	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
432	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
433	/** ECX Bit 17 - PCID - Process-context identifiers. */
434	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
435	/** ECX Bit 18 - DCA - Direct Cache Access. */
436	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
437	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
438	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
439	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
440	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
441	/** ECX Bit 21 - x2APIC support. */
442	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
443	/** ECX Bit 22 - MOVBE instruction. */
444	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
445	/** ECX Bit 23 - POPCNT instruction. */
446	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
447	/** ECX Bir 24 - TSC-Deadline. */
448	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
449	/** ECX Bit 25 - AES instructions. */
450	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
451	/** ECX Bit 26 - XSAVE instruction. */
452	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
453	/** ECX Bit 27 - OSXSAVE instruction. */
454	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
455	/** ECX Bit 28 - AVX. */
456	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
457	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
458	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT(29)
459	/** ECX Bit 30 - RDRAND instruction. */
460	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT(30)
461	/** ECX Bit 31 - Hypervisor Present (software only). */
462	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
463
464
465	/** Bit 0 - FPU - x87 FPU on Chip. */
466	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
467	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
468	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
469	/** Bit 2 - DE - Debugging extensions. */
470	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
471	/** Bit 3 - PSE - Page Size Extension. */
472	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
473	/** Bit 4 - TSC - Time Stamp Counter. */
474	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
475	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
476	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
477	/** Bit 6 - PAE - Physical Address Extension. */
478	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
479	/** Bit 7 - MCE - Machine Check Exception. */
480	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
481	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
482	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
483	/** Bit 9 - APIC - APIC On-Chip. */
484	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
485	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
486	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
487	/** Bit 12 - MTRR - Memory Type Range Registers. */
488	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
489	/** Bit 13 - PGE - PTE Global Bit. */
490	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
491	/** Bit 14 - MCA - Machine Check Architecture. */
492	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
493	/** Bit 15 - CMOV - Conditional Move Instructions. */
494	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
495	/** Bit 16 - PAT - Page Attribute Table. */
496	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
497	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
498	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
499	/** Bit 18 - PSN - Processor Serial Number. */
500	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
501	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
502	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
503	/** Bit 21 - DS - Debug Store. */
504	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
505	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
506	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
507	/** Bit 23 - MMX - Intel MMX Technology. */
508	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
509	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
510	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
511	/** Bit 25 - SSE - SSE Support. */
512	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
513	/** Bit 26 - SSE2 - SSE2 Support. */
514	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
515	/** Bit 27 - SS - Self Snoop. */
516	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
517	/** Bit 28 - HTT - Hyper-Threading Technology. */
518	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
519	/** Bit 29 - TM - Therm. Monitor. */
520	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
521	/** Bit 31 - PBE - Pending Break Enabled. */
522	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
523	/** @} */
524
525	/** @name CPUID mwait/monitor information.
526	* CPUID query with EAX=5.
527	* @{
528	*/
529	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
530	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
531	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
532	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
533	/** @} */
534
535
536	/** @name CPUID Structured Extended Feature information.
537	* CPUID query with EAX=7.
538	* @{
539	*/
540	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
541	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
542	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
543	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
544	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
545	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
546	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
547	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
548	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
549	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT(5)
550	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
551	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
552	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
553	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
554	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
555	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
556	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
557	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
558	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
559	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
560	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
561	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
562	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
563	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT(13)
564	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
565	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
566	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
567	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
568	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
569	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
570	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
571	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT(18)
572	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
573	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
574	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
575	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
576	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
577	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT(23)
578	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
579	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
580	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
581	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
582	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
583	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
584	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
585	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
586	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
587	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
588
589	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
590	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT(0)
591	/** @} */
592
593
594	/** @name CPUID Extended Feature information.
595	* CPUID query with EAX=0x80000001.
596	* @{
597	*/
598	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
599	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
600
601	/** EDX Bit 11 - SYSCALL/SYSRET. */
602	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
603	/** EDX Bit 20 - No-Execute/Execute-Disable. */
604	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
605	/** EDX Bit 26 - 1 GB large page. */
606	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
607	/** EDX Bit 27 - RDTSCP. */
608	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
609	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
610	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
611	/** @}*/
612
613	/** @name CPUID AMD Feature information.
614	* CPUID query with EAX=0x80000001.
615	* @{
616	*/
617	/** Bit 0 - FPU - x87 FPU on Chip. */
618	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
619	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
620	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
621	/** Bit 2 - DE - Debugging extensions. */
622	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
623	/** Bit 3 - PSE - Page Size Extension. */
624	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
625	/** Bit 4 - TSC - Time Stamp Counter. */
626	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
627	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
628	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
629	/** Bit 6 - PAE - Physical Address Extension. */
630	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
631	/** Bit 7 - MCE - Machine Check Exception. */
632	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
633	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
634	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
635	/** Bit 9 - APIC - APIC On-Chip. */
636	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
637	/** Bit 12 - MTRR - Memory Type Range Registers. */
638	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
639	/** Bit 13 - PGE - PTE Global Bit. */
640	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
641	/** Bit 14 - MCA - Machine Check Architecture. */
642	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
643	/** Bit 15 - CMOV - Conditional Move Instructions. */
644	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
645	/** Bit 16 - PAT - Page Attribute Table. */
646	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
647	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
648	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
649	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
650	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
651	/** Bit 23 - MMX - Intel MMX Technology. */
652	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
653	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
654	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
655	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
656	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
657	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
658	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
659	/** Bit 31 - 3DNOW - AMD 3DNow. */
660	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
661
662	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
663	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
664	/** Bit 2 - SVM - AMD VM extensions. */
665	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
666	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
667	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
668	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
669	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
670	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
671	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
672	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
673	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
674	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
675	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
676	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
677	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
678	/** Bit 9 - OSVW - AMD OS visible workaround. */
679	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
680	/** Bit 10 - IBS - Instruct based sampling. */
681	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
682	/** Bit 11 - XOP - Extended operation support (see APM6). */
683	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT(11)
684	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
685	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
686	/** Bit 13 - WDT - AMD Watchdog timer support. */
687	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
688	/** Bit 15 - LWP - Lightweight profiling support. */
689	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT(15)
690	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
691	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT(16)
692	/** Bit 19 - NodeId - Indicates support for
693	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
694	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT(19)
695	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
696	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT(21)
697	/** Bit 22 - TopologyExtensions - . */
698	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT(22)
699	/** @} */
700
701
702	/** @name CPUID AMD Feature information.
703	* CPUID query with EAX=0x80000007.
704	* @{
705	*/
706	/** Bit 0 - TS - Temperature Sensor. */
707	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
708	/** Bit 1 - FID - Frequency ID Control. */
709	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
710	/** Bit 2 - VID - Voltage ID Control. */
711	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
712	/** Bit 3 - TTP - THERMTRIP. */
713	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
714	/** Bit 4 - TM - Hardware Thermal Control. */
715	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
716	/** Bit 5 - STC - Software Thermal Control. */
717	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
718	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
719	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
720	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
721	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
722	/** Bit 8 - TSCINVAR - TSC Invariant. */
723	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
724	/** Bit 9 - CPB - TSC Invariant. */
725	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
726	/** Bit 10 - EffFreqRO - MPERF/APERF. */
727	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
728	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
729	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
730	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
731	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
732	/** @} */
733
734
735	/** @name CR0
736	* @{ */
737	/** Bit 0 - PE - Protection Enabled */
738	#define X86_CR0_PE RT_BIT(0)
739	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
740	/** Bit 1 - MP - Monitor Coprocessor */
741	#define X86_CR0_MP RT_BIT(1)
742	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
743	/** Bit 2 - EM - Emulation. */
744	#define X86_CR0_EM RT_BIT(2)
745	#define X86_CR0_EMULATE_FPU RT_BIT(2)
746	/** Bit 3 - TS - Task Switch. */
747	#define X86_CR0_TS RT_BIT(3)
748	#define X86_CR0_TASK_SWITCH RT_BIT(3)
749	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
750	#define X86_CR0_ET RT_BIT(4)
751	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
752	/** Bit 5 - NE - Numeric error. */
753	#define X86_CR0_NE RT_BIT(5)
754	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
755	/** Bit 16 - WP - Write Protect. */
756	#define X86_CR0_WP RT_BIT(16)
757	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
758	/** Bit 18 - AM - Alignment Mask. */
759	#define X86_CR0_AM RT_BIT(18)
760	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
761	/** Bit 29 - NW - Not Write-though. */
762	#define X86_CR0_NW RT_BIT(29)
763	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
764	/** Bit 30 - WP - Cache Disable. */
765	#define X86_CR0_CD RT_BIT(30)
766	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
767	/** Bit 31 - PG - Paging. */
768	#define X86_CR0_PG RT_BIT(31)
769	#define X86_CR0_PAGING RT_BIT(31)
770	/** @} */
771
772
773	/** @name CR3
774	* @{ */
775	/** Bit 3 - PWT - Page-level Writes Transparent. */
776	#define X86_CR3_PWT RT_BIT(3)
777	/** Bit 4 - PCD - Page-level Cache Disable. */
778	#define X86_CR3_PCD RT_BIT(4)
779	/** Bits 12-31 - - Page directory page number. */
780	#define X86_CR3_PAGE_MASK (0xfffff000)
781	/** Bits 5-31 - - PAE Page directory page number. */
782	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
783	/** Bits 12-51 - - AMD64 Page directory page number. */
784	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
785	/** @} */
786
787
788	/** @name CR4
789	* @{ */
790	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
791	#define X86_CR4_VME RT_BIT(0)
792	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
793	#define X86_CR4_PVI RT_BIT(1)
794	/** Bit 2 - TSD - Time Stamp Disable. */
795	#define X86_CR4_TSD RT_BIT(2)
796	/** Bit 3 - DE - Debugging Extensions. */
797	#define X86_CR4_DE RT_BIT(3)
798	/** Bit 4 - PSE - Page Size Extension. */
799	#define X86_CR4_PSE RT_BIT(4)
800	/** Bit 5 - PAE - Physical Address Extension. */
801	#define X86_CR4_PAE RT_BIT(5)
802	/** Bit 6 - MCE - Machine-Check Enable. */
803	#define X86_CR4_MCE RT_BIT(6)
804	/** Bit 7 - PGE - Page Global Enable. */
805	#define X86_CR4_PGE RT_BIT(7)
806	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
807	#define X86_CR4_PCE RT_BIT(8)
808	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
809	#define X86_CR4_OSFXSR RT_BIT(9)
810	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
811	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
812	/** Bit 13 - VMXE - VMX mode is enabled. */
813	#define X86_CR4_VMXE RT_BIT(13)
814	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
815	#define X86_CR4_SMXE RT_BIT(14)
816	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
817	#define X86_CR4_PCIDE RT_BIT(17)
818	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
819	* extended states. */
820	#define X86_CR4_OSXSAVE RT_BIT(18)
821	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
822	#define X86_CR4_SMEP RT_BIT(20)
823	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
824	#define X86_CR4_SMAP RT_BIT(21)
825	/** @} */
826
827
828	/** @name DR6
829	* @{ */
830	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
831	#define X86_DR6_B0 RT_BIT(0)
832	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
833	#define X86_DR6_B1 RT_BIT(1)
834	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
835	#define X86_DR6_B2 RT_BIT(2)
836	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
837	#define X86_DR6_B3 RT_BIT(3)
838	/** Mask of all the Bx bits. */
839	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
840	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
841	#define X86_DR6_BD RT_BIT(13)
842	/** Bit 14 - BS - Single step */
843	#define X86_DR6_BS RT_BIT(14)
844	/** Bit 15 - BT - Task switch. (TSS T bit.) */
845	#define X86_DR6_BT RT_BIT(15)
846	/** Value of DR6 after powerup/reset. */
847	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
848	/** Bits which must be 1s in DR6. */
849	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
850	/** Bits which must be 0s in DR6. */
851	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
852	/** Bits which must be 0s on writes to DR6. */
853	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
854	/** @} */
855
856	/** Get the DR6.Bx bit for a the given breakpoint. */
857	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
858
859
860	/** @name DR7
861	* @{ */
862	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
863	#define X86_DR7_L0 RT_BIT(0)
864	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
865	#define X86_DR7_G0 RT_BIT(1)
866	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
867	#define X86_DR7_L1 RT_BIT(2)
868	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
869	#define X86_DR7_G1 RT_BIT(3)
870	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
871	#define X86_DR7_L2 RT_BIT(4)
872	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
873	#define X86_DR7_G2 RT_BIT(5)
874	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
875	#define X86_DR7_L3 RT_BIT(6)
876	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
877	#define X86_DR7_G3 RT_BIT(7)
878	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
879	#define X86_DR7_LE RT_BIT(8)
880	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
881	#define X86_DR7_GE RT_BIT(9)
882
883	/** L0, L1, L2, and L3. */
884	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
885	/** L0, L1, L2, and L3. */
886	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
887
888	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
889	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
890	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
891	* instruction is executed.
892	* @see http://www.rcollins.org/secrets/DR7.html */
893	#define X86_DR7_ICE_IR RT_BIT(12)
894	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
895	* any DR register is accessed. */
896	#define X86_DR7_GD RT_BIT(13)
897	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
898	* Pentium. */
899	#define X86_DR7_ICE_TR1 RT_BIT(14)
900	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
901	#define X86_DR7_ICE_TR2 RT_BIT(15)
902	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
903	#define X86_DR7_RW0_MASK (3 << 16)
904	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
905	#define X86_DR7_LEN0_MASK (3 << 18)
906	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
907	#define X86_DR7_RW1_MASK (3 << 20)
908	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
909	#define X86_DR7_LEN1_MASK (3 << 22)
910	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
911	#define X86_DR7_RW2_MASK (3 << 24)
912	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
913	#define X86_DR7_LEN2_MASK (3 << 26)
914	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
915	#define X86_DR7_RW3_MASK (3 << 28)
916	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
917	#define X86_DR7_LEN3_MASK (3 << 30)
918
919	/** Bits which reads as 1s. */
920	#define X86_DR7_RA1_MASK (RT_BIT(10))
921	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
922	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
923	/** Bits which must be 0s when writing to DR7. */
924	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
925
926	/** Calcs the L bit of Nth breakpoint.
927	* @param iBp The breakpoint number [0..3].
928	*/
929	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
930
931	/** Calcs the G bit of Nth breakpoint.
932	* @param iBp The breakpoint number [0..3].
933	*/
934	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
935
936	/** Calcs the L and G bits of Nth breakpoint.
937	* @param iBp The breakpoint number [0..3].
938	*/
939	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
940
941	/** @name Read/Write values.
942	* @{ */
943	/** Break on instruction fetch only. */
944	#define X86_DR7_RW_EO 0U
945	/** Break on write only. */
946	#define X86_DR7_RW_WO 1U
947	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
948	#define X86_DR7_RW_IO 2U
949	/** Break on read or write (but not instruction fetches). */
950	#define X86_DR7_RW_RW 3U
951	/** @} */
952
953	/** Shifts a X86_DR7_RW_* value to its right place.
954	* @param iBp The breakpoint number [0..3].
955	* @param fRw One of the X86_DR7_RW_* value.
956	*/
957	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
958
959	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
960	* one of the X86_DR7_RW_XXX constants).
961	*
962	* @returns X86_DR7_RW_XXX
963	* @param uDR7 DR7 value
964	* @param iBp The breakpoint number [0..3].
965	*/
966	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
967
968	/** R/W0, R/W1, R/W2, and R/W3. */
969	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
970
971	#ifndef VBOX_FOR_DTRACE_LIB
972	/** Checks if there are any I/O breakpoint types configured in the RW
973	* registers. Does NOT check if these are enabled, sorry. */
974	# define X86_DR7_ANY_RW_IO(uDR7) \
975	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
976	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
977	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
978	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
979	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
980	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
981	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
982	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
983	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
984	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
985	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
986	#endif /* !VBOX_FOR_DTRACE_LIB */
987
988	/** @name Length values.
989	* @{ */
990	#define X86_DR7_LEN_BYTE 0U
991	#define X86_DR7_LEN_WORD 1U
992	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
993	#define X86_DR7_LEN_DWORD 3U
994	/** @} */
995
996	/** Shifts a X86_DR7_LEN_* value to its right place.
997	* @param iBp The breakpoint number [0..3].
998	* @param cb One of the X86_DR7_LEN_* values.
999	*/
1000	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1001
1002	/** Fetch the breakpoint length bits from the DR7 value.
1003	* @param uDR7 DR7 value
1004	* @param iBp The breakpoint number [0..3].
1005	*/
1006	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1007
1008	/** Mask used to check if any breakpoints are enabled. */
1009	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1010
1011	/** LEN0, LEN1, LEN2, and LEN3. */
1012	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1013	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1014	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1015
1016	/** Value of DR7 after powerup/reset. */
1017	#define X86_DR7_INIT_VAL 0x400
1018	/** @} */
1019
1020
1021	/** @name Machine Specific Registers
1022	* @{
1023	*/
1024	/** Machine check address register (P5). */
1025	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1026	/** Machine check type register (P5). */
1027	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1028	/** Time Stamp Counter. */
1029	#define MSR_IA32_TSC 0x10
1030	#define MSR_IA32_CESR UINT32_C(0x00000011)
1031	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1032	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1033
1034	#define MSR_IA32_PLATFORM_ID 0x17
1035
1036	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1037	# define MSR_IA32_APICBASE 0x1b
1038	/** Local APIC enabled. */
1039	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1040	/** X2APIC enabled (requires the EN bit to be set). */
1041	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1042	/** The processor is the boot strap processor (BSP). */
1043	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1044	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1045	* width. */
1046	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1047	#endif
1048
1049	/** Undocumented intel MSR for reporting thread and core counts.
1050	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1051	* first 16 bits is the thread count. The next 16 bits the core count, except
1052	* on Westmere where it seems it's only the next 4 bits for some reason. */
1053	#define MSR_CORE_THREAD_COUNT 0x35
1054
1055	/** CPU Feature control. */
1056	#define MSR_IA32_FEATURE_CONTROL 0x3A
1057	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
1058	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT(1)
1059	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
1060
1061	/** Per-processor TSC adjust MSR. */
1062	#define MSR_IA32_TSC_ADJUST 0x3B
1063
1064	/** BIOS update trigger (microcode update). */
1065	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1066
1067	/** BIOS update signature (microcode). */
1068	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1069
1070	/** General performance counter no. 0. */
1071	#define MSR_IA32_PMC0 0xC1
1072	/** General performance counter no. 1. */
1073	#define MSR_IA32_PMC1 0xC2
1074	/** General performance counter no. 2. */
1075	#define MSR_IA32_PMC2 0xC3
1076	/** General performance counter no. 3. */
1077	#define MSR_IA32_PMC3 0xC4
1078
1079	/** Nehalem power control. */
1080	#define MSR_IA32_PLATFORM_INFO 0xCE
1081
1082	/** Get FSB clock status (Intel-specific). */
1083	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1084
1085	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1086	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1087
1088	/** C0 Maximum Frequency Clock Count */
1089	#define MSR_IA32_MPERF 0xE7
1090	/** C0 Actual Frequency Clock Count */
1091	#define MSR_IA32_APERF 0xE8
1092
1093	/** MTRR Capabilities. */
1094	#define MSR_IA32_MTRR_CAP 0xFE
1095
1096	/** Cache control/info. */
1097	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1098
1099	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1100	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1101	* R0 SS == CS + 8
1102	* R3 CS == CS + 16
1103	* R3 SS == CS + 24
1104	*/
1105	#define MSR_IA32_SYSENTER_CS 0x174
1106	/** SYSENTER_ESP - the R0 ESP. */
1107	#define MSR_IA32_SYSENTER_ESP 0x175
1108	/** SYSENTER_EIP - the R0 EIP. */
1109	#define MSR_IA32_SYSENTER_EIP 0x176
1110	#endif
1111
1112	/** Machine Check Global Capabilities Register. */
1113	#define MSR_IA32_MCG_CAP 0x179
1114	/** Machine Check Global Status Register. */
1115	#define MSR_IA32_MCG_STATUS 0x17A
1116	/** Machine Check Global Control Register. */
1117	#define MSR_IA32_MCG_CTRL 0x17B
1118
1119	/** Page Attribute Table. */
1120	#define MSR_IA32_CR_PAT 0x277
1121
1122	/** Performance counter MSRs. (Intel only) */
1123	#define MSR_IA32_PERFEVTSEL0 0x186
1124	#define MSR_IA32_PERFEVTSEL1 0x187
1125	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1126	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1127	* holds a ratio that Apple takes for TSC granularity.
1128	*
1129	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1130	#define MSR_FLEX_RATIO 0x194
1131	/** Performance state value and starting with Intel core more.
1132	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1133	#define MSR_IA32_PERF_STATUS 0x198
1134	#define MSR_IA32_PERF_CTL 0x199
1135	#define MSR_IA32_THERM_STATUS 0x19c
1136
1137	/** Enable misc. processor features (R/W). */
1138	#define MSR_IA32_MISC_ENABLE 0x1A0
1139	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1140	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1141	/** Automatic Thermal Control Circuit Enable (R/W). */
1142	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1143	/** Performance Monitoring Available (R). */
1144	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1145	/** Branch Trace Storage Unavailable (R/O). */
1146	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1147	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1148	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1149	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1150	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1151	/** If MONITOR/MWAIT is supported (R/W). */
1152	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1153	/** Limit CPUID Maxval to 3 leafs (R/W). */
1154	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1155	/** When set to 1, xTPR messages are disabled (R/W). */
1156	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1157	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1158	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1159
1160	/** Trace/Profile Resource Control (R/W) */
1161	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1162	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1163	* related Xeons. */
1164	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1165	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1166	* @{ */
1167	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1168	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1169	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1170	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1171	/** @} */
1172
1173
1174	#define IA32_MTRR_PHYSBASE0 0x200
1175	#define IA32_MTRR_PHYSMASK0 0x201
1176	#define IA32_MTRR_PHYSBASE1 0x202
1177	#define IA32_MTRR_PHYSMASK1 0x203
1178	#define IA32_MTRR_PHYSBASE2 0x204
1179	#define IA32_MTRR_PHYSMASK2 0x205
1180	#define IA32_MTRR_PHYSBASE3 0x206
1181	#define IA32_MTRR_PHYSMASK3 0x207
1182	#define IA32_MTRR_PHYSBASE4 0x208
1183	#define IA32_MTRR_PHYSMASK4 0x209
1184	#define IA32_MTRR_PHYSBASE5 0x20a
1185	#define IA32_MTRR_PHYSMASK5 0x20b
1186	#define IA32_MTRR_PHYSBASE6 0x20c
1187	#define IA32_MTRR_PHYSMASK6 0x20d
1188	#define IA32_MTRR_PHYSBASE7 0x20e
1189	#define IA32_MTRR_PHYSMASK7 0x20f
1190	#define IA32_MTRR_PHYSBASE8 0x210
1191	#define IA32_MTRR_PHYSMASK8 0x211
1192	#define IA32_MTRR_PHYSBASE9 0x212
1193	#define IA32_MTRR_PHYSMASK9 0x213
1194
1195	/** Fixed range MTRRs.
1196	* @{ */
1197	#define IA32_MTRR_FIX64K_00000 0x250
1198	#define IA32_MTRR_FIX16K_80000 0x258
1199	#define IA32_MTRR_FIX16K_A0000 0x259
1200	#define IA32_MTRR_FIX4K_C0000 0x268
1201	#define IA32_MTRR_FIX4K_C8000 0x269
1202	#define IA32_MTRR_FIX4K_D0000 0x26a
1203	#define IA32_MTRR_FIX4K_D8000 0x26b
1204	#define IA32_MTRR_FIX4K_E0000 0x26c
1205	#define IA32_MTRR_FIX4K_E8000 0x26d
1206	#define IA32_MTRR_FIX4K_F0000 0x26e
1207	#define IA32_MTRR_FIX4K_F8000 0x26f
1208	/** @} */
1209
1210	/** MTRR Default Range. */
1211	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1212
1213	#define MSR_IA32_MC0_CTL 0x400
1214	#define MSR_IA32_MC0_STATUS 0x401
1215
1216	/** Basic VMX information. */
1217	#define MSR_IA32_VMX_BASIC_INFO 0x480
1218	/** Allowed settings for pin-based VM execution controls */
1219	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1220	/** Allowed settings for proc-based VM execution controls */
1221	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1222	/** Allowed settings for the VMX exit controls. */
1223	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1224	/** Allowed settings for the VMX entry controls. */
1225	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1226	/** Misc VMX info. */
1227	#define MSR_IA32_VMX_MISC 0x485
1228	/** Fixed cleared bits in CR0. */
1229	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1230	/** Fixed set bits in CR0. */
1231	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1232	/** Fixed cleared bits in CR4. */
1233	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1234	/** Fixed set bits in CR4. */
1235	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1236	/** Information for enumerating fields in the VMCS. */
1237	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1238	/** Allowed settings for the VM-functions controls. */
1239	#define MSR_IA32_VMX_VMFUNC 0x491
1240	/** Allowed settings for secondary proc-based VM execution controls */
1241	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1242	/** EPT capabilities. */
1243	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1244	/** DS Save Area (R/W). */
1245	#define MSR_IA32_DS_AREA 0x600
1246	/** Running Average Power Limit (RAPL) power units. */
1247	#define MSR_RAPL_POWER_UNIT 0x606
1248	/** X2APIC MSR ranges. */
1249	#define MSR_IA32_X2APIC_START 0x800
1250	#define MSR_IA32_X2APIC_TPR 0x808
1251	#define MSR_IA32_X2APIC_END 0xBFF
1252
1253	/** K6 EFER - Extended Feature Enable Register. */
1254	#define MSR_K6_EFER UINT32_C(0xc0000080)
1255	/** @todo document EFER */
1256	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1257	#define MSR_K6_EFER_SCE RT_BIT(0)
1258	/** Bit 8 - LME - Long mode enabled. (R/W) */
1259	#define MSR_K6_EFER_LME RT_BIT(8)
1260	/** Bit 10 - LMA - Long mode active. (R) */
1261	#define MSR_K6_EFER_LMA RT_BIT(10)
1262	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1263	#define MSR_K6_EFER_NXE RT_BIT(11)
1264	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1265	#define MSR_K6_EFER_SVME RT_BIT(12)
1266	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1267	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1268	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1269	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1270	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1271	#define MSR_K6_EFER_TCE RT_BIT(15)
1272	/** K6 STAR - SYSCALL/RET targets. */
1273	#define MSR_K6_STAR UINT32_C(0xc0000081)
1274	/** Shift value for getting the SYSRET CS and SS value. */
1275	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1276	/** Shift value for getting the SYSCALL CS and SS value. */
1277	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1278	/** Selector mask for use after shifting. */
1279	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1280	/** The mask which give the SYSCALL EIP. */
1281	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1282	/** K6 WHCR - Write Handling Control Register. */
1283	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1284	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1285	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1286	/** K6 PSOR - Processor State Observability Register. */
1287	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1288	/** K6 PFIR - Page Flush/Invalidate Register. */
1289	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1290
1291	/** Performance counter MSRs. (AMD only) */
1292	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1293	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1294	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1295	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1296	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1297	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1298	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1299	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1300
1301	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1302	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1303	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1304	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1305	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1306	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1307	/** K8 FS.base - The 64-bit base FS register. */
1308	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1309	/** K8 GS.base - The 64-bit base GS register. */
1310	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1311	/** K8 KernelGSbase - Used with SWAPGS. */
1312	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1313	/** K8 TSC_AUX - Used with RDTSCP. */
1314	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1315	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1316	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1317	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1318	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1319	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1320	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1321	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1322	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1323	/** North bridge config? See BIOS & Kernel dev guides for
1324	* details. */
1325	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1326
1327	/** Hypertransport interrupt pending register.
1328	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1329	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1330	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1331	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1332
1333	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1334	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1335	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1336	* host state during world switch. */
1337	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1338
1339	/** @} */
1340
1341
1342	/** @name Page Table / Directory / Directory Pointers / L4.
1343	* @{
1344	*/
1345
1346	/** Page table/directory entry as an unsigned integer. */
1347	typedef uint32_t X86PGUINT;
1348	/** Pointer to a page table/directory table entry as an unsigned integer. */
1349	typedef X86PGUINT *PX86PGUINT;
1350	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1351	typedef X86PGUINT const *PCX86PGUINT;
1352
1353	/** Number of entries in a 32-bit PT/PD. */
1354	#define X86_PG_ENTRIES 1024
1355
1356
1357	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1358	typedef uint64_t X86PGPAEUINT;
1359	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1360	typedef X86PGPAEUINT *PX86PGPAEUINT;
1361	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1362	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1363
1364	/** Number of entries in a PAE PT/PD. */
1365	#define X86_PG_PAE_ENTRIES 512
1366	/** Number of entries in a PAE PDPT. */
1367	#define X86_PG_PAE_PDPE_ENTRIES 4
1368
1369	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1370	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1371	/** Number of entries in an AMD64 PDPT.
1372	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1373	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1374
1375	/** The size of a 4KB page. */
1376	#define X86_PAGE_4K_SIZE _4K
1377	/** The page shift of a 4KB page. */
1378	#define X86_PAGE_4K_SHIFT 12
1379	/** The 4KB page offset mask. */
1380	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1381	/** The 4KB page base mask for virtual addresses. */
1382	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1383	/** The 4KB page base mask for virtual addresses - 32bit version. */
1384	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1385
1386	/** The size of a 2MB page. */
1387	#define X86_PAGE_2M_SIZE _2M
1388	/** The page shift of a 2MB page. */
1389	#define X86_PAGE_2M_SHIFT 21
1390	/** The 2MB page offset mask. */
1391	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1392	/** The 2MB page base mask for virtual addresses. */
1393	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1394	/** The 2MB page base mask for virtual addresses - 32bit version. */
1395	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1396
1397	/** The size of a 4MB page. */
1398	#define X86_PAGE_4M_SIZE _4M
1399	/** The page shift of a 4MB page. */
1400	#define X86_PAGE_4M_SHIFT 22
1401	/** The 4MB page offset mask. */
1402	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1403	/** The 4MB page base mask for virtual addresses. */
1404	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1405	/** The 4MB page base mask for virtual addresses - 32bit version. */
1406	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1407
1408	/**
1409	* Check if the given address is canonical.
1410	*/
1411	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1412
1413
1414	/** @name Page Table Entry
1415	* @{
1416	*/
1417	/** Bit 0 - P - Present bit. */
1418	#define X86_PTE_BIT_P 0
1419	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1420	#define X86_PTE_BIT_RW 1
1421	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1422	#define X86_PTE_BIT_US 2
1423	/** Bit 3 - PWT - Page level write thru bit. */
1424	#define X86_PTE_BIT_PWT 3
1425	/** Bit 4 - PCD - Page level cache disable bit. */
1426	#define X86_PTE_BIT_PCD 4
1427	/** Bit 5 - A - Access bit. */
1428	#define X86_PTE_BIT_A 5
1429	/** Bit 6 - D - Dirty bit. */
1430	#define X86_PTE_BIT_D 6
1431	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1432	#define X86_PTE_BIT_PAT 7
1433	/** Bit 8 - G - Global flag. */
1434	#define X86_PTE_BIT_G 8
1435
1436	/** Bit 0 - P - Present bit mask. */
1437	#define X86_PTE_P RT_BIT(0)
1438	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1439	#define X86_PTE_RW RT_BIT(1)
1440	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1441	#define X86_PTE_US RT_BIT(2)
1442	/** Bit 3 - PWT - Page level write thru bit mask. */
1443	#define X86_PTE_PWT RT_BIT(3)
1444	/** Bit 4 - PCD - Page level cache disable bit mask. */
1445	#define X86_PTE_PCD RT_BIT(4)
1446	/** Bit 5 - A - Access bit mask. */
1447	#define X86_PTE_A RT_BIT(5)
1448	/** Bit 6 - D - Dirty bit mask. */
1449	#define X86_PTE_D RT_BIT(6)
1450	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1451	#define X86_PTE_PAT RT_BIT(7)
1452	/** Bit 8 - G - Global bit mask. */
1453	#define X86_PTE_G RT_BIT(8)
1454
1455	/** Bits 9-11 - - Available for use to system software. */
1456	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1457	/** Bits 12-31 - - Physical Page number of the next level. */
1458	#define X86_PTE_PG_MASK ( 0xfffff000 )
1459
1460	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1461	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1462	/** Bits 63 - NX - PAE/LM - No execution flag. */
1463	#define X86_PTE_PAE_NX RT_BIT_64(63)
1464	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1465	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1466	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1467	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1468	/** No bits - - LM - MBZ bits when NX is active. */
1469	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1470	/** Bits 63 - - LM - MBZ bits when no NX. */
1471	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1472
1473	/**
1474	* Page table entry.
1475	*/
1476	typedef struct X86PTEBITS
1477	{
1478	/** Flags whether(=1) or not the page is present. */
1479	unsigned u1Present : 1;
1480	/** Read(=0) / Write(=1) flag. */
1481	unsigned u1Write : 1;
1482	/** User(=1) / Supervisor (=0) flag. */
1483	unsigned u1User : 1;
1484	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1485	unsigned u1WriteThru : 1;
1486	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1487	unsigned u1CacheDisable : 1;
1488	/** Accessed flag.
1489	* Indicates that the page have been read or written to. */
1490	unsigned u1Accessed : 1;
1491	/** Dirty flag.
1492	* Indicates that the page has been written to. */
1493	unsigned u1Dirty : 1;
1494	/** Reserved / If PAT enabled, bit 2 of the index. */
1495	unsigned u1PAT : 1;
1496	/** Global flag. (Ignored in all but final level.) */
1497	unsigned u1Global : 1;
1498	/** Available for use to system software. */
1499	unsigned u3Available : 3;
1500	/** Physical Page number of the next level. */
1501	unsigned u20PageNo : 20;
1502	} X86PTEBITS;
1503	/** Pointer to a page table entry. */
1504	typedef X86PTEBITS *PX86PTEBITS;
1505	/** Pointer to a const page table entry. */
1506	typedef const X86PTEBITS *PCX86PTEBITS;
1507
1508	/**
1509	* Page table entry.
1510	*/
1511	typedef union X86PTE
1512	{
1513	/** Unsigned integer view */
1514	X86PGUINT u;
1515	/** Bit field view. */
1516	X86PTEBITS n;
1517	/** 32-bit view. */
1518	uint32_t au32[1];
1519	/** 16-bit view. */
1520	uint16_t au16[2];
1521	/** 8-bit view. */
1522	uint8_t au8[4];
1523	} X86PTE;
1524	/** Pointer to a page table entry. */
1525	typedef X86PTE *PX86PTE;
1526	/** Pointer to a const page table entry. */
1527	typedef const X86PTE *PCX86PTE;
1528
1529
1530	/**
1531	* PAE page table entry.
1532	*/
1533	typedef struct X86PTEPAEBITS
1534	{
1535	/** Flags whether(=1) or not the page is present. */
1536	uint32_t u1Present : 1;
1537	/** Read(=0) / Write(=1) flag. */
1538	uint32_t u1Write : 1;
1539	/** User(=1) / Supervisor(=0) flag. */
1540	uint32_t u1User : 1;
1541	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1542	uint32_t u1WriteThru : 1;
1543	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1544	uint32_t u1CacheDisable : 1;
1545	/** Accessed flag.
1546	* Indicates that the page have been read or written to. */
1547	uint32_t u1Accessed : 1;
1548	/** Dirty flag.
1549	* Indicates that the page has been written to. */
1550	uint32_t u1Dirty : 1;
1551	/** Reserved / If PAT enabled, bit 2 of the index. */
1552	uint32_t u1PAT : 1;
1553	/** Global flag. (Ignored in all but final level.) */
1554	uint32_t u1Global : 1;
1555	/** Available for use to system software. */
1556	uint32_t u3Available : 3;
1557	/** Physical Page number of the next level - Low Part. Don't use this. */
1558	uint32_t u20PageNoLow : 20;
1559	/** Physical Page number of the next level - High Part. Don't use this. */
1560	uint32_t u20PageNoHigh : 20;
1561	/** MBZ bits */
1562	uint32_t u11Reserved : 11;
1563	/** No Execute flag. */
1564	uint32_t u1NoExecute : 1;
1565	} X86PTEPAEBITS;
1566	/** Pointer to a page table entry. */
1567	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1568	/** Pointer to a page table entry. */
1569	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1570
1571	/**
1572	* PAE Page table entry.
1573	*/
1574	typedef union X86PTEPAE
1575	{
1576	/** Unsigned integer view */
1577	X86PGPAEUINT u;
1578	/** Bit field view. */
1579	X86PTEPAEBITS n;
1580	/** 32-bit view. */
1581	uint32_t au32[2];
1582	/** 16-bit view. */
1583	uint16_t au16[4];
1584	/** 8-bit view. */
1585	uint8_t au8[8];
1586	} X86PTEPAE;
1587	/** Pointer to a PAE page table entry. */
1588	typedef X86PTEPAE *PX86PTEPAE;
1589	/** Pointer to a const PAE page table entry. */
1590	typedef const X86PTEPAE *PCX86PTEPAE;
1591	/** @} */
1592
1593	/**
1594	* Page table.
1595	*/
1596	typedef struct X86PT
1597	{
1598	/** PTE Array. */
1599	X86PTE a[X86_PG_ENTRIES];
1600	} X86PT;
1601	/** Pointer to a page table. */
1602	typedef X86PT *PX86PT;
1603	/** Pointer to a const page table. */
1604	typedef const X86PT *PCX86PT;
1605
1606	/** The page shift to get the PT index. */
1607	#define X86_PT_SHIFT 12
1608	/** The PT index mask (apply to a shifted page address). */
1609	#define X86_PT_MASK 0x3ff
1610
1611
1612	/**
1613	* Page directory.
1614	*/
1615	typedef struct X86PTPAE
1616	{
1617	/** PTE Array. */
1618	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1619	} X86PTPAE;
1620	/** Pointer to a page table. */
1621	typedef X86PTPAE *PX86PTPAE;
1622	/** Pointer to a const page table. */
1623	typedef const X86PTPAE *PCX86PTPAE;
1624
1625	/** The page shift to get the PA PTE index. */
1626	#define X86_PT_PAE_SHIFT 12
1627	/** The PAE PT index mask (apply to a shifted page address). */
1628	#define X86_PT_PAE_MASK 0x1ff
1629
1630
1631	/** @name 4KB Page Directory Entry
1632	* @{
1633	*/
1634	/** Bit 0 - P - Present bit. */
1635	#define X86_PDE_P RT_BIT(0)
1636	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1637	#define X86_PDE_RW RT_BIT(1)
1638	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1639	#define X86_PDE_US RT_BIT(2)
1640	/** Bit 3 - PWT - Page level write thru bit. */
1641	#define X86_PDE_PWT RT_BIT(3)
1642	/** Bit 4 - PCD - Page level cache disable bit. */
1643	#define X86_PDE_PCD RT_BIT(4)
1644	/** Bit 5 - A - Access bit. */
1645	#define X86_PDE_A RT_BIT(5)
1646	/** Bit 7 - PS - Page size attribute.
1647	* Clear mean 4KB pages, set means large pages (2/4MB). */
1648	#define X86_PDE_PS RT_BIT(7)
1649	/** Bits 9-11 - - Available for use to system software. */
1650	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1651	/** Bits 12-31 - - Physical Page number of the next level. */
1652	#define X86_PDE_PG_MASK ( 0xfffff000 )
1653
1654	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1655	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1656	/** Bits 63 - NX - PAE/LM - No execution flag. */
1657	#define X86_PDE_PAE_NX RT_BIT_64(63)
1658	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1659	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1660	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1661	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1662	/** Bit 7 - - LM - MBZ bits when NX is active. */
1663	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1664	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1665	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1666
1667	/**
1668	* Page directory entry.
1669	*/
1670	typedef struct X86PDEBITS
1671	{
1672	/** Flags whether(=1) or not the page is present. */
1673	unsigned u1Present : 1;
1674	/** Read(=0) / Write(=1) flag. */
1675	unsigned u1Write : 1;
1676	/** User(=1) / Supervisor (=0) flag. */
1677	unsigned u1User : 1;
1678	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1679	unsigned u1WriteThru : 1;
1680	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1681	unsigned u1CacheDisable : 1;
1682	/** Accessed flag.
1683	* Indicates that the page has been read or written to. */
1684	unsigned u1Accessed : 1;
1685	/** Reserved / Ignored (dirty bit). */
1686	unsigned u1Reserved0 : 1;
1687	/** Size bit if PSE is enabled - in any event it's 0. */
1688	unsigned u1Size : 1;
1689	/** Reserved / Ignored (global bit). */
1690	unsigned u1Reserved1 : 1;
1691	/** Available for use to system software. */
1692	unsigned u3Available : 3;
1693	/** Physical Page number of the next level. */
1694	unsigned u20PageNo : 20;
1695	} X86PDEBITS;
1696	/** Pointer to a page directory entry. */
1697	typedef X86PDEBITS *PX86PDEBITS;
1698	/** Pointer to a const page directory entry. */
1699	typedef const X86PDEBITS *PCX86PDEBITS;
1700
1701
1702	/**
1703	* PAE page directory entry.
1704	*/
1705	typedef struct X86PDEPAEBITS
1706	{
1707	/** Flags whether(=1) or not the page is present. */
1708	uint32_t u1Present : 1;
1709	/** Read(=0) / Write(=1) flag. */
1710	uint32_t u1Write : 1;
1711	/** User(=1) / Supervisor (=0) flag. */
1712	uint32_t u1User : 1;
1713	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1714	uint32_t u1WriteThru : 1;
1715	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1716	uint32_t u1CacheDisable : 1;
1717	/** Accessed flag.
1718	* Indicates that the page has been read or written to. */
1719	uint32_t u1Accessed : 1;
1720	/** Reserved / Ignored (dirty bit). */
1721	uint32_t u1Reserved0 : 1;
1722	/** Size bit if PSE is enabled - in any event it's 0. */
1723	uint32_t u1Size : 1;
1724	/** Reserved / Ignored (global bit). / */
1725	uint32_t u1Reserved1 : 1;
1726	/** Available for use to system software. */
1727	uint32_t u3Available : 3;
1728	/** Physical Page number of the next level - Low Part. Don't use! */
1729	uint32_t u20PageNoLow : 20;
1730	/** Physical Page number of the next level - High Part. Don't use! */
1731	uint32_t u20PageNoHigh : 20;
1732	/** MBZ bits */
1733	uint32_t u11Reserved : 11;
1734	/** No Execute flag. */
1735	uint32_t u1NoExecute : 1;
1736	} X86PDEPAEBITS;
1737	/** Pointer to a page directory entry. */
1738	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1739	/** Pointer to a const page directory entry. */
1740	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1741
1742	/** @} */
1743
1744
1745	/** @name 2/4MB Page Directory Entry
1746	* @{
1747	*/
1748	/** Bit 0 - P - Present bit. */
1749	#define X86_PDE4M_P RT_BIT(0)
1750	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1751	#define X86_PDE4M_RW RT_BIT(1)
1752	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1753	#define X86_PDE4M_US RT_BIT(2)
1754	/** Bit 3 - PWT - Page level write thru bit. */
1755	#define X86_PDE4M_PWT RT_BIT(3)
1756	/** Bit 4 - PCD - Page level cache disable bit. */
1757	#define X86_PDE4M_PCD RT_BIT(4)
1758	/** Bit 5 - A - Access bit. */
1759	#define X86_PDE4M_A RT_BIT(5)
1760	/** Bit 6 - D - Dirty bit. */
1761	#define X86_PDE4M_D RT_BIT(6)
1762	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1763	#define X86_PDE4M_PS RT_BIT(7)
1764	/** Bit 8 - G - Global flag. */
1765	#define X86_PDE4M_G RT_BIT(8)
1766	/** Bits 9-11 - AVL - Available for use to system software. */
1767	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1768	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1769	#define X86_PDE4M_PAT RT_BIT(12)
1770	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1771	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1772	/** Bits 22-31 - - Physical Page number. */
1773	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1774	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1775	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1776	/** The number of bits to the high part of the page number. */
1777	#define X86_PDE4M_PG_HIGH_SHIFT 19
1778	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1779	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1780
1781	/** Bits 21-51 - - PAE/LM - Physical Page number.
1782	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1783	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1784	/** Bits 63 - NX - PAE/LM - No execution flag. */
1785	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1786	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1787	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1788	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1789	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1790	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1791	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1792	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1793	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1794
1795	/**
1796	* 4MB page directory entry.
1797	*/
1798	typedef struct X86PDE4MBITS
1799	{
1800	/** Flags whether(=1) or not the page is present. */
1801	unsigned u1Present : 1;
1802	/** Read(=0) / Write(=1) flag. */
1803	unsigned u1Write : 1;
1804	/** User(=1) / Supervisor (=0) flag. */
1805	unsigned u1User : 1;
1806	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1807	unsigned u1WriteThru : 1;
1808	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1809	unsigned u1CacheDisable : 1;
1810	/** Accessed flag.
1811	* Indicates that the page have been read or written to. */
1812	unsigned u1Accessed : 1;
1813	/** Dirty flag.
1814	* Indicates that the page has been written to. */
1815	unsigned u1Dirty : 1;
1816	/** Page size flag - always 1 for 4MB entries. */
1817	unsigned u1Size : 1;
1818	/** Global flag. */
1819	unsigned u1Global : 1;
1820	/** Available for use to system software. */
1821	unsigned u3Available : 3;
1822	/** Reserved / If PAT enabled, bit 2 of the index. */
1823	unsigned u1PAT : 1;
1824	/** Bits 32-39 of the page number on AMD64.
1825	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1826	unsigned u8PageNoHigh : 8;
1827	/** Reserved. */
1828	unsigned u1Reserved : 1;
1829	/** Physical Page number of the page. */
1830	unsigned u10PageNo : 10;
1831	} X86PDE4MBITS;
1832	/** Pointer to a page table entry. */
1833	typedef X86PDE4MBITS *PX86PDE4MBITS;
1834	/** Pointer to a const page table entry. */
1835	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1836
1837
1838	/**
1839	* 2MB PAE page directory entry.
1840	*/
1841	typedef struct X86PDE2MPAEBITS
1842	{
1843	/** Flags whether(=1) or not the page is present. */
1844	uint32_t u1Present : 1;
1845	/** Read(=0) / Write(=1) flag. */
1846	uint32_t u1Write : 1;
1847	/** User(=1) / Supervisor(=0) flag. */
1848	uint32_t u1User : 1;
1849	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1850	uint32_t u1WriteThru : 1;
1851	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1852	uint32_t u1CacheDisable : 1;
1853	/** Accessed flag.
1854	* Indicates that the page have been read or written to. */
1855	uint32_t u1Accessed : 1;
1856	/** Dirty flag.
1857	* Indicates that the page has been written to. */
1858	uint32_t u1Dirty : 1;
1859	/** Page size flag - always 1 for 2MB entries. */
1860	uint32_t u1Size : 1;
1861	/** Global flag. */
1862	uint32_t u1Global : 1;
1863	/** Available for use to system software. */
1864	uint32_t u3Available : 3;
1865	/** Reserved / If PAT enabled, bit 2 of the index. */
1866	uint32_t u1PAT : 1;
1867	/** Reserved. */
1868	uint32_t u9Reserved : 9;
1869	/** Physical Page number of the next level - Low part. Don't use! */
1870	uint32_t u10PageNoLow : 10;
1871	/** Physical Page number of the next level - High part. Don't use! */
1872	uint32_t u20PageNoHigh : 20;
1873	/** MBZ bits */
1874	uint32_t u11Reserved : 11;
1875	/** No Execute flag. */
1876	uint32_t u1NoExecute : 1;
1877	} X86PDE2MPAEBITS;
1878	/** Pointer to a 2MB PAE page table entry. */
1879	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1880	/** Pointer to a 2MB PAE page table entry. */
1881	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1882
1883	/** @} */
1884
1885	/**
1886	* Page directory entry.
1887	*/
1888	typedef union X86PDE
1889	{
1890	/** Unsigned integer view. */
1891	X86PGUINT u;
1892	/** Normal view. */
1893	X86PDEBITS n;
1894	/** 4MB view (big). */
1895	X86PDE4MBITS b;
1896	/** 8 bit unsigned integer view. */
1897	uint8_t au8[4];
1898	/** 16 bit unsigned integer view. */
1899	uint16_t au16[2];
1900	/** 32 bit unsigned integer view. */
1901	uint32_t au32[1];
1902	} X86PDE;
1903	/** Pointer to a page directory entry. */
1904	typedef X86PDE *PX86PDE;
1905	/** Pointer to a const page directory entry. */
1906	typedef const X86PDE *PCX86PDE;
1907
1908	/**
1909	* PAE page directory entry.
1910	*/
1911	typedef union X86PDEPAE
1912	{
1913	/** Unsigned integer view. */
1914	X86PGPAEUINT u;
1915	/** Normal view. */
1916	X86PDEPAEBITS n;
1917	/** 2MB page view (big). */
1918	X86PDE2MPAEBITS b;
1919	/** 8 bit unsigned integer view. */
1920	uint8_t au8[8];
1921	/** 16 bit unsigned integer view. */
1922	uint16_t au16[4];
1923	/** 32 bit unsigned integer view. */
1924	uint32_t au32[2];
1925	} X86PDEPAE;
1926	/** Pointer to a page directory entry. */
1927	typedef X86PDEPAE *PX86PDEPAE;
1928	/** Pointer to a const page directory entry. */
1929	typedef const X86PDEPAE *PCX86PDEPAE;
1930
1931	/**
1932	* Page directory.
1933	*/
1934	typedef struct X86PD
1935	{
1936	/** PDE Array. */
1937	X86PDE a[X86_PG_ENTRIES];
1938	} X86PD;
1939	/** Pointer to a page directory. */
1940	typedef X86PD *PX86PD;
1941	/** Pointer to a const page directory. */
1942	typedef const X86PD *PCX86PD;
1943
1944	/** The page shift to get the PD index. */
1945	#define X86_PD_SHIFT 22
1946	/** The PD index mask (apply to a shifted page address). */
1947	#define X86_PD_MASK 0x3ff
1948
1949
1950	/**
1951	* PAE page directory.
1952	*/
1953	typedef struct X86PDPAE
1954	{
1955	/** PDE Array. */
1956	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1957	} X86PDPAE;
1958	/** Pointer to a PAE page directory. */
1959	typedef X86PDPAE *PX86PDPAE;
1960	/** Pointer to a const PAE page directory. */
1961	typedef const X86PDPAE *PCX86PDPAE;
1962
1963	/** The page shift to get the PAE PD index. */
1964	#define X86_PD_PAE_SHIFT 21
1965	/** The PAE PD index mask (apply to a shifted page address). */
1966	#define X86_PD_PAE_MASK 0x1ff
1967
1968
1969	/** @name Page Directory Pointer Table Entry (PAE)
1970	* @{
1971	*/
1972	/** Bit 0 - P - Present bit. */
1973	#define X86_PDPE_P RT_BIT(0)
1974	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1975	#define X86_PDPE_RW RT_BIT(1)
1976	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1977	#define X86_PDPE_US RT_BIT(2)
1978	/** Bit 3 - PWT - Page level write thru bit. */
1979	#define X86_PDPE_PWT RT_BIT(3)
1980	/** Bit 4 - PCD - Page level cache disable bit. */
1981	#define X86_PDPE_PCD RT_BIT(4)
1982	/** Bit 5 - A - Access bit. Long Mode only. */
1983	#define X86_PDPE_A RT_BIT(5)
1984	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1985	#define X86_PDPE_LM_PS RT_BIT(7)
1986	/** Bits 9-11 - - Available for use to system software. */
1987	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1988	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1989	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1990	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1991	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1992	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1993	#define X86_PDPE_LM_NX RT_BIT_64(63)
1994	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1995	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1996	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1997	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1998	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1999	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2000	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2001	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2002
2003
2004	/**
2005	* Page directory pointer table entry.
2006	*/
2007	typedef struct X86PDPEBITS
2008	{
2009	/** Flags whether(=1) or not the page is present. */
2010	uint32_t u1Present : 1;
2011	/** Chunk of reserved bits. */
2012	uint32_t u2Reserved : 2;
2013	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2014	uint32_t u1WriteThru : 1;
2015	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2016	uint32_t u1CacheDisable : 1;
2017	/** Chunk of reserved bits. */
2018	uint32_t u4Reserved : 4;
2019	/** Available for use to system software. */
2020	uint32_t u3Available : 3;
2021	/** Physical Page number of the next level - Low Part. Don't use! */
2022	uint32_t u20PageNoLow : 20;
2023	/** Physical Page number of the next level - High Part. Don't use! */
2024	uint32_t u20PageNoHigh : 20;
2025	/** MBZ bits */
2026	uint32_t u12Reserved : 12;
2027	} X86PDPEBITS;
2028	/** Pointer to a page directory pointer table entry. */
2029	typedef X86PDPEBITS *PX86PTPEBITS;
2030	/** Pointer to a const page directory pointer table entry. */
2031	typedef const X86PDPEBITS *PCX86PTPEBITS;
2032
2033	/**
2034	* Page directory pointer table entry. AMD64 version
2035	*/
2036	typedef struct X86PDPEAMD64BITS
2037	{
2038	/** Flags whether(=1) or not the page is present. */
2039	uint32_t u1Present : 1;
2040	/** Read(=0) / Write(=1) flag. */
2041	uint32_t u1Write : 1;
2042	/** User(=1) / Supervisor (=0) flag. */
2043	uint32_t u1User : 1;
2044	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2045	uint32_t u1WriteThru : 1;
2046	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2047	uint32_t u1CacheDisable : 1;
2048	/** Accessed flag.
2049	* Indicates that the page have been read or written to. */
2050	uint32_t u1Accessed : 1;
2051	/** Chunk of reserved bits. */
2052	uint32_t u3Reserved : 3;
2053	/** Available for use to system software. */
2054	uint32_t u3Available : 3;
2055	/** Physical Page number of the next level - Low Part. Don't use! */
2056	uint32_t u20PageNoLow : 20;
2057	/** Physical Page number of the next level - High Part. Don't use! */
2058	uint32_t u20PageNoHigh : 20;
2059	/** MBZ bits */
2060	uint32_t u11Reserved : 11;
2061	/** No Execute flag. */
2062	uint32_t u1NoExecute : 1;
2063	} X86PDPEAMD64BITS;
2064	/** Pointer to a page directory pointer table entry. */
2065	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2066	/** Pointer to a const page directory pointer table entry. */
2067	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2068
2069	/**
2070	* Page directory pointer table entry.
2071	*/
2072	typedef union X86PDPE
2073	{
2074	/** Unsigned integer view. */
2075	X86PGPAEUINT u;
2076	/** Normal view. */
2077	X86PDPEBITS n;
2078	/** AMD64 view. */
2079	X86PDPEAMD64BITS lm;
2080	/** 8 bit unsigned integer view. */
2081	uint8_t au8[8];
2082	/** 16 bit unsigned integer view. */
2083	uint16_t au16[4];
2084	/** 32 bit unsigned integer view. */
2085	uint32_t au32[2];
2086	} X86PDPE;
2087	/** Pointer to a page directory pointer table entry. */
2088	typedef X86PDPE *PX86PDPE;
2089	/** Pointer to a const page directory pointer table entry. */
2090	typedef const X86PDPE *PCX86PDPE;
2091
2092
2093	/**
2094	* Page directory pointer table.
2095	*/
2096	typedef struct X86PDPT
2097	{
2098	/** PDE Array. */
2099	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2100	} X86PDPT;
2101	/** Pointer to a page directory pointer table. */
2102	typedef X86PDPT *PX86PDPT;
2103	/** Pointer to a const page directory pointer table. */
2104	typedef const X86PDPT *PCX86PDPT;
2105
2106	/** The page shift to get the PDPT index. */
2107	#define X86_PDPT_SHIFT 30
2108	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2109	#define X86_PDPT_MASK_PAE 0x3
2110	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2111	#define X86_PDPT_MASK_AMD64 0x1ff
2112
2113	/** @} */
2114
2115
2116	/** @name Page Map Level-4 Entry (Long Mode PAE)
2117	* @{
2118	*/
2119	/** Bit 0 - P - Present bit. */
2120	#define X86_PML4E_P RT_BIT(0)
2121	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2122	#define X86_PML4E_RW RT_BIT(1)
2123	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2124	#define X86_PML4E_US RT_BIT(2)
2125	/** Bit 3 - PWT - Page level write thru bit. */
2126	#define X86_PML4E_PWT RT_BIT(3)
2127	/** Bit 4 - PCD - Page level cache disable bit. */
2128	#define X86_PML4E_PCD RT_BIT(4)
2129	/** Bit 5 - A - Access bit. */
2130	#define X86_PML4E_A RT_BIT(5)
2131	/** Bits 9-11 - - Available for use to system software. */
2132	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2133	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2134	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2135	/** Bits 8, 7 - - MBZ bits when NX is active. */
2136	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2137	/** Bits 63, 7 - - MBZ bits when no NX. */
2138	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2139	/** Bits 63 - NX - PAE - No execution flag. */
2140	#define X86_PML4E_NX RT_BIT_64(63)
2141
2142	/**
2143	* Page Map Level-4 Entry
2144	*/
2145	typedef struct X86PML4EBITS
2146	{
2147	/** Flags whether(=1) or not the page is present. */
2148	uint32_t u1Present : 1;
2149	/** Read(=0) / Write(=1) flag. */
2150	uint32_t u1Write : 1;
2151	/** User(=1) / Supervisor (=0) flag. */
2152	uint32_t u1User : 1;
2153	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2154	uint32_t u1WriteThru : 1;
2155	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2156	uint32_t u1CacheDisable : 1;
2157	/** Accessed flag.
2158	* Indicates that the page have been read or written to. */
2159	uint32_t u1Accessed : 1;
2160	/** Chunk of reserved bits. */
2161	uint32_t u3Reserved : 3;
2162	/** Available for use to system software. */
2163	uint32_t u3Available : 3;
2164	/** Physical Page number of the next level - Low Part. Don't use! */
2165	uint32_t u20PageNoLow : 20;
2166	/** Physical Page number of the next level - High Part. Don't use! */
2167	uint32_t u20PageNoHigh : 20;
2168	/** MBZ bits */
2169	uint32_t u11Reserved : 11;
2170	/** No Execute flag. */
2171	uint32_t u1NoExecute : 1;
2172	} X86PML4EBITS;
2173	/** Pointer to a page map level-4 entry. */
2174	typedef X86PML4EBITS *PX86PML4EBITS;
2175	/** Pointer to a const page map level-4 entry. */
2176	typedef const X86PML4EBITS *PCX86PML4EBITS;
2177
2178	/**
2179	* Page Map Level-4 Entry.
2180	*/
2181	typedef union X86PML4E
2182	{
2183	/** Unsigned integer view. */
2184	X86PGPAEUINT u;
2185	/** Normal view. */
2186	X86PML4EBITS n;
2187	/** 8 bit unsigned integer view. */
2188	uint8_t au8[8];
2189	/** 16 bit unsigned integer view. */
2190	uint16_t au16[4];
2191	/** 32 bit unsigned integer view. */
2192	uint32_t au32[2];
2193	} X86PML4E;
2194	/** Pointer to a page map level-4 entry. */
2195	typedef X86PML4E *PX86PML4E;
2196	/** Pointer to a const page map level-4 entry. */
2197	typedef const X86PML4E *PCX86PML4E;
2198
2199
2200	/**
2201	* Page Map Level-4.
2202	*/
2203	typedef struct X86PML4
2204	{
2205	/** PDE Array. */
2206	X86PML4E a[X86_PG_PAE_ENTRIES];
2207	} X86PML4;
2208	/** Pointer to a page map level-4. */
2209	typedef X86PML4 *PX86PML4;
2210	/** Pointer to a const page map level-4. */
2211	typedef const X86PML4 *PCX86PML4;
2212
2213	/** The page shift to get the PML4 index. */
2214	#define X86_PML4_SHIFT 39
2215	/** The PML4 index mask (apply to a shifted page address). */
2216	#define X86_PML4_MASK 0x1ff
2217
2218	/** @} */
2219
2220	/** @} */
2221
2222	/**
2223	* 32-bit protected mode FSTENV image.
2224	*/
2225	typedef struct X86FSTENV32P
2226	{
2227	uint16_t FCW;
2228	uint16_t padding1;
2229	uint16_t FSW;
2230	uint16_t padding2;
2231	uint16_t FTW;
2232	uint16_t padding3;
2233	uint32_t FPUIP;
2234	uint16_t FPUCS;
2235	uint16_t FOP;
2236	uint32_t FPUDP;
2237	uint16_t FPUDS;
2238	uint16_t padding4;
2239	} X86FSTENV32P;
2240	/** Pointer to a 32-bit protected mode FSTENV image. */
2241	typedef X86FSTENV32P *PX86FSTENV32P;
2242	/** Pointer to a const 32-bit protected mode FSTENV image. */
2243	typedef X86FSTENV32P const *PCX86FSTENV32P;
2244
2245
2246	/**
2247	* 80-bit MMX/FPU register type.
2248	*/
2249	typedef struct X86FPUMMX
2250	{
2251	uint8_t reg[10];
2252	} X86FPUMMX;
2253	#ifndef VBOX_FOR_DTRACE_LIB
2254	AssertCompileSize(X86FPUMMX, 10);
2255	#endif
2256	/** Pointer to a 80-bit MMX/FPU register type. */
2257	typedef X86FPUMMX *PX86FPUMMX;
2258	/** Pointer to a const 80-bit MMX/FPU register type. */
2259	typedef const X86FPUMMX *PCX86FPUMMX;
2260
2261	/** FPU (x87) register. */
2262	typedef union X86FPUREG
2263	{
2264	/** MMX view. */
2265	uint64_t mmx;
2266	/** FPU view - todo. */
2267	X86FPUMMX fpu;
2268	/** Extended precision floating point view. */
2269	RTFLOAT80U r80;
2270	/** Extended precision floating point view v2 */
2271	RTFLOAT80U2 r80Ex;
2272	/** 8-bit view. */
2273	uint8_t au8[16];
2274	/** 16-bit view. */
2275	uint16_t au16[8];
2276	/** 32-bit view. */
2277	uint32_t au32[4];
2278	/** 64-bit view. */
2279	uint64_t au64[2];
2280	/** 128-bit view. (yeah, very helpful) */
2281	uint128_t au128[1];
2282	} X86FPUREG;
2283	#ifndef VBOX_FOR_DTRACE_LIB
2284	AssertCompileSize(X86FPUREG, 16);
2285	#endif
2286	/** Pointer to a FPU register. */
2287	typedef X86FPUREG *PX86FPUREG;
2288	/** Pointer to a const FPU register. */
2289	typedef X86FPUREG const *PCX86FPUREG;
2290
2291	/**
2292	* XMM register union.
2293	*/
2294	typedef union X86XMMREG
2295	{
2296	/** XMM Register view . /
2297	uint128_t xmm;
2298	/** 8-bit view. */
2299	uint8_t au8[16];
2300	/** 16-bit view. */
2301	uint16_t au16[8];
2302	/** 32-bit view. */
2303	uint32_t au32[4];
2304	/** 64-bit view. */
2305	uint64_t au64[2];
2306	/** 128-bit view. (yeah, very helpful) */
2307	uint128_t au128[1];
2308	} X86XMMREG;
2309	#ifndef VBOX_FOR_DTRACE_LIB
2310	AssertCompileSize(X86XMMREG, 16);
2311	#endif
2312	/** Pointer to an XMM register state. */
2313	typedef X86XMMREG *PX86XMMREG;
2314	/** Pointer to a const XMM register state. */
2315	typedef X86XMMREG const *PCX86XMMREG;
2316
2317	/**
2318	* YMM register union.
2319	*/
2320	typedef union X86YMMREG
2321	{
2322	/** 8-bit view. */
2323	uint8_t au8[32];
2324	/** 16-bit view. */
2325	uint16_t au16[16];
2326	/** 32-bit view. */
2327	uint32_t au32[8];
2328	/** 64-bit view. */
2329	uint64_t au64[4];
2330	/** 128-bit view. (yeah, very helpful) */
2331	uint128_t au128[2];
2332	/** XMM sub register view. */
2333	X86XMMREG aXmm[2];
2334	} X86YMMREG;
2335	#ifndef VBOX_FOR_DTRACE_LIB
2336	AssertCompileSize(X86YMMREG, 32);
2337	#endif
2338	/** Pointer to an YMM register state. */
2339	typedef X86YMMREG *PX86YMMREG;
2340	/** Pointer to a const YMM register state. */
2341	typedef X86YMMREG const *PCX86YMMREG;
2342
2343	/**
2344	* ZMM register union.
2345	*/
2346	typedef union X86ZMMREG
2347	{
2348	/** 8-bit view. */
2349	uint8_t au8[64];
2350	/** 16-bit view. */
2351	uint16_t au16[32];
2352	/** 32-bit view. */
2353	uint32_t au32[16];
2354	/** 64-bit view. */
2355	uint64_t au64[8];
2356	/** 128-bit view. (yeah, very helpful) */
2357	uint128_t au128[4];
2358	/** XMM sub register view. */
2359	X86XMMREG aXmm[4];
2360	/** YMM sub register view. */
2361	X86YMMREG aYmm[2];
2362	} X86ZMMREG;
2363	#ifndef VBOX_FOR_DTRACE_LIB
2364	AssertCompileSize(X86ZMMREG, 64);
2365	#endif
2366	/** Pointer to an ZMM register state. */
2367	typedef X86ZMMREG *PX86ZMMREG;
2368	/** Pointer to a const ZMM register state. */
2369	typedef X86ZMMREG const *PCX86ZMMREG;
2370
2371
2372	/**
2373	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2374	* @todo verify this...
2375	*/
2376	#pragma pack(1)
2377	typedef struct X86FPUSTATE
2378	{
2379	/** 0x00 - Control word. */
2380	uint16_t FCW;
2381	/** 0x02 - Alignment word */
2382	uint16_t Dummy1;
2383	/** 0x04 - Status word. */
2384	uint16_t FSW;
2385	/** 0x06 - Alignment word */
2386	uint16_t Dummy2;
2387	/** 0x08 - Tag word */
2388	uint16_t FTW;
2389	/** 0x0a - Alignment word */
2390	uint16_t Dummy3;
2391
2392	/** 0x0c - Instruction pointer. */
2393	uint32_t FPUIP;
2394	/** 0x10 - Code selector. */
2395	uint16_t CS;
2396	/** 0x12 - Opcode. */
2397	uint16_t FOP;
2398	/** 0x14 - FOO. */
2399	uint32_t FPUOO;
2400	/** 0x18 - FOS. */
2401	uint32_t FPUOS;
2402	/** 0x1c - FPU register. */
2403	X86FPUREG regs[8];
2404	} X86FPUSTATE;
2405	#pragma pack()
2406	/** Pointer to a FPU state. */
2407	typedef X86FPUSTATE *PX86FPUSTATE;
2408	/** Pointer to a const FPU state. */
2409	typedef const X86FPUSTATE *PCX86FPUSTATE;
2410
2411	/**
2412	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2413	*/
2414	#pragma pack(1)
2415	typedef struct X86FXSTATE
2416	{
2417	/** 0x00 - Control word. */
2418	uint16_t FCW;
2419	/** 0x02 - Status word. */
2420	uint16_t FSW;
2421	/** 0x04 - Tag word. (The upper byte is always zero.) */
2422	uint16_t FTW;
2423	/** 0x06 - Opcode. */
2424	uint16_t FOP;
2425	/** 0x08 - Instruction pointer. */
2426	uint32_t FPUIP;
2427	/** 0x0c - Code selector. */
2428	uint16_t CS;
2429	uint16_t Rsrvd1;
2430	/** 0x10 - Data pointer. */
2431	uint32_t FPUDP;
2432	/** 0x14 - Data segment */
2433	uint16_t DS;
2434	/** 0x16 */
2435	uint16_t Rsrvd2;
2436	/** 0x18 */
2437	uint32_t MXCSR;
2438	/** 0x1c */
2439	uint32_t MXCSR_MASK;
2440	/** 0x20 - FPU registers. */
2441	X86FPUREG aRegs[8];
2442	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2443	X86XMMREG aXMM[16];
2444	/* - offset 416 - */
2445	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2446	/* - offset 464 - Software usable reserved bits. */
2447	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2448	} X86FXSTATE;
2449	#pragma pack()
2450	/** Pointer to a FPU Extended state. */
2451	typedef X86FXSTATE *PX86FXSTATE;
2452	/** Pointer to a const FPU Extended state. */
2453	typedef const X86FXSTATE *PCX86FXSTATE;
2454
2455	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2456	* magic. Don't forget to update x86.mac if you change this! */
2457	#define X86_OFF_FXSTATE_RSVD 0x1d0
2458	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2459	* forget to update x86.mac if you change this! */
2460	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2461	#ifndef VBOX_FOR_DTRACE_LIB
2462	AssertCompileSize(X86FXSTATE, 512);
2463	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2464	#endif
2465
2466	/** @name FPU status word flags.
2467	* @{ */
2468	/** Exception Flag: Invalid operation. */
2469	#define X86_FSW_IE RT_BIT(0)
2470	/** Exception Flag: Denormalized operand. */
2471	#define X86_FSW_DE RT_BIT(1)
2472	/** Exception Flag: Zero divide. */
2473	#define X86_FSW_ZE RT_BIT(2)
2474	/** Exception Flag: Overflow. */
2475	#define X86_FSW_OE RT_BIT(3)
2476	/** Exception Flag: Underflow. */
2477	#define X86_FSW_UE RT_BIT(4)
2478	/** Exception Flag: Precision. */
2479	#define X86_FSW_PE RT_BIT(5)
2480	/** Stack fault. */
2481	#define X86_FSW_SF RT_BIT(6)
2482	/** Error summary status. */
2483	#define X86_FSW_ES RT_BIT(7)
2484	/** Mask of exceptions flags, excluding the summary bit. */
2485	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2486	/** Mask of exceptions flags, including the summary bit. */
2487	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2488	/** Condition code 0. */
2489	#define X86_FSW_C0 RT_BIT(8)
2490	/** Condition code 1. */
2491	#define X86_FSW_C1 RT_BIT(9)
2492	/** Condition code 2. */
2493	#define X86_FSW_C2 RT_BIT(10)
2494	/** Top of the stack mask. */
2495	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2496	/** TOP shift value. */
2497	#define X86_FSW_TOP_SHIFT 11
2498	/** Mask for getting TOP value after shifting it right. */
2499	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2500	/** Get the TOP value. */
2501	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2502	/** Condition code 3. */
2503	#define X86_FSW_C3 RT_BIT(14)
2504	/** Mask of exceptions flags, including the summary bit. */
2505	#define X86_FSW_C_MASK UINT16_C(0x4700)
2506	/** FPU busy. */
2507	#define X86_FSW_B RT_BIT(15)
2508	/** @} */
2509
2510
2511	/** @name FPU control word flags.
2512	* @{ */
2513	/** Exception Mask: Invalid operation. */
2514	#define X86_FCW_IM RT_BIT(0)
2515	/** Exception Mask: Denormalized operand. */
2516	#define X86_FCW_DM RT_BIT(1)
2517	/** Exception Mask: Zero divide. */
2518	#define X86_FCW_ZM RT_BIT(2)
2519	/** Exception Mask: Overflow. */
2520	#define X86_FCW_OM RT_BIT(3)
2521	/** Exception Mask: Underflow. */
2522	#define X86_FCW_UM RT_BIT(4)
2523	/** Exception Mask: Precision. */
2524	#define X86_FCW_PM RT_BIT(5)
2525	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2526	* @remarks This includes reserved bit 6. */
2527	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2528	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2529	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2530	/** Precision control mask. */
2531	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2532	/** Precision control: 24-bit. */
2533	#define X86_FCW_PC_24 UINT16_C(0x0000)
2534	/** Precision control: Reserved. */
2535	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2536	/** Precision control: 53-bit. */
2537	#define X86_FCW_PC_53 UINT16_C(0x0200)
2538	/** Precision control: 64-bit. */
2539	#define X86_FCW_PC_64 UINT16_C(0x0300)
2540	/** Rounding control mask. */
2541	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2542	/** Rounding control: To nearest. */
2543	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2544	/** Rounding control: Down. */
2545	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2546	/** Rounding control: Up. */
2547	#define X86_FCW_RC_UP UINT16_C(0x0800)
2548	/** Rounding control: Towards zero. */
2549	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2550	/** Bits which should be zero, apparently. */
2551	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2552	/** @} */
2553
2554	/** @name SSE MXCSR
2555	* @{ */
2556	/** Exception Flag: Invalid operation. */
2557	#define X86_MXSCR_IE RT_BIT(0)
2558	/** Exception Flag: Denormalized operand. */
2559	#define X86_MXSCR_DE RT_BIT(1)
2560	/** Exception Flag: Zero divide. */
2561	#define X86_MXSCR_ZE RT_BIT(2)
2562	/** Exception Flag: Overflow. */
2563	#define X86_MXSCR_OE RT_BIT(3)
2564	/** Exception Flag: Underflow. */
2565	#define X86_MXSCR_UE RT_BIT(4)
2566	/** Exception Flag: Precision. */
2567	#define X86_MXSCR_PE RT_BIT(5)
2568
2569	/** Denormals are zero. */
2570	#define X86_MXSCR_DAZ RT_BIT(6)
2571
2572	/** Exception Mask: Invalid operation. */
2573	#define X86_MXSCR_IM RT_BIT(7)
2574	/** Exception Mask: Denormalized operand. */
2575	#define X86_MXSCR_DM RT_BIT(8)
2576	/** Exception Mask: Zero divide. */
2577	#define X86_MXSCR_ZM RT_BIT(9)
2578	/** Exception Mask: Overflow. */
2579	#define X86_MXSCR_OM RT_BIT(10)
2580	/** Exception Mask: Underflow. */
2581	#define X86_MXSCR_UM RT_BIT(11)
2582	/** Exception Mask: Precision. */
2583	#define X86_MXSCR_PM RT_BIT(12)
2584
2585	/** Rounding control mask. */
2586	#define X86_MXSCR_RC_MASK UINT16_C(0x6000)
2587	/** Rounding control: To nearest. */
2588	#define X86_MXSCR_RC_NEAREST UINT16_C(0x0000)
2589	/** Rounding control: Down. */
2590	#define X86_MXSCR_RC_DOWN UINT16_C(0x2000)
2591	/** Rounding control: Up. */
2592	#define X86_MXSCR_RC_UP UINT16_C(0x4000)
2593	/** Rounding control: Towards zero. */
2594	#define X86_MXSCR_RC_ZERO UINT16_C(0x6000)
2595
2596	/** Flush-to-zero for masked underflow. */
2597	#define X86_MXSCR_FZ RT_BIT(15)
2598
2599	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
2600	#define X86_MXSCR_MM RT_BIT(17)
2601	/** @} */
2602
2603	/**
2604	* XSAVE header.
2605	*/
2606	typedef struct X86XSAVEHDR
2607	{
2608	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
2609	uint64_t bmXState;
2610	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
2611	uint64_t bmXComp;
2612	/** Reserved for furture extensions, probably MBZ. */
2613	uint64_t au64Reserved[6];
2614	} X86XSAVEHDR;
2615	#ifndef VBOX_FOR_DTRACE_LIB
2616	AssertCompileSize(X86XSAVEHDR, 64);
2617	#endif
2618	/** Pointer to an XSAVE header. */
2619	typedef X86XSAVEHDR *PX86XSAVEHDR;
2620	/** Pointer to a const XSAVE header. */
2621	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
2622
2623
2624	/**
2625	* The high 128-bit YMM register state (XSAVE_C_YMM).
2626	* (The lower 128-bits being in X86FXSTATE.)
2627	*/
2628	typedef struct X86XSAVEYMMHI
2629	{
2630	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
2631	X86XMMREG aYmmHi[16];
2632	} X86XSAVEYMMHI;
2633	#ifndef VBOX_FOR_DTRACE_LIB
2634	AssertCompileSize(X86XSAVEYMMHI, 256);
2635	#endif
2636	/** Pointer to a high 128-bit YMM register state. */
2637	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
2638	/** Pointer to a const high 128-bit YMM register state. */
2639	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
2640
2641	/**
2642	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
2643	*/
2644	typedef struct X86XSAVEBNDREGS
2645	{
2646	/** Array of registers (BND0...BND3). */
2647	struct
2648	{
2649	/** Lower bound. */
2650	uint64_t uLowerBound;
2651	/** Upper bound. */
2652	uint64_t uUpperBound;
2653	} aRegs[4];
2654	} X86XSAVEBNDREGS;
2655	#ifndef VBOX_FOR_DTRACE_LIB
2656	AssertCompileSize(X86XSAVEBNDREGS, 64);
2657	#endif
2658	/** Pointer to a MPX bound register state. */
2659	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
2660	/** Pointer to a const MPX bound register state. */
2661	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
2662
2663	/**
2664	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
2665	*/
2666	typedef struct X86XSAVEBNDCFG
2667	{
2668	uint64_t fConfig;
2669	uint64_t fStatus;
2670	} X86XSAVEBNDCFG;
2671	#ifndef VBOX_FOR_DTRACE_LIB
2672	AssertCompileSize(X86XSAVEBNDCFG, 16);
2673	#endif
2674	/** Pointer to a MPX bound config and status register state. */
2675	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
2676	/** Pointer to a const MPX bound config and status register state. */
2677	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
2678
2679	/**
2680	* AVX-512 opmask state (XSAVE_C_OPMASK).
2681	*/
2682	typedef struct X86XSAVEOPMASK
2683	{
2684	/** The K0..K7 values. */
2685	uint64_t aKRegs[8];
2686	} X86XSAVEOPMASK;
2687	#ifndef VBOX_FOR_DTRACE_LIB
2688	AssertCompileSize(X86XSAVEOPMASK, 64);
2689	#endif
2690	/** Pointer to a AVX-512 opmask state. */
2691	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
2692	/** Pointer to a const AVX-512 opmask state. */
2693	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
2694
2695	/**
2696	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
2697	*/
2698	typedef struct X86XSAVEZMMHI256
2699	{
2700	/** Upper 256-bits of ZMM0-15. */
2701	X86YMMREG aHi256Regs[16];
2702	} X86XSAVEZMMHI256;
2703	#ifndef VBOX_FOR_DTRACE_LIB
2704	AssertCompileSize(X86XSAVEZMMHI256, 512);
2705	#endif
2706	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
2707	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
2708	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
2709	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
2710
2711	/**
2712	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
2713	*/
2714	typedef struct X86XSAVEZMM16HI
2715	{
2716	/** ZMM16 thru ZMM31. */
2717	X86ZMMREG aRegs[16];
2718	} X86XSAVEZMM16HI;
2719	#ifndef VBOX_FOR_DTRACE_LIB
2720	AssertCompileSize(X86XSAVEZMM16HI, 1024);
2721	#endif
2722	/** Pointer to a state comprising ZMM16-32. */
2723	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
2724	/** Pointer to a const state comprising ZMM16-32. */
2725	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
2726
2727	/**
2728	* AMD Light weight profiling state (XSAVE_C_LWP).
2729	*
2730	* We probably won't play with this as AMD seems to be dropping from their "zen"
2731	* processor micro architecture.
2732	*/
2733	typedef struct X86XSAVELWP
2734	{
2735	/** Details when needed. */
2736	uint64_t auLater[128/8];
2737	} X86XSAVELWP;
2738	#ifndef VBOX_FOR_DTRACE_LIB
2739	AssertCompileSize(X86XSAVELWP, 128);
2740	#endif
2741
2742
2743
2744	typedef struct X86XSAVEAREA
2745	{
2746	/** The x87 and SSE region (or legacy region if you like). */
2747	X86FXSTATE x87;
2748	/** The XSAVE header. */
2749	X86XSAVEHDR Hdr;
2750	/** Beyond the header, there isn't really a fixed layout, but we can
2751	generally assume the YMM (AVX) register extensions are present and
2752	follows immediately. */
2753	union
2754	{
2755	/** This is a typical layout on intel CPUs (good for debuggers). */
2756	struct
2757	{
2758	X86XSAVEYMMHI YmmHi;
2759	X86XSAVEBNDREGS BndRegs;
2760	X86XSAVEBNDCFG BndCfg;
2761	uint8_t abFudgeToMatchDocs[0xB0];
2762	X86XSAVEOPMASK Opmask;
2763	X86XSAVEZMMHI256 ZmmHi256;
2764	X86XSAVEZMM16HI Zmm16Hi;
2765	} Intel;
2766
2767	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
2768	struct
2769	{
2770	X86XSAVEYMMHI YmmHi;
2771	X86XSAVELWP Lwp;
2772	} AmdBd;
2773
2774	/** To enbling static deployments that have a reasonable chance of working for
2775	* the next 3-6 CPU generations without running short on space, we allocate a
2776	* lot of extra space here, making the structure a round 8KB in size. This
2777	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
2778	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
2779	uint8_t ab[8192 - 512 - 64];
2780	} u;
2781	} X86XSAVEAREA;
2782	#ifndef VBOX_FOR_DTRACE_LIB
2783	AssertCompileSize(X86XSAVEAREA, 8192);
2784	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
2785	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
2786	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
2787	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
2788	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
2789	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
2790	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
2791	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
2792	#endif
2793
2794
2795	/** @name XSAVE_C_XXX - XSAVE State Components Bits.
2796	* @{ */
2797	/** Bit 0 - x87 - Legacy FPU state. */
2798	#define XSAVE_C_X87 RT_BIT_64(0)
2799	/** Bit 1 - SSE - 128-bit SSE state. */
2800	#define XSAVE_C_SSE RT_BIT_64(1)
2801	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
2802	#define XSAVE_C_YMM RT_BIT_64(2)
2803	/** Bit 3 - BNDREGS - MPX bound register state. */
2804	#define XSAVE_C_BNDREGS RT_BIT_64(3)
2805	/** Bit 4 - BNDCSR - MPX bound config and status state. */
2806	#define XSAVE_C_BNDCSR RT_BIT_64(4)
2807	/** Bit 5 - Opmask - opmask state. */
2808	#define XSAVE_C_OPMASK RT_BIT_64(5)
2809	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
2810	#define XSAVE_C_ZMM_HI256 RT_BIT_64(6)
2811	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
2812	#define XSAVE_C_ZMM_16HI RT_BIT_64(7)
2813	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
2814	#define XSAVE_C_LWP RT_BIT_64(62)
2815	/** @} */
2816
2817
2818
2819	/** @name Selector Descriptor
2820	* @{
2821	*/
2822
2823	#ifndef VBOX_FOR_DTRACE_LIB
2824	/**
2825	* Descriptor attributes (as seen by VT-x).
2826	*/
2827	typedef struct X86DESCATTRBITS
2828	{
2829	/** 00 - Segment Type. */
2830	unsigned u4Type : 4;
2831	/** 04 - Descriptor Type. System(=0) or code/data selector */
2832	unsigned u1DescType : 1;
2833	/** 05 - Descriptor Privilege level. */
2834	unsigned u2Dpl : 2;
2835	/** 07 - Flags selector present(=1) or not. */
2836	unsigned u1Present : 1;
2837	/** 08 - Segment limit 16-19. */
2838	unsigned u4LimitHigh : 4;
2839	/** 0c - Available for system software. */
2840	unsigned u1Available : 1;
2841	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2842	unsigned u1Long : 1;
2843	/** 0e - This flags meaning depends on the segment type. Try make sense out
2844	* of the intel manual yourself. */
2845	unsigned u1DefBig : 1;
2846	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2847	* clear byte. */
2848	unsigned u1Granularity : 1;
2849	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2850	unsigned u1Unusable : 1;
2851	} X86DESCATTRBITS;
2852	#endif /* !VBOX_FOR_DTRACE_LIB */
2853
2854	/** @name X86DESCATTR masks
2855	* @{ */
2856	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2857	#define X86DESCATTR_DT UINT32_C(0x00000010)
2858	#define X86DESCATTR_DPL UINT32_C(0x00000060)
2859	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
2860	#define X86DESCATTR_P UINT32_C(0x00000080)
2861	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2862	#define X86DESCATTR_AVL UINT32_C(0x00001000)
2863	#define X86DESCATTR_L UINT32_C(0x00002000)
2864	#define X86DESCATTR_D UINT32_C(0x00004000)
2865	#define X86DESCATTR_G UINT32_C(0x00008000)
2866	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2867	/** @} */
2868
2869	#pragma pack(1)
2870	typedef union X86DESCATTR
2871	{
2872	/** Unsigned integer view. */
2873	uint32_t u;
2874	#ifndef VBOX_FOR_DTRACE_LIB
2875	/** Normal view. */
2876	X86DESCATTRBITS n;
2877	#endif
2878	} X86DESCATTR;
2879	#pragma pack()
2880	/** Pointer to descriptor attributes. */
2881	typedef X86DESCATTR *PX86DESCATTR;
2882	/** Pointer to const descriptor attributes. */
2883	typedef const X86DESCATTR *PCX86DESCATTR;
2884
2885	#ifndef VBOX_FOR_DTRACE_LIB
2886
2887	/**
2888	* Generic descriptor table entry
2889	*/
2890	#pragma pack(1)
2891	typedef struct X86DESCGENERIC
2892	{
2893	/** 00 - Limit - Low word. */
2894	unsigned u16LimitLow : 16;
2895	/** 10 - Base address - lowe word.
2896	* Don't try set this to 24 because MSC is doing stupid things then. */
2897	unsigned u16BaseLow : 16;
2898	/** 20 - Base address - first 8 bits of high word. */
2899	unsigned u8BaseHigh1 : 8;
2900	/** 28 - Segment Type. */
2901	unsigned u4Type : 4;
2902	/** 2c - Descriptor Type. System(=0) or code/data selector */
2903	unsigned u1DescType : 1;
2904	/** 2d - Descriptor Privilege level. */
2905	unsigned u2Dpl : 2;
2906	/** 2f - Flags selector present(=1) or not. */
2907	unsigned u1Present : 1;
2908	/** 30 - Segment limit 16-19. */
2909	unsigned u4LimitHigh : 4;
2910	/** 34 - Available for system software. */
2911	unsigned u1Available : 1;
2912	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2913	unsigned u1Long : 1;
2914	/** 36 - This flags meaning depends on the segment type. Try make sense out
2915	* of the intel manual yourself. */
2916	unsigned u1DefBig : 1;
2917	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
2918	* clear byte. */
2919	unsigned u1Granularity : 1;
2920	/** 38 - Base address - highest 8 bits. */
2921	unsigned u8BaseHigh2 : 8;
2922	} X86DESCGENERIC;
2923	#pragma pack()
2924	/** Pointer to a generic descriptor entry. */
2925	typedef X86DESCGENERIC *PX86DESCGENERIC;
2926	/** Pointer to a const generic descriptor entry. */
2927	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2928
2929	/** @name Bit offsets of X86DESCGENERIC members.
2930	* @{*/
2931	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
2932	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
2933	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
2934	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
2935	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
2936	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
2937	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
2938	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
2939	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
2940	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
2941	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
2942	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
2943	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
2944	/** @} */
2945
2946	/**
2947	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2948	*/
2949	typedef struct X86DESCGATE
2950	{
2951	/** 00 - Target code segment offset - Low word.
2952	* Ignored if task-gate. */
2953	unsigned u16OffsetLow : 16;
2954	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2955	* TSS selector if task-gate. */
2956	unsigned u16Sel : 16;
2957	/** 20 - Number of parameters for a call-gate.
2958	* Ignored if interrupt-, trap- or task-gate. */
2959	unsigned u4ParmCount : 4;
2960	/** 24 - Reserved / ignored. */
2961	unsigned u4Reserved : 4;
2962	/** 28 - Segment Type. */
2963	unsigned u4Type : 4;
2964	/** 2c - Descriptor Type (0 = system). */
2965	unsigned u1DescType : 1;
2966	/** 2d - Descriptor Privilege level. */
2967	unsigned u2Dpl : 2;
2968	/** 2f - Flags selector present(=1) or not. */
2969	unsigned u1Present : 1;
2970	/** 30 - Target code segment offset - High word.
2971	* Ignored if task-gate. */
2972	unsigned u16OffsetHigh : 16;
2973	} X86DESCGATE;
2974	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2975	typedef X86DESCGATE *PX86DESCGATE;
2976	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2977	typedef const X86DESCGATE *PCX86DESCGATE;
2978
2979	#endif /* VBOX_FOR_DTRACE_LIB */
2980
2981	/**
2982	* Descriptor table entry.
2983	*/
2984	#pragma pack(1)
2985	typedef union X86DESC
2986	{
2987	#ifndef VBOX_FOR_DTRACE_LIB
2988	/** Generic descriptor view. */
2989	X86DESCGENERIC Gen;
2990	/** Gate descriptor view. */
2991	X86DESCGATE Gate;
2992	#endif
2993
2994	/** 8 bit unsigned integer view. */
2995	uint8_t au8[8];
2996	/** 16 bit unsigned integer view. */
2997	uint16_t au16[4];
2998	/** 32 bit unsigned integer view. */
2999	uint32_t au32[2];
3000	/** 64 bit unsigned integer view. */
3001	uint64_t au64[1];
3002	/** Unsigned integer view. */
3003	uint64_t u;
3004	} X86DESC;
3005	#ifndef VBOX_FOR_DTRACE_LIB
3006	AssertCompileSize(X86DESC, 8);
3007	#endif
3008	#pragma pack()
3009	/** Pointer to descriptor table entry. */
3010	typedef X86DESC *PX86DESC;
3011	/** Pointer to const descriptor table entry. */
3012	typedef const X86DESC *PCX86DESC;
3013
3014	/** @def X86DESC_BASE
3015	* Return the base address of a descriptor.
3016	*/
3017	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3018	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3019	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3020	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3021
3022	/** @def X86DESC_LIMIT
3023	* Return the limit of a descriptor.
3024	*/
3025	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3026	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3027	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3028
3029	/** @def X86DESC_LIMIT_G
3030	* Return the limit of a descriptor with the granularity bit taken into account.
3031	* @returns Selector limit (uint32_t).
3032	* @param a_pDesc Pointer to the descriptor.
3033	*/
3034	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3035	( (a_pDesc)->Gen.u1Granularity \
3036	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3037	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3038	)
3039
3040	/** @def X86DESC_GET_HID_ATTR
3041	* Get the descriptor attributes for the hidden register.
3042	*/
3043	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3044	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3045
3046	#ifndef VBOX_FOR_DTRACE_LIB
3047
3048	/**
3049	* 64 bits generic descriptor table entry
3050	* Note: most of these bits have no meaning in long mode.
3051	*/
3052	#pragma pack(1)
3053	typedef struct X86DESC64GENERIC
3054	{
3055	/** Limit - Low word - IGNORED. */
3056	unsigned u16LimitLow : 16;
3057	/** Base address - low word. - IGNORED
3058	* Don't try set this to 24 because MSC is doing stupid things then. */
3059	unsigned u16BaseLow : 16;
3060	/** Base address - first 8 bits of high word. - IGNORED */
3061	unsigned u8BaseHigh1 : 8;
3062	/** Segment Type. */
3063	unsigned u4Type : 4;
3064	/** Descriptor Type. System(=0) or code/data selector */
3065	unsigned u1DescType : 1;
3066	/** Descriptor Privilege level. */
3067	unsigned u2Dpl : 2;
3068	/** Flags selector present(=1) or not. */
3069	unsigned u1Present : 1;
3070	/** Segment limit 16-19. - IGNORED */
3071	unsigned u4LimitHigh : 4;
3072	/** Available for system software. - IGNORED */
3073	unsigned u1Available : 1;
3074	/** Long mode flag. */
3075	unsigned u1Long : 1;
3076	/** This flags meaning depends on the segment type. Try make sense out
3077	* of the intel manual yourself. */
3078	unsigned u1DefBig : 1;
3079	/** Granularity of the limit. If set 4KB granularity is used, if
3080	* clear byte. - IGNORED */
3081	unsigned u1Granularity : 1;
3082	/** Base address - highest 8 bits. - IGNORED */
3083	unsigned u8BaseHigh2 : 8;
3084	/** Base address - bits 63-32. */
3085	unsigned u32BaseHigh3 : 32;
3086	unsigned u8Reserved : 8;
3087	unsigned u5Zeros : 5;
3088	unsigned u19Reserved : 19;
3089	} X86DESC64GENERIC;
3090	#pragma pack()
3091	/** Pointer to a generic descriptor entry. */
3092	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3093	/** Pointer to a const generic descriptor entry. */
3094	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3095
3096	/**
3097	* System descriptor table entry (64 bits)
3098	*
3099	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3100	*/
3101	#pragma pack(1)
3102	typedef struct X86DESC64SYSTEM
3103	{
3104	/** Limit - Low word. */
3105	unsigned u16LimitLow : 16;
3106	/** Base address - lowe word.
3107	* Don't try set this to 24 because MSC is doing stupid things then. */
3108	unsigned u16BaseLow : 16;
3109	/** Base address - first 8 bits of high word. */
3110	unsigned u8BaseHigh1 : 8;
3111	/** Segment Type. */
3112	unsigned u4Type : 4;
3113	/** Descriptor Type. System(=0) or code/data selector */
3114	unsigned u1DescType : 1;
3115	/** Descriptor Privilege level. */
3116	unsigned u2Dpl : 2;
3117	/** Flags selector present(=1) or not. */
3118	unsigned u1Present : 1;
3119	/** Segment limit 16-19. */
3120	unsigned u4LimitHigh : 4;
3121	/** Available for system software. */
3122	unsigned u1Available : 1;
3123	/** Reserved - 0. */
3124	unsigned u1Reserved : 1;
3125	/** This flags meaning depends on the segment type. Try make sense out
3126	* of the intel manual yourself. */
3127	unsigned u1DefBig : 1;
3128	/** Granularity of the limit. If set 4KB granularity is used, if
3129	* clear byte. */
3130	unsigned u1Granularity : 1;
3131	/** Base address - bits 31-24. */
3132	unsigned u8BaseHigh2 : 8;
3133	/** Base address - bits 63-32. */
3134	unsigned u32BaseHigh3 : 32;
3135	unsigned u8Reserved : 8;
3136	unsigned u5Zeros : 5;
3137	unsigned u19Reserved : 19;
3138	} X86DESC64SYSTEM;
3139	#pragma pack()
3140	/** Pointer to a system descriptor entry. */
3141	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3142	/** Pointer to a const system descriptor entry. */
3143	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3144
3145	/**
3146	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3147	*/
3148	typedef struct X86DESC64GATE
3149	{
3150	/** Target code segment offset - Low word. */
3151	unsigned u16OffsetLow : 16;
3152	/** Target code segment selector. */
3153	unsigned u16Sel : 16;
3154	/** Interrupt stack table for interrupt- and trap-gates.
3155	* Ignored by call-gates. */
3156	unsigned u3IST : 3;
3157	/** Reserved / ignored. */
3158	unsigned u5Reserved : 5;
3159	/** Segment Type. */
3160	unsigned u4Type : 4;
3161	/** Descriptor Type (0 = system). */
3162	unsigned u1DescType : 1;
3163	/** Descriptor Privilege level. */
3164	unsigned u2Dpl : 2;
3165	/** Flags selector present(=1) or not. */
3166	unsigned u1Present : 1;
3167	/** Target code segment offset - High word.
3168	* Ignored if task-gate. */
3169	unsigned u16OffsetHigh : 16;
3170	/** Target code segment offset - Top dword.
3171	* Ignored if task-gate. */
3172	unsigned u32OffsetTop : 32;
3173	/** Reserved / ignored / must be zero.
3174	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3175	unsigned u32Reserved : 32;
3176	} X86DESC64GATE;
3177	AssertCompileSize(X86DESC64GATE, 16);
3178	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3179	typedef X86DESC64GATE *PX86DESC64GATE;
3180	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3181	typedef const X86DESC64GATE *PCX86DESC64GATE;
3182
3183	#endif /* VBOX_FOR_DTRACE_LIB */
3184
3185	/**
3186	* Descriptor table entry.
3187	*/
3188	#pragma pack(1)
3189	typedef union X86DESC64
3190	{
3191	#ifndef VBOX_FOR_DTRACE_LIB
3192	/** Generic descriptor view. */
3193	X86DESC64GENERIC Gen;
3194	/** System descriptor view. */
3195	X86DESC64SYSTEM System;
3196	/** Gate descriptor view. */
3197	X86DESC64GATE Gate;
3198	#endif
3199
3200	/** 8 bit unsigned integer view. */
3201	uint8_t au8[16];
3202	/** 16 bit unsigned integer view. */
3203	uint16_t au16[8];
3204	/** 32 bit unsigned integer view. */
3205	uint32_t au32[4];
3206	/** 64 bit unsigned integer view. */
3207	uint64_t au64[2];
3208	} X86DESC64;
3209	#ifndef VBOX_FOR_DTRACE_LIB
3210	AssertCompileSize(X86DESC64, 16);
3211	#endif
3212	#pragma pack()
3213	/** Pointer to descriptor table entry. */
3214	typedef X86DESC64 *PX86DESC64;
3215	/** Pointer to const descriptor table entry. */
3216	typedef const X86DESC64 *PCX86DESC64;
3217
3218	/** @def X86DESC64_BASE
3219	* Return the base of a 64-bit descriptor.
3220	*/
3221	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3222	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3223	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3224	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3225	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3226
3227
3228
3229	/** @name Host system descriptor table entry - Use with care!
3230	* @{ */
3231	/** Host system descriptor table entry. */
3232	#if HC_ARCH_BITS == 64
3233	typedef X86DESC64 X86DESCHC;
3234	#else
3235	typedef X86DESC X86DESCHC;
3236	#endif
3237	/** Pointer to a host system descriptor table entry. */
3238	#if HC_ARCH_BITS == 64
3239	typedef PX86DESC64 PX86DESCHC;
3240	#else
3241	typedef PX86DESC PX86DESCHC;
3242	#endif
3243	/** Pointer to a const host system descriptor table entry. */
3244	#if HC_ARCH_BITS == 64
3245	typedef PCX86DESC64 PCX86DESCHC;
3246	#else
3247	typedef PCX86DESC PCX86DESCHC;
3248	#endif
3249	/** @} */
3250
3251
3252	/** @name Selector Descriptor Types.
3253	* @{
3254	*/
3255
3256	/** @name Non-System Selector Types.
3257	* @{ */
3258	/** Code(=set)/Data(=clear) bit. */
3259	#define X86_SEL_TYPE_CODE 8
3260	/** Memory(=set)/System(=clear) bit. */
3261	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
3262	/** Accessed bit. */
3263	#define X86_SEL_TYPE_ACCESSED 1
3264	/** Expand down bit (for data selectors only). */
3265	#define X86_SEL_TYPE_DOWN 4
3266	/** Conforming bit (for code selectors only). */
3267	#define X86_SEL_TYPE_CONF 4
3268	/** Write bit (for data selectors only). */
3269	#define X86_SEL_TYPE_WRITE 2
3270	/** Read bit (for code selectors only). */
3271	#define X86_SEL_TYPE_READ 2
3272	/** The bit number of the code segment read bit (relative to u4Type). */
3273	#define X86_SEL_TYPE_READ_BIT 1
3274
3275	/** Read only selector type. */
3276	#define X86_SEL_TYPE_RO 0
3277	/** Accessed read only selector type. */
3278	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
3279	/** Read write selector type. */
3280	#define X86_SEL_TYPE_RW 2
3281	/** Accessed read write selector type. */
3282	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
3283	/** Expand down read only selector type. */
3284	#define X86_SEL_TYPE_RO_DOWN 4
3285	/** Accessed expand down read only selector type. */
3286	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
3287	/** Expand down read write selector type. */
3288	#define X86_SEL_TYPE_RW_DOWN 6
3289	/** Accessed expand down read write selector type. */
3290	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
3291	/** Execute only selector type. */
3292	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
3293	/** Accessed execute only selector type. */
3294	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3295	/** Execute and read selector type. */
3296	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
3297	/** Accessed execute and read selector type. */
3298	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3299	/** Conforming execute only selector type. */
3300	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3301	/** Accessed Conforming execute only selector type. */
3302	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3303	/** Conforming execute and write selector type. */
3304	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3305	/** Accessed Conforming execute and write selector type. */
3306	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3307	/** @} */
3308
3309
3310	/** @name System Selector Types.
3311	* @{ */
3312	/** The TSS busy bit mask. */
3313	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3314
3315	/** Undefined system selector type. */
3316	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3317	/** 286 TSS selector. */
3318	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3319	/** LDT selector. */
3320	#define X86_SEL_TYPE_SYS_LDT 2
3321	/** 286 TSS selector - Busy. */
3322	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3323	/** 286 Callgate selector. */
3324	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3325	/** Taskgate selector. */
3326	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3327	/** 286 Interrupt gate selector. */
3328	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3329	/** 286 Trapgate selector. */
3330	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3331	/** Undefined system selector. */
3332	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3333	/** 386 TSS selector. */
3334	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3335	/** Undefined system selector. */
3336	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3337	/** 386 TSS selector - Busy. */
3338	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3339	/** 386 Callgate selector. */
3340	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3341	/** Undefined system selector. */
3342	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3343	/** 386 Interruptgate selector. */
3344	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3345	/** 386 Trapgate selector. */
3346	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3347	/** @} */
3348
3349	/** @name AMD64 System Selector Types.
3350	* @{ */
3351	/** LDT selector. */
3352	#define AMD64_SEL_TYPE_SYS_LDT 2
3353	/** TSS selector - Busy. */
3354	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3355	/** TSS selector - Busy. */
3356	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3357	/** Callgate selector. */
3358	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3359	/** Interruptgate selector. */
3360	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3361	/** Trapgate selector. */
3362	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3363	/** @} */
3364
3365	/** @} */
3366
3367
3368	/** @name Descriptor Table Entry Flag Masks.
3369	* These are for the 2nd 32-bit word of a descriptor.
3370	* @{ */
3371	/** Bits 8-11 - TYPE - Descriptor type mask. */
3372	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
3373	/** Bit 12 - S - System (=0) or Code/Data (=1). */
3374	#define X86_DESC_S RT_BIT(12)
3375	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3376	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
3377	/** Bit 15 - P - Present. */
3378	#define X86_DESC_P RT_BIT(15)
3379	/** Bit 20 - AVL - Available for system software. */
3380	#define X86_DESC_AVL RT_BIT(20)
3381	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3382	#define X86_DESC_DB RT_BIT(22)
3383	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3384	* used, if clear byte. */
3385	#define X86_DESC_G RT_BIT(23)
3386	/** @} */
3387
3388	/** @} */
3389
3390
3391	/** @name Task Segments.
3392	* @{
3393	*/
3394
3395	/**
3396	* The minimum TSS descriptor limit for 286 tasks.
3397	*/
3398	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3399
3400	/**
3401	* The minimum TSS descriptor segment limit for 386 tasks.
3402	*/
3403	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3404
3405	/**
3406	* 16-bit Task Segment (TSS).
3407	*/
3408	#pragma pack(1)
3409	typedef struct X86TSS16
3410	{
3411	/** Back link to previous task. (static) */
3412	RTSEL selPrev;
3413	/** Ring-0 stack pointer. (static) */
3414	uint16_t sp0;
3415	/** Ring-0 stack segment. (static) */
3416	RTSEL ss0;
3417	/** Ring-1 stack pointer. (static) */
3418	uint16_t sp1;
3419	/** Ring-1 stack segment. (static) */
3420	RTSEL ss1;
3421	/** Ring-2 stack pointer. (static) */
3422	uint16_t sp2;
3423	/** Ring-2 stack segment. (static) */
3424	RTSEL ss2;
3425	/** IP before task switch. */
3426	uint16_t ip;
3427	/** FLAGS before task switch. */
3428	uint16_t flags;
3429	/** AX before task switch. */
3430	uint16_t ax;
3431	/** CX before task switch. */
3432	uint16_t cx;
3433	/** DX before task switch. */
3434	uint16_t dx;
3435	/** BX before task switch. */
3436	uint16_t bx;
3437	/** SP before task switch. */
3438	uint16_t sp;
3439	/** BP before task switch. */
3440	uint16_t bp;
3441	/** SI before task switch. */
3442	uint16_t si;
3443	/** DI before task switch. */
3444	uint16_t di;
3445	/** ES before task switch. */
3446	RTSEL es;
3447	/** CS before task switch. */
3448	RTSEL cs;
3449	/** SS before task switch. */
3450	RTSEL ss;
3451	/** DS before task switch. */
3452	RTSEL ds;
3453	/** LDTR before task switch. */
3454	RTSEL selLdt;
3455	} X86TSS16;
3456	#ifndef VBOX_FOR_DTRACE_LIB
3457	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3458	#endif
3459	#pragma pack()
3460	/** Pointer to a 16-bit task segment. */
3461	typedef X86TSS16 *PX86TSS16;
3462	/** Pointer to a const 16-bit task segment. */
3463	typedef const X86TSS16 *PCX86TSS16;
3464
3465
3466	/**
3467	* 32-bit Task Segment (TSS).
3468	*/
3469	#pragma pack(1)
3470	typedef struct X86TSS32
3471	{
3472	/** Back link to previous task. (static) */
3473	RTSEL selPrev;
3474	uint16_t padding1;
3475	/** Ring-0 stack pointer. (static) */
3476	uint32_t esp0;
3477	/** Ring-0 stack segment. (static) */
3478	RTSEL ss0;
3479	uint16_t padding_ss0;
3480	/** Ring-1 stack pointer. (static) */
3481	uint32_t esp1;
3482	/** Ring-1 stack segment. (static) */
3483	RTSEL ss1;
3484	uint16_t padding_ss1;
3485	/** Ring-2 stack pointer. (static) */
3486	uint32_t esp2;
3487	/** Ring-2 stack segment. (static) */
3488	RTSEL ss2;
3489	uint16_t padding_ss2;
3490	/** Page directory for the task. (static) */
3491	uint32_t cr3;
3492	/** EIP before task switch. */
3493	uint32_t eip;
3494	/** EFLAGS before task switch. */
3495	uint32_t eflags;
3496	/** EAX before task switch. */
3497	uint32_t eax;
3498	/** ECX before task switch. */
3499	uint32_t ecx;
3500	/** EDX before task switch. */
3501	uint32_t edx;
3502	/** EBX before task switch. */
3503	uint32_t ebx;
3504	/** ESP before task switch. */
3505	uint32_t esp;
3506	/** EBP before task switch. */
3507	uint32_t ebp;
3508	/** ESI before task switch. */
3509	uint32_t esi;
3510	/** EDI before task switch. */
3511	uint32_t edi;
3512	/** ES before task switch. */
3513	RTSEL es;
3514	uint16_t padding_es;
3515	/** CS before task switch. */
3516	RTSEL cs;
3517	uint16_t padding_cs;
3518	/** SS before task switch. */
3519	RTSEL ss;
3520	uint16_t padding_ss;
3521	/** DS before task switch. */
3522	RTSEL ds;
3523	uint16_t padding_ds;
3524	/** FS before task switch. */
3525	RTSEL fs;
3526	uint16_t padding_fs;
3527	/** GS before task switch. */
3528	RTSEL gs;
3529	uint16_t padding_gs;
3530	/** LDTR before task switch. */
3531	RTSEL selLdt;
3532	uint16_t padding_ldt;
3533	/** Debug trap flag */
3534	uint16_t fDebugTrap;
3535	/** Offset relative to the TSS of the start of the I/O Bitmap
3536	* and the end of the interrupt redirection bitmap. */
3537	uint16_t offIoBitmap;
3538	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3539	uint8_t IntRedirBitmap[32];
3540	} X86TSS32;
3541	#pragma pack()
3542	/** Pointer to task segment. */
3543	typedef X86TSS32 *PX86TSS32;
3544	/** Pointer to const task segment. */
3545	typedef const X86TSS32 *PCX86TSS32;
3546
3547	/**
3548	* 64-bit Task segment.
3549	*/
3550	#pragma pack(1)
3551	typedef struct X86TSS64
3552	{
3553	/** Reserved. */
3554	uint32_t u32Reserved;
3555	/** Ring-0 stack pointer. (static) */
3556	uint64_t rsp0;
3557	/** Ring-1 stack pointer. (static) */
3558	uint64_t rsp1;
3559	/** Ring-2 stack pointer. (static) */
3560	uint64_t rsp2;
3561	/** Reserved. */
3562	uint32_t u32Reserved2[2];
3563	/* IST */
3564	uint64_t ist1;
3565	uint64_t ist2;
3566	uint64_t ist3;
3567	uint64_t ist4;
3568	uint64_t ist5;
3569	uint64_t ist6;
3570	uint64_t ist7;
3571	/* Reserved. */
3572	uint16_t u16Reserved[5];
3573	/** Offset relative to the TSS of the start of the I/O Bitmap
3574	* and the end of the interrupt redirection bitmap. */
3575	uint16_t offIoBitmap;
3576	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
3577	uint8_t IntRedirBitmap[32];
3578	} X86TSS64;
3579	#pragma pack()
3580	/** Pointer to a 64-bit task segment. */
3581	typedef X86TSS64 *PX86TSS64;
3582	/** Pointer to a const 64-bit task segment. */
3583	typedef const X86TSS64 *PCX86TSS64;
3584	#ifndef VBOX_FOR_DTRACE_LIB
3585	AssertCompileSize(X86TSS64, 136);
3586	#endif
3587
3588	/** @} */
3589
3590
3591	/** @name Selectors.
3592	* @{
3593	*/
3594
3595	/**
3596	* The shift used to convert a selector from and to index an index (C).
3597	*/
3598	#define X86_SEL_SHIFT 3
3599
3600	/**
3601	* The mask used to mask off the table indicator and RPL of an selector.
3602	*/
3603	#define X86_SEL_MASK 0xfff8U
3604
3605	/**
3606	* The mask used to mask off the RPL of an selector.
3607	* This is suitable for checking for NULL selectors.
3608	*/
3609	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3610
3611	/**
3612	* The bit indicating that a selector is in the LDT and not in the GDT.
3613	*/
3614	#define X86_SEL_LDT 0x0004U
3615
3616	/**
3617	* The bit mask for getting the RPL of a selector.
3618	*/
3619	#define X86_SEL_RPL 0x0003U
3620
3621	/**
3622	* The mask covering both RPL and LDT.
3623	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3624	* checks.
3625	*/
3626	#define X86_SEL_RPL_LDT 0x0007U
3627
3628	/** @} */
3629
3630
3631	/**
3632	* x86 Exceptions/Faults/Traps.
3633	*/
3634	typedef enum X86XCPT
3635	{
3636	/** \#DE - Divide error. */
3637	X86_XCPT_DE = 0x00,
3638	/** \#DB - Debug event (single step, DRx, ..) */
3639	X86_XCPT_DB = 0x01,
3640	/** NMI - Non-Maskable Interrupt */
3641	X86_XCPT_NMI = 0x02,
3642	/** \#BP - Breakpoint (INT3). */
3643	X86_XCPT_BP = 0x03,
3644	/** \#OF - Overflow (INTO). */
3645	X86_XCPT_OF = 0x04,
3646	/** \#BR - Bound range exceeded (BOUND). */
3647	X86_XCPT_BR = 0x05,
3648	/** \#UD - Undefined opcode. */
3649	X86_XCPT_UD = 0x06,
3650	/** \#NM - Device not available (math coprocessor device). */
3651	X86_XCPT_NM = 0x07,
3652	/** \#DF - Double fault. */
3653	X86_XCPT_DF = 0x08,
3654	/** ??? - Coprocessor segment overrun (obsolete). */
3655	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3656	/** \#TS - Taskswitch (TSS). */
3657	X86_XCPT_TS = 0x0a,
3658	/** \#NP - Segment no present. */
3659	X86_XCPT_NP = 0x0b,
3660	/** \#SS - Stack segment fault. */
3661	X86_XCPT_SS = 0x0c,
3662	/** \#GP - General protection fault. */
3663	X86_XCPT_GP = 0x0d,
3664	/** \#PF - Page fault. */
3665	X86_XCPT_PF = 0x0e,
3666	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3667	/** \#MF - Math fault (FPU). */
3668	X86_XCPT_MF = 0x10,
3669	/** \#AC - Alignment check. */
3670	X86_XCPT_AC = 0x11,
3671	/** \#MC - Machine check. */
3672	X86_XCPT_MC = 0x12,
3673	/** \#XF - SIMD Floating-Pointer Exception. */
3674	X86_XCPT_XF = 0x13,
3675	/** \#VE - Virtualization Exception. */
3676	X86_XCPT_VE = 0x14,
3677	/** \#SX - Security Exception. */
3678	X86_XCPT_SX = 0x1f
3679	} X86XCPT;
3680	/** Pointer to a x86 exception code. */
3681	typedef X86XCPT *PX86XCPT;
3682	/** Pointer to a const x86 exception code. */
3683	typedef const X86XCPT *PCX86XCPT;
3684	/** The maximum exception value. */
3685	#define X86_XCPT_MAX (X86_XCPT_SX)
3686
3687
3688	/** @name Trap Error Codes
3689	* @{
3690	*/
3691	/** External indicator. */
3692	#define X86_TRAP_ERR_EXTERNAL 1
3693	/** IDT indicator. */
3694	#define X86_TRAP_ERR_IDT 2
3695	/** Descriptor table indicator - If set LDT, if clear GDT. */
3696	#define X86_TRAP_ERR_TI 4
3697	/** Mask for getting the selector. */
3698	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3699	/** Shift for getting the selector table index (C type index). */
3700	#define X86_TRAP_ERR_SEL_SHIFT 3
3701	/** @} */
3702
3703
3704	/** @name \#PF Trap Error Codes
3705	* @{
3706	*/
3707	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3708	#define X86_TRAP_PF_P RT_BIT(0)
3709	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3710	#define X86_TRAP_PF_RW RT_BIT(1)
3711	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3712	#define X86_TRAP_PF_US RT_BIT(2)
3713	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3714	#define X86_TRAP_PF_RSVD RT_BIT(3)
3715	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3716	#define X86_TRAP_PF_ID RT_BIT(4)
3717	/** @} */
3718
3719	#pragma pack(1)
3720	/**
3721	* 16-bit IDTR.
3722	*/
3723	typedef struct X86IDTR16
3724	{
3725	/** Offset. */
3726	uint16_t offSel;
3727	/** Selector. */
3728	uint16_t uSel;
3729	} X86IDTR16, *PX86IDTR16;
3730	#pragma pack()
3731
3732	#pragma pack(1)
3733	/**
3734	* 32-bit IDTR/GDTR.
3735	*/
3736	typedef struct X86XDTR32
3737	{
3738	/** Size of the descriptor table. */
3739	uint16_t cb;
3740	/** Address of the descriptor table. */
3741	#ifndef VBOX_FOR_DTRACE_LIB
3742	uint32_t uAddr;
3743	#else
3744	uint16_t au16Addr[2];
3745	#endif
3746	} X86XDTR32, *PX86XDTR32;
3747	#pragma pack()
3748
3749	#pragma pack(1)
3750	/**
3751	* 64-bit IDTR/GDTR.
3752	*/
3753	typedef struct X86XDTR64
3754	{
3755	/** Size of the descriptor table. */
3756	uint16_t cb;
3757	/** Address of the descriptor table. */
3758	#ifndef VBOX_FOR_DTRACE_LIB
3759	uint64_t uAddr;
3760	#else
3761	uint16_t au16Addr[4];
3762	#endif
3763	} X86XDTR64, *PX86XDTR64;
3764	#pragma pack()
3765
3766
3767	/** @name ModR/M
3768	* @{ */
3769	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3770	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3771	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3772	#define X86_MODRM_REG_SHIFT 3
3773	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3774	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3775	#define X86_MODRM_MOD_SHIFT 6
3776	#ifndef VBOX_FOR_DTRACE_LIB
3777	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3778	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3779	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3780	#endif
3781	/** @} */
3782
3783	/** @name SIB
3784	* @{ */
3785	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3786	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3787	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3788	#define X86_SIB_INDEX_SHIFT 3
3789	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3790	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3791	#define X86_SIB_SCALE_SHIFT 6
3792	#ifndef VBOX_FOR_DTRACE_LIB
3793	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3794	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3795	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3796	#endif
3797	/** @} */
3798
3799	/** @name General register indexes
3800	* @{ */
3801	#define X86_GREG_xAX 0
3802	#define X86_GREG_xCX 1
3803	#define X86_GREG_xDX 2
3804	#define X86_GREG_xBX 3
3805	#define X86_GREG_xSP 4
3806	#define X86_GREG_xBP 5
3807	#define X86_GREG_xSI 6
3808	#define X86_GREG_xDI 7
3809	#define X86_GREG_x8 8
3810	#define X86_GREG_x9 9
3811	#define X86_GREG_x10 10
3812	#define X86_GREG_x11 11
3813	#define X86_GREG_x12 12
3814	#define X86_GREG_x13 13
3815	#define X86_GREG_x14 14
3816	#define X86_GREG_x15 15
3817	/** @} */
3818
3819	/** @name X86_SREG_XXX - Segment register indexes.
3820	* @{ */
3821	#define X86_SREG_ES 0
3822	#define X86_SREG_CS 1
3823	#define X86_SREG_SS 2
3824	#define X86_SREG_DS 3
3825	#define X86_SREG_FS 4
3826	#define X86_SREG_GS 5
3827	/** @} */
3828	/** Segment register count. */
3829	#define X86_SREG_COUNT 6
3830
3831
3832	/** @name X86_OP_XXX - Prefixes
3833	* @{ */
3834	#define X86_OP_PRF_CS UINT8_C(0x2e)
3835	#define X86_OP_PRF_SS UINT8_C(0x36)
3836	#define X86_OP_PRF_DS UINT8_C(0x3e)
3837	#define X86_OP_PRF_ES UINT8_C(0x26)
3838	#define X86_OP_PRF_FS UINT8_C(0x64)
3839	#define X86_OP_PRF_GS UINT8_C(0x65)
3840	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3841	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3842	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3843	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3844	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3845	#define X86_OP_REX_B UINT8_C(0x41)
3846	#define X86_OP_REX_X UINT8_C(0x42)
3847	#define X86_OP_REX_R UINT8_C(0x44)
3848	#define X86_OP_REX_W UINT8_C(0x48)
3849	/** @} */
3850
3851
3852	/** @} */
3853
3854	#endif
3855

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source: vbox/trunk/include/iprt/x86.h@ 54924

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