VirtualBox

source: vbox/trunk/include/iprt/x86.mac@ 47942

Last change on this file since 47942 was 47876, checked in by vboxsync, 11 years ago

kmk incs
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 36.2 KB
Line 
1%ifndef ___iprt_x86_h
2%define ___iprt_x86_h
3%ifndef VBOX_FOR_DTRACE_LIB
4%else
5%endif
6%ifdef RT_OS_SOLARIS
7%endif
8%ifndef VBOX_FOR_DTRACE_LIB
9%endif
10%ifndef VBOX_FOR_DTRACE_LIB
11%endif
12%ifndef VBOX_FOR_DTRACE_LIB
13%endif
14%define X86_EFL_CF RT_BIT(0)
15%define X86_EFL_1 RT_BIT(1)
16%define X86_EFL_PF RT_BIT(2)
17%define X86_EFL_AF RT_BIT(4)
18%define X86_EFL_ZF RT_BIT(6)
19%define X86_EFL_SF RT_BIT(7)
20%define X86_EFL_TF RT_BIT(8)
21%define X86_EFL_IF RT_BIT(9)
22%define X86_EFL_DF RT_BIT(10)
23%define X86_EFL_OF RT_BIT(11)
24%define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
25%define X86_EFL_NT RT_BIT(14)
26%define X86_EFL_RF RT_BIT(16)
27%define X86_EFL_VM RT_BIT(17)
28%define X86_EFL_AC RT_BIT(18)
29%define X86_EFL_VIF RT_BIT(19)
30%define X86_EFL_VIP RT_BIT(20)
31%define X86_EFL_ID RT_BIT(21)
32%define X86_EFL_LIVE_MASK 0x003f7fd5
33%define X86_EFL_RA1_MASK RT_BIT_32(1)
34%define X86_EFL_IOPL_SHIFT 12
35%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
36%define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
37 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
38%ifndef VBOX_FOR_DTRACE_LIB
39%else
40%endif
41%ifndef VBOX_FOR_DTRACE_LIB
42%else
43%endif
44%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
45%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
46%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
47%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
48%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
49%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
50%define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
51%define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
52%define X86_CPUID_VENDOR_VIA_EDX 0x48727561
53%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
54%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
55%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
56%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
57%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
58%define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
59%define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
60%define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
61%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
62%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
63%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
64%define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
65%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
66%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
67%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
68%define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
69%define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
70%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
71%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
72%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
73%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
74%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
75%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
76%define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
77%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
78%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
79%define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
80%define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
81%define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
82%define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
83%define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
84%define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
85%define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
86%define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
87%define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
88%define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
89%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
90%define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
91%define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
92%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
93%define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
94%define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
95%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
96%define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
97%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
98%define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
99%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
100%define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
101%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
102%define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
103%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
104%define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
105%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
106%define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
107%define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
108%define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
109%define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
110%define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
111%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
112%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
113%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
114%define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
115%define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
116%define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
117%define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
118%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
119%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
120%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
121%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
122%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
123%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
124%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
125%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
126%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
127%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
128%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
129%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
130%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
131%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
132%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
133%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
134%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
135%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
136%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
137%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
138%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
139%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
140%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
141%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
142%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
143%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
144%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
145%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
146%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
147%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
148%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
149%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
150%define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
151%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
152%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
153%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
154%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
155%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
156%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
157%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
158%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
159%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
160%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
161%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
162%define X86_CR0_PE RT_BIT(0)
163%define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
164%define X86_CR0_MP RT_BIT(1)
165%define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
166%define X86_CR0_EM RT_BIT(2)
167%define X86_CR0_EMULATE_FPU RT_BIT(2)
168%define X86_CR0_TS RT_BIT(3)
169%define X86_CR0_TASK_SWITCH RT_BIT(3)
170%define X86_CR0_ET RT_BIT(4)
171%define X86_CR0_EXTENSION_TYPE RT_BIT(4)
172%define X86_CR0_NE RT_BIT(5)
173%define X86_CR0_NUMERIC_ERROR RT_BIT(5)
174%define X86_CR0_WP RT_BIT(16)
175%define X86_CR0_WRITE_PROTECT RT_BIT(16)
176%define X86_CR0_AM RT_BIT(18)
177%define X86_CR0_ALIGMENT_MASK RT_BIT(18)
178%define X86_CR0_NW RT_BIT(29)
179%define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
180%define X86_CR0_CD RT_BIT(30)
181%define X86_CR0_CACHE_DISABLE RT_BIT(30)
182%define X86_CR0_PG RT_BIT(31)
183%define X86_CR0_PAGING RT_BIT(31)
184%define X86_CR3_PWT RT_BIT(3)
185%define X86_CR3_PCD RT_BIT(4)
186%define X86_CR3_PAGE_MASK (0xfffff000)
187%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
188%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
189%define X86_CR4_VME RT_BIT(0)
190%define X86_CR4_PVI RT_BIT(1)
191%define X86_CR4_TSD RT_BIT(2)
192%define X86_CR4_DE RT_BIT(3)
193%define X86_CR4_PSE RT_BIT(4)
194%define X86_CR4_PAE RT_BIT(5)
195%define X86_CR4_MCE RT_BIT(6)
196%define X86_CR4_PGE RT_BIT(7)
197%define X86_CR4_PCE RT_BIT(8)
198%define X86_CR4_OSFSXR RT_BIT(9)
199%define X86_CR4_OSXMMEEXCPT RT_BIT(10)
200%define X86_CR4_VMXE RT_BIT(13)
201%define X86_CR4_SMXE RT_BIT(14)
202%define X86_CR4_PCIDE RT_BIT(17)
203%define X86_CR4_OSXSAVE RT_BIT(18)
204%define X86_CR4_SMEP RT_BIT(20)
205%define X86_DR6_B0 RT_BIT(0)
206%define X86_DR6_B1 RT_BIT(1)
207%define X86_DR6_B2 RT_BIT(2)
208%define X86_DR6_B3 RT_BIT(3)
209%define X86_DR6_B_MASK 0x0000000f
210%define X86_DR6_BD RT_BIT(13)
211%define X86_DR6_BS RT_BIT(14)
212%define X86_DR6_BT RT_BIT(15)
213%define X86_DR6_INIT_VAL 0xFFFF0FF0
214%define X86_DR6_RA1_MASK 0xffff0ff0
215%define X86_DR6_RAZ_MASK RT_BIT_64(12)
216%define X86_DR6_MBZ_MASK 0xffffffff00000000
217%define X86_DR6_B(iBp) RT_BIT_64(iBp)
218%define X86_DR7_L0 RT_BIT(0)
219%define X86_DR7_G0 RT_BIT(1)
220%define X86_DR7_L1 RT_BIT(2)
221%define X86_DR7_G1 RT_BIT(3)
222%define X86_DR7_L2 RT_BIT(4)
223%define X86_DR7_G2 RT_BIT(5)
224%define X86_DR7_L3 RT_BIT(6)
225%define X86_DR7_G3 RT_BIT(7)
226%define X86_DR7_LE RT_BIT(8)
227%define X86_DR7_GE RT_BIT(9)
228%define X86_DR7_LE_ALL 0x0000000000000055
229%define X86_DR7_GE_ALL 0x00000000000000aa
230%define X86_DR7_GD RT_BIT(13)
231%define X86_DR7_RW0_MASK (3 << 16)
232%define X86_DR7_LEN0_MASK (3 << 18)
233%define X86_DR7_RW1_MASK (3 << 20)
234%define X86_DR7_LEN1_MASK (3 << 22)
235%define X86_DR7_RW2_MASK (3 << 24)
236%define X86_DR7_LEN2_MASK (3 << 26)
237%define X86_DR7_RW3_MASK (3 << 28)
238%define X86_DR7_LEN3_MASK (3 << 30)
239%define X86_DR7_RA1_MASK (RT_BIT(10))
240%define X86_DR7_RAZ_MASK 0x0000d800
241%define X86_DR7_MBZ_MASK 0xffffffff00000000
242%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
243%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
244%define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
245%define X86_DR7_RW_EO 0
246%define X86_DR7_RW_WO 1
247%define X86_DR7_RW_IO 2
248%define X86_DR7_RW_RW 3
249%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
250%define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
251%define X86_DR7_RW_ALL_MASKS 0x33330000
252%define X86_DR7_ANY_RW_IO(uDR7) \
253 ( ( 0x22220000 & (uDR7) )
254%define X86_DR7_LEN_BYTE 0
255%define X86_DR7_LEN_WORD 1
256%define X86_DR7_LEN_QWORD 2
257%define X86_DR7_LEN_DWORD 3
258%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
259%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
260%define X86_DR7_ENABLED_MASK 0x000000ff
261%define X86_DR7_LEN_ALL_MASKS 0xcccc0000
262%define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000
263%define X86_DR7_INIT_VAL 0x400
264%define MSR_IA32_TSC 0x10
265%define MSR_IA32_PLATFORM_ID 0x17
266%ifndef MSR_IA32_APICBASE
267 %define MSR_IA32_APICBASE 0x1b
268 %define MSR_IA32_APICBASE_EN RT_BIT_64(11)
269 %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
270 %define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
271 %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000
272%endif
273%define MSR_IA32_FEATURE_CONTROL 0x3A
274%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
275%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
276%define MSR_IA32_BIOS_UPDT_TRIG 0x79
277%define MSR_IA32_BIOS_SIGN_ID 0x8B
278%define MSR_IA32_PMC0 0xC1
279%define MSR_IA32_PMC1 0xC2
280%define MSR_IA32_PMC2 0xC3
281%define MSR_IA32_PMC3 0xC4
282%define MSR_IA32_PLATFORM_INFO 0xCE
283%define MSR_IA32_FSB_CLOCK_STS 0xCD
284%define MSR_IA32_MTRR_CAP 0xFE
285%ifndef MSR_IA32_SYSENTER_CS
286%define MSR_IA32_SYSENTER_CS 0x174
287%define MSR_IA32_SYSENTER_ESP 0x175
288%define MSR_IA32_SYSENTER_EIP 0x176
289%endif
290%define MSR_IA32_MCP_CAP 0x179
291%define MSR_IA32_MCP_STATUS 0x17A
292%define MSR_IA32_MCP_CTRL 0x17B
293%define MSR_IA32_DEBUGCTL 0x1D9
294%define MSR_IA32_CR_PAT 0x277
295%define MSR_IA32_PERFEVTSEL0 0x186
296%define MSR_IA32_PERFEVTSEL1 0x187
297%define MSR_IA32_FLEX_RATIO 0x194
298%define MSR_IA32_PERF_STATUS 0x198
299%define MSR_IA32_PERF_CTL 0x199
300%define MSR_IA32_THERM_STATUS 0x19c
301%define MSR_IA32_MISC_ENABLE 0x1A0
302%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
303%define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
304%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
305%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
306%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
307%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
308%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
309%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
310%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
311%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
312%define IA32_MTRR_PHYSBASE0 0x200
313%define IA32_MTRR_PHYSMASK0 0x201
314%define IA32_MTRR_PHYSBASE1 0x202
315%define IA32_MTRR_PHYSMASK1 0x203
316%define IA32_MTRR_PHYSBASE2 0x204
317%define IA32_MTRR_PHYSMASK2 0x205
318%define IA32_MTRR_PHYSBASE3 0x206
319%define IA32_MTRR_PHYSMASK3 0x207
320%define IA32_MTRR_PHYSBASE4 0x208
321%define IA32_MTRR_PHYSMASK4 0x209
322%define IA32_MTRR_PHYSBASE5 0x20a
323%define IA32_MTRR_PHYSMASK5 0x20b
324%define IA32_MTRR_PHYSBASE6 0x20c
325%define IA32_MTRR_PHYSMASK6 0x20d
326%define IA32_MTRR_PHYSBASE7 0x20e
327%define IA32_MTRR_PHYSMASK7 0x20f
328%define IA32_MTRR_PHYSBASE8 0x210
329%define IA32_MTRR_PHYSMASK8 0x211
330%define IA32_MTRR_PHYSBASE9 0x212
331%define IA32_MTRR_PHYSMASK9 0x213
332%define IA32_MTRR_FIX64K_00000 0x250
333%define IA32_MTRR_FIX16K_80000 0x258
334%define IA32_MTRR_FIX16K_A0000 0x259
335%define IA32_MTRR_FIX4K_C0000 0x268
336%define IA32_MTRR_FIX4K_C8000 0x269
337%define IA32_MTRR_FIX4K_D0000 0x26a
338%define IA32_MTRR_FIX4K_D8000 0x26b
339%define IA32_MTRR_FIX4K_E0000 0x26c
340%define IA32_MTRR_FIX4K_E8000 0x26d
341%define IA32_MTRR_FIX4K_F0000 0x26e
342%define IA32_MTRR_FIX4K_F8000 0x26f
343%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
344%define MSR_IA32_MC0_CTL 0x400
345%define MSR_IA32_MC0_STATUS 0x401
346%define MSR_IA32_VMX_BASIC_INFO 0x480
347%define MSR_IA32_VMX_PINBASED_CTLS 0x481
348%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
349%define MSR_IA32_VMX_EXIT_CTLS 0x483
350%define MSR_IA32_VMX_ENTRY_CTLS 0x484
351%define MSR_IA32_VMX_MISC 0x485
352%define MSR_IA32_VMX_CR0_FIXED0 0x486
353%define MSR_IA32_VMX_CR0_FIXED1 0x487
354%define MSR_IA32_VMX_CR4_FIXED0 0x488
355%define MSR_IA32_VMX_CR4_FIXED1 0x489
356%define MSR_IA32_VMX_VMCS_ENUM 0x48A
357%define MSR_IA32_VMX_VMFUNC 0x491
358%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
359%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
360%define MSR_IA32_DS_AREA 0x600
361%define MSR_IA32_X2APIC_START 0x800
362%define MSR_IA32_X2APIC_TPR 0x808
363%define MSR_IA32_X2APIC_END 0xBFF
364%define MSR_K6_EFER 0xc0000080
365%define MSR_K6_EFER_SCE RT_BIT(0)
366%define MSR_K6_EFER_LME RT_BIT(8)
367%define MSR_K6_EFER_LMA RT_BIT(10)
368%define MSR_K6_EFER_NXE RT_BIT(11)
369%define MSR_K6_EFER_SVME RT_BIT(12)
370%define MSR_K6_EFER_LMSLE RT_BIT(13)
371%define MSR_K6_EFER_FFXSR RT_BIT(14)
372%define MSR_K6_STAR 0xc0000081
373%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
374%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
375%define MSR_K6_STAR_SEL_MASK 0xffff
376%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
377%define MSR_K6_WHCR 0xc0000082
378%define MSR_K6_UWCCR 0xc0000085
379%define MSR_K6_PSOR 0xc0000087
380%define MSR_K6_PFIR 0xc0000088
381%define MSR_K7_EVNTSEL0 0xc0010000
382%define MSR_K7_EVNTSEL1 0xc0010001
383%define MSR_K7_EVNTSEL2 0xc0010002
384%define MSR_K7_EVNTSEL3 0xc0010003
385%define MSR_K7_PERFCTR0 0xc0010004
386%define MSR_K7_PERFCTR1 0xc0010005
387%define MSR_K7_PERFCTR2 0xc0010006
388%define MSR_K7_PERFCTR3 0xc0010007
389%define MSR_K8_LSTAR 0xc0000082
390%define MSR_K8_CSTAR 0xc0000083
391%define MSR_K8_SF_MASK 0xc0000084
392%define MSR_K8_FS_BASE 0xc0000100
393%define MSR_K8_GS_BASE 0xc0000101
394%define MSR_K8_KERNEL_GS_BASE 0xc0000102
395%define MSR_K8_TSC_AUX 0xc0000103
396%define MSR_K8_SYSCFG 0xc0010010
397%define MSR_K8_HWCR 0xc0010015
398%define MSR_K8_IORRBASE0 0xc0010016
399%define MSR_K8_IORRMASK0 0xc0010017
400%define MSR_K8_IORRBASE1 0xc0010018
401%define MSR_K8_IORRMASK1 0xc0010019
402%define MSR_K8_TOP_MEM1 0xc001001a
403%define MSR_K8_TOP_MEM2 0xc001001d
404%define MSR_K8_VM_CR 0xc0010114
405%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
406%define MSR_K8_IGNNE 0xc0010115
407%define MSR_K8_SMM_CTL 0xc0010116
408%define MSR_K8_VM_HSAVE_PA 0xc0010117
409%define X86_PG_ENTRIES 1024
410%define X86_PG_PAE_ENTRIES 512
411%define X86_PG_PAE_PDPE_ENTRIES 4
412%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
413%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
414%define X86_PAGE_4K_SIZE _4K
415%define X86_PAGE_4K_SHIFT 12
416%define X86_PAGE_4K_OFFSET_MASK 0xfff
417%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
418%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
419%define X86_PAGE_2M_SIZE _2M
420%define X86_PAGE_2M_SHIFT 21
421%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
422%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
423%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
424%define X86_PAGE_4M_SIZE _4M
425%define X86_PAGE_4M_SHIFT 22
426%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
427%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
428%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
429%define X86_PTE_BIT_P 0
430%define X86_PTE_BIT_RW 1
431%define X86_PTE_BIT_US 2
432%define X86_PTE_BIT_PWT 3
433%define X86_PTE_BIT_PCD 4
434%define X86_PTE_BIT_A 5
435%define X86_PTE_BIT_D 6
436%define X86_PTE_BIT_PAT 7
437%define X86_PTE_BIT_G 8
438%define X86_PTE_P RT_BIT(0)
439%define X86_PTE_RW RT_BIT(1)
440%define X86_PTE_US RT_BIT(2)
441%define X86_PTE_PWT RT_BIT(3)
442%define X86_PTE_PCD RT_BIT(4)
443%define X86_PTE_A RT_BIT(5)
444%define X86_PTE_D RT_BIT(6)
445%define X86_PTE_PAT RT_BIT(7)
446%define X86_PTE_G RT_BIT(8)
447%define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
448%define X86_PTE_PG_MASK ( 0xfffff000 )
449%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
450%define X86_PTE_PAE_NX RT_BIT_64(63)
451%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
452%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
453%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
454%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
455%define X86_PT_SHIFT 12
456%define X86_PT_MASK 0x3ff
457%define X86_PT_PAE_SHIFT 12
458%define X86_PT_PAE_MASK 0x1ff
459%define X86_PDE_P RT_BIT(0)
460%define X86_PDE_RW RT_BIT(1)
461%define X86_PDE_US RT_BIT(2)
462%define X86_PDE_PWT RT_BIT(3)
463%define X86_PDE_PCD RT_BIT(4)
464%define X86_PDE_A RT_BIT(5)
465%define X86_PDE_PS RT_BIT(7)
466%define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
467%define X86_PDE_PG_MASK ( 0xfffff000 )
468%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
469%define X86_PDE_PAE_NX RT_BIT_64(63)
470%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
471%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
472%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
473%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
474%define X86_PDE4M_P RT_BIT(0)
475%define X86_PDE4M_RW RT_BIT(1)
476%define X86_PDE4M_US RT_BIT(2)
477%define X86_PDE4M_PWT RT_BIT(3)
478%define X86_PDE4M_PCD RT_BIT(4)
479%define X86_PDE4M_A RT_BIT(5)
480%define X86_PDE4M_D RT_BIT(6)
481%define X86_PDE4M_PS RT_BIT(7)
482%define X86_PDE4M_G RT_BIT(8)
483%define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
484%define X86_PDE4M_PAT RT_BIT(12)
485%define X86_PDE4M_PAT_SHIFT (12 - 7)
486%define X86_PDE4M_PG_MASK ( 0xffc00000 )
487%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
488%define X86_PDE4M_PG_HIGH_SHIFT 19
489%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
490%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
491%define X86_PDE2M_PAE_NX RT_BIT_64(63)
492%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
493%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
494%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
495%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
496%define X86_PD_SHIFT 22
497%define X86_PD_MASK 0x3ff
498%define X86_PD_PAE_SHIFT 21
499%define X86_PD_PAE_MASK 0x1ff
500%define X86_PDPE_P RT_BIT(0)
501%define X86_PDPE_RW RT_BIT(1)
502%define X86_PDPE_US RT_BIT(2)
503%define X86_PDPE_PWT RT_BIT(3)
504%define X86_PDPE_PCD RT_BIT(4)
505%define X86_PDPE_A RT_BIT(5)
506%define X86_PDPE_LM_PS RT_BIT(7)
507%define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
508%define X86_PDPE_PG_MASK 0x000ffffffffff000
509%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
510%define X86_PDPE_LM_NX RT_BIT_64(63)
511%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
512%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
513%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
514%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
515%define X86_PDPT_SHIFT 30
516%define X86_PDPT_MASK_PAE 0x3
517%define X86_PDPT_MASK_AMD64 0x1ff
518%define X86_PML4E_P RT_BIT(0)
519%define X86_PML4E_RW RT_BIT(1)
520%define X86_PML4E_US RT_BIT(2)
521%define X86_PML4E_PWT RT_BIT(3)
522%define X86_PML4E_PCD RT_BIT(4)
523%define X86_PML4E_A RT_BIT(5)
524%define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
525%define X86_PML4E_PG_MASK 0x000ffffffffff000
526%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
527%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
528%define X86_PML4E_NX RT_BIT_64(63)
529%define X86_PML4_SHIFT 39
530%define X86_PML4_MASK 0x1ff
531%define X86_FSW_IE RT_BIT(0)
532%define X86_FSW_DE RT_BIT(1)
533%define X86_FSW_ZE RT_BIT(2)
534%define X86_FSW_OE RT_BIT(3)
535%define X86_FSW_UE RT_BIT(4)
536%define X86_FSW_PE RT_BIT(5)
537%define X86_FSW_SF RT_BIT(6)
538%define X86_FSW_ES RT_BIT(7)
539%define X86_FSW_XCPT_MASK 0x007f
540%define X86_FSW_XCPT_ES_MASK 0x00ff
541%define X86_FSW_C0 RT_BIT(8)
542%define X86_FSW_C1 RT_BIT(9)
543%define X86_FSW_C2 RT_BIT(10)
544%define X86_FSW_TOP_MASK 0x3800
545%define X86_FSW_TOP_SHIFT 11
546%define X86_FSW_TOP_SMASK 0x0007
547%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
548%define X86_FSW_C3 RT_BIT(14)
549%define X86_FSW_C_MASK 0x4700
550%define X86_FSW_B RT_BIT(15)
551%define X86_FCW_IM RT_BIT(0)
552%define X86_FCW_DM RT_BIT(1)
553%define X86_FCW_ZM RT_BIT(2)
554%define X86_FCW_OM RT_BIT(3)
555%define X86_FCW_UM RT_BIT(4)
556%define X86_FCW_PM RT_BIT(5)
557%define X86_FCW_MASK_ALL 0x007f
558%define X86_FCW_XCPT_MASK 0x003f
559%define X86_FCW_PC_MASK 0x0300
560%define X86_FCW_PC_24 0x0000
561%define X86_FCW_PC_RSVD 0x0100
562%define X86_FCW_PC_53 0x0200
563%define X86_FCW_PC_64 0x0300
564%define X86_FCW_RC_MASK 0x0c00
565%define X86_FCW_RC_NEAREST 0x0000
566%define X86_FCW_RC_DOWN 0x0400
567%define X86_FCW_RC_UP 0x0800
568%define X86_FCW_RC_ZERO 0x0c00
569%define X86_FCW_ZERO_MASK 0xf080
570%define X86_MSXCR_IE RT_BIT(0)
571%define X86_MSXCR_DE RT_BIT(1)
572%define X86_MSXCR_ZE RT_BIT(2)
573%define X86_MSXCR_OE RT_BIT(3)
574%define X86_MSXCR_UE RT_BIT(4)
575%define X86_MSXCR_PE RT_BIT(5)
576%define X86_MSXCR_DAZ RT_BIT(6)
577%define X86_MSXCR_IM RT_BIT(7)
578%define X86_MSXCR_DM RT_BIT(8)
579%define X86_MSXCR_ZM RT_BIT(9)
580%define X86_MSXCR_OM RT_BIT(10)
581%define X86_MSXCR_UM RT_BIT(11)
582%define X86_MSXCR_PM RT_BIT(12)
583%define X86_MSXCR_RC_MASK 0x6000
584%define X86_MSXCR_RC_NEAREST 0x0000
585%define X86_MSXCR_RC_DOWN 0x2000
586%define X86_MSXCR_RC_UP 0x4000
587%define X86_MSXCR_RC_ZERO 0x6000
588%define X86_MSXCR_FZ RT_BIT(15)
589%define X86_MSXCR_MM RT_BIT(16)
590%ifndef VBOX_FOR_DTRACE_LIB
591%endif
592%define X86DESCATTR_TYPE 0x0000000f
593%define X86DESCATTR_DT 0x00000010
594%define X86DESCATTR_DPL 0x00000060
595%define X86DESCATTR_DPL_SHIFT 5
596%define X86DESCATTR_P 0x00000080
597%define X86DESCATTR_LIMIT_HIGH 0x00000f00
598%define X86DESCATTR_AVL 0x00001000
599%define X86DESCATTR_L 0x00002000
600%define X86DESCATTR_D 0x00004000
601%define X86DESCATTR_G 0x00008000
602%define X86DESCATTR_UNUSABLE 0x00010000
603%ifndef VBOX_FOR_DTRACE_LIB
604%endif
605%ifndef VBOX_FOR_DTRACE_LIB
606%define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
607%define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
608%define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
609%define X86DESCGENERIC_BIT_OFF_TYPE (40)
610%define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
611%define X86DESCGENERIC_BIT_OFF_DPL (45)
612%define X86DESCGENERIC_BIT_OFF_PRESENT (47)
613%define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
614%define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
615%define X86DESCGENERIC_BIT_OFF_LONG (53)
616%define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
617%define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
618%define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
619%endif
620%ifndef VBOX_FOR_DTRACE_LIB
621%endif
622%ifndef VBOX_FOR_DTRACE_LIB
623%endif
624%ifndef VBOX_FOR_DTRACE_LIB
625%endif
626%ifndef VBOX_FOR_DTRACE_LIB
627%endif
628%ifndef VBOX_FOR_DTRACE_LIB
629%endif
630%if HC_ARCH_BITS == 64
631%else
632%endif
633%if HC_ARCH_BITS == 64
634%else
635%endif
636%if HC_ARCH_BITS == 64
637%else
638%endif
639%define X86_SEL_TYPE_CODE 8
640%define X86_SEL_TYPE_MEMORY RT_BIT(4)
641%define X86_SEL_TYPE_ACCESSED 1
642%define X86_SEL_TYPE_DOWN 4
643%define X86_SEL_TYPE_CONF 4
644%define X86_SEL_TYPE_WRITE 2
645%define X86_SEL_TYPE_READ 2
646%define X86_SEL_TYPE_READ_BIT 1
647%define X86_SEL_TYPE_RO 0
648%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
649%define X86_SEL_TYPE_RW 2
650%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
651%define X86_SEL_TYPE_RO_DOWN 4
652%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
653%define X86_SEL_TYPE_RW_DOWN 6
654%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
655%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
656%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
657%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
658%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
659%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
660%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
661%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
662%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
663%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
664%define X86_SEL_TYPE_SYS_UNDEFINED 0
665%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
666%define X86_SEL_TYPE_SYS_LDT 2
667%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
668%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
669%define X86_SEL_TYPE_SYS_TASK_GATE 5
670%define X86_SEL_TYPE_SYS_286_INT_GATE 6
671%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
672%define X86_SEL_TYPE_SYS_UNDEFINED2 8
673%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
674%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
675%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
676%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
677%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
678%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
679%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
680%define AMD64_SEL_TYPE_SYS_LDT 2
681%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
682%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
683%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
684%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
685%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
686%define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
687%define X86_DESC_S RT_BIT(12)
688%define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
689%define X86_DESC_P RT_BIT(15)
690%define X86_DESC_AVL RT_BIT(20)
691%define X86_DESC_DB RT_BIT(22)
692%define X86_DESC_G RT_BIT(23)
693%ifndef VBOX_FOR_DTRACE_LIB
694%endif
695%ifndef VBOX_FOR_DTRACE_LIB
696%endif
697%define X86_SEL_SHIFT 3
698%define X86_SEL_MASK 0xfff8
699%define X86_SEL_MASK_OFF_RPL 0xfffc
700%define X86_SEL_LDT 0x0004
701%define X86_SEL_RPL 0x0003
702%define X86_SEL_RPL_LDT 0x0007
703%define X86_XCPT_MAX (X86_XCPT_SX)
704%define X86_TRAP_ERR_EXTERNAL 1
705%define X86_TRAP_ERR_IDT 2
706%define X86_TRAP_ERR_TI 4
707%define X86_TRAP_ERR_SEL_MASK 0xfff8
708%define X86_TRAP_ERR_SEL_SHIFT 3
709%define X86_TRAP_PF_P RT_BIT(0)
710%define X86_TRAP_PF_RW RT_BIT(1)
711%define X86_TRAP_PF_US RT_BIT(2)
712%define X86_TRAP_PF_RSVD RT_BIT(3)
713%define X86_TRAP_PF_ID RT_BIT(4)
714%ifndef VBOX_FOR_DTRACE_LIB
715%else
716%endif
717%ifndef VBOX_FOR_DTRACE_LIB
718%else
719%endif
720%define X86_MODRM_RM_MASK 0x07
721%define X86_MODRM_REG_MASK 0x38
722%define X86_MODRM_REG_SMASK 0x07
723%define X86_MODRM_REG_SHIFT 3
724%define X86_MODRM_MOD_MASK 0xc0
725%define X86_MODRM_MOD_SMASK 0x03
726%define X86_MODRM_MOD_SHIFT 6
727%ifndef VBOX_FOR_DTRACE_LIB
728%endif
729%define X86_SIB_BASE_MASK 0x07
730%define X86_SIB_INDEX_MASK 0x38
731%define X86_SIB_INDEX_SMASK 0x07
732%define X86_SIB_INDEX_SHIFT 3
733%define X86_SIB_SCALE_MASK 0xc0
734%define X86_SIB_SCALE_SMASK 0x03
735%define X86_SIB_SCALE_SHIFT 6
736%ifndef VBOX_FOR_DTRACE_LIB
737%endif
738%define X86_GREG_xAX 0
739%define X86_GREG_xCX 1
740%define X86_GREG_xDX 2
741%define X86_GREG_xBX 3
742%define X86_GREG_xSP 4
743%define X86_GREG_xBP 5
744%define X86_GREG_xSI 6
745%define X86_GREG_xDI 7
746%define X86_GREG_x8 8
747%define X86_GREG_x9 9
748%define X86_GREG_x10 10
749%define X86_GREG_x11 11
750%define X86_GREG_x12 12
751%define X86_GREG_x13 13
752%define X86_GREG_x14 14
753%define X86_GREG_x15 15
754%define X86_SREG_ES 0
755%define X86_SREG_CS 1
756%define X86_SREG_SS 2
757%define X86_SREG_DS 3
758%define X86_SREG_FS 4
759%define X86_SREG_GS 5
760%define X86_SREG_COUNT 6
761%define X86_OP_PRF_CS 0x2e
762%define X86_OP_PRF_SS 0x36
763%define X86_OP_PRF_DS 0x3e
764%define X86_OP_PRF_ES 0x26
765%define X86_OP_PRF_FS 0x64
766%define X86_OP_PRF_GS 0x65
767%define X86_OP_PRF_SIZE_OP 0x66
768%define X86_OP_PRF_SIZE_ADDR 0x67
769%define X86_OP_PRF_LOCK 0xf0
770%define X86_OP_PRF_REPZ 0xf2
771%define X86_OP_PRF_REPNZ 0xf3
772%define X86_OP_REX_B 0x41
773%define X86_OP_REX_X 0x42
774%define X86_OP_REX_R 0x44
775%define X86_OP_REX_W 0x48
776%endif
777%include "iprt/x86extra.mac"
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