DevHda.h@ 89888

Last change on this file since 89888 was 89888, checked in by vboxsync, 4 years ago
DevHda: Moved the HDA_SAVED_STATE_XXX defines to DevHda.h (no idea why it was in the codec header). bugref:9890
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1	/* $Id: DevHda.h 89888 2021-06-24 12:52:47Z vboxsync $ */
2	/** @file
3	* Intel HD Audio Controller Emulation - Structures.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
19	#define VBOX_INCLUDED_SRC_Audio_DevHda_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <iprt/path.h>
25	#include <VBox/vmm/pdmdev.h>
26	#include "AudioMixer.h"
27
28	/*
29	* Compile time feature configuration.
30	*/
31
32	/** @def VBOX_HDA_WITH_ON_REG_ACCESS_DMA
33	* Enables doing DMA work on certain register accesses (LPIB, WALCLK) in
34	* addition to the DMA timer. All but the last frame can be done during
35	* register accesses (as we don't wish to leave the DMA timer w/o work to
36	* do in case that upsets it). */
37	#if defined(DOXYGEN_RUNNING) \|\| 0
38	# define VBOX_HDA_WITH_ON_REG_ACCESS_DMA
39	#endif
40
41	#ifdef DEBUG_andy
42	/** Enables strict mode, which checks for stuff which isn't supposed to happen.
43	* Be prepared for assertions coming in! */
44	//# define HDA_STRICT
45	#endif
46
47	/** @def HDA_AS_PCI_EXPRESS
48	* Enables PCI express hardware. */
49	#if defined(DOXYGEN_RUNNING) \|\| 0
50	# define HDA_AS_PCI_EXPRESS
51	#endif
52
53	/** @def HDA_DEBUG_SILENCE
54	* To debug silence coming from the guest in form of audio gaps.
55	* Very crude implementation for now.
56	* @todo probably borked atm */
57	#if defined(DOXYGEN_RUNNING) \|\| 0
58	# define HDA_DEBUG_SILENCE
59	#endif
60
61
62	/*
63	* Common pointer types.
64	*/
65	/** Pointer to an HDA stream (SDI / SDO). */
66	typedef struct HDASTREAMR3 *PHDASTREAMR3;
67	/** Pointer to a shared HDA device state. */
68	typedef struct HDASTATE *PHDASTATE;
69	/** Pointer to a ring-3 HDA device state. */
70	typedef struct HDASTATER3 *PHDASTATER3;
71	/** Pointer to an HDA mixer sink definition (ring-3). */
72	typedef struct HDAMIXERSINK *PHDAMIXERSINK;
73
74
75	/*
76	* The rest of the headers.
77	*/
78	#include "DevHdaStream.h"
79	#include "DevHdaCodec.h"
80
81
82
83	/** @name Stream counts.
84	*
85	* At the moment we support 4 input + 4 output streams max, which is 8 in total.
86	* Bidirectional streams are currently not supported.
87	*
88	* @note When changing any of those values, be prepared for some saved state
89	* fixups / trouble!
90	* @{
91	*/
92	#define HDA_MAX_SDI 4
93	#define HDA_MAX_SDO 4
94	#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
95	/** @} */
96	AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
97
98
99	/** Number of general registers. */
100	#define HDA_NUM_GENERAL_REGS 34
101	/** Number of total registers in the HDA's register map. */
102	#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
103	/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
104	#define HDA_MAX_TAGS 16
105
106
107	/** Read callback. */
108	typedef VBOXSTRICTRC FNHDAREGREAD(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
109	/** Write callback. */
110	typedef VBOXSTRICTRC FNHDAREGWRITE(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
111
112	/**
113	* HDA register descriptor.
114	*/
115	typedef struct HDAREGDESC
116	{
117	/** Register offset in the register space. */
118	uint32_t offset;
119	/** Size in bytes. Registers of size > 4 are in fact tables. */
120	uint32_t size;
121	/** Readable bits. */
122	uint32_t readable;
123	/** Writable bits. */
124	uint32_t writable;
125	/** Register descriptor (RD) flags of type HDA_RD_F_XXX. These are used to
126	* specify the read/write handling policy of the register. */
127	uint32_t fFlags;
128	/** Read callback. */
129	FNHDAREGREAD *pfnRead;
130	/** Write callback. */
131	FNHDAREGWRITE *pfnWrite;
132	/** Index into the register storage array.
133	* @todo r=bird: Bad structure layout. Move up before pfnRead. */
134	uint32_t mem_idx;
135	/** Abbreviated name. */
136	const char *abbrev;
137	/** Descripton. */
138	const char *desc;
139	} HDAREGDESC;
140
141	extern const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS];
142
143
144	/**
145	* ICH6 datasheet defines limits for FIFOS registers (18.2.39).
146	* Formula: size - 1
147	* Other values not listed are not supported.
148	*/
149
150	/** Offset of the SD0 register map. */
151	#define HDA_REG_DESC_SD0_BASE 0x80
152
153	/** Turn a short global register name into an memory index and a stringized name. */
154	#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
155
156	/** Turns a short stream register name into an memory index and a stringized name. */
157	#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
158
159	/** Same as above for a register not stored in memory. */
160	#define HDA_REG_IDX_NOMEM(abbrev) 0, #abbrev
161
162	/*
163	* NB: Register values stored in memory (au32Regs[]) are indexed through
164	* the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
165	* register descriptors in g_aHdaRegMap[] are indexed through the
166	* HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
167	*
168	* The au32Regs[] layout is kept unchanged for saved state compatibility.
169	*/
170
171	/* Registers */
172	#define HDA_REG_IND_NAME(x) HDA_REG_##x
173	#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
174	#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
175	#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
176
177
178	#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
179	#define HDA_RMX_GCAP 0
180	/**
181	* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
182	*
183	* oss (15:12) - Number of output streams supported.
184	* iss (11:8) - Number of input streams supported.
185	* bss (7:3) - Number of bidirectional streams supported.
186	* bds (2:1) - Number of serial data out (SDO) signals supported.
187	* b64sup (0) - 64 bit addressing supported.
188	*/
189	#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
190	( (((oss) & 0xF) << 12) \
191	\| (((iss) & 0xF) << 8) \
192	\| (((bss) & 0x1F) << 3) \
193	\| (((bds) & 0x3) << 2) \
194	\| ((b64sup) & 1))
195
196	#define HDA_REG_VMIN 1 /* 0x02 */
197	#define HDA_RMX_VMIN 1
198
199	#define HDA_REG_VMAJ 2 /* 0x03 */
200	#define HDA_RMX_VMAJ 2
201
202	#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
203	#define HDA_RMX_OUTPAY 3
204
205	#define HDA_REG_INPAY 4 /* 0x06-0x07 */
206	#define HDA_RMX_INPAY 4
207
208	#define HDA_REG_GCTL 5 /* 0x08-0x0B */
209	#define HDA_RMX_GCTL 5
210	#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
211	#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
212	#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
213
214	#define HDA_REG_WAKEEN 6 /* 0x0C */
215	#define HDA_RMX_WAKEEN 6
216
217	#define HDA_REG_STATESTS 7 /* 0x0E */
218	#define HDA_RMX_STATESTS 7
219	#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
220
221	#define HDA_REG_GSTS 8 /* 0x10-0x11*/
222	#define HDA_RMX_GSTS 8
223	#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
224
225	#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
226	#define HDA_RMX_OUTSTRMPAY 112
227
228	#define HDA_REG_INSTRMPAY 10 /* 0x1a */
229	#define HDA_RMX_INSTRMPAY 113
230
231	#define HDA_REG_INTCTL 11 /* 0x20 */
232	#define HDA_RMX_INTCTL 9
233	#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
234	#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
235	/** Bits 0-29 correspond to streams 0-29. */
236	#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
237
238	#define HDA_REG_INTSTS 12 /* 0x24 */
239	#define HDA_RMX_INTSTS 10
240	#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
241	#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
242
243	#define HDA_REG_WALCLK 13 /* 0x30 */
244	/*NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. /
245
246	/**
247	* Note: The HDA specification defines a SSYNC register at offset 0x38. The
248	* ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
249	* the datasheet.
250	*/
251	#define HDA_REG_SSYNC 14 /* 0x34 */
252	#define HDA_RMX_SSYNC 12
253
254	#define HDA_REG_CORBLBASE 15 /* 0x40 */
255	#define HDA_RMX_CORBLBASE 13
256
257	#define HDA_REG_CORBUBASE 16 /* 0x44 */
258	#define HDA_RMX_CORBUBASE 14
259
260	#define HDA_REG_CORBWP 17 /* 0x48 */
261	#define HDA_RMX_CORBWP 15
262
263	#define HDA_REG_CORBRP 18 /* 0x4A */
264	#define HDA_RMX_CORBRP 16
265	#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
266
267	#define HDA_REG_CORBCTL 19 /* 0x4C */
268	#define HDA_RMX_CORBCTL 17
269	#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
270	#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
271
272	#define HDA_REG_CORBSTS 20 /* 0x4D */
273	#define HDA_RMX_CORBSTS 18
274
275	#define HDA_REG_CORBSIZE 21 /* 0x4E */
276	#define HDA_RMX_CORBSIZE 19
277	#define HDA_CORBSIZE_SZ_CAP 0xF0
278	#define HDA_CORBSIZE_SZ 0x3
279
280	/** Number of CORB buffer entries. */
281	#define HDA_CORB_SIZE 256
282	/** CORB element size (in bytes). */
283	#define HDA_CORB_ELEMENT_SIZE 4
284	/** Number of RIRB buffer entries. */
285	#define HDA_RIRB_SIZE 256
286	/** RIRB element size (in bytes). */
287	#define HDA_RIRB_ELEMENT_SIZE 8
288
289	#define HDA_REG_RIRBLBASE 22 /* 0x50 */
290	#define HDA_RMX_RIRBLBASE 20
291
292	#define HDA_REG_RIRBUBASE 23 /* 0x54 */
293	#define HDA_RMX_RIRBUBASE 21
294
295	#define HDA_REG_RIRBWP 24 /* 0x58 */
296	#define HDA_RMX_RIRBWP 22
297	#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
298
299	#define HDA_REG_RINTCNT 25 /* 0x5A */
300	#define HDA_RMX_RINTCNT 23
301
302	/** Maximum number of Response Interrupts. */
303	#define HDA_MAX_RINTCNT 256
304
305	#define HDA_REG_RIRBCTL 26 /* 0x5C */
306	#define HDA_RMX_RIRBCTL 24
307	#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
308	#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
309	#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
310
311	#define HDA_REG_RIRBSTS 27 /* 0x5D */
312	#define HDA_RMX_RIRBSTS 25
313	#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
314	#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
315
316	#define HDA_REG_RIRBSIZE 28 /* 0x5E */
317	#define HDA_RMX_RIRBSIZE 26
318
319	#define HDA_REG_IC 29 /* 0x60 */
320	#define HDA_RMX_IC 27
321
322	#define HDA_REG_IR 30 /* 0x64 */
323	#define HDA_RMX_IR 28
324
325	#define HDA_REG_IRS 31 /* 0x68 */
326	#define HDA_RMX_IRS 29
327	#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
328	#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
329
330	#define HDA_REG_DPLBASE 32 /* 0x70 */
331	#define HDA_RMX_DPLBASE 30
332
333	#define HDA_REG_DPUBASE 33 /* 0x74 */
334	#define HDA_RMX_DPUBASE 31
335
336	#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
337
338	#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
339	#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
340	/** @note sdnum here _MUST_ be stream reg number [0,7]. */
341	#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
342
343	#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
344
345	/** @todo Condense marcos! */
346
347	#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
348	#define HDA_RMX_SD0CTL 32
349	#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
350	#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
351	#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
352	#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
353	#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
354	#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
355	#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
356
357	#define HDA_SDCTL_NUM_MASK 0xF
358	#define HDA_SDCTL_NUM_SHIFT 20
359	#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
360	#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
361	#define HDA_SDCTL_STRIPE_MASK 0x3
362	#define HDA_SDCTL_STRIPE_SHIFT 16
363	#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
364	#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
365	#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
366	#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
367	#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
368
369	#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
370	#define HDA_RMX_SD0STS 33
371	#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
372	#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
373	#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
374	#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
375	#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
376	#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
377	#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
378
379	#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
380	#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
381	#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
382	#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
383
384	#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
385	#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
386	#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
387	#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
388	#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
389	#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
390	#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
391	#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
392	#define HDA_RMX_SD0LPIB 34
393	#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
394	#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
395	#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
396	#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
397	#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
398	#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
399	#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
400
401	#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
402	#define HDA_RMX_SD0CBL 35
403	#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
404	#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
405	#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
406	#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
407	#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
408	#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
409	#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
410
411	#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
412	#define HDA_RMX_SD0LVI 36
413	#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
414	#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
415	#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
416	#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
417	#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
418	#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
419	#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
420
421	#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
422	#define HDA_RMX_SD0FIFOW 37
423	#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
424	#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
425	#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
426	#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
427	#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
428	#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
429	#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
430
431	/*
432	* ICH6 datasheet defined limits for FIFOW values (18.2.38).
433	*/
434	#define HDA_SDFIFOW_8B 0x2
435	#define HDA_SDFIFOW_16B 0x3
436	#define HDA_SDFIFOW_32B 0x4
437
438	#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
439	#define HDA_RMX_SD0FIFOS 38
440	#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
441	#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
442	#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
443	#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
444	#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
445	#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
446	#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
447
448	#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
449	#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
450
451	#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
452	#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
453	#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
454	#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
455	#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
456	#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
457
458	#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
459	#define HDA_RMX_SD0FMT 39
460	#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
461	#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
462	#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
463	#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
464	#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
465	#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
466	#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
467
468	#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
469	#define HDA_RMX_SD0BDPL 40
470	#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
471	#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
472	#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
473	#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
474	#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
475	#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
476	#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
477
478	#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
479	#define HDA_RMX_SD0BDPU 41
480	#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
481	#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
482	#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
483	#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
484	#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
485	#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
486	#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
487
488	#define HDA_CODEC_CAD_SHIFT 28
489	/** Encodes the (required) LUN into a codec command. */
490	#define HDA_CODEC_CMD(cmd, lun) ((cmd) \| (lun << HDA_CODEC_CAD_SHIFT))
491
492	#define HDA_SDFMT_NON_PCM_SHIFT 15
493	#define HDA_SDFMT_NON_PCM_MASK 0x1
494	#define HDA_SDFMT_BASE_RATE_SHIFT 14
495	#define HDA_SDFMT_BASE_RATE_MASK 0x1
496	#define HDA_SDFMT_MULT_SHIFT 11
497	#define HDA_SDFMT_MULT_MASK 0x7
498	#define HDA_SDFMT_DIV_SHIFT 8
499	#define HDA_SDFMT_DIV_MASK 0x7
500	#define HDA_SDFMT_BITS_SHIFT 4
501	#define HDA_SDFMT_BITS_MASK 0x7
502	#define HDA_SDFMT_CHANNELS_MASK 0xF
503
504	#define HDA_SDFMT_TYPE RT_BIT(15)
505	#define HDA_SDFMT_TYPE_PCM (0)
506	#define HDA_SDFMT_TYPE_NON_PCM (1)
507
508	#define HDA_SDFMT_BASE RT_BIT(14)
509	#define HDA_SDFMT_BASE_48KHZ (0)
510	#define HDA_SDFMT_BASE_44KHZ (1)
511
512	#define HDA_SDFMT_MULT_1X (0)
513	#define HDA_SDFMT_MULT_2X (1)
514	#define HDA_SDFMT_MULT_3X (2)
515	#define HDA_SDFMT_MULT_4X (3)
516
517	#define HDA_SDFMT_DIV_1X (0)
518	#define HDA_SDFMT_DIV_2X (1)
519	#define HDA_SDFMT_DIV_3X (2)
520	#define HDA_SDFMT_DIV_4X (3)
521	#define HDA_SDFMT_DIV_5X (4)
522	#define HDA_SDFMT_DIV_6X (5)
523	#define HDA_SDFMT_DIV_7X (6)
524	#define HDA_SDFMT_DIV_8X (7)
525
526	#define HDA_SDFMT_8_BIT (0)
527	#define HDA_SDFMT_16_BIT (1)
528	#define HDA_SDFMT_20_BIT (2)
529	#define HDA_SDFMT_24_BIT (3)
530	#define HDA_SDFMT_32_BIT (4)
531
532	#define HDA_SDFMT_CHAN_MONO (0)
533	#define HDA_SDFMT_CHAN_STEREO (1)
534
535	/** Emits a SDnFMT register format.
536	* Also being used in the codec's converter format. */
537	#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
538	( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
539	\| (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
540	\| (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
541	\| (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
542	\| (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
543	\| ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
544
545	/** Interrupt on completion (IOC) flag. */
546	#define HDA_BDLE_F_IOC RT_BIT(0)
547
548
549	/**
550	* BDL description structure.
551	* Do not touch this, as this must match to the HDA specs.
552	*/
553	typedef struct HDABDLEDESC
554	{
555	/** Starting address of the actual buffer. Must be 128-bit aligned. */
556	uint64_t u64BufAddr;
557	/** Size of the actual buffer (in bytes). */
558	uint32_t u32BufSize;
559	/** Bit 0: Interrupt on completion; the controller will generate
560	* an interrupt when the last byte of the buffer has been
561	* fetched by the DMA engine.
562	*
563	* Rest is reserved for further use and must be 0. */
564	uint32_t fFlags;
565	} HDABDLEDESC, *PHDABDLEDESC;
566	AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
567
568
569
570	/**
571	* HDA mixer sink definition (ring-3).
572	*
573	* Its purpose is to know which audio mixer sink is bound to which SDn
574	* (SDI/SDO) device stream.
575	*
576	* This is needed in order to handle interleaved streams (that is, multiple
577	* channels in one stream) or non-interleaved streams (each channel has a
578	* dedicated stream).
579	*
580	* This is only known to the actual device emulation level.
581	*/
582	typedef struct HDAMIXERSINK
583	{
584	R3PTRTYPE(PHDASTREAM) pStreamShared;
585	R3PTRTYPE(PHDASTREAMR3) pStreamR3;
586	/** Pointer to the actual audio mixer sink. */
587	R3PTRTYPE(PAUDMIXSINK) pMixSink;
588	} HDAMIXERSINK;
589
590	/**
591	* Mapping a stream tag to an HDA stream (ring-3).
592	*/
593	typedef struct HDATAG
594	{
595	/** Own stream tag. */
596	uint8_t uTag;
597	uint8_t Padding[7];
598	/** Pointer to associated stream. */
599	R3PTRTYPE(PHDASTREAMR3) pStreamR3;
600	} HDATAG;
601	/** Pointer to a HDA stream tag mapping. */
602	typedef HDATAG *PHDATAG;
603
604	/**
605	* Shared ICH Intel HD audio controller state.
606	*/
607	typedef struct HDASTATE
608	{
609	/** Critical section protecting the HDA state. */
610	PDMCRITSECT CritSect;
611	/** Internal stream states (aligned on 64 byte boundrary). */
612	HDASTREAM aStreams[HDA_MAX_STREAMS];
613	/** The HDA's register set. */
614	uint32_t au32Regs[HDA_NUM_REGS];
615	/** CORB buffer base address. */
616	uint64_t u64CORBBase;
617	/** RIRB buffer base address. */
618	uint64_t u64RIRBBase;
619	/** DMA base address.
620	* Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
621	uint64_t u64DPBase;
622	/** Size in bytes of CORB buffer (#au32CorbBuf). */
623	uint32_t cbCorbBuf;
624	/** Size in bytes of RIRB buffer (#au64RirbBuf). */
625	uint32_t cbRirbBuf;
626	/** Response Interrupt Count (RINTCNT). */
627	uint16_t u16RespIntCnt;
628	/** DMA position buffer enable bit. */
629	bool fDMAPosition;
630	/** Current IRQ level. */
631	uint8_t u8IRQL;
632	/** Config: Internal input DMA buffer size override, specified in milliseconds.
633	* Zero means default size according to buffer and stream config.
634	* @sa BufSizeInMs config value. */
635	uint16_t cMsCircBufIn;
636	/** Config: Internal output DMA buffer size override, specified in milliseconds.
637	* Zero means default size according to buffer and stream config.
638	* @sa BufSizeOutMs config value. */
639	uint16_t cMsCircBufOut;
640	/** The start time of the wall clock (WALCLK), measured on the virtual sync clock. */
641	uint64_t tsWalClkStart;
642	/** CORB DMA task handle.
643	* We use this when there is stuff we cannot handle in ring-0. */
644	PDMTASKHANDLE hCorbDmaTask;
645	/** The CORB buffer. */
646	uint32_t au32CorbBuf[HDA_CORB_SIZE];
647	/** Pointer to RIRB buffer. */
648	uint64_t au64RirbBuf[HDA_RIRB_SIZE];
649
650	/** PCI Region \#0: 16KB of MMIO stuff. */
651	IOMMMIOHANDLE hMmio;
652
653	/** Shared R0/R3 HDA codec to use. */
654	HDACODEC Codec;
655
656	#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
657	STAMCOUNTER StatAccessDmaOutput;
658	STAMCOUNTER StatAccessDmaOutputToR3;
659	#endif
660	#ifdef VBOX_WITH_STATISTICS
661	STAMPROFILE StatIn;
662	STAMPROFILE StatOut;
663	STAMCOUNTER StatBytesRead;
664	STAMCOUNTER StatBytesWritten;
665
666	/** @name Register statistics.
667	* The array members run parallel to g_aHdaRegMap.
668	* @{ */
669	STAMCOUNTER aStatRegReads[HDA_NUM_REGS];
670	STAMCOUNTER aStatRegReadsToR3[HDA_NUM_REGS];
671	STAMCOUNTER aStatRegWrites[HDA_NUM_REGS];
672	STAMCOUNTER aStatRegWritesToR3[HDA_NUM_REGS];
673	STAMCOUNTER StatRegMultiReadsRZ;
674	STAMCOUNTER StatRegMultiReadsR3;
675	STAMCOUNTER StatRegMultiWritesRZ;
676	STAMCOUNTER StatRegMultiWritesR3;
677	STAMCOUNTER StatRegSubWriteRZ;
678	STAMCOUNTER StatRegSubWriteR3;
679	STAMCOUNTER StatRegUnknownReads;
680	STAMCOUNTER StatRegUnknownWrites;
681	STAMCOUNTER StatRegWritesBlockedByReset;
682	STAMCOUNTER StatRegWritesBlockedByRun;
683	/** @} */
684	#endif
685
686	#ifdef DEBUG
687	/** Debug stuff.
688	* @todo Make STAM values out some of this? */
689	struct
690	{
691	# if 0 /* unused */
692	/** Timestamp (in ns) of the last timer callback (hdaTimer).
693	* Used to calculate the time actually elapsed between two timer callbacks. */
694	uint64_t tsTimerLastCalledNs;
695	# endif
696	/** IRQ debugging information. */
697	struct
698	{
699	/** Timestamp (in ns) of last processed (asserted / deasserted) IRQ. */
700	uint64_t tsProcessedLastNs;
701	/** Timestamp (in ns) of last asserted IRQ. */
702	uint64_t tsAssertedNs;
703	# if 0 /* unused */
704	/** How many IRQs have been asserted already. */
705	uint64_t cAsserted;
706	/** Accumulated elapsed time (in ns) of all IRQ being asserted. */
707	uint64_t tsAssertedTotalNs;
708	/** Timestamp (in ns) of last deasserted IRQ. */
709	uint64_t tsDeassertedNs;
710	/** How many IRQs have been deasserted already. */
711	uint64_t cDeasserted;
712	/** Accumulated elapsed time (in ns) of all IRQ being deasserted. */
713	uint64_t tsDeassertedTotalNs;
714	# endif
715	} IRQ;
716	} Dbg;
717	#endif
718	/** This is for checking that the build was correctly configured in all contexts.
719	* This is set to HDASTATE_ALIGNMENT_CHECK_MAGIC. */
720	uint64_t uAlignmentCheckMagic;
721	} HDASTATE;
722	AssertCompileMemberAlignment(HDASTATE, aStreams, 64);
723	/** Pointer to a shared HDA device state. */
724	typedef HDASTATE *PHDASTATE;
725
726	/** Value for HDASTATE:uAlignmentCheckMagic. */
727	#define HDASTATE_ALIGNMENT_CHECK_MAGIC UINT64_C(0x1298afb75893e059)
728
729	/**
730	* Ring-0 ICH Intel HD audio controller state.
731	*/
732	typedef struct HDASTATER0
733	{
734	# if 0 /* Codec is not yet kosher enough for ring-0. @bugref{9890c64} */
735	/** Pointer to HDA codec to use. */
736	HDACODECR0 Codec;
737	# else
738	uint32_t u32Dummy;
739	# endif
740	} HDASTATER0;
741	/** Pointer to a ring-0 HDA device state. */
742	typedef HDASTATER0 *PHDASTATER0;
743
744	/**
745	* Ring-3 ICH Intel HD audio controller state.
746	*/
747	typedef struct HDASTATER3
748	{
749	/** Internal stream states. */
750	HDASTREAMR3 aStreams[HDA_MAX_STREAMS];
751	/** Mapping table between stream tags and stream states. */
752	HDATAG aTags[HDA_MAX_TAGS];
753	/** R3 Pointer to the device instance. */
754	PPDMDEVINSR3 pDevIns;
755	/** The base interface for LUN\#0. */
756	PDMIBASE IBase;
757	/** Pointer to HDA codec to use. */
758	R3PTRTYPE(PHDACODECR3) pCodec;
759	/** List of associated LUN drivers (HDADRIVER). */
760	RTLISTANCHORR3 lstDrv;
761	/** The device' software mixer. */
762	R3PTRTYPE(PAUDIOMIXER) pMixer;
763	/** HDA sink for (front) output. */
764	HDAMIXERSINK SinkFront;
765	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
766	/** HDA sink for center / LFE output. */
767	HDAMIXERSINK SinkCenterLFE;
768	/** HDA sink for rear output. */
769	HDAMIXERSINK SinkRear;
770	#endif
771	/** HDA mixer sink for line input. */
772	HDAMIXERSINK SinkLineIn;
773	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
774	/** Audio mixer sink for microphone input. */
775	HDAMIXERSINK SinkMicIn;
776	#endif
777	/** Debug stuff. */
778	struct
779	{
780	/** Whether debugging is enabled or not. */
781	bool fEnabled;
782	/** Path where to dump the debug output to.
783	* Can be NULL, in which the system's temporary directory will be used then. */
784	R3PTRTYPE(char *) pszOutPath;
785	} Dbg;
786	} HDASTATER3;
787
788
789	/** Pointer to the context specific HDA state (HDASTATER3 or HDASTATER0). */
790	typedef CTX_SUFF(PHDASTATE) PHDASTATECC;
791
792
793	/** @def HDA_PROCESS_INTERRUPT
794	* Wrapper around hdaProcessInterrupt that supplies the source function name
795	* string in logging builds. */
796	#if defined(LOG_ENABLED) \|\| defined(DOXYGEN_RUNNING)
797	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis, const char *pszSource);
798	# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis), __FUNCTION__)
799	#else
800	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis);
801	# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis))
802	#endif
803
804	/**
805	* Returns the audio direction of a specified stream descriptor.
806	*
807	* The register layout specifies that input streams (SDI) come first,
808	* followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
809	* is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
810	*
811	* @note SDnFMT register does not provide that information, so we have to judge
812	* for ourselves.
813	*
814	* @return Audio direction.
815	* @param uSD The stream number.
816	*/
817	DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
818	{
819	if (uSD < HDA_MAX_SDI)
820	return PDMAUDIODIR_IN;
821	AssertReturn(uSD < HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
822	return PDMAUDIODIR_OUT;
823	}
824
825	/* Used by hdaR3StreamSetUp: */
826	uint8_t hdaSDFIFOWToBytes(uint16_t u16RegFIFOW);
827
828
829
830	/** @name Saved state versions for the HDA device
831	* @{ */
832	/** The current staved state version.
833	* @note Only for the registration call. Never used for tests. */
834	#define HDA_SAVED_STATE_VERSION HDA_SAVED_STATE_WITHOUT_PERIOD
835
836	/** Removed period and redefined wall clock. */
837	#define HDA_SAVED_STATE_WITHOUT_PERIOD 8
838	/** Added (Controller): Current wall clock value (this independent from WALCLK register value).
839	* Added (Controller): Current IRQ level.
840	* Added (Per stream): Ring buffer. This is optional and can be skipped if (not) needed.
841	* Added (Per stream): Struct g_aSSMStreamStateFields7.
842	* Added (Per stream): Struct g_aSSMStreamPeriodFields7.
843	* Added (Current BDLE per stream): Struct g_aSSMBDLEDescFields7.
844	* Added (Current BDLE per stream): Struct g_aSSMBDLEStateFields7. */
845	#define HDA_SAVED_STATE_VERSION_7 7
846	/** Saves the current BDLE state.
847	* @since 5.0.14 (r104839) */
848	#define HDA_SAVED_STATE_VERSION_6 6
849	/** Introduced dynamic number of streams + stream identifiers for serialization.
850	* Bug: Did not save the BDLE states correctly.
851	* Those will be skipped on load then.
852	* @since 5.0.12 (r104520) */
853	#define HDA_SAVED_STATE_VERSION_5 5
854	/** Since this version the number of MMIO registers can be flexible. */
855	#define HDA_SAVED_STATE_VERSION_4 4
856	#define HDA_SAVED_STATE_VERSION_3 3
857	#define HDA_SAVED_STATE_VERSION_2 2
858	#define HDA_SAVED_STATE_VERSION_1 1
859	/** @} */
860
861	#endif /* !VBOX_INCLUDED_SRC_Audio_DevHda_h */
862

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source: vbox/trunk/src/VBox/Devices/Audio/DevHda.h@ 89888

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