VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 87293

Last change on this file since 87293 was 87293, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Add profiling stat for device table lookups (uncached).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 212.7 KB
Line 
1/* $Id: DevIommuAmd.cpp 87293 2021-01-18 08:36:08Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/alloc.h>
30#include <iprt/string.h>
31
32#include "VBoxDD.h"
33#include "DevIommuAmd.h"
34
35
36/*********************************************************************************************************************************
37* Defined Constants And Macros *
38*********************************************************************************************************************************/
39/** Release log prefix string. */
40#define IOMMU_LOG_PFX "AMD-IOMMU"
41/** The current saved state version. */
42#define IOMMU_SAVED_STATE_VERSION 1
43/** The IOTLB entry magic. */
44#define IOMMU_IOTLBE_MAGIC 0x10acce55
45
46
47/*********************************************************************************************************************************
48* Structures and Typedefs *
49*********************************************************************************************************************************/
50/**
51 * Acquires the IOMMU PDM lock.
52 * This will make a long jump to ring-3 to acquire the lock if necessary.
53 */
54#define IOMMU_LOCK(a_pDevIns) \
55 do { \
56 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
57 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
58 { /* likely */ } \
59 else \
60 return rcLock; \
61 } while (0)
62
63/**
64 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
65 * This will make a long jump to ring-3 to acquire the lock if necessary.
66 */
67#define IOMMU_LOCK_NORET(a_pDevIns) \
68 do { \
69 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
70 AssertRC(rcLock); \
71 } while (0)
72
73/**
74 * Releases the IOMMU PDM lock.
75 */
76#define IOMMU_UNLOCK(a_pDevIns) \
77 do { \
78 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
79 } while (0)
80
81/**
82 * Asserts that the critsect is owned by this thread.
83 */
84#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
85 do { \
86 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
87 } while (0)
88
89/**
90 * Asserts that the critsect is not owned by this thread.
91 */
92#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
93 do { \
94 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
95 } while (0)
96
97/**
98 * IOMMU operations (transaction) types.
99 */
100typedef enum IOMMUOP
101{
102 /** Address translation request. */
103 IOMMUOP_TRANSLATE_REQ = 0,
104 /** Memory read request. */
105 IOMMUOP_MEM_READ,
106 /** Memory write request. */
107 IOMMUOP_MEM_WRITE,
108 /** Interrupt request. */
109 IOMMUOP_INTR_REQ,
110 /** Command. */
111 IOMMUOP_CMD
112} IOMMUOP;
113AssertCompileSize(IOMMUOP, 4);
114
115/**
116 * I/O page walk result.
117 */
118typedef struct
119{
120 /** The translated system physical address. */
121 RTGCPHYS GCPhysSpa;
122 /** The number of offset bits in the system physical address. */
123 uint8_t cShift;
124 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
125 uint8_t fIoPerm;
126 /** Padding. */
127 uint8_t abPadding[2];
128} IOWALKRESULT;
129/** Pointer to an I/O walk result struct. */
130typedef IOWALKRESULT *PIOWALKRESULT;
131/** Pointer to a const I/O walk result struct. */
132typedef IOWALKRESULT *PCIOWALKRESULT;
133
134/**
135 * IOMMU I/O TLB Entry.
136 * Keep this as small and aligned as possible.
137 */
138typedef struct
139{
140 /** The translated system physical address (SPA) of the page. */
141 RTGCPHYS GCPhysSpa;
142 /** The index of the 4K page within a large page. */
143 uint32_t idxSubPage;
144 /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
145 uint8_t fIoPerm;
146 /** The number of offset bits in the translation indicating page size. */
147 uint8_t cShift;
148 /** Alignment padding. */
149 uint8_t afPadding[2];
150} IOTLBE_T;
151AssertCompileSize(IOTLBE_T, 16);
152/** Pointer to an IOMMU I/O TLB entry struct. */
153typedef IOTLBE_T *PIOTLBE_T;
154/** Pointer to a const IOMMU I/O TLB entry struct. */
155typedef IOTLBE_T const *PCIOTLBE_T;
156
157/**
158 * The shared IOMMU device state.
159 */
160typedef struct IOMMU
161{
162 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
163 uint32_t idxIommu;
164 /** Alignment padding. */
165 uint32_t uPadding0;
166
167 /** Whether the command thread is sleeping. */
168 bool volatile fCmdThreadSleeping;
169 /** Alignment padding. */
170 uint8_t afPadding0[3];
171 /** Whether the command thread has been signaled for wake up. */
172 bool volatile fCmdThreadSignaled;
173 /** Alignment padding. */
174 uint8_t afPadding1[3];
175
176 /** The event semaphore the command thread waits on. */
177 SUPSEMEVENT hEvtCmdThread;
178 /** The MMIO handle. */
179 IOMMMIOHANDLE hMmio;
180
181 /** @name PCI: Base capability block registers.
182 * @{ */
183 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
184 /** @} */
185
186 /** @name MMIO: Control and status registers.
187 * @{ */
188 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
189 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
190 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
191 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
192 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
193 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
194 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
195 /** @} */
196
197 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
198 * @{ */
199 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
200 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
201 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
202 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
203 /** @} */
204
205 /** @todo IOMMU: SMI filter. */
206
207 /** @name MMIO: Guest Virtual-APIC Log registers.
208 * @{ */
209 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
210 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
211 /** @} */
212
213 /** @name MMIO: Alternate PPR and Event Log registers.
214 * @{ */
215 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
216 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
217 /** @} */
218
219 /** @name MMIO: Device-specific feature registers.
220 * @{ */
221 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
222 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
223 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
224 /** @} */
225
226 /** @name MMIO: MSI Capability Block registers.
227 * @{ */
228 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
229 /** @} */
230
231 /** @name MMIO: Performance Optimization Control registers.
232 * @{ */
233 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
234 /** @} */
235
236 /** @name MMIO: x2APIC Control registers.
237 * @{ */
238 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
239 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
240 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
241 /** @} */
242
243 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
244 * @{ */
245 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
246 /** @} */
247
248 /** @name MMIO: Reserved register.
249 * @{ */
250 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
251 /** @} */
252
253 /** @name MMIO: Command and Event Log pointer registers.
254 * @{ */
255 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
256 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
257 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
258 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
259 /** @} */
260
261 /** @name MMIO: Command and Event Status register.
262 * @{ */
263 IOMMU_STATUS_T Status; /**< IOMMU status register. */
264 /** @} */
265
266 /** @name MMIO: PPR Log Head and Tail pointer registers.
267 * @{ */
268 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
269 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
270 /** @} */
271
272 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
273 * @{ */
274 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
275 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
276 /** @} */
277
278 /** @name MMIO: PPR Log B Head and Tail pointer registers.
279 * @{ */
280 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
281 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
282 /** @} */
283
284 /** @name MMIO: Event Log B Head and Tail pointer registers.
285 * @{ */
286 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
287 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
288 /** @} */
289
290 /** @name MMIO: PPR Log Overflow protection registers.
291 * @{ */
292 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
293 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
294 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
295 /** @} */
296
297 /** @todo IOMMU: IOMMU Event counter registers. */
298
299#ifdef VBOX_WITH_STATISTICS
300 /** @name IOMMU: Stat counters.
301 * @{ */
302 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
303 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
304 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
305 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
306
307 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
308 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
309
310 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
311 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
312 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
313 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
314
315 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
316 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
317 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
318 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
319
320 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
321 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
322 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
323 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
324 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
325 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
326 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
327 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
328 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
329
330 STAMPROFILEADV StatDteLookup; /**< Profiling of device table entry lookup (uncached). */
331 /** @} */
332#endif
333} IOMMU;
334/** Pointer to the IOMMU device state. */
335typedef struct IOMMU *PIOMMU;
336/** Pointer to the const IOMMU device state. */
337typedef const struct IOMMU *PCIOMMU;
338AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
339AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
340AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
341AssertCompileMemberAlignment(IOMMU, hMmio, 8);
342AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
343AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
344AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
345AssertCompileMemberAlignment(IOMMU, Status, 8);
346
347/**
348 * The ring-3 IOMMU device state.
349 */
350typedef struct IOMMUR3
351{
352 /** Device instance. */
353 PPDMDEVINSR3 pDevInsR3;
354 /** The IOMMU helpers. */
355 PCPDMIOMMUHLPR3 pIommuHlpR3;
356 /** The command thread handle. */
357 R3PTRTYPE(PPDMTHREAD) pCmdThread;
358} IOMMUR3;
359/** Pointer to the ring-3 IOMMU device state. */
360typedef IOMMUR3 *PIOMMUR3;
361
362/**
363 * The ring-0 IOMMU device state.
364 */
365typedef struct IOMMUR0
366{
367 /** Device instance. */
368 PPDMDEVINSR0 pDevInsR0;
369 /** The IOMMU helpers. */
370 PCPDMIOMMUHLPR0 pIommuHlpR0;
371} IOMMUR0;
372/** Pointer to the ring-0 IOMMU device state. */
373typedef IOMMUR0 *PIOMMUR0;
374
375/**
376 * The raw-mode IOMMU device state.
377 */
378typedef struct IOMMURC
379{
380 /** Device instance. */
381 PPDMDEVINSR0 pDevInsRC;
382 /** The IOMMU helpers. */
383 PCPDMIOMMUHLPRC pIommuHlpRC;
384} IOMMURC;
385/** Pointer to the raw-mode IOMMU device state. */
386typedef IOMMURC *PIOMMURC;
387
388/** The IOMMU device state for the current context. */
389typedef CTX_SUFF(IOMMU) IOMMUCC;
390/** Pointer to the IOMMU device state for the current context. */
391typedef CTX_SUFF(PIOMMU) PIOMMUCC;
392
393/**
394 * IOMMU register access.
395 */
396typedef struct IOMMUREGACC
397{
398 const char *pszName;
399 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
400 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
401} IOMMUREGACC;
402/** Pointer to an IOMMU register access. */
403typedef IOMMUREGACC *PIOMMUREGACC;
404/** Pointer to a const IOMMU register access. */
405typedef IOMMUREGACC const *PCIOMMUREGACC;
406
407
408/*********************************************************************************************************************************
409* Global Variables *
410*********************************************************************************************************************************/
411/**
412 * An array of the number of device table segments supported.
413 * Indexed by u2DevTabSegSup.
414 */
415static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
416
417/**
418 * An array of the masks to select the device table segment index from a device ID.
419 */
420static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
421
422/**
423 * An array of the shift values to select the device table segment index from a
424 * device ID.
425 */
426static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
427
428/**
429 * The maximum size (inclusive) of each device table segment (0 to 7).
430 * Indexed by the device table segment index.
431 */
432static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
433
434
435#ifndef VBOX_DEVICE_STRUCT_TESTCASE
436/**
437 * Gets the maximum number of buffer entries for the given buffer length.
438 *
439 * @returns Number of buffer entries.
440 * @param uEncodedLen The length (power-of-2 encoded).
441 */
442DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
443{
444 Assert(uEncodedLen > 7);
445 return 2 << (uEncodedLen - 1);
446}
447
448
449/**
450 * Gets the total length of the buffer given a base register's encoded length.
451 *
452 * @returns The length of the buffer in bytes.
453 * @param uEncodedLen The length (power-of-2 encoded).
454 */
455DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
456{
457 Assert(uEncodedLen > 7);
458 return (2 << (uEncodedLen - 1)) << 4;
459}
460
461
462/**
463 * Gets the number of (unconsumed) entries in the event log.
464 *
465 * @returns The number of entries in the event log.
466 * @param pThis The IOMMU device state.
467 */
468static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
469{
470 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
471 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
472 if (idxTail >= idxHead)
473 return idxTail - idxHead;
474
475 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
476 return cMaxEvts - idxHead + idxTail;
477}
478
479
480#if 0
481/**
482 * Gets the number of (unconsumed) commands in the command buffer.
483 *
484 * @returns The number of commands in the command buffer.
485 * @param pThis The IOMMU device state.
486 */
487static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
488{
489 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
490 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
491 if (idxTail >= idxHead)
492 return idxTail - idxHead;
493
494 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
495 return cMaxCmds - idxHead + idxTail;
496}
497#endif
498
499
500DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
501{
502 IOMMU_STATUS_T Status;
503 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
504 return Status;
505}
506
507
508DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
509{
510 IOMMU_CTRL_T Ctrl;
511 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
512 return Ctrl;
513}
514
515
516/**
517 * Returns whether MSI is enabled for the IOMMU.
518 *
519 * @returns Whether MSI is enabled.
520 * @param pDevIns The IOMMU device instance.
521 *
522 * @note There should be a PCIDevXxx function for this.
523 */
524static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
525{
526 MSI_CAP_HDR_T MsiCapHdr;
527 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
528 return MsiCapHdr.n.u1MsiEnable;
529}
530
531
532/**
533 * Signals a PCI target abort.
534 *
535 * @param pDevIns The IOMMU device instance.
536 */
537static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
538{
539 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
540 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
541 PDMPciDevSetStatus(pPciDev, u16Status);
542}
543
544
545/**
546 * Wakes up the command thread if there are commands to be processed or if
547 * processing is requested to be stopped by software.
548 *
549 * @param pDevIns The IOMMU device instance.
550 */
551static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
552{
553 IOMMU_ASSERT_LOCKED(pDevIns);
554 Log4Func(("\n"));
555
556 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
557 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
558 if (Status.n.u1CmdBufRunning)
559 {
560 Log4Func(("Signaling command thread\n"));
561 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
562 }
563}
564
565
566/**
567 * Reads the Device Table Base Address Register.
568 */
569static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
570{
571 RT_NOREF(pDevIns, offReg);
572 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
573 return VINF_SUCCESS;
574}
575
576
577/**
578 * Reads the Command Buffer Base Address Register.
579 */
580static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
581{
582 RT_NOREF(pDevIns, offReg);
583 *pu64Value = pThis->CmdBufBaseAddr.u64;
584 return VINF_SUCCESS;
585}
586
587
588/**
589 * Reads the Event Log Base Address Register.
590 */
591static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
592{
593 RT_NOREF(pDevIns, offReg);
594 *pu64Value = pThis->EvtLogBaseAddr.u64;
595 return VINF_SUCCESS;
596}
597
598
599/**
600 * Reads the Control Register.
601 */
602static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
603{
604 RT_NOREF(pDevIns, offReg);
605 *pu64Value = pThis->Ctrl.u64;
606 return VINF_SUCCESS;
607}
608
609
610/**
611 * Reads the Exclusion Range Base Address Register.
612 */
613static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
614{
615 RT_NOREF(pDevIns, offReg);
616 *pu64Value = pThis->ExclRangeBaseAddr.u64;
617 return VINF_SUCCESS;
618}
619
620
621/**
622 * Reads to the Exclusion Range Limit Register.
623 */
624static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
625{
626 RT_NOREF(pDevIns, offReg);
627 *pu64Value = pThis->ExclRangeLimit.u64;
628 return VINF_SUCCESS;
629}
630
631
632/**
633 * Reads to the Extended Feature Register.
634 */
635static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
636{
637 RT_NOREF(pDevIns, offReg);
638 *pu64Value = pThis->ExtFeat.u64;
639 return VINF_SUCCESS;
640}
641
642
643/**
644 * Reads to the PPR Log Base Address Register.
645 */
646static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
647{
648 RT_NOREF(pDevIns, offReg);
649 *pu64Value = pThis->PprLogBaseAddr.u64;
650 return VINF_SUCCESS;
651}
652
653
654/**
655 * Writes the Hardware Event Register (Hi).
656 */
657static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
658{
659 RT_NOREF(pDevIns, offReg);
660 *pu64Value = pThis->HwEvtHi.u64;
661 return VINF_SUCCESS;
662}
663
664
665/**
666 * Reads the Hardware Event Register (Lo).
667 */
668static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
669{
670 RT_NOREF(pDevIns, offReg);
671 *pu64Value = pThis->HwEvtLo;
672 return VINF_SUCCESS;
673}
674
675
676/**
677 * Reads the Hardware Event Status Register.
678 */
679static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
680{
681 RT_NOREF(pDevIns, offReg);
682 *pu64Value = pThis->HwEvtStatus.u64;
683 return VINF_SUCCESS;
684}
685
686
687/**
688 * Reads to the GA Log Base Address Register.
689 */
690static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
691{
692 RT_NOREF(pDevIns, offReg);
693 *pu64Value = pThis->GALogBaseAddr.u64;
694 return VINF_SUCCESS;
695}
696
697
698/**
699 * Reads to the PPR Log B Base Address Register.
700 */
701static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
702{
703 RT_NOREF(pDevIns, offReg);
704 *pu64Value = pThis->PprLogBBaseAddr.u64;
705 return VINF_SUCCESS;
706}
707
708
709/**
710 * Reads to the Event Log B Base Address Register.
711 */
712static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
713{
714 RT_NOREF(pDevIns, offReg);
715 *pu64Value = pThis->EvtLogBBaseAddr.u64;
716 return VINF_SUCCESS;
717}
718
719
720/**
721 * Reads the Device Table Segment Base Address Register.
722 */
723static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
724{
725 RT_NOREF(pDevIns);
726
727 /* Figure out which segment is being written. */
728 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
729 uint8_t const idxSegment = offSegment + 1;
730 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
731
732 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
733 return VINF_SUCCESS;
734}
735
736
737/**
738 * Reads the Device Specific Feature Extension (DSFX) Register.
739 */
740static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
741{
742 RT_NOREF(pDevIns, offReg);
743 *pu64Value = pThis->DevSpecificFeat.u64;
744 return VINF_SUCCESS;
745}
746
747/**
748 * Reads the Device Specific Control Extension (DSCX) Register.
749 */
750static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
751{
752 RT_NOREF(pDevIns, offReg);
753 *pu64Value = pThis->DevSpecificCtrl.u64;
754 return VINF_SUCCESS;
755}
756
757
758/**
759 * Reads the Device Specific Status Extension (DSSX) Register.
760 */
761static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
762{
763 RT_NOREF(pDevIns, offReg);
764 *pu64Value = pThis->DevSpecificStatus.u64;
765 return VINF_SUCCESS;
766}
767
768
769/**
770 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
771 */
772static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
773{
774 RT_NOREF(pDevIns, offReg);
775 uint32_t const uLo = pThis->MiscInfo.au32[0];
776 uint32_t const uHi = pThis->MiscInfo.au32[1];
777 *pu64Value = RT_MAKE_U64(uLo, uHi);
778 return VINF_SUCCESS;
779}
780
781
782/**
783 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
784 * Register (32-bit).
785 */
786static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
787{
788 RT_NOREF(pThis, offReg);
789 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
790 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
791 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
792 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
793 *pu64Value = RT_MAKE_U64(uLo, uHi);
794 return VINF_SUCCESS;
795}
796
797
798/**
799 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
800 */
801static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
802{
803 RT_NOREF(pThis, offReg);
804 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
805 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
806 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
807 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
808 *pu64Value = RT_MAKE_U64(uLo, uHi);
809 return VINF_SUCCESS;
810}
811
812
813/**
814 * Reads the Command Buffer Head Pointer Register.
815 */
816static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
817{
818 RT_NOREF(pDevIns, offReg);
819 *pu64Value = pThis->CmdBufHeadPtr.u64;
820 return VINF_SUCCESS;
821}
822
823
824/**
825 * Reads the Command Buffer Tail Pointer Register.
826 */
827static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
828{
829 RT_NOREF(pDevIns, offReg);
830 *pu64Value = pThis->CmdBufTailPtr.u64;
831 return VINF_SUCCESS;
832}
833
834
835/**
836 * Reads the Event Log Head Pointer Register.
837 */
838static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
839{
840 RT_NOREF(pDevIns, offReg);
841 *pu64Value = pThis->EvtLogHeadPtr.u64;
842 return VINF_SUCCESS;
843}
844
845
846/**
847 * Reads the Event Log Tail Pointer Register.
848 */
849static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
850{
851 RT_NOREF(pDevIns, offReg);
852 *pu64Value = pThis->EvtLogTailPtr.u64;
853 return VINF_SUCCESS;
854}
855
856
857/**
858 * Reads the Status Register.
859 */
860static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
861{
862 RT_NOREF(pDevIns, offReg);
863 *pu64Value = pThis->Status.u64;
864 return VINF_SUCCESS;
865}
866
867
868/**
869 * Writes the Device Table Base Address Register.
870 */
871static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
872{
873 RT_NOREF(pDevIns, offReg);
874
875 /* Mask out all unrecognized bits. */
876 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
877
878 /* Update the register. */
879 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
880
881 /* Paranoia. */
882 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
883 return VINF_SUCCESS;
884}
885
886
887/**
888 * Writes the Command Buffer Base Address Register.
889 */
890static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
891{
892 RT_NOREF(pDevIns, offReg);
893
894 /*
895 * While this is not explicitly specified like the event log base address register,
896 * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
897 * Inconsistent specs :/
898 */
899 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
900 if (Status.n.u1CmdBufRunning)
901 {
902 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
903 return VINF_SUCCESS;
904 }
905
906 /* Mask out all unrecognized bits. */
907 CMD_BUF_BAR_T CmdBufBaseAddr;
908 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
909
910 /* Validate the length. */
911 if (CmdBufBaseAddr.n.u4Len >= 8)
912 {
913 /* Update the register. */
914 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
915
916 /*
917 * Writing the command buffer base address, clears the command buffer head and tail pointers.
918 * See AMD spec. 2.4 "Commands".
919 */
920 pThis->CmdBufHeadPtr.u64 = 0;
921 pThis->CmdBufTailPtr.u64 = 0;
922 }
923 else
924 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
925
926 return VINF_SUCCESS;
927}
928
929
930/**
931 * Writes the Event Log Base Address Register.
932 */
933static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
934{
935 RT_NOREF(pDevIns, offReg);
936
937 /*
938 * IOMMU behavior is undefined when software writes this register when event logging is running.
939 * In our emulation, we ignore the write entirely.
940 * See AMD IOMMU spec. "Event Log Base Address Register".
941 */
942 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
943 if (Status.n.u1EvtLogRunning)
944 {
945 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
946 return VINF_SUCCESS;
947 }
948
949 /* Mask out all unrecognized bits. */
950 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
951 EVT_LOG_BAR_T EvtLogBaseAddr;
952 EvtLogBaseAddr.u64 = u64Value;
953
954 /* Validate the length. */
955 if (EvtLogBaseAddr.n.u4Len >= 8)
956 {
957 /* Update the register. */
958 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
959
960 /*
961 * Writing the event log base address, clears the event log head and tail pointers.
962 * See AMD spec. 2.5 "Event Logging".
963 */
964 pThis->EvtLogHeadPtr.u64 = 0;
965 pThis->EvtLogTailPtr.u64 = 0;
966 }
967 else
968 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
969
970 return VINF_SUCCESS;
971}
972
973
974/**
975 * Writes the Control Register.
976 */
977static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
978{
979 RT_NOREF(pDevIns, offReg);
980
981 /* Mask out all unrecognized bits. */
982 u64Value &= IOMMU_CTRL_VALID_MASK;
983 IOMMU_CTRL_T NewCtrl;
984 NewCtrl.u64 = u64Value;
985
986 /* Ensure the device table segments are within limits. */
987 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
988 {
989 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
990
991 /* Update the register. */
992 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
993
994 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
995 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
996
997 /* Enable or disable event logging when the bit transitions. */
998 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
999 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
1000 if ( fOldEvtLogEn != fNewEvtLogEn
1001 || fOldIommuEn != fNewIommuEn)
1002 {
1003 if ( fNewIommuEn
1004 && fNewEvtLogEn)
1005 {
1006 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
1007 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
1008 }
1009 else
1010 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
1011 }
1012
1013 /* Enable or disable command buffer processing when the bit transitions. */
1014 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
1015 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
1016 if ( fOldCmdBufEn != fNewCmdBufEn
1017 || fOldIommuEn != fNewIommuEn)
1018 {
1019 if ( fNewCmdBufEn
1020 && fNewIommuEn)
1021 {
1022 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
1023 LogFunc(("Command buffer enabled\n"));
1024
1025 /* Wake up the command thread to start processing commands. */
1026 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1027 }
1028 else
1029 {
1030 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1031 LogFunc(("Command buffer disabled\n"));
1032 }
1033 }
1034 }
1035 else
1036 {
1037 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
1038 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
1039 }
1040
1041 return VINF_SUCCESS;
1042}
1043
1044
1045/**
1046 * Writes to the Exclusion Range Base Address Register.
1047 */
1048static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1049{
1050 RT_NOREF(pDevIns, offReg);
1051 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
1052 return VINF_SUCCESS;
1053}
1054
1055
1056/**
1057 * Writes to the Exclusion Range Limit Register.
1058 */
1059static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1060{
1061 RT_NOREF(pDevIns, offReg);
1062 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
1063 u64Value |= UINT64_C(0xfff);
1064 pThis->ExclRangeLimit.u64 = u64Value;
1065 return VINF_SUCCESS;
1066}
1067
1068
1069/**
1070 * Writes the Hardware Event Register (Hi).
1071 */
1072static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1073{
1074 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1075 RT_NOREF(pDevIns, offReg);
1076 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
1077 pThis->HwEvtHi.u64 = u64Value;
1078 return VINF_SUCCESS;
1079}
1080
1081
1082/**
1083 * Writes the Hardware Event Register (Lo).
1084 */
1085static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1086{
1087 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1088 RT_NOREF(pDevIns, offReg);
1089 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
1090 pThis->HwEvtLo = u64Value;
1091 return VINF_SUCCESS;
1092}
1093
1094
1095/**
1096 * Writes the Hardware Event Status Register.
1097 */
1098static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1099{
1100 RT_NOREF(pDevIns, offReg);
1101
1102 /* Mask out all unrecognized bits. */
1103 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
1104
1105 /*
1106 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
1107 * If the current status bits or the bits being written are both 0, we've nothing to do.
1108 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
1109 */
1110 uint64_t HwStatus = pThis->HwEvtStatus.u64;
1111 if (!(HwStatus & RT_BIT(0)))
1112 return VINF_SUCCESS;
1113 if (u64Value & HwStatus & RT_BIT_64(0))
1114 HwStatus &= ~RT_BIT_64(0);
1115 if (u64Value & HwStatus & RT_BIT_64(1))
1116 HwStatus &= ~RT_BIT_64(1);
1117
1118 /* Update the register. */
1119 pThis->HwEvtStatus.u64 = HwStatus;
1120 return VINF_SUCCESS;
1121}
1122
1123
1124/**
1125 * Writes the Device Table Segment Base Address Register.
1126 */
1127static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1128{
1129 RT_NOREF(pDevIns);
1130
1131 /* Figure out which segment is being written. */
1132 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1133 uint8_t const idxSegment = offSegment + 1;
1134 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1135
1136 /* Mask out all unrecognized bits. */
1137 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
1138 DEV_TAB_BAR_T DevTabSegBar;
1139 DevTabSegBar.u64 = u64Value;
1140
1141 /* Validate the size. */
1142 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
1143 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
1144 if (uSegSize <= uMaxSegSize)
1145 {
1146 /* Update the register. */
1147 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
1148 }
1149 else
1150 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
1151
1152 return VINF_SUCCESS;
1153}
1154
1155
1156/**
1157 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1158 */
1159static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1160{
1161 RT_NOREF(pDevIns, offReg);
1162
1163 /* MSI Vector Register 0 is read-only. */
1164 /* MSI Vector Register 1. */
1165 uint32_t const uReg = u64Value >> 32;
1166 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
1167 return VINF_SUCCESS;
1168}
1169
1170
1171/**
1172 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
1173 * Register (32-bit).
1174 */
1175static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1176{
1177 RT_NOREF(pThis, offReg);
1178 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1179 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1180
1181 /* MSI capability header. */
1182 {
1183 uint32_t const uReg = u64Value;
1184 MSI_CAP_HDR_T MsiCapHdr;
1185 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1186 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1187 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1188 }
1189
1190 /* MSI Address Lo. */
1191 {
1192 uint32_t const uReg = u64Value >> 32;
1193 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
1194 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
1195 }
1196
1197 return VINF_SUCCESS;
1198}
1199
1200
1201/**
1202 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
1203 */
1204static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1205{
1206 RT_NOREF(pThis, offReg);
1207 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1208 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1209
1210 /* MSI Address Hi. */
1211 {
1212 uint32_t const uReg = u64Value;
1213 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
1214 }
1215
1216 /* MSI Data. */
1217 {
1218 uint32_t const uReg = u64Value >> 32;
1219 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
1220 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
1221 }
1222
1223 return VINF_SUCCESS;
1224}
1225
1226
1227/**
1228 * Writes the Command Buffer Head Pointer Register.
1229 */
1230static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1231{
1232 RT_NOREF(pDevIns, offReg);
1233
1234 /*
1235 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
1236 * In our emulation, we ignore the write entirely.
1237 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1238 */
1239 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1240 if (Status.n.u1CmdBufRunning)
1241 {
1242 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1243 return VINF_SUCCESS;
1244 }
1245
1246 /*
1247 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1248 * In our emulation, we ignore the write entirely.
1249 */
1250 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
1251 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1252 Assert(cbBuf <= _512K);
1253 if (offBuf >= cbBuf)
1254 {
1255 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
1256 return VINF_SUCCESS;
1257 }
1258
1259 /* Update the register. */
1260 pThis->CmdBufHeadPtr.au32[0] = offBuf;
1261
1262 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1263
1264 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
1265 return VINF_SUCCESS;
1266}
1267
1268
1269/**
1270 * Writes the Command Buffer Tail Pointer Register.
1271 */
1272static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1273{
1274 RT_NOREF(pDevIns, offReg);
1275
1276 /*
1277 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1278 * In our emulation, we ignore the write entirely.
1279 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1280 */
1281 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
1282 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1283 Assert(cbBuf <= _512K);
1284 if (offBuf >= cbBuf)
1285 {
1286 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1287 return VINF_SUCCESS;
1288 }
1289
1290 /*
1291 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
1292 * head pointer after adding one or more commands to the buffer.
1293 *
1294 * However, we cannot enforce this strictly because it's legal for software to shrink the
1295 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
1296 * at 0). Software might even make the queue empty by making head and tail equal which is
1297 * allowed. I don't think we can or should try too hard to prevent software shooting itself
1298 * in the foot here. As long as we make sure the offset value is within the circular buffer
1299 * bounds (which we do by masking bits above) it should be sufficient.
1300 */
1301 pThis->CmdBufTailPtr.au32[0] = offBuf;
1302
1303 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1304
1305 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
1306 return VINF_SUCCESS;
1307}
1308
1309
1310/**
1311 * Writes the Event Log Head Pointer Register.
1312 */
1313static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1314{
1315 RT_NOREF(pDevIns, offReg);
1316
1317 /*
1318 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1319 * In our emulation, we ignore the write entirely.
1320 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1321 */
1322 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
1323 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1324 Assert(cbBuf <= _512K);
1325 if (offBuf >= cbBuf)
1326 {
1327 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1328 return VINF_SUCCESS;
1329 }
1330
1331 /* Update the register. */
1332 pThis->EvtLogHeadPtr.au32[0] = offBuf;
1333
1334 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
1335 return VINF_SUCCESS;
1336}
1337
1338
1339/**
1340 * Writes the Event Log Tail Pointer Register.
1341 */
1342static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1343{
1344 RT_NOREF(pDevIns, offReg);
1345 NOREF(pThis);
1346
1347 /*
1348 * IOMMU behavior is undefined when software writes this register when the event log is running.
1349 * In our emulation, we ignore the write entirely.
1350 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1351 */
1352 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1353 if (Status.n.u1EvtLogRunning)
1354 {
1355 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
1356 return VINF_SUCCESS;
1357 }
1358
1359 /*
1360 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1361 * In our emulation, we ignore the write entirely.
1362 */
1363 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
1364 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1365 Assert(cbBuf <= _512K);
1366 if (offBuf >= cbBuf)
1367 {
1368 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1369 return VINF_SUCCESS;
1370 }
1371
1372 /* Update the register. */
1373 pThis->EvtLogTailPtr.au32[0] = offBuf;
1374
1375 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1376 return VINF_SUCCESS;
1377}
1378
1379
1380/**
1381 * Writes the Status Register.
1382 */
1383static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1384{
1385 RT_NOREF(pDevIns, offReg);
1386
1387 /* Mask out all unrecognized bits. */
1388 u64Value &= IOMMU_STATUS_VALID_MASK;
1389
1390 /*
1391 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1392 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1393 */
1394 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1395 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1396 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1397 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1398
1399 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1400
1401 /* Update the register. */
1402 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1403 return VINF_SUCCESS;
1404}
1405
1406
1407/**
1408 * Register access table 0.
1409 * The MMIO offset of each entry must be a multiple of 8!
1410 */
1411static const IOMMUREGACC g_aRegAccess0[] =
1412{
1413 /* MMIO off. Register name Read function Write function */
1414 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
1415 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
1416 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
1417 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
1418 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
1419 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
1420 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
1421 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
1422 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
1423 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
1424 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
1425 { /* 0x58 */ NULL, NULL, NULL },
1426
1427 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
1428 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
1429 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
1430 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
1431 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
1432 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
1433 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
1434 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
1435 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
1436 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
1437 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
1438 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
1439 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
1440 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
1441 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
1442 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
1443
1444 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
1445 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
1446 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
1447 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
1448
1449 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1450 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1451 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1452 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1453 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1454 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1455 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1456
1457 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
1458 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
1459 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
1460
1461 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
1462 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
1463 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
1464 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
1465
1466 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
1467 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
1468 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
1469};
1470AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
1471
1472/**
1473 * Register access table 1.
1474 * The MMIO offset of each entry must be a multiple of 8!
1475 */
1476static const IOMMUREGACC g_aRegAccess1[] =
1477{
1478 /* MMIO offset Register name Read function Write function */
1479 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
1480 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
1481 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
1482 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
1483 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
1484 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
1485 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
1486 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
1487 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
1488 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
1489 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
1490 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
1491};
1492AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
1493
1494/**
1495 * Register access table 2.
1496 * The MMIO offset of each entry must be a multiple of 8!
1497 */
1498static const IOMMUREGACC g_aRegAccess2[] =
1499{
1500 /* MMIO offset Register name Read Function Write function */
1501 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
1502
1503 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
1504 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
1505 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
1506 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
1507
1508 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
1509 { /* 0x2028 */ NULL, NULL, NULL },
1510
1511 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
1512 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
1513
1514 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
1515 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
1516
1517 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
1518 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
1519
1520 { /* 0x2060 */ NULL, NULL, NULL },
1521 { /* 0x2068 */ NULL, NULL, NULL },
1522
1523 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
1524 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
1525
1526 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
1527 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
1528 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
1529};
1530AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
1531
1532
1533/**
1534 * Gets the register access structure given its MMIO offset.
1535 *
1536 * @returns The register access structure, or NULL if the offset is invalid.
1537 * @param off The MMIO offset of the register being accessed.
1538 */
1539static PCIOMMUREGACC iommuAmdGetRegAccessForOffset(uint32_t off)
1540{
1541 /* Figure out which table the register belongs to and validate its index. */
1542 PCIOMMUREGACC pReg;
1543 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
1544 {
1545 uint32_t const idxReg = off >> 3;
1546 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
1547 pReg = &g_aRegAccess0[idxReg];
1548 }
1549 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
1550 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
1551 {
1552 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
1553 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
1554 pReg = &g_aRegAccess1[idxReg];
1555 }
1556 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
1557 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
1558 {
1559 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
1560 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
1561 pReg = &g_aRegAccess2[idxReg];
1562 }
1563 else
1564 return NULL;
1565
1566 return pReg;
1567}
1568
1569
1570/**
1571 * Writes an IOMMU register (32-bit and 64-bit).
1572 *
1573 * @returns Strict VBox status code.
1574 * @param pDevIns The IOMMU device instance.
1575 * @param off MMIO byte offset to the register.
1576 * @param cb The size of the write access.
1577 * @param uValue The value being written.
1578 *
1579 * @thread EMT.
1580 */
1581static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1582{
1583 /*
1584 * Validate the access in case of IOM bug or incorrect assumption.
1585 */
1586 Assert(off < IOMMU_MMIO_REGION_SIZE);
1587 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
1588 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
1589
1590 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1591
1592 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1593 PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
1594 if (pReg)
1595 { /* likely */ }
1596 else
1597 {
1598 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
1599 return VINF_SUCCESS;
1600 }
1601
1602 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
1603 if (pReg->pfnWrite)
1604 { /* likely */ }
1605 else
1606 {
1607 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1608 return VINF_SUCCESS;
1609 }
1610
1611 /*
1612 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
1613 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
1614 * consecutive 32-bit registers.
1615 */
1616 if (cb == 8)
1617 {
1618 if (!(off & 7))
1619 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1620
1621 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1622 return VINF_SUCCESS;
1623 }
1624
1625 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
1626 Assert(cb == 4);
1627 if (!(off & 7))
1628 {
1629 /*
1630 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
1631 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1632 */
1633 uint64_t u64Read;
1634 if (pReg->pfnRead)
1635 {
1636 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
1637 if (RT_FAILURE(rcStrict))
1638 {
1639 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1640 return rcStrict;
1641 }
1642 }
1643 else
1644 u64Read = 0;
1645
1646 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
1647 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1648 }
1649
1650 /*
1651 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
1652 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1653 */
1654 Assert(!(off & 3));
1655 Assert(off & 7);
1656 Assert(off >= 4);
1657 uint64_t u64Read;
1658 if (pReg->pfnRead)
1659 {
1660 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
1661 if (RT_FAILURE(rcStrict))
1662 {
1663 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1664 return rcStrict;
1665 }
1666 }
1667 else
1668 u64Read = 0;
1669
1670 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
1671 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
1672}
1673
1674
1675/**
1676 * Reads an IOMMU register (64-bit) given its MMIO offset.
1677 *
1678 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1679 * boundary include the lower half of the subsequent register.
1680 *
1681 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1682 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1683 * software will only perform 32-bit reads on those 32-bit registers that are
1684 * aligned on 8-byte boundaries.
1685 *
1686 * @returns Strict VBox status code.
1687 * @param pDevIns The IOMMU device instance.
1688 * @param off The MMIO offset of the register in bytes.
1689 * @param puResult Where to store the value being read.
1690 *
1691 * @thread EMT.
1692 */
1693static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1694{
1695 Assert(off < IOMMU_MMIO_REGION_SIZE);
1696 Assert(!(off & 7) || !(off & 3));
1697
1698 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1699 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1700 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
1701
1702 Log4Func(("off=%#x\n", off));
1703
1704 PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
1705 if (pReg)
1706 { /* likely */ }
1707 else
1708 {
1709 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
1710 return VINF_IOM_MMIO_UNUSED_FF;
1711 }
1712
1713 /* If a read handler doesn't exist, it's a reserved or unknown register. */
1714 if (pReg->pfnRead)
1715 { /* likely */ }
1716 else
1717 {
1718 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
1719 return VINF_IOM_MMIO_UNUSED_00;
1720 }
1721
1722 /*
1723 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
1724 * The caller takes care of truncating upper 32 bits for 32-bit reads.
1725 */
1726 if (!(off & 7))
1727 return pReg->pfnRead(pDevIns, pThis, off, puResult);
1728
1729 /*
1730 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
1731 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
1732 */
1733 Assert(!(off & 3));
1734 Assert(off & 7);
1735 Assert(off >= 4);
1736 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
1737 if (RT_SUCCESS(rcStrict))
1738 *puResult >>= 32;
1739 else
1740 {
1741 *puResult = 0;
1742 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1743 }
1744
1745 return rcStrict;
1746}
1747
1748
1749/**
1750 * Raises the MSI interrupt for the IOMMU device.
1751 *
1752 * @param pDevIns The IOMMU device instance.
1753 *
1754 * @thread Any.
1755 * @remarks The IOMMU lock may or may not be held.
1756 */
1757static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
1758{
1759 LogFlowFunc(("\n"));
1760 if (iommuAmdIsMsiEnabled(pDevIns))
1761 {
1762 LogFunc(("Raising MSI\n"));
1763 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
1764 }
1765}
1766
1767#if 0
1768/**
1769 * Clears the MSI interrupt for the IOMMU device.
1770 *
1771 * @param pDevIns The IOMMU device instance.
1772 *
1773 * @thread Any.
1774 * @remarks The IOMMU lock may or may not be held.
1775 */
1776static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
1777{
1778 if (iommuAmdIsMsiEnabled(pDevIns))
1779 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
1780}
1781#endif
1782
1783/**
1784 * Writes an entry to the event log in memory.
1785 *
1786 * @returns VBox status code.
1787 * @param pDevIns The IOMMU device instance.
1788 * @param pEvent The event to log.
1789 *
1790 * @thread Any.
1791 */
1792static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1793{
1794 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1795
1796 IOMMU_ASSERT_LOCKED(pDevIns);
1797
1798 /* Check if event logging is active and the log has not overflowed. */
1799 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1800 if ( Status.n.u1EvtLogRunning
1801 && !Status.n.u1EvtOverflow)
1802 {
1803 uint32_t const cbEvt = sizeof(*pEvent);
1804
1805 /* Get the offset we need to write the event to in memory (circular buffer offset). */
1806 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
1807 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
1808
1809 /* Ensure we have space in the event log. */
1810 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
1811 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
1812 if (cEvts + 1 < cMaxEvts)
1813 {
1814 /* Write the event log entry to memory. */
1815 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
1816 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
1817 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
1818 if (RT_FAILURE(rc))
1819 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
1820
1821 /* Increment the event log tail pointer. */
1822 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1823 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
1824
1825 /* Indicate that an event log entry was written. */
1826 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
1827
1828 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
1829 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1830 if (Ctrl.n.u1EvtIntrEn)
1831 iommuAmdRaiseMsiInterrupt(pDevIns);
1832 }
1833 else
1834 {
1835 /* Indicate that the event log has overflowed. */
1836 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
1837
1838 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
1839 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1840 if (Ctrl.n.u1EvtIntrEn)
1841 iommuAmdRaiseMsiInterrupt(pDevIns);
1842 }
1843 }
1844
1845 return VINF_SUCCESS;
1846}
1847
1848
1849/**
1850 * Sets an event in the hardware error registers.
1851 *
1852 * @param pDevIns The IOMMU device instance.
1853 * @param pEvent The event.
1854 *
1855 * @thread Any.
1856 */
1857static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1858{
1859 IOMMU_ASSERT_LOCKED(pDevIns);
1860
1861 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1862 if (pThis->ExtFeat.n.u1HwErrorSup)
1863 {
1864 if (pThis->HwEvtStatus.n.u1Valid)
1865 pThis->HwEvtStatus.n.u1Overflow = 1;
1866 pThis->HwEvtStatus.n.u1Valid = 1;
1867 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
1868 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
1869 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
1870 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
1871 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
1872 }
1873}
1874
1875
1876/**
1877 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
1878 *
1879 * @param uDevId The device ID.
1880 * @param uDomainId The domain ID.
1881 * @param GCPhysPtEntity The system physical address of the page table
1882 * entity.
1883 * @param enmOp The IOMMU operation being performed.
1884 * @param pEvtPageTabHwErr Where to store the initialized event.
1885 */
1886static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
1887 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1888{
1889 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
1890 pEvtPageTabHwErr->n.u16DevId = uDevId;
1891 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
1892 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
1893 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1894 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1895 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1896 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1897 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
1898 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
1899}
1900
1901
1902/**
1903 * Raises a PAGE_TAB_HARDWARE_ERROR event.
1904 *
1905 * @param pDevIns The IOMMU device instance.
1906 * @param enmOp The IOMMU operation being performed.
1907 * @param pEvtPageTabHwErr The page table hardware error event.
1908 *
1909 * @thread Any.
1910 */
1911static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1912{
1913 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
1914 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
1915
1916 IOMMU_LOCK_NORET(pDevIns);
1917
1918 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1919 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1920 if (enmOp != IOMMUOP_CMD)
1921 iommuAmdSetPciTargetAbort(pDevIns);
1922
1923 IOMMU_UNLOCK(pDevIns);
1924
1925 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
1926 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
1927 pEvtPageTabHwErr->n.u2Type));
1928}
1929
1930
1931#ifdef IN_RING3
1932/**
1933 * Initializes a COMMAND_HARDWARE_ERROR event.
1934 *
1935 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
1936 * @param pEvtCmdHwErr Where to store the initialized event.
1937 */
1938static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1939{
1940 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
1941 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
1942 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
1943 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
1944}
1945
1946
1947/**
1948 * Raises a COMMAND_HARDWARE_ERROR event.
1949 *
1950 * @param pDevIns The IOMMU device instance.
1951 * @param pEvtCmdHwErr The command hardware error event.
1952 *
1953 * @thread Any.
1954 */
1955static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1956{
1957 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
1958 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
1959 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1960
1961 IOMMU_LOCK_NORET(pDevIns);
1962
1963 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1964 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1965 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1966
1967 IOMMU_UNLOCK(pDevIns);
1968
1969 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
1970}
1971#endif /* IN_RING3 */
1972
1973
1974/**
1975 * Initializes a DEV_TAB_HARDWARE_ERROR event.
1976 *
1977 * @param uDevId The device ID.
1978 * @param GCPhysDte The system physical address of the failed device table
1979 * access.
1980 * @param enmOp The IOMMU operation being performed.
1981 * @param pEvtDevTabHwErr Where to store the initialized event.
1982 */
1983static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
1984 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
1985{
1986 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
1987 pEvtDevTabHwErr->n.u16DevId = uDevId;
1988 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1989 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
1990 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1991 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1992 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1993 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
1994 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
1995}
1996
1997
1998/**
1999 * Raises a DEV_TAB_HARDWARE_ERROR event.
2000 *
2001 * @param pDevIns The IOMMU device instance.
2002 * @param enmOp The IOMMU operation being performed.
2003 * @param pEvtDevTabHwErr The device table hardware error event.
2004 *
2005 * @thread Any.
2006 */
2007static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2008{
2009 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
2010 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
2011
2012 IOMMU_LOCK_NORET(pDevIns);
2013
2014 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2015 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2016 if (enmOp != IOMMUOP_CMD)
2017 iommuAmdSetPciTargetAbort(pDevIns);
2018
2019 IOMMU_UNLOCK(pDevIns);
2020
2021 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
2022 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
2023}
2024
2025
2026#ifdef IN_RING3
2027/**
2028 * Initializes an ILLEGAL_COMMAND_ERROR event.
2029 *
2030 * @param GCPhysCmd The system physical address of the failed command
2031 * access.
2032 * @param pEvtIllegalCmd Where to store the initialized event.
2033 */
2034static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2035{
2036 Assert(!(GCPhysCmd & UINT64_C(0xf)));
2037 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
2038 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
2039 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
2040}
2041
2042
2043/**
2044 * Raises an ILLEGAL_COMMAND_ERROR event.
2045 *
2046 * @param pDevIns The IOMMU device instance.
2047 * @param pEvtIllegalCmd The illegal command error event.
2048 */
2049static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2050{
2051 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2052 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
2053 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2054
2055 IOMMU_LOCK_NORET(pDevIns);
2056
2057 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2058 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2059
2060 IOMMU_UNLOCK(pDevIns);
2061
2062 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
2063}
2064#endif /* IN_RING3 */
2065
2066
2067/**
2068 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
2069 *
2070 * @param uDevId The device ID.
2071 * @param uIova The I/O virtual address.
2072 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
2073 * event was caused by an invalid level encoding in the
2074 * DTE.
2075 * @param enmOp The IOMMU operation being performed.
2076 * @param pEvtIllegalDte Where to store the initialized event.
2077 */
2078static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
2079 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
2080{
2081 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
2082 pEvtIllegalDte->n.u16DevId = uDevId;
2083 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2084 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2085 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
2086 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2087 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
2088 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
2089 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
2090 * IOMMU spec here but not for this field for I/O page fault event. */
2091 Assert(!(uIova & UINT64_C(0x3)));
2092}
2093
2094
2095/**
2096 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
2097 *
2098 * @param pDevIns The IOMMU instance data.
2099 * @param enmOp The IOMMU operation being performed.
2100 * @param pEvtIllegalDte The illegal device table entry event.
2101 * @param enmEvtType The illegal device table entry event type.
2102 *
2103 * @thread Any.
2104 */
2105static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
2106 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
2107{
2108 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2109 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
2110
2111 IOMMU_LOCK_NORET(pDevIns);
2112
2113 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2114 if (enmOp != IOMMUOP_CMD)
2115 iommuAmdSetPciTargetAbort(pDevIns);
2116
2117 IOMMU_UNLOCK(pDevIns);
2118
2119 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
2120 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
2121 NOREF(enmEvtType);
2122}
2123
2124
2125/**
2126 * Initializes an IO_PAGE_FAULT event.
2127 *
2128 * @param uDevId The device ID.
2129 * @param uDomainId The domain ID.
2130 * @param uIova The I/O virtual address being accessed.
2131 * @param fPresent Transaction to a page marked as present (including
2132 * DTE.V=1) or interrupt marked as remapped
2133 * (IRTE.RemapEn=1).
2134 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
2135 * the I/O page fault was caused by invalid level
2136 * encoding.
2137 * @param fPermDenied Permission denied for the address being accessed.
2138 * @param enmOp The IOMMU operation being performed.
2139 * @param pEvtIoPageFault Where to store the initialized event.
2140 */
2141static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
2142 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
2143{
2144 Assert(!fPermDenied || fPresent);
2145 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
2146 pEvtIoPageFault->n.u16DevId = uDevId;
2147 //pEvtIoPageFault->n.u4PasidHi = 0;
2148 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
2149 //pEvtIoPageFault->n.u1GuestOrNested = 0;
2150 //pEvtIoPageFault->n.u1NoExecute = 0;
2151 //pEvtIoPageFault->n.u1User = 0;
2152 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2153 pEvtIoPageFault->n.u1Present = fPresent;
2154 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2155 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
2156 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
2157 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2158 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
2159 pEvtIoPageFault->n.u64Addr = uIova;
2160}
2161
2162
2163/**
2164 * Raises an IO_PAGE_FAULT event.
2165 *
2166 * @param pDevIns The IOMMU instance data.
2167 * @param pDte The device table entry. Optional, can be NULL
2168 * depending on @a enmOp.
2169 * @param pIrte The interrupt remapping table entry. Optional, can
2170 * be NULL depending on @a enmOp.
2171 * @param enmOp The IOMMU operation being performed.
2172 * @param pEvtIoPageFault The I/O page fault event.
2173 * @param enmEvtType The I/O page fault event type.
2174 *
2175 * @thread Any.
2176 */
2177static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
2178 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
2179{
2180 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
2181 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
2182
2183 IOMMU_LOCK_NORET(pDevIns);
2184
2185 bool fSuppressEvtLogging = false;
2186 if ( enmOp == IOMMUOP_MEM_READ
2187 || enmOp == IOMMUOP_MEM_WRITE)
2188 {
2189 if ( pDte
2190 && pDte->n.u1Valid)
2191 {
2192 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
2193 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
2194 * suppression. Perhaps will be possible when we complete IOTLB/cache
2195 * handling. */
2196 }
2197 }
2198 else if (enmOp == IOMMUOP_INTR_REQ)
2199 {
2200 if ( pDte
2201 && pDte->n.u1IntrMapValid)
2202 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
2203
2204 if ( !fSuppressEvtLogging
2205 && pIrte)
2206 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
2207 }
2208 /* else: Events are never suppressed for commands. */
2209
2210 switch (enmEvtType)
2211 {
2212 case kIoPageFaultType_PermDenied:
2213 {
2214 /* Cannot be triggered by a command. */
2215 Assert(enmOp != IOMMUOP_CMD);
2216 RT_FALL_THRU();
2217 }
2218 case kIoPageFaultType_DteRsvdPagingMode:
2219 case kIoPageFaultType_PteInvalidPageSize:
2220 case kIoPageFaultType_PteInvalidLvlEncoding:
2221 case kIoPageFaultType_SkippedLevelIovaNotZero:
2222 case kIoPageFaultType_PteRsvdNotZero:
2223 case kIoPageFaultType_PteValidNotSet:
2224 case kIoPageFaultType_DteTranslationDisabled:
2225 case kIoPageFaultType_PasidInvalidRange:
2226 {
2227 /*
2228 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
2229 * create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
2230 */
2231 if (enmOp != IOMMUOP_TRANSLATE_REQ)
2232 {
2233 if (!fSuppressEvtLogging)
2234 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2235 if (enmOp != IOMMUOP_CMD)
2236 iommuAmdSetPciTargetAbort(pDevIns);
2237 }
2238 break;
2239 }
2240
2241 case kIoPageFaultType_UserSupervisor:
2242 {
2243 /* Access is blocked and only creates an event log entry. */
2244 if (!fSuppressEvtLogging)
2245 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2246 break;
2247 }
2248
2249 case kIoPageFaultType_IrteAddrInvalid:
2250 case kIoPageFaultType_IrteRsvdNotZero:
2251 case kIoPageFaultType_IrteRemapEn:
2252 case kIoPageFaultType_IrteRsvdIntType:
2253 case kIoPageFaultType_IntrReqAborted:
2254 case kIoPageFaultType_IntrWithPasid:
2255 {
2256 /* Only trigerred by interrupt requests. */
2257 Assert(enmOp == IOMMUOP_INTR_REQ);
2258 if (!fSuppressEvtLogging)
2259 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2260 iommuAmdSetPciTargetAbort(pDevIns);
2261 break;
2262 }
2263
2264 case kIoPageFaultType_SmiFilterMismatch:
2265 {
2266 /* Not supported and probably will never be, assert. */
2267 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
2268 break;
2269 }
2270
2271 case kIoPageFaultType_DevId_Invalid:
2272 {
2273 /* Cannot be triggered by a command. */
2274 Assert(enmOp != IOMMUOP_CMD);
2275 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
2276 if (!fSuppressEvtLogging)
2277 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2278 if ( enmOp == IOMMUOP_MEM_READ
2279 || enmOp == IOMMUOP_MEM_WRITE)
2280 iommuAmdSetPciTargetAbort(pDevIns);
2281 break;
2282 }
2283 }
2284
2285 IOMMU_UNLOCK(pDevIns);
2286}
2287
2288
2289/**
2290 * Returns whether the I/O virtual address is to be excluded from translation and
2291 * permission checks.
2292 *
2293 * @returns @c true if the DVA is excluded, @c false otherwise.
2294 * @param pThis The IOMMU device state.
2295 * @param pDte The device table entry.
2296 * @param uIova The I/O virtual address.
2297 *
2298 * @remarks Ensure the exclusion range is enabled prior to calling this function.
2299 *
2300 * @thread Any.
2301 */
2302static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
2303{
2304 /* Ensure the exclusion range is enabled. */
2305 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
2306
2307 /* Check if the IOVA falls within the exclusion range. */
2308 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
2309 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
2310 if (uIovaExclLast - uIova >= uIovaExclFirst)
2311 {
2312 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
2313 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
2314 || pDte->n.u1AllowExclusion)
2315 return true;
2316 }
2317 return false;
2318}
2319
2320
2321/**
2322 * Reads a device table entry from guest memory given the device ID.
2323 *
2324 * @returns VBox status code.
2325 * @param pDevIns The IOMMU device instance.
2326 * @param uDevId The device ID.
2327 * @param enmOp The IOMMU operation being performed.
2328 * @param pDte Where to store the device table entry.
2329 *
2330 * @thread Any.
2331 */
2332static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
2333{
2334 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2335 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2336
2337 /* Figure out which device table segment is being accessed. */
2338 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
2339 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
2340
2341 uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
2342 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2343 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
2344
2345 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
2346 uint32_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
2347 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
2348
2349 /* Ensure the DTE falls completely within the device table segment. */
2350 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
2351 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
2352 {
2353 /* Read the device table entry from guest memory. */
2354 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
2355 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
2356 if (RT_SUCCESS(rc))
2357 return rc;
2358
2359 /* Raise a device table hardware error. */
2360 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
2361
2362 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
2363 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
2364 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
2365 return VERR_IOMMU_DTE_READ_FAILED;
2366 }
2367
2368 /* Raise an I/O page fault for out-of-bounds acccess. */
2369 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2370 iommuAmdInitIoPageFaultEvent(uDevId, 0 /* uDomainId */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
2371 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2372 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_DevId_Invalid);
2373 return VERR_IOMMU_DTE_BAD_OFFSET;
2374}
2375
2376
2377/**
2378 * Walks the I/O page table to translate the I/O virtual address to a system
2379 * physical address.
2380 *
2381 * @returns VBox status code.
2382 * @param pDevIns The IOMMU device instance.
2383 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
2384 * @param uDevId The device ID.
2385 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2386 * permissions for the access being made.
2387 * @param pDte The device table entry.
2388 * @param enmOp The IOMMU operation being performed.
2389 * @param pWalkResult Where to store the results of the I/O page walk. This is
2390 * only updated when VINF_SUCCESS is returned.
2391 *
2392 * @thread Any.
2393 */
2394static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2395 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2396{
2397 Assert(pDte->n.u1Valid);
2398 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2399
2400 /* If the translation is not valid, raise an I/O page fault. */
2401 if (pDte->n.u1TranslationValid)
2402 { /* likely */ }
2403 else
2404 {
2405 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2406 * doesn't explicitly say whether an I/O page fault is raised. From other
2407 * places in the spec. it seems early page walk terminations (starting with
2408 * the DTE) return the state computed so far and raises an I/O page fault. So
2409 * returning an invalid translation rather than skipping translation. */
2410 LogFunc(("Translation valid bit not set -> IOPF\n"));
2411 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2412 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2413 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2414 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2415 kIoPageFaultType_DteTranslationDisabled);
2416 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2417 }
2418
2419 /* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2420 uint8_t const uMaxLevel = pDte->n.u3Mode;
2421 if (uMaxLevel != 0)
2422 { /* likely */ }
2423 else
2424 {
2425 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2426 if ((fAccess & fDtePerm) != fAccess)
2427 {
2428 LogFunc(("Access denied for IOVA %#RX64. uDevId=%#x fAccess=%#x fDtePerm=%#x\n", uIova, uDevId, fAccess, fDtePerm));
2429 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2430 }
2431 pWalkResult->GCPhysSpa = uIova;
2432 pWalkResult->cShift = 0;
2433 pWalkResult->fIoPerm = fDtePerm;
2434 return VINF_SUCCESS;
2435 }
2436
2437 /* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2438 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2439 { /* likely */ }
2440 else
2441 {
2442 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2443 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2444 * I'm just going with I/O page fault. */
2445 LogFunc(("Invalid root page table level %#x (uDevId=%#x) -> IOPF\n", uMaxLevel, uDevId));
2446 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2447 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2448 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2449 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2450 kIoPageFaultType_PteInvalidLvlEncoding);
2451 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2452 }
2453
2454 /* Check permissions bits of the root page table. */
2455 uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2456 if ((fAccess & fRootPtePerm) == fAccess)
2457 { /* likely */ }
2458 else
2459 {
2460 LogFunc(("Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF\n", fAccess, fRootPtePerm));
2461 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2462 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2463 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2464 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2465 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2466 }
2467
2468 /** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2469 * function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2470 * accesses from the 2nd page. We can avoid re-checking the DTE root-page
2471 * table entry every time. Not sure if it's worth optimizing that case now
2472 * or if at all. */
2473
2474 /* The virtual address bits indexing table. */
2475 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2476 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2477 UINT64_C(0x00000000001ff000),
2478 UINT64_C(0x000000003fe00000),
2479 UINT64_C(0x0000007fc0000000),
2480 UINT64_C(0x0000ff8000000000),
2481 UINT64_C(0x01ff000000000000),
2482 UINT64_C(0xfe00000000000000),
2483 UINT64_C(0x0000000000000000) };
2484 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2485 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2486
2487 /* Traverse the I/O page table starting with the page directory in the DTE. */
2488 IOPTENTITY_T PtEntity;
2489 PtEntity.u64 = pDte->au64[0];
2490 for (;;)
2491 {
2492 /* Figure out the system physical address of the page table at the current level. */
2493 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2494
2495 /* Read the page table entity at the current level. */
2496 {
2497 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2498 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2499 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2500 uint64_t const offPte = idxPte << 3;
2501 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2502 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2503 if (RT_FAILURE(rc))
2504 {
2505 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2506 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2507 iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2508 iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2509 return VERR_IOMMU_IPE_2;
2510 }
2511 }
2512
2513 /* Check present bit. */
2514 if (PtEntity.n.u1Present)
2515 { /* likely */ }
2516 else
2517 {
2518 LogFunc(("Page table entry not present (uDevId=%#x) -> IOPF\n", uDevId));
2519 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2520 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2521 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2522 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2523 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2524 }
2525
2526 /* Check permission bits. */
2527 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2528 if ((fAccess & fPtePerm) == fAccess)
2529 { /* likely */ }
2530 else
2531 {
2532 LogFunc(("Page table entry access denied (uDevId=%#x fAccess=%#x fPtePerm=%#x) -> IOPF\n", uDevId, fAccess, fPtePerm));
2533 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2534 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2535 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2536 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2537 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2538 }
2539
2540 /* If this is a PTE, we're at the final level and we're done. */
2541 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2542 if (uNextLevel == 0)
2543 {
2544 /* The page size of the translation is the default (4K). */
2545 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2546 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2547 pWalkResult->fIoPerm = fPtePerm;
2548 return VINF_SUCCESS;
2549 }
2550 if (uNextLevel == 7)
2551 {
2552 /* The default page size of the translation is overridden. */
2553 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2554 uint8_t cShift = X86_PAGE_4K_SHIFT;
2555 while (GCPhysPte & RT_BIT_64(cShift++))
2556 ;
2557
2558 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2559 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2560 if ( cShift > s_acIovaLevelShifts[uLevel]
2561 && cShift < s_acIovaLevelShifts[uLevel + 1])
2562 {
2563 pWalkResult->GCPhysSpa = GCPhysPte;
2564 pWalkResult->cShift = cShift;
2565 pWalkResult->fIoPerm = fPtePerm;
2566 return VINF_SUCCESS;
2567 }
2568
2569 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
2570 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2571 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2572 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2573 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2574 kIoPageFaultType_PteInvalidPageSize);
2575 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2576 }
2577
2578 /* Validate the next level encoding of the PDE. */
2579#if IOMMU_MAX_HOST_PT_LEVEL < 6
2580 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2581 { /* likely */ }
2582 else
2583 {
2584 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
2585 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2586 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2587 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2588 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2589 kIoPageFaultType_PteInvalidLvlEncoding);
2590 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2591 }
2592#else
2593 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2594#endif
2595
2596 /* Validate level transition. */
2597 if (uNextLevel < uLevel)
2598 { /* likely */ }
2599 else
2600 {
2601 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
2602 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2603 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2604 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2605 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2606 kIoPageFaultType_PteInvalidLvlEncoding);
2607 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2608 }
2609
2610 /* Ensure IOVA bits of skipped levels are zero. */
2611 Assert(uLevel > 0);
2612 uint64_t uIovaSkipMask = 0;
2613 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2614 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2615 if (!(uIova & uIovaSkipMask))
2616 { /* likely */ }
2617 else
2618 {
2619 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
2620 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2621 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2622 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2623 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2624 kIoPageFaultType_SkippedLevelIovaNotZero);
2625 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2626 }
2627
2628 /* Continue with traversing the page directory at this level. */
2629 }
2630}
2631
2632
2633/**
2634 * Looks up an I/O virtual address from the device table.
2635 *
2636 * @returns VBox status code.
2637 * @param pDevIns The IOMMU instance data.
2638 * @param uDevId The device ID.
2639 * @param uIova The I/O virtual address to lookup.
2640 * @param cbAccess The size of the access.
2641 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2642 * permissions for the access being made.
2643 * @param enmOp The IOMMU operation being performed.
2644 * @param pGCPhysSpa Where to store the translated system physical address. Only
2645 * valid when translation succeeds and VINF_SUCCESS is
2646 * returned!
2647 *
2648 * @thread Any.
2649 */
2650static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2651 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2652{
2653 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2654 STAM_PROFILE_ADV_START(&pThis->StatDteLookup, a);
2655
2656 /* Read the device table entry from memory. */
2657 DTE_T Dte;
2658 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2659 if (RT_SUCCESS(rc))
2660 {
2661 /* If the DTE is not valid, addresses are forwarded without translation */
2662 if (Dte.n.u1Valid)
2663 { /* likely */ }
2664 else
2665 {
2666 /** @todo IOMMU: Add to IOLTB cache. */
2667 *pGCPhysSpa = uIova;
2668 STAM_PROFILE_ADV_STOP(&pThis->StatDteLookup, a);
2669 return VINF_SUCCESS;
2670 }
2671
2672 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2673 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2674 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2675 if (RT_LIKELY( !fRsvd0
2676 && !fRsvd1))
2677 { /* likely */ }
2678 else
2679 {
2680 LogFunc(("Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
2681 EVT_ILLEGAL_DTE_T Event;
2682 iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
2683 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2684 STAM_PROFILE_ADV_STOP(&pThis->StatDteLookup, a);
2685 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2686 }
2687
2688 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
2689 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable /** @todo lock or make atomic read? */
2690 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
2691 { /* likely */ }
2692 else
2693 {
2694 /** @todo IOMMU: Add to IOLTB cache. */
2695 *pGCPhysSpa = uIova;
2696 STAM_PROFILE_ADV_STOP(&pThis->StatDteLookup, a);
2697 return VINF_SUCCESS;
2698 }
2699
2700 /** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
2701 * below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
2702
2703 uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
2704 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
2705 uint64_t cbRemaining = cbAccess;
2706 for (;;)
2707 {
2708 /* Walk the I/O page tables to translate the IOVA and check permission for the access. */
2709 IOWALKRESULT WalkResult;
2710 rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
2711 if (RT_SUCCESS(rc))
2712 {
2713 /** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
2714
2715 /* If translation is disabled for this device (root paging mode is 0), we're done. */
2716 if (WalkResult.cShift == 0)
2717 {
2718 *pGCPhysSpa = uIova;
2719 break;
2720 }
2721
2722 /* Store the translated base address before continuing to check permissions for any more pages. */
2723 Assert(WalkResult.cShift >= X86_PAGE_4K_SHIFT);
2724 if (cbRemaining == cbAccess)
2725 {
2726 uint64_t const offMask = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
2727 uint64_t const offSpa = uIova & offMask;
2728 *pGCPhysSpa = WalkResult.GCPhysSpa | offSpa;
2729 }
2730
2731 /* If the access exceeds the page size, check permissions for the subsequent page. */
2732 uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
2733 if (cbRemaining > cbPhysPage - offIova)
2734 {
2735 cbRemaining -= (cbPhysPage - offIova);
2736 uBaseIova += cbPhysPage; /** @todo r=ramshankar: Should we mask the offset based on page size here? */
2737 offIova = 0;
2738 }
2739 else
2740 break;
2741 }
2742 else
2743 {
2744 LogFunc(("I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
2745 uBaseIova, fAccess, rc));
2746 *pGCPhysSpa = NIL_RTGCPHYS;
2747 STAM_PROFILE_ADV_STOP(&pThis->StatDteLookup, a);
2748 return rc;
2749 }
2750 }
2751
2752 STAM_PROFILE_ADV_STOP(&pThis->StatDteLookup, a);
2753 return rc;
2754 }
2755
2756 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2757 STAM_PROFILE_ADV_STOP(&pThis->StatDteLookup, a);
2758 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2759}
2760
2761
2762/**
2763 * Memory access transaction from a device.
2764 *
2765 * @returns VBox status code.
2766 * @param pDevIns The IOMMU device instance.
2767 * @param uDevId The device ID (bus, device, function).
2768 * @param uIova The I/O virtual address being accessed.
2769 * @param cbAccess The number of bytes being accessed.
2770 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2771 * @param pGCPhysSpa Where to store the translated system physical address.
2772 *
2773 * @thread Any.
2774 */
2775static DECLCALLBACK(int) iommuAmdDeviceMemAccess(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
2776 uint32_t fFlags, PRTGCPHYS pGCPhysSpa)
2777{
2778 /* Validate. */
2779 AssertPtr(pDevIns);
2780 AssertPtr(pGCPhysSpa);
2781 Assert(cbAccess > 0);
2782 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2783
2784 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2785 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2786 if (Ctrl.n.u1IommuEn)
2787 {
2788 IOMMUOP enmOp;
2789 uint8_t fAccess;
2790 if (fFlags & PDMIOMMU_MEM_F_READ)
2791 {
2792 enmOp = IOMMUOP_MEM_READ;
2793 fAccess = IOMMU_IO_PERM_READ;
2794 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2795 }
2796 else
2797 {
2798 Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
2799 enmOp = IOMMUOP_MEM_WRITE;
2800 fAccess = IOMMU_IO_PERM_WRITE;
2801 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2802 }
2803
2804#ifdef VBOX_STRICT
2805 static const char * const s_apszAccess[] = { "none", "read", "write" };
2806 Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
2807 const char *pszAccess = s_apszAccess[fAccess];
2808 LogFlowFunc(("uDevId=%#x uIova=%#RX64 szAccess=%s cbAccess=%zu\n", uDevId, uIova, pszAccess, cbAccess));
2809#endif
2810
2811 /** @todo IOMMU: IOTLB cache lookup. */
2812
2813 /* Lookup the IOVA from the device table. */
2814 int rc = iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbAccess, fAccess, enmOp, pGCPhysSpa);
2815 if (RT_SUCCESS(rc))
2816 { /* likely */ }
2817 else
2818 LogFunc(("DTE lookup failed! uDevId=%#x uIova=%#RX64 fAccess=%u cbAccess=%zu rc=%#Rrc\n", uDevId, uIova, fAccess,
2819 cbAccess, rc));
2820 return rc;
2821 }
2822
2823 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2824 *pGCPhysSpa = uIova;
2825 return VINF_SUCCESS;
2826}
2827
2828
2829/**
2830 * Memory access bulk (one or more 4K pages) request from a device.
2831 *
2832 * @returns VBox status code.
2833 * @param pDevIns The IOMMU device instance.
2834 * @param uDevId The device ID (bus, device, function).
2835 * @param cIovas The number of addresses being accessed.
2836 * @param pauIovas The I/O virtual addresses for each page being accessed.
2837 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2838 * @param paGCPhysSpa Where to store the translated physical addresses.
2839 *
2840 * @thread Any.
2841 */
2842static DECLCALLBACK(int) iommuAmdDeviceMemBulkAccess(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas,
2843 uint64_t const *pauIovas, uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2844{
2845 /* Validate. */
2846 AssertPtr(pDevIns);
2847 Assert(cIovas > 0);
2848 AssertPtr(pauIovas);
2849 AssertPtr(paGCPhysSpa);
2850 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2851
2852 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2853 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2854 if (Ctrl.n.u1IommuEn)
2855 {
2856 IOMMUOP enmOp;
2857 uint8_t fAccess;
2858 if (fFlags & PDMIOMMU_MEM_F_READ)
2859 {
2860 enmOp = IOMMUOP_MEM_READ;
2861 fAccess = IOMMU_IO_PERM_READ;
2862 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
2863 }
2864 else
2865 {
2866 Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
2867 enmOp = IOMMUOP_MEM_WRITE;
2868 fAccess = IOMMU_IO_PERM_WRITE;
2869 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
2870 }
2871
2872#ifdef VBOX_STRICT
2873 static const char * const s_apszAccess[] = { "none", "read", "write" };
2874 Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
2875 const char *pszAccess = s_apszAccess[fAccess];
2876 LogFlowFunc(("uDevId=%#x cIovas=%zu szAccess=%s\n", uDevId, cIovas, pszAccess));
2877#endif
2878
2879 /** @todo IOMMU: IOTLB cache lookup. */
2880
2881 /* Lookup each IOVA from the device table. */
2882 for (size_t i = 0; i < cIovas; i++)
2883 {
2884 int rc = iommuAmdLookupDeviceTable(pDevIns, uDevId, pauIovas[i], X86_PAGE_SIZE, fAccess, enmOp, &paGCPhysSpa[i]);
2885 if (RT_SUCCESS(rc))
2886 { /* likely */ }
2887 else
2888 {
2889 LogFunc(("Failed! uDevId=%#x uIova=%#RX64 fAccess=%u rc=%Rrc\n", uDevId, pauIovas[i], fAccess, rc));
2890 return rc;
2891 }
2892 }
2893 }
2894 else
2895 {
2896 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2897 for (size_t i = 0; i < cIovas; i++)
2898 paGCPhysSpa[i] = pauIovas[i];
2899 }
2900
2901 return VINF_SUCCESS;
2902}
2903
2904
2905
2906/**
2907 * Reads an interrupt remapping table entry from guest memory given its DTE.
2908 *
2909 * @returns VBox status code.
2910 * @param pDevIns The IOMMU device instance.
2911 * @param uDevId The device ID.
2912 * @param pDte The device table entry.
2913 * @param GCPhysIn The source MSI address (used for reporting errors).
2914 * @param uDataIn The source MSI data.
2915 * @param enmOp The IOMMU operation being performed.
2916 * @param pIrte Where to store the interrupt remapping table entry.
2917 *
2918 * @thread Any.
2919 */
2920static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
2921 IOMMUOP enmOp, PIRTE_T pIrte)
2922{
2923 /* Ensure the IRTE length is valid. */
2924 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
2925
2926 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
2927 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
2928 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) * sizeof(IRTE_T);
2929 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
2930
2931 /* Ensure the IRTE falls completely within the interrupt table. */
2932 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
2933 { /* likely */ }
2934 else
2935 {
2936 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
2937 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
2938
2939 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2940 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
2941 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2942 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteAddrInvalid);
2943 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2944 }
2945
2946 /* Read the IRTE from memory. */
2947 Assert(!(GCPhysIrte & 3));
2948 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
2949 if (RT_SUCCESS(rc))
2950 return VINF_SUCCESS;
2951
2952 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
2953 * situation. Is it an I/O page fault or a device table hardware error?
2954 * There's no interrupt table hardware error event, but it's unclear what
2955 * we should do here. */
2956 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
2957 return VERR_IOMMU_IPE_4;
2958}
2959
2960
2961/**
2962 * Remaps the interrupt using the interrupt remapping table.
2963 *
2964 * @returns VBox status code.
2965 * @param pDevIns The IOMMU instance data.
2966 * @param uDevId The device ID.
2967 * @param pDte The device table entry.
2968 * @param enmOp The IOMMU operation being performed.
2969 * @param pMsiIn The source MSI.
2970 * @param pMsiOut Where to store the remapped MSI.
2971 *
2972 * @thread Any.
2973 */
2974static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
2975 PMSIMSG pMsiOut)
2976{
2977 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
2978
2979 IRTE_T Irte;
2980 int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
2981 if (RT_SUCCESS(rc))
2982 {
2983 if (Irte.n.u1RemapEnable)
2984 {
2985 if (!Irte.n.u1GuestMode)
2986 {
2987 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
2988 {
2989 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
2990 *pMsiOut = *pMsiIn;
2991
2992 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
2993 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
2994
2995 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
2996 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
2997
2998 return VINF_SUCCESS;
2999 }
3000
3001 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
3002 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3003 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3004 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3005 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
3006 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3007 }
3008
3009 LogFunc(("Guest mode not supported -> IOPF\n"));
3010 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3011 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3012 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3013 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
3014 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3015 }
3016
3017 LogFunc(("Remapping disabled -> IOPF\n"));
3018 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3019 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3020 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3021 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
3022 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3023 }
3024
3025 return rc;
3026}
3027
3028
3029/**
3030 * Looks up an MSI interrupt from the interrupt remapping table.
3031 *
3032 * @returns VBox status code.
3033 * @param pDevIns The IOMMU instance data.
3034 * @param uDevId The device ID.
3035 * @param enmOp The IOMMU operation being performed.
3036 * @param pMsiIn The source MSI.
3037 * @param pMsiOut Where to store the remapped MSI.
3038 *
3039 * @thread Any.
3040 */
3041static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3042{
3043 /* Read the device table entry from memory. */
3044 LogFlowFunc(("uDevId=%#x (%#x:%#x:%#x) enmOp=%u\n", uDevId,
3045 ((uDevId >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
3046 ((uDevId >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (uDevId & VBOX_PCI_DEVFN_FUN_MASK), enmOp));
3047
3048 DTE_T Dte;
3049 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
3050 if (RT_SUCCESS(rc))
3051 {
3052 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
3053 if (Dte.n.u1IntrMapValid)
3054 {
3055 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
3056 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
3057 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
3058 if (RT_LIKELY( !fRsvd0
3059 && !fRsvd1))
3060 { /* likely */ }
3061 else
3062 {
3063 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
3064 fRsvd1));
3065 EVT_ILLEGAL_DTE_T Event;
3066 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3067 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3068 return VERR_IOMMU_INTR_REMAP_FAILED;
3069 }
3070
3071 /*
3072 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
3073 * that's connected through HyperTransport it might be possible; but for us, it
3074 * doesn't seem we need to specially handle these pins.
3075 */
3076
3077 /*
3078 * Validate the MSI source address.
3079 *
3080 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
3081 * CPU is concerned, the MSI region is fixed and we must ensure no other device
3082 * claims the region as I/O space.
3083 *
3084 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
3085 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
3086 * See Intel spec. 10.11.1 "Message Address Register Format".
3087 */
3088 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
3089 {
3090 /*
3091 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
3092 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
3093 */
3094 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
3095 bool fPassThru = false;
3096 switch (u8DeliveryMode)
3097 {
3098 case VBOX_MSI_DELIVERY_MODE_FIXED:
3099 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
3100 {
3101 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
3102 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
3103 {
3104 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
3105 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
3106 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
3107 {
3108 /*
3109 * We don't support guest interrupt remapping yet. When we do, we'll need to
3110 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
3111 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
3112 * already reads the control register, add that as a parameter when we eventually
3113 * support guest interrupt remapping. For now, just assert.
3114 */
3115 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3116 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
3117 NOREF(pThis);
3118
3119 return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
3120 }
3121
3122 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
3123 EVT_ILLEGAL_DTE_T Event;
3124 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
3125 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
3126 return VERR_IOMMU_INTR_REMAP_FAILED;
3127 }
3128
3129 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
3130 {
3131 fPassThru = true;
3132 break;
3133 }
3134
3135 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
3136 {
3137 LogFunc(("IntCtl=0: Remapping disallowed for fixed/arbitrated interrupt (%#x) -> Target abort\n",
3138 pMsiIn->Data.n.u8Vector));
3139 iommuAmdSetPciTargetAbort(pDevIns);
3140 return VERR_IOMMU_INTR_REMAP_DENIED;
3141 }
3142
3143 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
3144 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
3145 EVT_ILLEGAL_DTE_T Event;
3146 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3147 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
3148 return VERR_IOMMU_INTR_REMAP_FAILED;
3149 }
3150
3151 /* SMIs are passed through unmapped. We don't implement SMI filters. */
3152 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
3153 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
3154 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
3155 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
3156 default:
3157 {
3158 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
3159 iommuAmdSetPciTargetAbort(pDevIns);
3160 return VERR_IOMMU_INTR_REMAP_FAILED;
3161 }
3162 }
3163
3164 /*
3165 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
3166 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
3167 */
3168 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
3169 || !pMsiIn->Addr.n.u1DestMode)
3170 {
3171 if (fPassThru)
3172 {
3173 *pMsiOut = *pMsiIn;
3174 return VINF_SUCCESS;
3175 }
3176 LogFunc(("Remapping/passthru disallowed for interrupt %#x -> Target abort\n", pMsiIn->Data.n.u8Vector));
3177 }
3178 else
3179 LogFunc(("Logical destination mode invalid for delivery mode %#x\n -> Target abort\n", u8DeliveryMode));
3180
3181 iommuAmdSetPciTargetAbort(pDevIns);
3182 return VERR_IOMMU_INTR_REMAP_DENIED;
3183 }
3184 else
3185 {
3186 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
3187 return VERR_IOMMU_INTR_REMAP_FAILED;
3188 }
3189 }
3190 else
3191 {
3192 /** @todo IOMMU: Add to interrupt remapping cache. */
3193 LogFlowFunc(("DTE interrupt map not valid\n"));
3194 *pMsiOut = *pMsiIn;
3195 return VINF_SUCCESS;
3196 }
3197 }
3198
3199 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3200 return VERR_IOMMU_INTR_REMAP_FAILED;
3201}
3202
3203
3204/**
3205 * Interrupt remap request from a device.
3206 *
3207 * @returns VBox status code.
3208 * @param pDevIns The IOMMU device instance.
3209 * @param uDevId The device ID (bus, device, function).
3210 * @param pMsiIn The source MSI.
3211 * @param pMsiOut Where to store the remapped MSI.
3212 */
3213static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3214{
3215 /* Validate. */
3216 Assert(pDevIns);
3217 Assert(pMsiIn);
3218 Assert(pMsiOut);
3219
3220 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3221
3222 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
3223 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3224 if (Ctrl.n.u1IommuEn)
3225 {
3226 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
3227 /** @todo Cache? */
3228
3229 return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
3230 }
3231
3232 *pMsiOut = *pMsiIn;
3233 return VINF_SUCCESS;
3234}
3235
3236
3237/**
3238 * @callback_method_impl{FNIOMMMIONEWWRITE}
3239 */
3240static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
3241{
3242 NOREF(pvUser);
3243 Assert(cb == 4 || cb == 8);
3244 Assert(!(off & (cb - 1)));
3245
3246 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3247 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
3248
3249 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
3250 return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
3251}
3252
3253
3254/**
3255 * @callback_method_impl{FNIOMMMIONEWREAD}
3256 */
3257static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
3258{
3259 NOREF(pvUser);
3260 Assert(cb == 4 || cb == 8);
3261 Assert(!(off & (cb - 1)));
3262
3263 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3264 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
3265
3266 uint64_t uResult;
3267 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
3268 if (cb == 8)
3269 *(uint64_t *)pv = uResult;
3270 else
3271 *(uint32_t *)pv = (uint32_t)uResult;
3272
3273 return rcStrict;
3274}
3275
3276
3277#ifdef IN_RING3
3278/**
3279 * Processes an IOMMU command.
3280 *
3281 * @returns VBox status code.
3282 * @param pDevIns The IOMMU device instance.
3283 * @param pCmd The command to process.
3284 * @param GCPhysCmd The system physical address of the command.
3285 * @param pEvtError Where to store the error event in case of failures.
3286 *
3287 * @thread Command thread.
3288 */
3289static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
3290{
3291 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
3292
3293 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3294 STAM_COUNTER_INC(&pThis->StatCmd);
3295
3296 uint8_t const bCmd = pCmd->n.u4Opcode;
3297 switch (bCmd)
3298 {
3299 case IOMMU_CMD_COMPLETION_WAIT:
3300 {
3301 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
3302
3303 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
3304 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
3305
3306 /* Validate reserved bits in the command. */
3307 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
3308 {
3309 /* If Completion Store is requested, write the StoreData to the specified address. */
3310 if (pCmdComWait->n.u1Store)
3311 {
3312 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
3313 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
3314 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
3315 if (RT_FAILURE(rc))
3316 {
3317 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
3318 GCPhysStore, rc));
3319 iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
3320 return VERR_IOMMU_CMD_HW_ERROR;
3321 }
3322 }
3323
3324 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
3325 if (pCmdComWait->n.u1Interrupt)
3326 {
3327 IOMMU_LOCK(pDevIns);
3328 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
3329 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3330 bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
3331 IOMMU_UNLOCK(pDevIns);
3332
3333 if (fRaiseInt)
3334 iommuAmdRaiseMsiInterrupt(pDevIns);
3335 }
3336 return VINF_SUCCESS;
3337 }
3338 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3339 return VERR_IOMMU_CMD_INVALID_FORMAT;
3340 }
3341
3342 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
3343 {
3344 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3345 * then. */
3346 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
3347 return VINF_SUCCESS;
3348 }
3349
3350 case IOMMU_CMD_INV_IOMMU_PAGES:
3351 {
3352 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3353 * then. */
3354 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
3355 return VINF_SUCCESS;
3356 }
3357
3358 case IOMMU_CMD_INV_IOTLB_PAGES:
3359 {
3360 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
3361
3362 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
3363 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
3364 {
3365 /** @todo IOMMU: Implement remote IOTLB invalidation. */
3366 return VERR_NOT_IMPLEMENTED;
3367 }
3368 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3369 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3370 }
3371
3372 case IOMMU_CMD_INV_INTR_TABLE:
3373 {
3374 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3375 * then. */
3376 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
3377 return VINF_SUCCESS;
3378 }
3379
3380 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
3381 {
3382 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
3383 if (pThis->ExtFeat.n.u1PrefetchSup)
3384 {
3385 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
3386 return VINF_SUCCESS;
3387 }
3388 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3389 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3390 }
3391
3392 case IOMMU_CMD_COMPLETE_PPR_REQ:
3393 {
3394 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
3395
3396 /* We don't support PPR requests yet. */
3397 Assert(!pThis->ExtFeat.n.u1PprSup);
3398 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3399 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3400 }
3401
3402 case IOMMU_CMD_INV_IOMMU_ALL:
3403 {
3404 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
3405
3406 if (pThis->ExtFeat.n.u1InvAllSup)
3407 {
3408 /** @todo IOMMU: Invalidate all. Pretend success until then. */
3409 return VINF_SUCCESS;
3410 }
3411 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3412 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3413 }
3414 }
3415
3416 STAM_COUNTER_DEC(&pThis->StatCmd);
3417 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
3418 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3419 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3420}
3421
3422
3423/**
3424 * The IOMMU command thread.
3425 *
3426 * @returns VBox status code.
3427 * @param pDevIns The IOMMU device instance.
3428 * @param pThread The command thread.
3429 */
3430static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3431{
3432 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3433
3434 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3435 return VINF_SUCCESS;
3436
3437 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3438 {
3439 /*
3440 * Sleep perpetually until we are woken up to process commands.
3441 */
3442 {
3443 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
3444 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
3445 if (!fSignaled)
3446 {
3447 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
3448 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
3449 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3450 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3451 break;
3452 Log4Func(("Woken up with rc=%Rrc\n", rc));
3453 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
3454 }
3455 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
3456 }
3457
3458 /*
3459 * Fetch and process IOMMU commands.
3460 */
3461 /** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
3462 * at a time) and is expensive due to calls to PGM for fetching guest memory.
3463 * We could optimize by fetching a bunch of commands at a time reducing
3464 * number of calls to PGM. In the longer run we could lock the memory and
3465 * mappings and accessing them directly. */
3466 IOMMU_LOCK(pDevIns);
3467
3468 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3469 if (Status.n.u1CmdBufRunning)
3470 {
3471 /* Get the offset we need to read the command from memory (circular buffer offset). */
3472 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3473 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
3474 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
3475 Assert(offHead < cbCmdBuf);
3476 while (offHead != pThis->CmdBufTailPtr.n.off)
3477 {
3478 /* Read the command from memory. */
3479 CMD_GENERIC_T Cmd;
3480 RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
3481 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
3482 if (RT_SUCCESS(rc))
3483 {
3484 /* Increment the command buffer head pointer. */
3485 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
3486 pThis->CmdBufHeadPtr.n.off = offHead;
3487
3488 /* Process the fetched command. */
3489 EVT_GENERIC_T EvtError;
3490 IOMMU_UNLOCK(pDevIns);
3491 rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
3492 IOMMU_LOCK(pDevIns);
3493 if (RT_FAILURE(rc))
3494 {
3495 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
3496 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
3497 {
3498 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
3499 iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
3500 }
3501 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
3502 {
3503 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3504 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", Cmd.n.u4Opcode));
3505 iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
3506 }
3507 break;
3508 }
3509 }
3510 else
3511 {
3512 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmd, rc));
3513 EVT_CMD_HW_ERR_T EvtCmdHwErr;
3514 iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
3515 iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
3516 break;
3517 }
3518 }
3519 }
3520
3521 IOMMU_UNLOCK(pDevIns);
3522 }
3523
3524 LogFlowFunc(("Command thread terminating\n"));
3525 return VINF_SUCCESS;
3526}
3527
3528
3529/**
3530 * Wakes up the command thread so it can respond to a state change.
3531 *
3532 * @returns VBox status code.
3533 * @param pDevIns The IOMMU device instance.
3534 * @param pThread The command thread.
3535 */
3536static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3537{
3538 RT_NOREF(pThread);
3539 LogFlowFunc(("\n"));
3540 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3541 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3542}
3543
3544
3545/**
3546 * @callback_method_impl{FNPCICONFIGREAD}
3547 */
3548static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3549 unsigned cb, uint32_t *pu32Value)
3550{
3551 /** @todo IOMMU: PCI config read stat counter. */
3552 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3553 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3554 return rcStrict;
3555}
3556
3557
3558/**
3559 * @callback_method_impl{FNPCICONFIGWRITE}
3560 */
3561static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3562 unsigned cb, uint32_t u32Value)
3563{
3564 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3565
3566 /*
3567 * Discard writes to read-only registers that are specific to the IOMMU.
3568 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3569 * See PCI spec. 6.1. "Configuration Space Organization".
3570 */
3571 switch (uAddress)
3572 {
3573 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3574 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3575 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3576 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3577 {
3578 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3579 return VINF_SUCCESS;
3580 }
3581 }
3582
3583 IOMMU_LOCK(pDevIns);
3584
3585 VBOXSTRICTRC rcStrict = VERR_IOMMU_IPE_3;
3586 switch (uAddress)
3587 {
3588 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3589 {
3590 if (pThis->IommuBar.n.u1Enable)
3591 {
3592 rcStrict = VINF_SUCCESS;
3593 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3594 break;
3595 }
3596
3597 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3598 if (pThis->IommuBar.n.u1Enable)
3599 {
3600 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
3601 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3602 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3603 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
3604
3605 /* If the MMIO region is already mapped at the specified address, we're done. */
3606 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
3607 if (GCPhysMmioBasePrev == GCPhysMmioBase)
3608 {
3609 rcStrict = VINF_SUCCESS;
3610 break;
3611 }
3612
3613 /* Unmap the previous MMIO region (which is at a different address). */
3614 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
3615 {
3616 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
3617 rcStrict = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3618 if (RT_FAILURE(rcStrict))
3619 {
3620 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3621 break;
3622 }
3623 }
3624
3625 /* Map the newly specified MMIO region. */
3626 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
3627 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3628 if (RT_FAILURE(rcStrict))
3629 {
3630 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3631 break;
3632 }
3633 }
3634 else
3635 rcStrict = VINF_SUCCESS;
3636 break;
3637 }
3638
3639 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3640 {
3641 if (!pThis->IommuBar.n.u1Enable)
3642 pThis->IommuBar.au32[1] = u32Value;
3643 else
3644 {
3645 rcStrict = VINF_SUCCESS;
3646 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3647 }
3648 break;
3649 }
3650
3651 case IOMMU_PCI_OFF_MSI_CAP_HDR:
3652 {
3653 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3654 RT_FALL_THRU();
3655 }
3656 default:
3657 {
3658 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3659 break;
3660 }
3661 }
3662
3663 IOMMU_UNLOCK(pDevIns);
3664
3665 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
3666 return rcStrict;
3667}
3668
3669
3670/**
3671 * @callback_method_impl{FNDBGFHANDLERDEV}
3672 */
3673static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3674{
3675 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3676 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3677 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3678
3679 bool fVerbose;
3680 if ( pszArgs
3681 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3682 fVerbose = true;
3683 else
3684 fVerbose = false;
3685
3686 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
3687 /* Device Table Base Addresses (all segments). */
3688 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3689 {
3690 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
3691 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
3692 if (fVerbose)
3693 {
3694 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
3695 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
3696 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
3697 }
3698 }
3699 /* Command Buffer Base Address Register. */
3700 {
3701 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
3702 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
3703 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3704 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3705 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
3706 if (fVerbose)
3707 {
3708 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
3709 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3710 cEntries, cbBuffer);
3711 }
3712 }
3713 /* Event Log Base Address Register. */
3714 {
3715 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
3716 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
3717 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3718 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3719 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
3720 if (fVerbose)
3721 {
3722 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3723 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3724 cEntries, cbBuffer);
3725 }
3726 }
3727 /* IOMMU Control Register. */
3728 {
3729 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
3730 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
3731 if (fVerbose)
3732 {
3733 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
3734 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
3735 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
3736 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3737 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3738 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
3739 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
3740 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
3741 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
3742 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
3743 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
3744 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
3745 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
3746 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
3747 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
3748 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
3749 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
3750 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
3751 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
3752 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
3753 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
3754 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
3755 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
3756 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
3757 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
3758 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
3759 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
3760 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
3761 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
3762 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
3763 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
3764 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
3765 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
3766 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
3767 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
3768 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
3769 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
3770 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
3771 }
3772 }
3773 /* Exclusion Base Address Register. */
3774 {
3775 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
3776 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
3777 if (fVerbose)
3778 {
3779 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
3780 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
3781 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
3782 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
3783 }
3784 }
3785 /* Exclusion Range Limit Register. */
3786 {
3787 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
3788 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
3789 if (fVerbose)
3790 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
3791 }
3792 /* Extended Feature Register. */
3793 {
3794 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
3795 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
3796 if (fVerbose)
3797 {
3798 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
3799 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
3800 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
3801 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
3802 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
3803 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
3804 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
3805 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
3806 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
3807 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
3808 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
3809 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
3810 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
3811 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
3812 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
3813 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
3814 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
3815 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
3816 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
3817 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
3818 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
3819 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
3820 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
3821 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
3822 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
3823 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
3824 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
3825 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
3826 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
3827 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
3828 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
3829 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
3830 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
3831 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
3832 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
3833 }
3834 }
3835 /* PPR Log Base Address Register. */
3836 {
3837 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
3838 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
3839 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3840 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3841 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
3842 if (fVerbose)
3843 {
3844 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3845 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3846 cEntries, cbBuffer);
3847 }
3848 }
3849 /* Hardware Event (Hi) Register. */
3850 {
3851 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
3852 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
3853 if (fVerbose)
3854 {
3855 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
3856 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
3857 }
3858 }
3859 /* Hardware Event (Lo) Register. */
3860 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
3861 /* Hardware Event Status. */
3862 {
3863 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
3864 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
3865 if (fVerbose)
3866 {
3867 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
3868 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
3869 }
3870 }
3871 /* Guest Virtual-APIC Log Base Address Register. */
3872 {
3873 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
3874 uint8_t const uEncodedLen = GALogBar.n.u4Len;
3875 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3876 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3877 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
3878 if (fVerbose)
3879 {
3880 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3881 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3882 cEntries, cbBuffer);
3883 }
3884 }
3885 /* Guest Virtual-APIC Log Tail Address Register. */
3886 {
3887 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
3888 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
3889 if (fVerbose)
3890 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
3891 }
3892 /* PPR Log B Base Address Register. */
3893 {
3894 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
3895 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
3896 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3897 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3898 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
3899 if (fVerbose)
3900 {
3901 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3902 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3903 cEntries, cbBuffer);
3904 }
3905 }
3906 /* Event Log B Base Address Register. */
3907 {
3908 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
3909 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
3910 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3911 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3912 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
3913 if (fVerbose)
3914 {
3915 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3916 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3917 cEntries, cbBuffer);
3918 }
3919 }
3920 /* Device-Specific Feature Extension Register. */
3921 {
3922 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
3923 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
3924 if (fVerbose)
3925 {
3926 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
3927 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
3928 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
3929 }
3930 }
3931 /* Device-Specific Control Extension Register. */
3932 {
3933 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
3934 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
3935 if (fVerbose)
3936 {
3937 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
3938 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
3939 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
3940 }
3941 }
3942 /* Device-Specific Status Extension Register. */
3943 {
3944 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
3945 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
3946 if (fVerbose)
3947 {
3948 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
3949 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
3950 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
3951 }
3952 }
3953 /* Miscellaneous Information Register (Lo and Hi). */
3954 {
3955 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
3956 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
3957 if (fVerbose)
3958 {
3959 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
3960 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
3961 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
3962 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
3963 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
3964 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
3965 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
3966 }
3967 }
3968 /* MSI Capability Header. */
3969 {
3970 MSI_CAP_HDR_T MsiCapHdr;
3971 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3972 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
3973 if (fVerbose)
3974 {
3975 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
3976 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
3977 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
3978 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
3979 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
3980 }
3981 }
3982 /* MSI Address Register (Lo and Hi). */
3983 {
3984 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3985 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3986 MSIADDR MsiAddr;
3987 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
3988 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
3989 if (fVerbose)
3990 {
3991 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
3992 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
3993 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
3994 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
3995 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
3996 }
3997 }
3998 /* MSI Data. */
3999 {
4000 MSIDATA MsiData;
4001 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
4002 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
4003 if (fVerbose)
4004 {
4005 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
4006 MsiData.n.u8Vector);
4007 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
4008 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
4009 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
4010 "level" : "edge");
4011 }
4012 }
4013 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
4014 {
4015 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
4016 MsiMapCapHdr.u32 = 0;
4017 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
4018 if (fVerbose)
4019 {
4020 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
4021 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
4022 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
4023 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
4024 }
4025 }
4026 /* Performance Optimization Control Register. */
4027 {
4028 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
4029 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
4030 if (fVerbose)
4031 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
4032 }
4033 /* XT (x2APIC) General Interrupt Control Register. */
4034 {
4035 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
4036 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
4037 if (fVerbose)
4038 {
4039 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4040 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4041 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4042 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
4043 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
4044 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4045 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4046 }
4047 }
4048 /* XT (x2APIC) PPR Interrupt Control Register. */
4049 {
4050 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
4051 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
4052 if (fVerbose)
4053 {
4054 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4055 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4056 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4057 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
4058 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
4059 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4060 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4061 }
4062 }
4063 /* XT (X2APIC) GA Log Interrupt Control Register. */
4064 {
4065 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
4066 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
4067 if (fVerbose)
4068 {
4069 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4070 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4071 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4072 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
4073 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
4074 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4075 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4076 }
4077 }
4078 /* MARC Registers. */
4079 {
4080 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
4081 {
4082 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
4083 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
4084 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
4085
4086 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
4087 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
4088 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
4089 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
4090
4091 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
4092 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
4093 }
4094 }
4095 /* Reserved Register. */
4096 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
4097 /* Command Buffer Head Pointer Register. */
4098 {
4099 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
4100 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
4101 CmdBufHeadPtr.n.off);
4102 }
4103 /* Command Buffer Tail Pointer Register. */
4104 {
4105 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
4106 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
4107 CmdBufTailPtr.n.off);
4108 }
4109 /* Event Log Head Pointer Register. */
4110 {
4111 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
4112 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
4113 EvtLogHeadPtr.n.off);
4114 }
4115 /* Event Log Tail Pointer Register. */
4116 {
4117 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
4118 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
4119 EvtLogTailPtr.n.off);
4120 }
4121 /* Status Register. */
4122 {
4123 IOMMU_STATUS_T const Status = pThis->Status;
4124 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
4125 if (fVerbose)
4126 {
4127 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
4128 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
4129 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
4130 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
4131 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
4132 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
4133 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
4134 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
4135 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
4136 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
4137 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
4138 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
4139 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
4140 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
4141 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
4142 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
4143 }
4144 }
4145 /* PPR Log Head Pointer. */
4146 {
4147 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
4148 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
4149 PprLogHeadPtr.n.off);
4150 }
4151 /* PPR Log Tail Pointer. */
4152 {
4153 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
4154 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
4155 PprLogTailPtr.n.off);
4156 }
4157 /* Guest Virtual-APIC Log Head Pointer. */
4158 {
4159 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
4160 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
4161 GALogHeadPtr.n.u12GALogPtr);
4162 }
4163 /* Guest Virtual-APIC Log Tail Pointer. */
4164 {
4165 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
4166 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
4167 GALogTailPtr.n.u12GALogPtr);
4168 }
4169 /* PPR Log B Head Pointer. */
4170 {
4171 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
4172 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
4173 PprLogBHeadPtr.n.off);
4174 }
4175 /* PPR Log B Tail Pointer. */
4176 {
4177 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
4178 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
4179 PprLogBTailPtr.n.off);
4180 }
4181 /* Event Log B Head Pointer. */
4182 {
4183 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
4184 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
4185 EvtLogBHeadPtr.n.off);
4186 }
4187 /* Event Log B Tail Pointer. */
4188 {
4189 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
4190 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
4191 EvtLogBTailPtr.n.off);
4192 }
4193 /* PPR Log Auto Response Register. */
4194 {
4195 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
4196 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
4197 if (fVerbose)
4198 {
4199 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
4200 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
4201 }
4202 }
4203 /* PPR Log Overflow Early Warning Indicator Register. */
4204 {
4205 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
4206 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
4207 if (fVerbose)
4208 {
4209 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
4210 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
4211 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
4212 }
4213 }
4214 /* PPR Log Overflow Early Warning Indicator Register. */
4215 {
4216 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
4217 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
4218 if (fVerbose)
4219 {
4220 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
4221 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
4222 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
4223 }
4224 }
4225}
4226
4227
4228/**
4229 * Dumps the DTE via the info callback helper.
4230 *
4231 * @param pHlp The info helper.
4232 * @param pDte The device table entry.
4233 * @param pszPrefix The string prefix.
4234 */
4235static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
4236{
4237 AssertReturnVoid(pHlp);
4238 AssertReturnVoid(pDte);
4239 AssertReturnVoid(pszPrefix);
4240
4241 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
4242 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
4243 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
4244 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
4245 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
4246 pDte->n.u40PageTableRootPtrLo << 12);
4247 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
4248 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
4249 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
4250 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
4251 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
4252 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
4253 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
4254 (pDte->n.u21GstCr3TableRootPtrHi << 31)
4255 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
4256 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
4257 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
4258 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
4259 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
4260 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
4261 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
4262 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
4263 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
4264 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
4265 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
4266 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
4267 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
4268 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
4269 pHlp->pfnPrintf(pHlp, "\n");
4270
4271 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
4272 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
4273 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4274 {
4275 uint16_t const cEntries = IOMMU_GET_INTR_TAB_ENTRIES(pDte);
4276 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
4277 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
4278 cbIntrTable);
4279 }
4280 else
4281 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
4282 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
4283 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
4284 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
4285 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
4286 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
4287 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
4288 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
4289 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
4290 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
4291 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
4292 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
4293 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
4294 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
4295 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
4296 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
4297 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
4298}
4299
4300
4301/**
4302 * @callback_method_impl{FNDBGFHANDLERDEV}
4303 */
4304static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4305{
4306 if (pszArgs)
4307 {
4308 uint16_t uDevId = 0;
4309 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDevId);
4310 if (RT_SUCCESS(rc))
4311 {
4312 DTE_T Dte;
4313 rc = iommuAmdReadDte(pDevIns, uDevId, IOMMUOP_TRANSLATE_REQ, &Dte);
4314 if (RT_SUCCESS(rc))
4315 {
4316 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", uDevId);
4317 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
4318 return;
4319 }
4320
4321 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", uDevId, uDevId, rc);
4322 }
4323 else
4324 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
4325 }
4326 else
4327 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
4328}
4329
4330
4331#if 0
4332/**
4333 * @callback_method_impl{FNDBGFHANDLERDEV}
4334 */
4335static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4336{
4337 RT_NOREF(pszArgs);
4338
4339 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4340 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4341 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4342
4343 uint8_t cTables = 0;
4344 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4345 {
4346 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4347 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4348 if (GCPhysDevTab)
4349 ++cTables;
4350 }
4351
4352 pHlp->pfnPrintf(pHlp, "AMD-IOMMU Device Tables:\n");
4353 pHlp->pfnPrintf(pHlp, " Tables active: %u\n", cTables);
4354 if (!cTables)
4355 return;
4356
4357 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4358 {
4359 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4360 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4361 if (GCPhysDevTab)
4362 {
4363 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
4364 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
4365 pHlp->pfnPrintf(pHlp, " Table %u (base=%#RGp size=%u bytes entries=%u):\n", i, GCPhysDevTab, cbDevTab, cDtes);
4366
4367 void *pvDevTab = RTMemAllocZ(cbDevTab);
4368 if (RT_LIKELY(pvDevTab))
4369 {
4370 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
4371 if (RT_SUCCESS(rc))
4372 {
4373 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
4374 {
4375 PCDTE_T pDte = (PCDTE_T)((char *)pvDevTab + idxDte * sizeof(DTE_T));
4376 if ( pDte->n.u1Valid
4377 || pDte->n.u1IntrMapValid)
4378 {
4379 pHlp->pfnPrintf(pHlp, " DTE %u:\n", idxDte);
4380 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
4381 }
4382 }
4383 pHlp->pfnPrintf(pHlp, "\n");
4384 }
4385 else
4386 {
4387 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %u bytes. rc=%Rrc!\n", GCPhysDevTab,
4388 cbDevTab, rc);
4389 }
4390
4391 RTMemFree(pvDevTab);
4392 }
4393 else
4394 {
4395 pHlp->pfnPrintf(pHlp, " Allocating %u bytes for reading the device table failed!\n", cbDevTab);
4396 return;
4397 }
4398 }
4399 }
4400}
4401#endif
4402
4403/**
4404 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4405 */
4406static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4407{
4408 /** @todo IOMMU: Save state. */
4409 RT_NOREF2(pDevIns, pSSM);
4410 LogFlowFunc(("\n"));
4411 return VERR_NOT_IMPLEMENTED;
4412}
4413
4414
4415/**
4416 * @callback_method_impl{FNSSMDEVLOADEXEC}
4417 */
4418static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4419{
4420 /** @todo IOMMU: Load state. */
4421 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
4422 LogFlowFunc(("\n"));
4423 return VERR_NOT_IMPLEMENTED;
4424}
4425
4426
4427/**
4428 * @interface_method_impl{PDMDEVREG,pfnReset}
4429 */
4430static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
4431{
4432 /*
4433 * Resets read-write portion of the IOMMU state.
4434 *
4435 * NOTE! State not initialized here is expected to be initialized during
4436 * device construction and remain read-only through the lifetime of the VM.
4437 */
4438 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4439 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4440 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4441
4442 IOMMU_LOCK_NORET(pDevIns);
4443
4444 LogFlowFunc(("\n"));
4445
4446 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
4447
4448 pThis->CmdBufBaseAddr.u64 = 0;
4449 pThis->CmdBufBaseAddr.n.u4Len = 8;
4450
4451 pThis->EvtLogBaseAddr.u64 = 0;
4452 pThis->EvtLogBaseAddr.n.u4Len = 8;
4453
4454 pThis->Ctrl.u64 = 0;
4455 pThis->Ctrl.n.u1Coherent = 1;
4456 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
4457
4458 pThis->ExclRangeBaseAddr.u64 = 0;
4459 pThis->ExclRangeLimit.u64 = 0;
4460
4461 pThis->PprLogBaseAddr.u64 = 0;
4462 pThis->PprLogBaseAddr.n.u4Len = 8;
4463
4464 pThis->HwEvtHi.u64 = 0;
4465 pThis->HwEvtLo = 0;
4466 pThis->HwEvtStatus.u64 = 0;
4467
4468 pThis->GALogBaseAddr.u64 = 0;
4469 pThis->GALogBaseAddr.n.u4Len = 8;
4470 pThis->GALogTailAddr.u64 = 0;
4471
4472 pThis->PprLogBBaseAddr.u64 = 0;
4473 pThis->PprLogBBaseAddr.n.u4Len = 8;
4474
4475 pThis->EvtLogBBaseAddr.u64 = 0;
4476 pThis->EvtLogBBaseAddr.n.u4Len = 8;
4477
4478 pThis->PerfOptCtrl.u32 = 0;
4479
4480 pThis->XtGenIntrCtrl.u64 = 0;
4481 pThis->XtPprIntrCtrl.u64 = 0;
4482 pThis->XtGALogIntrCtrl.u64 = 0;
4483
4484 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
4485
4486 pThis->CmdBufHeadPtr.u64 = 0;
4487 pThis->CmdBufTailPtr.u64 = 0;
4488 pThis->EvtLogHeadPtr.u64 = 0;
4489 pThis->EvtLogTailPtr.u64 = 0;
4490
4491 pThis->Status.u64 = 0;
4492
4493 pThis->PprLogHeadPtr.u64 = 0;
4494 pThis->PprLogTailPtr.u64 = 0;
4495
4496 pThis->GALogHeadPtr.u64 = 0;
4497 pThis->GALogTailPtr.u64 = 0;
4498
4499 pThis->PprLogBHeadPtr.u64 = 0;
4500 pThis->PprLogBTailPtr.u64 = 0;
4501
4502 pThis->EvtLogBHeadPtr.u64 = 0;
4503 pThis->EvtLogBTailPtr.u64 = 0;
4504
4505 pThis->PprLogAutoResp.u64 = 0;
4506 pThis->PprLogOverflowEarly.u64 = 0;
4507 pThis->PprLogBOverflowEarly.u64 = 0;
4508
4509 pThis->IommuBar.u64 = 0;
4510 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
4511 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
4512
4513 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
4514
4515 IOMMU_UNLOCK(pDevIns);
4516}
4517
4518
4519/**
4520 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4521 */
4522static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
4523{
4524 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4525 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4526 LogFlowFunc(("\n"));
4527
4528 /* Close the command thread semaphore. */
4529 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
4530 {
4531 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
4532 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
4533 }
4534 return VINF_SUCCESS;
4535}
4536
4537
4538/**
4539 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4540 */
4541static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4542{
4543 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4544 RT_NOREF(pCfg);
4545
4546 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4547 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4548 pThisCC->pDevInsR3 = pDevIns;
4549
4550 LogFlowFunc(("iInstance=%d\n", iInstance));
4551
4552 /*
4553 * Register the IOMMU with PDM.
4554 */
4555 PDMIOMMUREGR3 IommuReg;
4556 RT_ZERO(IommuReg);
4557 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4558 IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
4559 IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
4560 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4561 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4562 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4563 if (RT_FAILURE(rc))
4564 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4565 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4566 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4567 N_("IOMMU helper version mismatch; got %#x expected %#x"),
4568 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4569 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4570 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4571 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4572 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4573
4574 /*
4575 * Initialize read-only PCI configuration space.
4576 */
4577 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4578 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4579
4580 /* Header. */
4581 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
4582 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
4583 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
4584 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
4585 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4586 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4587 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
4588 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
4589 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
4590 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
4591 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
4592 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
4593 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
4594 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
4595
4596 /* Capability Header. */
4597 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
4598 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
4599 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
4600 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
4601 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
4602 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
4603 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
4604 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
4605 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
4606 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
4607 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
4608
4609 /* Base Address Register. */
4610 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
4611 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
4612
4613 /* IOMMU Range Register. */
4614 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
4615
4616 /* Misc. Information Register. */
4617 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
4618 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
4619 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
4620 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
4621 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
4622 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
4623 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
4624 uint32_t const uMiscInfoReg1 = 0;
4625 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
4626 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
4627
4628 /* MSI Capability Header register. */
4629 PDMMSIREG MsiReg;
4630 RT_ZERO(MsiReg);
4631 MsiReg.cMsiVectors = 1;
4632 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
4633 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
4634 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
4635
4636 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
4637#if 0
4638 /* MSI Address Lo. */
4639 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
4640 /* MSI Address Hi. */
4641 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
4642 /* MSI Data. */
4643 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
4644#endif
4645
4646#if 0
4647 /** @todo IOMMU: I don't know if we need to support this, enable later if
4648 * required. */
4649 /* MSI Mapping Capability Header register. */
4650 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
4651 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
4652 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
4653 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
4654 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
4655 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
4656 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
4657#endif
4658
4659 /*
4660 * Register the PCI function with PDM.
4661 */
4662 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4663 AssertLogRelRCReturn(rc, rc);
4664
4665 /*
4666 * Register MSI support for the PCI device.
4667 * This must be done -after- register it as a PCI device!
4668 */
4669 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4670 AssertRCReturn(rc, rc);
4671
4672 /*
4673 * Intercept PCI config. space accesses.
4674 */
4675 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
4676 AssertLogRelRCReturn(rc, rc);
4677
4678 /*
4679 * Create the MMIO region.
4680 * Mapping of the region is done when software configures it via PCI config space.
4681 */
4682 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
4683 NULL /* pvUser */,
4684 IOMMMIO_FLAGS_READ_DWORD_QWORD
4685 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
4686 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
4687 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
4688 "AMD-IOMMU", &pThis->hMmio);
4689 AssertLogRelRCReturn(rc, rc);
4690
4691 /*
4692 * Register saved state.
4693 */
4694 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
4695 NULL, NULL, NULL,
4696 NULL, iommuAmdR3SaveExec, NULL,
4697 NULL, iommuAmdR3LoadExec, NULL);
4698 AssertLogRelRCReturn(rc, rc);
4699
4700 /*
4701 * Register debugger info items.
4702 */
4703 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
4704 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device. Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
4705#if 0
4706 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display IOMMU device tables.", iommuAmdR3DbgInfoDevTabs);
4707#endif
4708
4709# ifdef VBOX_WITH_STATISTICS
4710 /*
4711 * Statistics.
4712 */
4713 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4714 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4715
4716 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4717 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4718
4719 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
4720 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
4721
4722 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
4723 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
4724
4725 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
4726 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
4727
4728 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
4729 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
4730
4731 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
4732 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
4733
4734 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
4735 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
4736 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
4737 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
4738 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
4739 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
4740 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
4741 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
4742 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
4743
4744 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDteLookup, STAMTYPE_PROFILE, "DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling device table entry lookup (uncached).");
4745# endif
4746
4747 /*
4748 * Create the command thread and its event semaphore.
4749 */
4750 char szDevIommu[64];
4751 RT_ZERO(szDevIommu);
4752 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
4753 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
4754 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
4755 AssertLogRelRCReturn(rc, rc);
4756
4757 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
4758 AssertLogRelRCReturn(rc, rc);
4759
4760 /*
4761 * Initialize read-only registers.
4762 * NOTE! Fields here must match their corresponding field in the ACPI tables.
4763 */
4764 /* Don't remove the commented lines below as it lets us see all features at a glance. */
4765 pThis->ExtFeat.u64 = 0;
4766 //pThis->ExtFeat.n.u1PrefetchSup = 0;
4767 //pThis->ExtFeat.n.u1PprSup = 0;
4768 //pThis->ExtFeat.n.u1X2ApicSup = 0;
4769 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
4770 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
4771 pThis->ExtFeat.n.u1InvAllSup = 1;
4772 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
4773 pThis->ExtFeat.n.u1HwErrorSup = 1;
4774 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
4775 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
4776 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
4777 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
4778 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
4779 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
4780 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
4781 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
4782 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
4783 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
4784 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
4785 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
4786 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
4787 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
4788 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
4789 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
4790 //pThis->ExtFeat.n.u2MarcSup = 0;
4791 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
4792 //pThis->ExtFeat.n.u1PerfOptSup = 0;
4793 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
4794 //pThis->ExtFeat.n.u1GstIoSup = 0;
4795 //pThis->ExtFeat.n.u1HostAccessSup = 0;
4796 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
4797 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
4798 //pThis->ExtFeat.n.u1HostDirtySup = 0;
4799 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
4800 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
4801 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
4802
4803 pThis->RsvdReg = 0;
4804
4805 pThis->DevSpecificFeat.u64 = 0;
4806 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
4807 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
4808
4809 pThis->DevSpecificCtrl.u64 = 0;
4810 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
4811 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
4812
4813 pThis->DevSpecificStatus.u64 = 0;
4814 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
4815 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
4816
4817 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
4818
4819 /*
4820 * Initialize parts of the IOMMU state as it would during reset.
4821 * Must be called -after- initializing PCI config. space registers.
4822 */
4823 iommuAmdR3Reset(pDevIns);
4824
4825 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
4826 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
4827 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
4828 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
4829 pThis->ExtFeat.u64));
4830 return VINF_SUCCESS;
4831}
4832
4833#else
4834
4835/**
4836 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4837 */
4838static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
4839{
4840 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4841 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4842 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4843
4844 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4845
4846 /* Set up the MMIO RZ handlers. */
4847 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
4848 AssertRCReturn(rc, rc);
4849
4850 /* Set up the IOMMU RZ callbacks. */
4851 PDMIOMMUREGCC IommuReg;
4852 RT_ZERO(IommuReg);
4853 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4854 IommuReg.idxIommu = pThis->idxIommu;
4855 IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
4856 IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
4857 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4858 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4859 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4860 AssertRCReturn(rc, rc);
4861
4862 return VINF_SUCCESS;
4863}
4864#endif
4865
4866
4867/**
4868 * The device registration structure.
4869 */
4870const PDMDEVREG g_DeviceIommuAmd =
4871{
4872 /* .u32Version = */ PDM_DEVREG_VERSION,
4873 /* .uReserved0 = */ 0,
4874 /* .szName = */ "iommu-amd",
4875 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4876 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4877 /* .cMaxInstances = */ ~0U,
4878 /* .uSharedVersion = */ 42,
4879 /* .cbInstanceShared = */ sizeof(IOMMU),
4880 /* .cbInstanceCC = */ sizeof(IOMMUCC),
4881 /* .cbInstanceRC = */ sizeof(IOMMURC),
4882 /* .cMaxPciDevices = */ 1,
4883 /* .cMaxMsixVectors = */ 0,
4884 /* .pszDescription = */ "IOMMU (AMD)",
4885#if defined(IN_RING3)
4886 /* .pszRCMod = */ "VBoxDDRC.rc",
4887 /* .pszR0Mod = */ "VBoxDDR0.r0",
4888 /* .pfnConstruct = */ iommuAmdR3Construct,
4889 /* .pfnDestruct = */ iommuAmdR3Destruct,
4890 /* .pfnRelocate = */ NULL,
4891 /* .pfnMemSetup = */ NULL,
4892 /* .pfnPowerOn = */ NULL,
4893 /* .pfnReset = */ iommuAmdR3Reset,
4894 /* .pfnSuspend = */ NULL,
4895 /* .pfnResume = */ NULL,
4896 /* .pfnAttach = */ NULL,
4897 /* .pfnDetach = */ NULL,
4898 /* .pfnQueryInterface = */ NULL,
4899 /* .pfnInitComplete = */ NULL,
4900 /* .pfnPowerOff = */ NULL,
4901 /* .pfnSoftReset = */ NULL,
4902 /* .pfnReserved0 = */ NULL,
4903 /* .pfnReserved1 = */ NULL,
4904 /* .pfnReserved2 = */ NULL,
4905 /* .pfnReserved3 = */ NULL,
4906 /* .pfnReserved4 = */ NULL,
4907 /* .pfnReserved5 = */ NULL,
4908 /* .pfnReserved6 = */ NULL,
4909 /* .pfnReserved7 = */ NULL,
4910#elif defined(IN_RING0)
4911 /* .pfnEarlyConstruct = */ NULL,
4912 /* .pfnConstruct = */ iommuAmdRZConstruct,
4913 /* .pfnDestruct = */ NULL,
4914 /* .pfnFinalDestruct = */ NULL,
4915 /* .pfnRequest = */ NULL,
4916 /* .pfnReserved0 = */ NULL,
4917 /* .pfnReserved1 = */ NULL,
4918 /* .pfnReserved2 = */ NULL,
4919 /* .pfnReserved3 = */ NULL,
4920 /* .pfnReserved4 = */ NULL,
4921 /* .pfnReserved5 = */ NULL,
4922 /* .pfnReserved6 = */ NULL,
4923 /* .pfnReserved7 = */ NULL,
4924#elif defined(IN_RC)
4925 /* .pfnConstruct = */ iommuAmdRZConstruct,
4926 /* .pfnReserved0 = */ NULL,
4927 /* .pfnReserved1 = */ NULL,
4928 /* .pfnReserved2 = */ NULL,
4929 /* .pfnReserved3 = */ NULL,
4930 /* .pfnReserved4 = */ NULL,
4931 /* .pfnReserved5 = */ NULL,
4932 /* .pfnReserved6 = */ NULL,
4933 /* .pfnReserved7 = */ NULL,
4934#else
4935# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4936#endif
4937 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4938};
4939
4940#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4941
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette