DevIommuAmd.cpp@ 83263

Last change on this file since 83263 was 83263, checked in by vboxsync, 5 years ago
AMD IOMMU: bugref:9654 Skeletal bits.
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File size: 41.9 KB

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1	/* $Id: DevIommuAmd.cpp 83263 2020-03-11 16:34:33Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/vmm/pdmdev.h>
24
25	#include "VBoxDD.h"
26
27
28	/*********************************************************************************************************************************
29	* Defined Constants And Macros *
30	*********************************************************************************************************************************/
31	/**
32	* @name Commands.
33	* In accordance with the AMD spec.
34	* @{
35	*/
36	#define IOMMU_CMD_COMPLETION_WAIT 0x01
37	#define IOMMU_CMD_INV_DEVTAB_ENTRY 0x02
38	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
39	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
40	#define IOMMU_CMD_INV_INTR_TABLE 0x05
41	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
42	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
43	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
44	/** @} */
45
46	/**
47	* @name Event codes.
48	* In accordance with the AMD spec.
49	* @{
50	*/
51	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
52	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
53	#define IOMMU_EVT_DEV_TAB_HARDWARE_ERROR 0x03
54	#define IOMMU_EVT_PAGE_TAB_HARDWARE_ERROR 0x04
55	#define IOMMU_EVT_ILLEGAL_COMMAND_ERROR 0x05
56	#define IOMMU_EVT_COMMAND_HARDWARE_ERROR 0x06
57	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
58	#define IOMMU_EVT_INVALID_DEVICE_REQUEST 0x08
59	#define IOMMU_EVT_INVALID_PPR_REQUEST 0x09
60	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
61	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
62	/** @} */
63
64	/**
65	* @name Capability Header.
66	* In accordance with the AMD spec.
67	* @{
68	*/
69	/** CapId: Capability ID. */
70	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
71	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
72	/** CapPtr: Capability Pointer. */
73	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
74	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
75	/** CapType: Capability Type. */
76	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
77	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
78	/** CapRev: Capability Revision. */
79	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
80	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
81	/** IoTlbSup: IO TLB Support. */
82	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
83	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
84	/** HtTunnel: HyperTransport Tunnel translation support. */
85	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
86	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
87	/** NpCache: Not Present table entries Cached. */
88	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
89	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
90	/** EFRSup: Extended Feature Register (EFR) Supported. */
91	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
92	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
93	/** CapExt: Miscellaneous Information Register Supported . */
94	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
95	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
96	/** Bits 31:29 reserved. */
97	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
98	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
99	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
100	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
101	/** @} */
102
103	/**
104	* @name Base Address Low Register.
105	* In accordance with the AMD spec.
106	* @{
107	*/
108	/** Enable: Enables access to the address specified in the Base Address Register. */
109	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
110	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
111	/** Bits 13:1 reserved. */
112	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
113	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
114	/** Base Address[18:14]: Low Base address (Lo) of IOMMU control registers. */
115	#define IOMMU_BF_BASEADDR_LO_ADDR_LO_SHIFT 14
116	#define IOMMU_BF_BASEADDR_LO_ADDR_LO_MASK UINT32_C(0x0007c000)
117	/** Base Address[31:19]: Low Base address (Hi) of IOMMU control registers. */
118	#define IOMMU_BF_BASEADDR_LO_ADDR_HI_SHIFT 19
119	#define IOMMU_BF_BASEADDR_LO_ADDR_HI_MASK UINT32_C(0xfff80000)
120	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
121	(ENABLE, RSVD_1_13, ADDR_LO, ADDR_HI));
122	/** @} */
123
124	/**
125	* @name Range Register.
126	* In accordance with the AMD spec.
127	* @{
128	*/
129	/** UnitID: HyperTransport Unit ID. */
130	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
131	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
132	/** Bits 6:5 reserved. */
133	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
134	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
135	/** RngValid: Range valid. */
136	#define IOMMU_BF_RANGE_VALID_SHIFT 7
137	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
138	/** BusNumber: Device range bus number. */
139	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
140	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
141	/** First Device. */
142	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
143	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
144	/** Last Device. */
145	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
146	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
147	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
148	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
149	/** @} */
150
151	/**
152	* @name Miscellaneous Information Register 0.
153	* In accordance with the AMD spec.
154	* @{
155	*/
156	/** MsiNum: MSI message number. */
157	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
158	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
159	/** GvaSize: Guest Virtual Address Size. */
160	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
161	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
162	/** PaSize: Physical Address Size. */
163	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
164	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
165	/** VaSize: Virtual Address Size. */
166	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
167	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
168	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
169	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
170	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
171	/** Bits 26:23 reserved. */
172	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
173	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
174	/** MsiNumPPR: Peripheral Page Request MSI message number. */
175	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
176	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
177	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
178	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
179	/** @} */
180
181	/**
182	* @name Miscellaneous Information Register 1.
183	* In accordance with the AMD spec.
184	* @{
185	*/
186	/** MsiNumGA: MSI message number for guest vAPIC. */
187	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
188	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
189	/** Bits 31:5 reserved. */
190	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
191	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
192	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
193	(MSI_NUM_GA, RSVD_5_31));
194	/** @} */
195
196
197	/*********************************************************************************************************************************
198	* Structures and Typedefs *
199	*********************************************************************************************************************************/
200	/**
201	* The Device ID.
202	* In accordance with the AMD spec.
203	*/
204	typedef union
205	{
206	struct
207	{
208	uint16_t uFunction : 3; /*< Bits 2:0 - Function. /
209	uint16_t uDevice : 5; /*< Bits 7:3 - Device. /
210	uint16_t uBus : 8; /*< Bits 15:8 - Bus. /
211	} n;
212	/** The unsigned integer view. */
213	uint16_t u;
214	} DEVICE_ID_T;
215	AssertCompileSize(DEVICE_ID_T, 2);
216
217	/**
218	* Device Table Entry (DTE).
219	* In accordance with the AMD spec.
220	*/
221	typedef union
222	{
223	struct
224	{
225	uint32_t u1Valid : 1; /*< Bit 0 - V: Valid. /
226	uint32_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
227	uint32_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
228	uint32_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
229	uint32_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
230	uint32_t u20PageTableRootPtrLo : 20; /*< Bits 31:12 - Page Table Root Pointer (Lo). /
231	uint32_t u20PageTableRootPtrHi : 20; /*< Bits 51:32 - Page Table Root Pointer (Hi). /
232	uint32_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
233	uint32_t u1Grpr : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
234	uint32_t u1GIov : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
235	uint32_t u1GValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
236	uint32_t u2Glx : 2; /*< Bits 57:56 - GLX: Guest Levels Translated. /
237	uint32_t u3GCr3TableRootPtrLo : 2; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Pointer (Lo). /
238	uint32_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
239	uint32_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
240	uint32_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
241	uint32_t u16DomainId : 1; /*< Bits 79:64 - Domain ID. /
242	uint32_t u16GCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Pointer (Mid). /
243	uint32_t u1IotlbEnable : 1; /*< Bit 96 - IOTLB Enable. /
244	uint32_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
245	uint32_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
246	uint32_t u2IoCtl : 1; /*< Bits 100:99 - IoCtl: Port I/O Control. /
247	uint32_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
248	uint32_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
249	uint32_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
250	uint32_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
251	uint32_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
252	uint32_t u21Gcr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Pointer (Hi). /
253	uint32_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
254	uint32_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
255	uint32_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
256	uint32_t u26IntrTableRootPtr : 26; /*< Bits 159:134 - Interrupt Root Table Pointer (Lo). /
257	uint32_t u20IntrTableRootPtr : 20; /*< Bits 179:160 - Interrupt Root Table Pointer (Hi). /
258	uint32_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
259	uint32_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
260	uint32_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
261	uint32_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
262	uint32_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
263	uint32_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
264	uint32_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 (Legacy PIC NMI) Pass-thru. /
265	uint32_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 (Legacy PIC NMI) Pass-thru. /
266	uint32_t u32Rsvd0; /*< Bits 223:192 - Reserved. /
267	uint32_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
268	uint32_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
269	uint32_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
270	uint32_t u8SnoopAttr: 1; /*< Bits 255:248 - Snoop Attribute. /
271	} n;
272	/** The 32-bit unsigned integer view. */
273	uint32_t au32[8];
274	} DEV_TAB_ENTRY_T;
275	AssertCompileSize(DEV_TAB_ENTRY_T, 32);
276
277	/**
278	* I/O Page Table Entry.
279	* In accordance with the AMD spec.
280	*/
281	typedef union
282	{
283	struct
284	{
285	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
286	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
287	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
288	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
289	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
290	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
291	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
292	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
293	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
294	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
295	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
296	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
297	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
298	} n;
299	/** The 64-bit unsigned integer view. */
300	uint64_t u;
301	} IOPTE_T;
302	AssertCompileSize(IOPTE_T, 8);
303
304	/**
305	* I/O Page Directory Entry.
306	* In accordance with the AMD spec.
307	*/
308	typedef union
309	{
310	struct
311	{
312	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
313	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
314	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
315	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
316	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
317	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
318	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
319	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
320	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
321	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
322	} n;
323	/** The 64-bit unsigned integer view. */
324	uint64_t u;
325	} IOPDE_T;
326	AssertCompileSize(IOPDE_T, 8);
327
328	/**
329	* Interrupt Remapping Table Entry.
330	* In accordance with the AMD spec.
331	*/
332	typedef union
333	{
334	struct
335	{
336	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap enable. /
337	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
338	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
339	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
340	uint32_t u1DstMode : 1; /*< Bit 6 - DM: Destination Mode. /
341	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
342	uint32_t u8Dst : 8; /*< Bits 15:8 - Destination. /
343	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
344	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
345	} n;
346	/** The 32-bit unsigned integer view. */
347	uint32_t u;
348	} IRTE_T;
349	AssertCompileSize(IRTE_T, 4);
350
351	/**
352	* Command: Generic Command Buffer Entry.
353	* In accordance with the AMD spec.
354	*/
355	typedef union
356	{
357	struct
358	{
359	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
360	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
361	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
362	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
363	} n;
364	/** The 64-bit unsigned integer view. */
365	uint64_t au64[2];
366	} CMD_GENERIC_T;
367	AssertCompileSize(CMD_GENERIC_T, 16);
368
369	/**
370	* Command: COMPLETION_WAIT.
371	* In accordance with the AMD spec.
372	*/
373	typedef union
374	{
375	struct
376	{
377	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
378	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
379	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
380	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
381	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
382	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
383	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
384	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
385	} n;
386	/** The 64-bit unsigned integer view. */
387	uint32_t au64[2];
388	} CMD_COMPLETION_WAIT_T;
389	AssertCompileSize(CMD_COMPLETION_WAIT_T, 16);
390
391	/**
392	* Command: INVALIDATE_DEVTAB_ENTRY.
393	* In accordance with the AMD spec.
394	*/
395	typedef union
396	{
397	struct
398	{
399	uint16_t u16DeviceId; /*< Bits 15:0 - DeviceID. /
400	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
401	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
402	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
403	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
404	} n;
405	/** The 64-bit unsigned integer view. */
406	uint64_t au64[2];
407	} CMD_INV_DEV_TAB_ENTRY_T;
408	AssertCompileSize(CMD_INV_DEV_TAB_ENTRY_T, 16);
409
410	/**
411	* Command: INVALIDATE_IOMMU_PAGES.
412	* In accordance with the AMD spec.
413	*/
414	typedef union
415	{
416	struct
417	{
418	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
419	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
420	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
421	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
422	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
423	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
424	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
425	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
426	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
427	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
428	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
429	} n;
430	/** The 64-bit unsigned integer view. */
431	uint64_t au64[2];
432	} CMD_INV_IOMMU_PAGES_T;
433	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
434
435	/**
436	* Command: INVALIDATE_IOTLB_PAGES.
437	* In accordance with the AMD spec.
438	*/
439	typedef union
440	{
441	struct
442	{
443	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
444	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
445	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
446	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
447	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
448	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
449	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
450	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
451	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
452	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
453	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
454	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
455	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
456	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
457	} n;
458	/** The 64-bit unsigned integer view. */
459	uint64_t au64[2];
460	} CMD_INV_IOTLB_PAGES_T;
461	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
462
463	/**
464	* Command: INVALIDATE_INTR_TABLE.
465	* In accordance with the AMD spec.
466	*/
467	typedef union
468	{
469	struct
470	{
471	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
472	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
473	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
474	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
475	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
476	} u;
477	/** The 64-bit unsigned integer view. */
478	uint64_t au64[2];
479	} CMD_INV_INTR_TABLE_T;
480	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
481
482	/**
483	* Command: COMPLETE_PPR_REQ.
484	* In accordance with the AMD spec.
485	*/
486	typedef union
487	{
488	struct
489	{
490	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
491	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
492	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
493	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
494	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
495	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
496	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
497	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
498	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
499	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
500	} n;
501	/** The 64-bit unsigned integer view. */
502	uint64_t au64[2];
503	} CMD_COMPLETE_PPR_REQ_T;
504	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
505
506	/**
507	* Command: INV_IOMMU_ALL.
508	* In accordance with the AMD spec.
509	*/
510	typedef union
511	{
512	struct
513	{
514	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
515	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
516	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
517	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
518	} n;
519	/** The 64-bit unsigned integer view. */
520	uint64_t au64[2];
521	} CMD_IOMMU_ALL_T;
522	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
523
524	/**
525	* Event Log Entry: Generic.
526	* In accordance with the AMD spec.
527	*/
528	typedef union
529	{
530	struct
531	{
532	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
533	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
534	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
535	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
536	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
537	} n;
538	/** The 32-bit unsigned integer view. */
539	uint32_t au32[4];
540	} EVT_GENERIC_T;
541	AssertCompileSize(EVT_GENERIC_T, 16);
542
543	/**
544	* Event Log Entry: ILLEGAL_DEV_TAB_ENTRY.
545	* In accordance with the AMD spec.
546	*/
547	typedef union
548	{
549	struct
550	{
551	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
552	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
553	uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
554	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
555	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
556	uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
557	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
558	uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
559	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
560	uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
561	uint16_t u1RsvdZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero or invalid level encoding. /
562	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
563	uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
564	uint16_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
565	uint32_t u2Rsvd1 : 2; /*< Bits 65:64 - Reserved. /
566	uint32_t u30AddrLo : 2; /*< Bits 95:66 - Address: Device Virtual Address (Lo). /
567	uint32_t u30AddrHi; /*< Bits 127:96 - Address: Device Virtual Address (Hi). /
568	} n;
569	/** The 32-bit unsigned integer view. */
570	uint32_t au32[4];
571	} EVT_ILLEGAL_DEV_TAB_ENTRY_T;
572	AssertCompileSize(EVT_ILLEGAL_DEV_TAB_ENTRY_T, 16);
573
574	/**
575	* Event Log Entry: IO_PAGE_FAULT_EVENT.
576	* In accordance with the AMD spec.
577	*/
578	typedef union
579	{
580	struct
581	{
582	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
583	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
584	uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
585	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
586	uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
587	uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
588	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
589	uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
590	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
591	uint16_t u1Perm : 1; /*< Bit 54 - PE: Permission Indicator. /
592	uint16_t u1RsvdZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero or invalid level encoding. /
593	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
594	uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
595	uint16_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
596	uint64_t u64Addr; /*< Bits 127:64 - Address: Device Virtual Address. /
597	} n;
598	/** The 32-bit unsigned integer view. */
599	uint32_t au32[4];
600	} EVT_IO_PAGE_FAULT_T;
601	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
602
603	/**
604	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
605	* In accordance with the AMD spec.
606	*/
607	typedef union
608	{
609	struct
610	{
611	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
612	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
613	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
614	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt. /
615	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
616	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
617	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
618	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
619	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
620	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
621	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
622	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
623	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: System Physical Address (Lo). /
624	uint32_t u32AddrHi; /*< Bits 127:96 - Address: System Physical Address (Hi). /
625	} n;
626	/** The 32-bit unsigned integer view. */
627	uint32_t au32[4];
628	} EVT_DEV_TAB_HARDWARE_ERROR;
629	AssertCompileSize(EVT_DEV_TAB_HARDWARE_ERROR, 16);
630
631	/**
632	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
633	* In accordance with the AMD spec.
634	*/
635	typedef union
636	{
637	struct
638	{
639	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
640	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
641	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
642	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
643	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
644	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
645	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
646	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
647	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
648	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
649	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
650	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
651	uint32_t u4EventCode : 4; /*< Bit 63:60 - Event code. /
652	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
653	* table 58 mentions Addr[31:4]. Looks like a typo in the figure. Use
654	* table as it makes more sense and matches address size in
655	* EVT_DEV_TAB_HARDWARE_ERROR. See AMD AMD IOMMU spec (3.05-PUB, Jan
656	* 2020). */
657	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
658	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of page table entry (Lo). /
659	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of page table entry (Hi). /
660	} n;
661	/** The 32-bit unsigned integer view. */
662	uint32_t au32[4];
663	} EVT_PAGE_TAB_HARDWARE_ERROR;
664	AssertCompileSize(EVT_PAGE_TAB_HARDWARE_ERROR, 16);
665
666	/**
667	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
668	* In accordance with the AMD spec.
669	*/
670	typedef union
671	{
672	struct
673	{
674	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
675	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
676	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
677	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
678	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalid command (Lo). /
679	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalid command (Hi). /
680	} n;
681	/** The 32-bit unsigned integer view. */
682	uint32_t au32[4];
683	} EVT_ILLEGAL_COMMAND_ENTRY;
684	AssertCompileSize(EVT_ILLEGAL_COMMAND_ENTRY, 16);
685
686	/**
687	* Event Log Entry: COMMAND_HARDWARE_ERROR.
688	* In accordance with the AMD spec.
689	*/
690	typedef union
691	{
692	struct
693	{
694	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
695	uint32_t u4Rsvd0 : 4; /*< Bits 35:32 - Reserved. /
696	uint32_t u28AddrLo : 28; /*< Bits 63:36 - Address: SPA of the attempted access (Lo). /
697	uint32_t u32AddrHi; /*< Bits 95:64 - Address: SPA of the attempted access (Hi). /
698	} n;
699	/** The 32-bit unsigned integer view. */
700	uint32_t au32[3];
701	} EVT_COMMAND_HARDWARE_ERROR;
702	AssertCompileSize(EVT_COMMAND_HARDWARE_ERROR, 12);
703
704	/**
705	* Event Log Entry: IOTLB_INV_TIMEOUT.
706	* In accordance with the AMD spec.
707	*/
708	typedef union
709	{
710	struct
711	{
712	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
713	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
714	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
715	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
716	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
717	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
718	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
719	} n;
720	/** The 32-bit unsigned integer view. */
721	uint32_t au32[4];
722	} EVT_IOTLB_INV_TIMEOUT;
723	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT, 16);
724
725	/**
726	* Event Log Entry: INVALID_DEVICE_REQUEST.
727	* In accordance with the AMD spec.
728	*/
729	typedef union
730	{
731	struct
732	{
733	uint32_t u16DeviceId : 16; /**< Bits 15:0 - Device ID. /
734	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
735	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
736	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
737	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
738	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
739	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
740	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
741	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
742	uint32_t u4EventCode : 4; /**< Bits 63:60 - Event code. /
743	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
744	} n;
745	/** The 32-bit unsigned integer view. */
746	uint32_t au32[4];
747	} EVT_INVALID_DEVICE_REQUEST;
748	AssertCompileSize(EVT_INVALID_DEVICE_REQUEST, 16);
749
750	/**
751	* Event Log Entry: EVENT_COUNTER_ZERO.
752	* In accordance with the AMD spec.
753	*/
754	typedef union
755	{
756	struct
757	{
758	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
759	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
760	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
761	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
762	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
763	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
764	} n;
765	/** The 32-bit unsigned integer view. */
766	uint32_t au32[4];
767	} EVT_EVENT_COUNTER_ZERO;
768	AssertCompileSize(EVT_EVENT_COUNTER_ZERO, 16);
769
770
771	/**
772	* The IOMMU device state.
773	*/
774	typedef struct IOMMU
775	{
776
777	} IOMMU;
778	/** Pointer to the IOMMU device state. */
779	typedef struct IOMMU *PIOMMU;
780
781	/**
782	* The ring-3 IOMMU device state.
783	*/
784	typedef struct IOMMUR3
785	{
786	} IOMMUR3;
787	/** Pointer to the ring-3 IOMMU device state. */
788	typedef IOMMUR3 *PIOMMUR3;
789
790	/**
791	* The ring-0 IOMMU device state.
792	*/
793	typedef struct IOMMUR0
794	{
795	uint64_t uUnused;
796	} IOMMUR0;
797	/** Pointer to the ring-0 IOMMU device state. */
798	typedef IOMMUR0 *PIOMMUR0;
799
800	/**
801	* The raw-mode IOMMU device state.
802	*/
803	typedef struct IOMMURC
804	{
805	uint64_t uUnused;
806	} IOMMURC;
807	/** Pointer to the raw-mode IOMMU device state. */
808	typedef IOMMURC *PIOMMURC;
809
810	/** The IOMMU device state for the current context. */
811	typedef CTX_SUFF(IOMMU) IOMMUCC;
812	/** Pointer to the IOMMU device state for the current context. */
813	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
814
815
816	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
817
818	# ifdef IN_RING3
819	/**
820	* @interface_method_impl{PDMDEVREG,pfnReset}
821	*/
822	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
823	{
824	NOREF(pDevIns);
825	}
826
827
828	/**
829	* @interface_method_impl{PDMDEVREG,pfnDestruct}
830	*/
831	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
832	{
833	NOREF(pDevIns);
834	return VINF_SUCCESS;
835	}
836
837
838	/**
839	* @interface_method_impl{PDMDEVREG,pfnConstruct}
840	*/
841	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
842	{
843	NOREF(iInstance);
844	NOREF(pCfg);
845
846	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
847	#if 0
848	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
849	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
850	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
851	int rc;
852	LogFlowFunc(("\n"));
853
854	/*
855	* Validate and read the configuration.
856	*/
857	//PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
858	#endif
859	return VINF_SUCCESS;
860	}
861
862	# else /* !IN_RING3 */
863
864	/**
865	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
866	*/
867	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
868	{
869	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
870	return VINF_SUCCESS;
871	}
872
873	# endif /* !IN_RING3 */
874
875	/**
876	* The device registration structure.
877	*/
878	const PDMDEVREG g_DeviceIommuAmd =
879	{
880	/* .u32Version = */ PDM_DEVREG_VERSION,
881	/* .uReserved0 = */ 0,
882	/* .szName = */ "iommu-amd",
883	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
884	/* .fClass = / PDM_DEVREG_CLASS_BUS_ISA, / Instantiate after PDM_DEVREG_CLASS_BUS_PCI */
885	/* .cMaxInstances = */ ~0U,
886	/* .uSharedVersion = */ 42,
887	/* .cbInstanceShared = */ sizeof(IOMMU),
888	/* .cbInstanceCC = */ sizeof(IOMMUCC),
889	/* .cbInstanceRC = */ sizeof(IOMMURC),
890	/* .cMaxPciDevices = */ 1,
891	/* .cMaxMsixVectors = */ 0,
892	/* .pszDescription = */ "IOMMU (AMD)",
893	#if defined(IN_RING3)
894	/* .pszRCMod = */ "VBoxDDRC.rc",
895	/* .pszR0Mod = */ "VBoxDDR0.r0",
896	/* .pfnConstruct = */ iommuAmdR3Construct,
897	/* .pfnDestruct = */ iommuAmdR3Destruct,
898	/* .pfnRelocate = */ NULL,
899	/* .pfnMemSetup = */ NULL,
900	/* .pfnPowerOn = */ NULL,
901	/* .pfnReset = */ iommuAmdR3Reset,
902	/* .pfnSuspend = */ NULL,
903	/* .pfnResume = */ NULL,
904	/* .pfnAttach = */ NULL,
905	/* .pfnDetach = */ NULL,
906	/* .pfnQueryInterface = */ NULL,
907	/* .pfnInitComplete = */ NULL,
908	/* .pfnPowerOff = */ NULL,
909	/* .pfnSoftReset = */ NULL,
910	/* .pfnReserved0 = */ NULL,
911	/* .pfnReserved1 = */ NULL,
912	/* .pfnReserved2 = */ NULL,
913	/* .pfnReserved3 = */ NULL,
914	/* .pfnReserved4 = */ NULL,
915	/* .pfnReserved5 = */ NULL,
916	/* .pfnReserved6 = */ NULL,
917	/* .pfnReserved7 = */ NULL,
918	#elif defined(IN_RING0)
919	/* .pfnEarlyConstruct = */ NULL,
920	/* .pfnConstruct = */ iommuAmdRZConstruct,
921	/* .pfnDestruct = */ NULL,
922	/* .pfnFinalDestruct = */ NULL,
923	/* .pfnRequest = */ NULL,
924	/* .pfnReserved0 = */ NULL,
925	/* .pfnReserved1 = */ NULL,
926	/* .pfnReserved2 = */ NULL,
927	/* .pfnReserved3 = */ NULL,
928	/* .pfnReserved4 = */ NULL,
929	/* .pfnReserved5 = */ NULL,
930	/* .pfnReserved6 = */ NULL,
931	/* .pfnReserved7 = */ NULL,
932	#elif defined(IN_RC)
933	/* .pfnConstruct = */ iommuAmdRZConstruct,
934	/* .pfnReserved0 = */ NULL,
935	/* .pfnReserved1 = */ NULL,
936	/* .pfnReserved2 = */ NULL,
937	/* .pfnReserved3 = */ NULL,
938	/* .pfnReserved4 = */ NULL,
939	/* .pfnReserved5 = */ NULL,
940	/* .pfnReserved6 = */ NULL,
941	/* .pfnReserved7 = */ NULL,
942	#else
943	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
944	#endif
945	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
946	};
947
948	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
949

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 83263

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