VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 87881

Last change on this file since 87881 was 87881, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Fix MemoryAccess Read/Write stats (was incorrectly swapped)
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1/* $Id: DevIommuAmd.cpp 87881 2021-02-26 05:09:24Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/string.h>
30#include <iprt/avl.h>
31#ifdef IN_RING3
32# include <iprt/mem.h>
33#endif
34
35#include "VBoxDD.h"
36#include "DevIommuAmd.h"
37
38
39/*********************************************************************************************************************************
40* Defined Constants And Macros *
41*********************************************************************************************************************************/
42/** Release log prefix string. */
43#define IOMMU_LOG_PFX "AMD-IOMMU"
44/** The current saved state version. */
45#define IOMMU_SAVED_STATE_VERSION 1
46/** The IOMMU device instance magic. */
47#define IOMMU_MAGIC 0x10acce55
48
49/** Enable the IOTLBE cache only in ring-3 for now, see @bugref{9654#c95}. */
50#ifdef IN_RING3
51# define IOMMU_WITH_IOTLBE_CACHE
52#endif
53/** Enable the interrupt cache. */
54#define IOMMU_WITH_IRTE_CACHE
55
56/* The DTE cache is mandatory for the IOTLB or interrupt cache to work. */
57#if defined(IOMMU_WITH_IOTLBE_CACHE) || defined(IOMMU_WITH_IRTE_CACHE)
58# define IOMMU_WITH_DTE_CACHE
59/** The maximum number of device IDs in the cache. */
60# define IOMMU_DEV_CACHE_COUNT 16
61/** An empty device ID. */
62# define IOMMU_DTE_CACHE_KEY_NIL 0
63#endif
64
65#ifdef IOMMU_WITH_IRTE_CACHE
66/** The maximum number of IRTE cache entries. */
67# define IOMMU_IRTE_CACHE_COUNT 32
68/** A NIL IRTE cache entry key. */
69# define IOMMU_IRTE_CACHE_KEY_NIL (~(uint32_t)0U)
70/** Gets the device ID from an IRTE cache entry key. */
71#define IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(a_Key) RT_HIWORD(a_Key)
72/** Gets the IOVA from the IOTLB entry key. */
73# define IOMMU_IRTE_CACHE_KEY_GET_OFF(a_Key) RT_LOWORD(a_Key)
74/** Makes an IRTE cache entry key.
75 *
76 * Bits 31:16 is the device ID (Bus, Device, Function).
77 * Bits 15:0 is the the offset into the IRTE table.
78 */
79# define IOMMU_IRTE_CACHE_KEY_MAKE(a_DevId, a_off) RT_MAKE_U32(a_off, a_DevId)
80#endif /* IOMMU_WITH_IRTE_CACHE */
81
82#ifdef IOMMU_WITH_IOTLBE_CACHE
83/** The maximum number of IOTLB entries. */
84# define IOMMU_IOTLBE_MAX 96
85/** The mask of bits covering the domain ID in the IOTLBE key. */
86# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
87/** The mask of bits covering the IOVA in the IOTLBE key. */
88# define IOMMU_IOTLB_IOVA_MASK (~IOMMU_IOTLB_DOMAIN_ID_MASK)
89/** The number of bits to shift for the domain ID of the IOTLBE key. */
90# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
91/** A NIL IOTLB key. */
92# define IOMMU_IOTLB_KEY_NIL UINT64_C(0)
93/** Gets the domain ID from an IOTLB entry key. */
94# define IOMMU_IOTLB_KEY_GET_DOMAIN_ID(a_Key) ((a_Key) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT)
95/** Gets the IOVA from the IOTLB entry key. */
96# define IOMMU_IOTLB_KEY_GET_IOVA(a_Key) (((a_Key) & IOMMU_IOTLB_IOVA_MASK) << X86_PAGE_4K_SHIFT)
97/** Makes an IOTLB entry key.
98 *
99 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
100 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
101 * so bottom 12 bits are free.
102 *
103 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
104 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
105 */
106# define IOMMU_IOTLB_KEY_MAKE(a_DomainId, a_uIova) ( ((uint64_t)(a_DomainId) << IOMMU_IOTLB_DOMAIN_ID_SHIFT) \
107 | (((a_uIova) >> X86_PAGE_4K_SHIFT) & IOMMU_IOTLB_IOVA_MASK))
108#endif /* IOMMU_WITH_IOTLBE_CACHE */
109
110#ifdef IOMMU_WITH_DTE_CACHE
111/** @name IOMMU_DTE_CACHE_F_XXX: DTE cache flags.
112 *
113 * Some of these flags are "basic" i.e. they correspond directly to their bits in
114 * the DTE. The rest of the flags are based on checks or operations on several DTE
115 * bits.
116 *
117 * The basic flags are:
118 * - VALID (DTE.V)
119 * - IO_PERM_READ (DTE.IR)
120 * - IO_PERM_WRITE (DTE.IW)
121 * - IO_PERM_RSVD (bit following DTW.IW reserved for future & to keep
122 * masking consistent)
123 * - SUPPRESS_ALL_IOPF (DTE.SA)
124 * - SUPPRESS_IOPF (DTE.SE)
125 * - INTR_MAP_VALID (DTE.IV)
126 * - IGNORE_UNMAPPED_INTR (DTE.IG)
127 *
128 * @see iommuAmdGetBasicDevFlags()
129 * @{ */
130/** The DTE is present. */
131# define IOMMU_DTE_CACHE_F_PRESENT RT_BIT(0)
132/** The DTE is valid. */
133# define IOMMU_DTE_CACHE_F_VALID RT_BIT(1)
134/** The DTE permissions apply for address translations. */
135# define IOMMU_DTE_CACHE_F_IO_PERM RT_BIT(2)
136/** DTE permission - I/O read allowed. */
137# define IOMMU_DTE_CACHE_F_IO_PERM_READ RT_BIT(3)
138/** DTE permission - I/O write allowed. */
139# define IOMMU_DTE_CACHE_F_IO_PERM_WRITE RT_BIT(4)
140/** DTE permission - reserved. */
141# define IOMMU_DTE_CACHE_F_IO_PERM_RSVD RT_BIT(5)
142/** Address translation required. */
143# define IOMMU_DTE_CACHE_F_ADDR_TRANSLATE RT_BIT(6)
144/** Suppress all I/O page faults. */
145# define IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF RT_BIT(7)
146/** Suppress I/O page faults. */
147# define IOMMU_DTE_CACHE_F_SUPPRESS_IOPF RT_BIT(8)
148/** Interrupt map valid. */
149# define IOMMU_DTE_CACHE_F_INTR_MAP_VALID RT_BIT(9)
150/** Ignore unmapped interrupts. */
151# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR RT_BIT(10)
152/** An I/O page fault has been raised for this device. */
153# define IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED RT_BIT(11)
154/** Fixed and arbitrary interrupt control: Target Abort. */
155# define IOMMU_DTE_CACHE_F_INTR_CTRL_TARGET_ABORT RT_BIT(12)
156/** Fixed and arbitrary interrupt control: Forward unmapped. */
157# define IOMMU_DTE_CACHE_F_INTR_CTRL_FWD_UNMAPPED RT_BIT(13)
158/** Fixed and arbitrary interrupt control: Remapped. */
159# define IOMMU_DTE_CACHE_F_INTR_CTRL_REMAPPED RT_BIT(14)
160/** Fixed and arbitrary interrupt control: Reserved. */
161# define IOMMU_DTE_CACHE_F_INTR_CTRL_RSVD RT_BIT(15)
162/** @} */
163
164/** The number of bits to shift I/O device flags for DTE permissions. */
165# define IOMMU_DTE_CACHE_F_IO_PERM_SHIFT 3
166/** The mask of DTE permissions in I/O device flags. */
167# define IOMMU_DTE_CACHE_F_IO_PERM_MASK 0x3
168/** The number of bits to shift I/O device flags for interrupt control bits. */
169# define IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT 12
170/** The mask of interrupt control bits in I/O device flags. */
171# define IOMMU_DTE_CACHE_F_INTR_CTRL_MASK 0x3
172/** The number of bits to shift for ignore-unmapped interrupts bit. */
173# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR_SHIFT 10
174
175/** Acquires the cache lock. */
176# define IOMMU_LOCK_CACHE(a_pDevIns, a_pThis) \
177 do { \
178 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_SEM_BUSY); \
179 if (rcLock == VINF_SUCCESS) \
180 { /* likely */ } \
181 else \
182 { \
183 AssertRC(rcLock); \
184 return rcLock; \
185 } \
186 } while (0)
187
188/** Acquires the cache lock (asserts on failure). */
189# define IOMMU_LOCK_CACHE_NORET(a_pDevIns, a_pThis) \
190 do { \
191 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_SEM_BUSY); \
192 AssertRC(rcLock); \
193 } while (0)
194
195/** Releases the cache lock. */
196# define IOMMU_UNLOCK_CACHE(a_pDevIns, a_pThis) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSectCache)
197#endif /* IOMMU_WITH_DTE_CACHE */
198
199/** Gets the page offset mask given the number of bits to shift. */
200#define IOMMU_GET_PAGE_OFF_MASK(a_cShift) (~(UINT64_C(0xffffffffffffffff) << (a_cShift)))
201
202/** Acquires the PDM lock. */
203#define IOMMU_LOCK(a_pDevIns, a_pThisCC) \
204 do { \
205 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_SEM_BUSY); \
206 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
207 { /* likely */ } \
208 else \
209 return rcLock; \
210 } while (0)
211
212/** Acquires the PDM lock (asserts on failure). */
213#define IOMMU_LOCK_NORET(a_pDevIns, a_pThisCC) \
214 do { \
215 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_SEM_BUSY); \
216 AssertRC(rcLock); \
217 } while (0)
218
219/** Releases the PDM lock. */
220# define IOMMU_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock((a_pDevIns))
221
222
223/*********************************************************************************************************************************
224* Structures and Typedefs *
225*********************************************************************************************************************************/
226/**
227 * IOMMU operation (transaction).
228 */
229typedef enum IOMMUOP
230{
231 /** Address translation request. */
232 IOMMUOP_TRANSLATE_REQ = 0,
233 /** Memory read request. */
234 IOMMUOP_MEM_READ,
235 /** Memory write request. */
236 IOMMUOP_MEM_WRITE,
237 /** Interrupt request. */
238 IOMMUOP_INTR_REQ,
239 /** Command. */
240 IOMMUOP_CMD
241} IOMMUOP;
242/** Pointer to a IOMMU operation. */
243typedef IOMMUOP *PIOMMUOP;
244
245/**
246 * I/O page lookup.
247 */
248typedef struct IOPAGELOOKUP
249{
250 /** The translated system physical address. */
251 RTGCPHYS GCPhysSpa;
252 /** The number of offset bits in the system physical address. */
253 uint8_t cShift;
254 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
255 uint8_t fPerm;
256} IOPAGELOOKUP;
257/** Pointer to an I/O page lookup. */
258typedef IOPAGELOOKUP *PIOPAGELOOKUP;
259/** Pointer to a const I/O page lookup. */
260typedef IOPAGELOOKUP const *PCIOPAGELOOKUP;
261
262/**
263 * I/O address range.
264 */
265typedef struct IOADDRRANGE
266{
267 /** The address (virtual or physical). */
268 uint64_t uAddr;
269 /** The size of the access in bytes. */
270 size_t cb;
271 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
272 uint8_t fPerm;
273} IOADDRRANGE;
274/** Pointer to an I/O address range. */
275typedef IOADDRRANGE *PIOADDRRANGE;
276/** Pointer to a const I/O address range. */
277typedef IOADDRRANGE const *PCIOADDRRANGE;
278
279#ifdef IOMMU_WITH_DTE_CACHE
280/**
281 * Device Table Entry Cache.
282 */
283typedef struct DTECACHE
284{
285 /** This device's flags, see IOMMU_DTE_CACHE_F_XXX. */
286 uint16_t fFlags;
287 /** The domain ID assigned for this device by software. */
288 uint16_t uDomainId;
289} DTECACHE;
290/** Pointer to an I/O device struct. */
291typedef DTECACHE *PDTECACHE;
292/** Pointer to a const I/O device struct. */
293typedef DTECACHE *PCDTECACHE;
294AssertCompileSize(DTECACHE, 4);
295#endif /* IOMMU_WITH_DTE_CACHE */
296
297#ifdef IOMMU_WITH_IOTLBE_CACHE
298/**
299 * I/O TLB Entry.
300 * Keep this as small and aligned as possible.
301 */
302typedef struct IOTLBE
303{
304 /** The AVL tree node. */
305 AVLU64NODECORE Core;
306 /** The least recently used (LRU) list node. */
307 RTLISTNODE NdLru;
308 /** The I/O page lookup results of the translation. */
309 IOPAGELOOKUP PageLookup;
310 /** Whether the entry needs to be evicted from the cache. */
311 bool fEvictPending;
312} IOTLBE;
313/** Pointer to an IOMMU I/O TLB entry struct. */
314typedef IOTLBE *PIOTLBE;
315/** Pointer to a const IOMMU I/O TLB entry struct. */
316typedef IOTLBE const *PCIOTLBE;
317AssertCompileSizeAlignment(IOTLBE, 8);
318AssertCompileMemberOffset(IOTLBE, Core, 0);
319#endif /* IOMMU_WITH_IOTLBE_CACHE */
320
321#ifdef IOMMU_WITH_IRTE_CACHE
322/**
323 * Interrupt Remap Table Entry Cache.
324 */
325typedef struct IRTECACHE
326{
327 /** The key, see IOMMU_IRTE_CACHE_KEY_MAKE. */
328 uint32_t uKey;
329 /** The IRTE. */
330 IRTE_T Irte;
331} IRTECACHE;
332/** Pointer to an IRTE cache struct. */
333typedef IRTECACHE *PIRTECACHE;
334/** Pointer to a const IRTE cache struct. */
335typedef IRTECACHE const *PCIRTECACHE;
336AssertCompileSizeAlignment(IRTECACHE, 4);
337#endif /* IOMMU_WITH_IRTE_CACHE */
338
339/**
340 * The shared IOMMU device state.
341 */
342typedef struct IOMMU
343{
344 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
345 uint32_t idxIommu;
346 /** IOMMU magic. */
347 uint32_t u32Magic;
348
349 /** The MMIO handle. */
350 IOMMMIOHANDLE hMmio;
351 /** The event semaphore the command thread waits on. */
352 SUPSEMEVENT hEvtCmdThread;
353 /** Whether the command thread has been signaled for wake up. */
354 bool volatile fCmdThreadSignaled;
355 /** Padding. */
356 bool afPadding0[7];
357
358#ifdef IOMMU_WITH_DTE_CACHE
359 /** The critsect that protects the cache from concurrent access. */
360 PDMCRITSECT CritSectCache;
361 /** Array of device IDs. */
362 uint16_t aDeviceIds[IOMMU_DEV_CACHE_COUNT];
363 /** Array of DTE cache entries. */
364 DTECACHE aDteCache[IOMMU_DEV_CACHE_COUNT];
365#endif
366#ifdef IOMMU_WITH_IRTE_CACHE
367 /** Array of IRTE cache entries. */
368 IRTECACHE aIrteCache[IOMMU_IRTE_CACHE_COUNT];
369#endif
370
371 /** @name PCI: Base capability block registers.
372 * @{ */
373 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
374 /** @} */
375
376 /** @name MMIO: Control and status registers.
377 * @{ */
378 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
379 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
380 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
381 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
382 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
383 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
384 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
385 /** @} */
386
387 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
388 * @{ */
389 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
390 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
391 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
392 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
393 /** @} */
394
395 /** @todo IOMMU: SMI filter. */
396
397 /** @name MMIO: Guest Virtual-APIC Log registers.
398 * @{ */
399 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
400 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
401 /** @} */
402
403 /** @name MMIO: Alternate PPR and Event Log registers.
404 * @{ */
405 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
406 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
407 /** @} */
408
409 /** @name MMIO: Device-specific feature registers.
410 * @{ */
411 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
412 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
413 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
414 /** @} */
415
416 /** @name MMIO: MSI Capability Block registers.
417 * @{ */
418 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
419 /** @} */
420
421 /** @name MMIO: Performance Optimization Control registers.
422 * @{ */
423 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
424 /** @} */
425
426 /** @name MMIO: x2APIC Control registers.
427 * @{ */
428 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
429 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
430 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
431 /** @} */
432
433 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
434 * @{ */
435 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
436 /** @} */
437
438 /** @name MMIO: Reserved register.
439 * @{ */
440 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
441 /** @} */
442
443 /** @name MMIO: Command and Event Log pointer registers.
444 * @{ */
445 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
446 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
447 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
448 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
449 /** @} */
450
451 /** @name MMIO: Command and Event Status register.
452 * @{ */
453 IOMMU_STATUS_T Status; /**< IOMMU status register. */
454 /** @} */
455
456 /** @name MMIO: PPR Log Head and Tail pointer registers.
457 * @{ */
458 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
459 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
460 /** @} */
461
462 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
463 * @{ */
464 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
465 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
466 /** @} */
467
468 /** @name MMIO: PPR Log B Head and Tail pointer registers.
469 * @{ */
470 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
471 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
472 /** @} */
473
474 /** @name MMIO: Event Log B Head and Tail pointer registers.
475 * @{ */
476 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
477 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
478 /** @} */
479
480 /** @name MMIO: PPR Log Overflow protection registers.
481 * @{ */
482 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
483 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
484 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
485 /** @} */
486
487 /** @todo IOMMU: IOMMU Event counter registers. */
488
489#ifdef VBOX_WITH_STATISTICS
490 /** @name IOMMU: Stat counters.
491 * @{ */
492 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
493 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
494 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
495 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
496
497 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
498 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
499
500 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
501 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
502 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
503 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
504
505 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
506 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
507 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
508 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
509
510 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
511 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
512 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
513 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
514 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
515 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
516 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
517 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
518 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
519
520 STAMCOUNTER StatIotlbeCached; /**< Number of IOTLB entries in the cache. */
521 STAMCOUNTER StatIotlbeLazyEvictReuse; /**< Number of IOTLB entries re-used after lazy eviction. */
522
523 STAMPROFILEADV StatProfDteLookup; /**< Profiling of I/O page walk (from memory). */
524 STAMPROFILEADV StatProfIotlbeLookup; /**< Profiling of IOTLB entry lookup (from cache). */
525
526 STAMPROFILEADV StatProfIrteLookup; /**< Profiling of IRTE entry lookup (from memory). */
527 STAMPROFILEADV StatProfIrteCacheLookup; /**< Profiling of IRTE entry lookup (from cache). */
528
529 STAMCOUNTER StatAccessCacheHit; /**< Number of IOTLB cache hits. */
530 STAMCOUNTER StatAccessCacheHitFull; /**< Number of accesses that were fully looked up from the cache. */
531 STAMCOUNTER StatAccessCacheMiss; /**< Number of cache misses (resulting in DTE lookups). */
532 STAMCOUNTER StatAccessCacheNonContig; /**< Number of cache accesses resulting in non-contiguous access. */
533 STAMCOUNTER StatAccessCachePermDenied; /**< Number of cache accesses resulting in insufficient permissions. */
534 STAMCOUNTER StatAccessDteNonContig; /**< Number of DTE accesses resulting in non-contiguous access. */
535 STAMCOUNTER StatAccessDtePermDenied; /**< Number of DTE accesses resulting in insufficient permissions. */
536
537 STAMCOUNTER StatIntrCacheHit; /**< Number of interrupt cache hits. */
538 STAMCOUNTER StatIntrCacheMiss; /**< Number of interrupt cache misses. */
539 /** @} */
540#endif
541} IOMMU;
542/** Pointer to the IOMMU device state. */
543typedef IOMMU *PIOMMU;
544/** Pointer to the const IOMMU device state. */
545typedef const IOMMU *PCIOMMU;
546AssertCompileMemberAlignment(IOMMU, hMmio, 8);
547#ifdef IOMMU_WITH_DTE_CACHE
548AssertCompileMemberAlignment(IOMMU, CritSectCache, 8);
549AssertCompileMemberAlignment(IOMMU, aDeviceIds, 8);
550AssertCompileMemberAlignment(IOMMU, aDteCache, 8);
551#endif
552#ifdef IOMMU_WITH_IRTE_CACHE
553AssertCompileMemberAlignment(IOMMU, aIrteCache, 8);
554#endif
555AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
556AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
557AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
558AssertCompileMemberAlignment(IOMMU, Status, 8);
559
560/**
561 * The ring-3 IOMMU device state.
562 */
563typedef struct IOMMUR3
564{
565 /** Device instance. */
566 PPDMDEVINSR3 pDevInsR3;
567 /** The IOMMU helpers. */
568 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
569 /** The command thread handle. */
570 R3PTRTYPE(PPDMTHREAD) pCmdThread;
571#ifdef IOMMU_WITH_IOTLBE_CACHE
572 /** Pointer to array of pre-allocated IOTLBEs. */
573 PIOTLBE paIotlbes;
574 /** Maps [DomainId,Iova] to [IOTLBE]. */
575 AVLU64TREE TreeIotlbe;
576 /** LRU list anchor for IOTLB entries. */
577 RTLISTANCHOR LstLruIotlbe;
578 /** Index of the next unused IOTLB. */
579 uint32_t idxUnusedIotlbe;
580 /** Number of cached IOTLB entries in the tree. */
581 uint32_t cCachedIotlbes;
582#endif
583} IOMMUR3;
584/** Pointer to the ring-3 IOMMU device state. */
585typedef IOMMUR3 *PIOMMUR3;
586/** Pointer to the const ring-3 IOMMU device state. */
587typedef const IOMMUR3 *PCIOMMUR3;
588#ifdef IOMMU_WITH_IOTLBE_CACHE
589AssertCompileMemberAlignment(IOMMUR3, paIotlbes, 8);
590AssertCompileMemberAlignment(IOMMUR3, TreeIotlbe, 8);
591AssertCompileMemberAlignment(IOMMUR3, LstLruIotlbe, 8);
592#endif
593
594/**
595 * The ring-0 IOMMU device state.
596 */
597typedef struct IOMMUR0
598{
599 /** Device instance. */
600 PPDMDEVINSR0 pDevInsR0;
601 /** The IOMMU helpers. */
602 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
603} IOMMUR0;
604/** Pointer to the ring-0 IOMMU device state. */
605typedef IOMMUR0 *PIOMMUR0;
606
607/**
608 * The raw-mode IOMMU device state.
609 */
610typedef struct IOMMURC
611{
612 /** Device instance. */
613 PPDMDEVINSRC pDevInsRC;
614 /** The IOMMU helpers. */
615 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
616} IOMMURC;
617/** Pointer to the raw-mode IOMMU device state. */
618typedef IOMMURC *PIOMMURC;
619
620/** The IOMMU device state for the current context. */
621typedef CTX_SUFF(IOMMU) IOMMUCC;
622/** Pointer to the IOMMU device state for the current context. */
623typedef CTX_SUFF(PIOMMU) PIOMMUCC;
624
625/**
626 * IOMMU register access.
627 */
628typedef struct IOMMUREGACC
629{
630 const char *pszName;
631 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
632 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
633} IOMMUREGACC;
634/** Pointer to an IOMMU register access. */
635typedef IOMMUREGACC *PIOMMUREGACC;
636/** Pointer to a const IOMMU register access. */
637typedef IOMMUREGACC const *PCIOMMUREGACC;
638
639#ifdef IOMMU_WITH_IOTLBE_CACHE
640/**
641 * IOTLBE flush argument.
642 */
643typedef struct IOTLBEFLUSHARG
644{
645 /** The ring-3 IOMMU device state. */
646 PIOMMUR3 pIommuR3;
647 /** The domain ID to flush. */
648 uint16_t uDomainId;
649} IOTLBEFLUSHARG;
650/** Pointer to an IOTLBE flush argument. */
651typedef IOTLBEFLUSHARG *PIOTLBEFLUSHARG;
652/** Pointer to a const IOTLBE flush argument. */
653typedef IOTLBEFLUSHARG const *PCIOTLBEFLUSHARG;
654
655/**
656 * IOTLBE Info. argument.
657 */
658typedef struct IOTLBEINFOARG
659{
660 /** The ring-3 IOMMU device state. */
661 PIOMMUR3 pIommuR3;
662 /** The info helper. */
663 PCDBGFINFOHLP pHlp;
664 /** The domain ID to dump IOTLB entry. */
665 uint16_t uDomainId;
666} IOTLBEINFOARG;
667/** Pointer to an IOTLBE flush argument. */
668typedef IOTLBEINFOARG *PIOTLBEINFOARG;
669/** Pointer to a const IOTLBE flush argument. */
670typedef IOTLBEINFOARG const *PCIOTLBEINFOARG;
671#endif
672
673/**
674 * IOMMU operation auxiliary info.
675 */
676typedef struct IOMMUOPAUX
677{
678 /** The IOMMU operation being performed. */
679 IOMMUOP enmOp;
680 /** The device table entry (can be NULL). */
681 PCDTE_T pDte;
682 /** The device ID. */
683 uint16_t uDeviceId;
684 /** The domain ID (when the DTE isn't provided). */
685 uint16_t uDomainId;
686} IOMMUOPAUX;
687/** Pointer to an I/O address lookup struct. */
688typedef IOMMUOPAUX *PIOMMUOPAUX;
689/** Pointer to a const I/O address lookup struct. */
690typedef IOMMUOPAUX const *PCIOMMUOPAUX;
691
692typedef DECLCALLBACKTYPE(int, FNIOPAGELOOKUP,(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
693 PIOPAGELOOKUP pPageLookup));
694typedef FNIOPAGELOOKUP *PFNIOPAGELOOKUP;
695
696
697/*********************************************************************************************************************************
698* Global Variables *
699*********************************************************************************************************************************/
700/**
701 * An array of the number of device table segments supported.
702 * Indexed by u2DevTabSegSup.
703 */
704static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
705
706/**
707 * An array of the masks to select the device table segment index from a device ID.
708 */
709static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
710
711/**
712 * An array of the shift values to select the device table segment index from a
713 * device ID.
714 */
715static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
716
717/**
718 * The maximum size (inclusive) of each device table segment (0 to 7).
719 * Indexed by the device table segment index.
720 */
721static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
722
723/**
724 * The IOMMU I/O permission names.
725 */
726static const char * const g_aszPerm[] = { "none", "read", "write", "read+write" };
727
728
729#ifndef VBOX_DEVICE_STRUCT_TESTCASE
730/**
731 * Gets the maximum number of buffer entries for the given buffer length.
732 *
733 * @returns Number of buffer entries.
734 * @param uEncodedLen The length (power-of-2 encoded).
735 */
736DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
737{
738 Assert(uEncodedLen > 7);
739 Assert(uEncodedLen < 16);
740 return 2 << (uEncodedLen - 1);
741}
742
743
744/**
745 * Gets the total length of the buffer given a base register's encoded length.
746 *
747 * @returns The length of the buffer in bytes.
748 * @param uEncodedLen The length (power-of-2 encoded).
749 */
750DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
751{
752 Assert(uEncodedLen > 7);
753 Assert(uEncodedLen < 16);
754 return (2 << (uEncodedLen - 1)) << 4;
755}
756
757
758/**
759 * Gets the number of (unconsumed) entries in the event log.
760 *
761 * @returns The number of entries in the event log.
762 * @param pThis The shared IOMMU device state.
763 */
764static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
765{
766 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
767 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
768 if (idxTail >= idxHead)
769 return idxTail - idxHead;
770
771 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
772 return cMaxEvts - idxHead + idxTail;
773}
774
775
776/**
777 * Gets the descriptive I/O permission name for a memory access.
778 *
779 * @returns The I/O permission name.
780 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
781 */
782static const char *iommuAmdMemAccessGetPermName(uint8_t fPerm)
783{
784 /* We shouldn't construct an access with "none" or "read+write" (must be read or write) permissions. */
785 Assert(fPerm > 0 && fPerm < RT_ELEMENTS(g_aszPerm));
786 return g_aszPerm[fPerm & IOMMU_IO_PERM_MASK];
787}
788
789
790/**
791 * Checks whether two consecutive I/O page lookup results translates to a physically
792 * contiguous region.
793 *
794 * @returns @c true if they are contiguous, @c false otherwise.
795 * @param pPageLookupPrev The I/O page lookup result of the previous page.
796 * @param pPageLookup The I/O page lookup result of the current page.
797 */
798static bool iommuAmdLookupIsAccessContig(PCIOPAGELOOKUP pPageLookupPrev, PCIOPAGELOOKUP pPageLookup)
799{
800 Assert(pPageLookupPrev->fPerm == pPageLookup->fPerm);
801 size_t const cbPrev = RT_BIT_64(pPageLookupPrev->cShift);
802 RTGCPHYS const GCPhysPrev = pPageLookupPrev->GCPhysSpa;
803 RTGCPHYS const GCPhys = pPageLookup->GCPhysSpa;
804 uint64_t const offMaskPrev = IOMMU_GET_PAGE_OFF_MASK(pPageLookupPrev->cShift);
805 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(pPageLookup->cShift);
806
807 /* Paranoia: Ensure offset bits are 0. */
808 Assert(!(GCPhysPrev & offMaskPrev));
809 Assert(!(GCPhys & offMask));
810
811 if ((GCPhysPrev & ~offMaskPrev) + cbPrev == (GCPhys & ~offMask))
812 return true;
813 return false;
814}
815
816
817/**
818 * Gets the basic I/O device flags for the given device table entry.
819 *
820 * @returns The basic I/O device flags.
821 * @param pDte The device table entry.
822 */
823static uint16_t iommuAmdGetBasicDevFlags(PCDTE_T pDte)
824{
825 /* Extract basic flags from bits 127:0 of the DTE. */
826 uint16_t fFlags = 0;
827 if (pDte->n.u1Valid)
828 {
829 fFlags |= IOMMU_DTE_CACHE_F_VALID;
830
831 /** @todo Skip the if checks here (shift/mask the relevant bits over). */
832 if (pDte->n.u1SuppressAllPfEvents)
833 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
834 if (pDte->n.u1SuppressPfEvents)
835 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_IOPF;
836
837 uint16_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
838 AssertCompile(IOMMU_DTE_CACHE_F_IO_PERM_MASK == IOMMU_IO_PERM_MASK);
839 fFlags |= fDtePerm << IOMMU_DTE_CACHE_F_IO_PERM_SHIFT;
840 }
841
842 /* Extract basic flags from bits 255:128 of the DTE. */
843 if (pDte->n.u1IntrMapValid)
844 {
845 fFlags |= IOMMU_DTE_CACHE_F_INTR_MAP_VALID;
846
847 /** @todo Skip the if check here (shift/mask the relevant bit over). */
848 if (pDte->n.u1IgnoreUnmappedIntrs)
849 fFlags |= IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
850
851 uint16_t const fIntrCtrl = IOMMU_DTE_GET_INTR_CTRL(pDte);
852 AssertCompile(IOMMU_DTE_CACHE_F_INTR_CTRL_MASK == IOMMU_DTE_INTR_CTRL_MASK);
853 fFlags |= fIntrCtrl << IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT;
854 }
855 return fFlags;
856}
857
858
859/**
860 * Remaps the source MSI to the destination MSI given the IRTE.
861 *
862 * @param pMsiIn The source MSI.
863 * @param pMsiOut Where to store the remapped MSI.
864 * @param pIrte The IRTE used for the remapping.
865 */
866static void iommuAmdIrteRemapMsi(PCMSIMSG pMsiIn, PMSIMSG pMsiOut, PCIRTE_T pIrte)
867{
868 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
869 *pMsiOut = *pMsiIn;
870
871 pMsiOut->Addr.n.u1DestMode = pIrte->n.u1DestMode;
872 pMsiOut->Addr.n.u8DestId = pIrte->n.u8Dest;
873
874 pMsiOut->Data.n.u8Vector = pIrte->n.u8Vector;
875 pMsiOut->Data.n.u3DeliveryMode = pIrte->n.u3IntrType;
876}
877
878
879#ifdef IOMMU_WITH_DTE_CACHE
880/**
881 * Looks up an entry in the DTE cache for the given device ID.
882 *
883 * @returns The index of the entry, or the cache capacity if no entry was found.
884 * @param pThis The shared IOMMU device state.
885 * @param uDevId The device ID (bus, device, function).
886 */
887DECLINLINE(uint16_t) iommuAmdDteCacheEntryLookup(PIOMMU pThis, uint16_t uDevId)
888{
889 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
890 for (uint16_t i = 0; i < cDeviceIds; i++)
891 {
892 if (pThis->aDeviceIds[i] == uDevId)
893 return i;
894 }
895 return cDeviceIds;
896}
897
898
899/**
900 * Gets an free/unused DTE cache entry.
901 *
902 * @returns The index of an unused entry, or cache capacity if the cache is full.
903 * @param pThis The shared IOMMU device state.
904 */
905DECLINLINE(uint16_t) iommuAmdDteCacheEntryGetUnused(PCIOMMU pThis)
906{
907 /*
908 * ASSUMES device ID 0 is the PCI host bridge or the IOMMU itself
909 * (the latter being an ugly hack) and cannot be a valid device ID.
910 */
911 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
912 for (uint16_t i = 0; i < cDeviceIds; i++)
913 {
914 if (!pThis->aDeviceIds[i])
915 return i;
916 }
917 return cDeviceIds;
918}
919
920
921/**
922 * Adds or updates the I/O device flags for the given device ID.
923 *
924 * @returns VBox status code.
925 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
926 *
927 * @param pDevIns The IOMMU instance data.
928 * @param uDevId The device ID (bus, device, function).
929 * @param pDte The device table entry.
930 * @param fOrMask The device flags (usually compound flags) to OR in with the
931 * basic flags, see IOMMU_DTE_CACHE_F_XXX.
932 */
933static int iommuAmdDteCacheAdd(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, uint16_t fOrMask)
934{
935 Assert(pDte);
936 Assert(uDevId);
937
938 int rc = VINF_SUCCESS;
939 uint16_t const fFlags = iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT | fOrMask;
940 uint16_t const uDomainId = pDte->n.u16DomainId;
941
942 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
943 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
944
945 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
946 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, uDevId);
947 if (idxDte < cDteCache)
948 {
949 pThis->aDteCache[idxDte].fFlags = fFlags;
950 pThis->aDteCache[idxDte].uDomainId = uDomainId;
951 }
952 else if ((idxDte = iommuAmdDteCacheEntryGetUnused(pThis)) < cDteCache)
953 {
954 pThis->aDeviceIds[idxDte] = uDevId;
955 pThis->aDteCache[idxDte].fFlags = fFlags;
956 pThis->aDteCache[idxDte].uDomainId = uDomainId;
957 }
958 else
959 rc = VERR_OUT_OF_RESOURCES;
960
961 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
962 return rc;
963}
964
965
966/**
967 * Adds one or more I/O device flags if the device is already present in the cache.
968 *
969 * @param pDevIns The IOMMU instance data.
970 * @param uDevId The device ID (bus, device, function).
971 * @param fFlags Additional device flags to OR with existing flags, see
972 * IOMMU_DTE_CACHE_F_XXX.
973 */
974static void iommuAmdDteCacheAddFlags(PPDMDEVINS pDevIns, uint16_t uDevId, uint16_t fFlags)
975{
976 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
977 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
978
979 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
980 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, uDevId);
981 if ( idxDte < cDteCache
982 && (pThis->aDteCache[idxDte].fFlags & IOMMU_DTE_CACHE_F_PRESENT))
983 pThis->aDteCache[idxDte].fFlags |= fFlags;
984
985 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
986}
987
988
989/**
990 * Removes a DTE cache entry.
991 *
992 * @param pDevIns The IOMMU instance data.
993 * @param uDevId The device ID to remove cache entries for.
994 */
995static void iommuAmdDteCacheRemove(PPDMDEVINS pDevIns, uint16_t uDevId)
996{
997 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
998 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
999
1000 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
1001 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, uDevId);
1002 if (idxDte < cDteCache)
1003 {
1004 pThis->aDteCache[idxDte].fFlags = 0;
1005 pThis->aDteCache[idxDte].uDomainId = 0;
1006 }
1007
1008 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1009}
1010
1011
1012/**
1013 * Removes all entries in the device table entry cache.
1014 *
1015 * @param pDevIns The IOMMU instance data.
1016 */
1017static void iommuAmdDteCacheRemoveAll(PPDMDEVINS pDevIns)
1018{
1019 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1020 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1021 RT_ZERO(pThis->aDeviceIds);
1022 RT_ZERO(pThis->aDteCache);
1023 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1024}
1025#endif /* IOMMU_WITH_DTE_CACHE */
1026
1027
1028#ifdef IOMMU_WITH_IOTLBE_CACHE
1029/**
1030 * Moves the IOTLB entry to the least recently used slot.
1031 *
1032 * @param pThisR3 The ring-3 IOMMU device state.
1033 * @param pIotlbe The IOTLB entry to move.
1034 */
1035static void iommuAmdIotlbEntryMoveToLru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1036{
1037 if (!RTListNodeIsFirst(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1038 {
1039 RTListNodeRemove(&pIotlbe->NdLru);
1040 RTListPrepend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1041 }
1042}
1043
1044
1045/**
1046 * Moves the IOTLB entry to the most recently used slot.
1047 *
1048 * @param pThisR3 The ring-3 IOMMU device state.
1049 * @param pIotlbe The IOTLB entry to move.
1050 */
1051DECLINLINE(void) iommuAmdIotlbEntryMoveToMru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1052{
1053 if (!RTListNodeIsLast(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1054 {
1055 RTListNodeRemove(&pIotlbe->NdLru);
1056 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1057 }
1058}
1059
1060
1061# ifdef IN_RING3
1062/**
1063 * Dumps the IOTLB entry via the debug info helper.
1064 *
1065 * @returns VINF_SUCCESS.
1066 * @param pNode Pointer to an IOTLB entry to dump info.
1067 * @param pvUser Pointer to an IOTLBEINFOARG.
1068 */
1069static DECLCALLBACK(int) iommuAmdR3IotlbEntryInfo(PAVLU64NODECORE pNode, void *pvUser)
1070{
1071 /* Validate. */
1072 PCIOTLBEINFOARG pArgs = (PCIOTLBEINFOARG)pvUser;
1073 AssertPtr(pArgs);
1074 AssertPtr(pArgs->pIommuR3);
1075 AssertPtr(pArgs->pHlp);
1076 //Assert(pArgs->pIommuCC->u32Magic == IOMMU_MAGIC);
1077
1078 uint16_t const uDomainId = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1079 if (uDomainId == pArgs->uDomainId)
1080 {
1081 PCIOTLBE pIotlbe = (PCIOTLBE)pNode;
1082 AVLU64KEY const uKey = pIotlbe->Core.Key;
1083 uint64_t const uIova = IOMMU_IOTLB_KEY_GET_IOVA(uKey);
1084 RTGCPHYS const GCPhysSpa = pIotlbe->PageLookup.GCPhysSpa;
1085 uint8_t const cShift = pIotlbe->PageLookup.cShift;
1086 size_t const cbPage = RT_BIT_64(cShift);
1087 uint8_t const fPerm = pIotlbe->PageLookup.fPerm;
1088 const char *pszPerm = iommuAmdMemAccessGetPermName(fPerm);
1089 bool const fEvictPending = pIotlbe->fEvictPending;
1090
1091 PCDBGFINFOHLP pHlp = pArgs->pHlp;
1092 pHlp->pfnPrintf(pHlp, " Key = %#RX64 (%#RX64)\n", uKey, uIova);
1093 pHlp->pfnPrintf(pHlp, " GCPhys = %#RGp\n", GCPhysSpa);
1094 pHlp->pfnPrintf(pHlp, " cShift = %u (%zu bytes)\n", cShift, cbPage);
1095 pHlp->pfnPrintf(pHlp, " fPerm = %#x (%s)\n", fPerm, pszPerm);
1096 pHlp->pfnPrintf(pHlp, " fEvictPending = %RTbool\n", fEvictPending);
1097 }
1098
1099 return VINF_SUCCESS;
1100}
1101# endif /* IN_RING3 */
1102
1103
1104/**
1105 * Removes the IOTLB entry if it's associated with the specified domain ID.
1106 *
1107 * @returns VINF_SUCCESS.
1108 * @param pNode Pointer to an IOTLBE.
1109 * @param pvUser Pointer to an IOTLBEFLUSHARG containing the domain ID.
1110 */
1111static DECLCALLBACK(int) iommuAmdIotlbEntryRemoveDomainId(PAVLU64NODECORE pNode, void *pvUser)
1112{
1113 /* Validate. */
1114 PCIOTLBEFLUSHARG pArgs = (PCIOTLBEFLUSHARG)pvUser;
1115 AssertPtr(pArgs);
1116 AssertPtr(pArgs->pIommuR3);
1117 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1118
1119 uint16_t const uDomainId = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1120 if (uDomainId == pArgs->uDomainId)
1121 {
1122 /* Mark this entry is as invalidated and needs to be evicted later. */
1123 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1124 pIotlbe->fEvictPending = true;
1125 iommuAmdIotlbEntryMoveToLru(pArgs->pIommuR3, (PIOTLBE)pNode);
1126 }
1127 return VINF_SUCCESS;
1128}
1129
1130
1131/**
1132 * Inserts an IOTLB entry into the cache.
1133 *
1134 * @param pThis The shared IOMMU device state.
1135 * @param pThisR3 The ring-3 IOMMU device state.
1136 * @param pIotlbe The IOTLB entry to initialize and insert.
1137 * @param uDomainId The domain ID.
1138 * @param uIova The I/O virtual address.
1139 * @param pPageLookup The I/O page lookup result of the access.
1140 */
1141static void iommuAmdIotlbEntryInsert(PIOMMU pThis, PIOMMUR3 pThisR3, PIOTLBE pIotlbe, uint16_t uDomainId, uint64_t uIova,
1142 PCIOPAGELOOKUP pPageLookup)
1143{
1144 /* Initialize the IOTLB entry with results of the I/O page walk. */
1145 pIotlbe->Core.Key = IOMMU_IOTLB_KEY_MAKE(uDomainId, uIova);
1146 pIotlbe->PageLookup = *pPageLookup;
1147
1148 /* Validate. */
1149 Assert(pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL);
1150 Assert(!pIotlbe->fEvictPending);
1151
1152 /* Check if the entry already exists. */
1153 PIOTLBE pFound = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, pIotlbe->Core.Key);
1154 if (!pFound)
1155 {
1156 /* Insert the entry into the cache. */
1157 bool const fInserted = RTAvlU64Insert(&pThisR3->TreeIotlbe, &pIotlbe->Core);
1158 Assert(fInserted); NOREF(fInserted);
1159 Assert(pThisR3->cCachedIotlbes < IOMMU_IOTLBE_MAX);
1160 ++pThisR3->cCachedIotlbes;
1161 STAM_COUNTER_INC(&pThis->StatIotlbeCached); NOREF(pThis);
1162 }
1163 else
1164 {
1165 /* Update the existing entry. */
1166 if (pFound->fEvictPending)
1167 {
1168 pFound->fEvictPending = false;
1169 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse); NOREF(pThis);
1170 }
1171 Assert(pFound->PageLookup.cShift == pPageLookup->cShift);
1172 pFound->PageLookup.fPerm = pPageLookup->fPerm;
1173 pFound->PageLookup.GCPhysSpa = pPageLookup->GCPhysSpa;
1174 }
1175}
1176
1177
1178/**
1179 * Removes an IOTLB entry from the cache for the given key.
1180 *
1181 * @returns Pointer to the removed IOTLB entry, NULL if the entry wasn't found in
1182 * the tree.
1183 * @param pThis The shared IOMMU device state.
1184 * @param pThisR3 The ring-3 IOMMU device state.
1185 * @param uKey The key of the IOTLB entry to remove.
1186 */
1187static PIOTLBE iommuAmdIotlbEntryRemove(PIOMMU pThis, PIOMMUR3 pThisR3, AVLU64KEY uKey)
1188{
1189 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Remove(&pThisR3->TreeIotlbe, uKey);
1190 if (pIotlbe)
1191 {
1192 if (pIotlbe->fEvictPending)
1193 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
1194
1195 RT_ZERO(pIotlbe->Core);
1196 RT_ZERO(pIotlbe->PageLookup);
1197 /* We must not erase the LRU node connections here! */
1198 pIotlbe->fEvictPending = false;
1199 Assert(pIotlbe->Core.Key == IOMMU_IOTLB_KEY_NIL);
1200
1201 Assert(pThisR3->cCachedIotlbes > 0);
1202 --pThisR3->cCachedIotlbes;
1203 STAM_COUNTER_DEC(&pThis->StatIotlbeCached); NOREF(pThis);
1204 }
1205 return pIotlbe;
1206}
1207
1208
1209/**
1210 * Looks up an IOTLB from the cache.
1211 *
1212 * @returns Pointer to IOTLB entry if found, NULL otherwise.
1213 * @param pThis The shared IOMMU device state.
1214 * @param pThisR3 The ring-3 IOMMU device state.
1215 * @param uDomainId The domain ID.
1216 * @param uIova The I/O virtual address.
1217 */
1218static PIOTLBE iommuAmdIotlbLookup(PIOMMU pThis, PIOMMUR3 pThisR3, uint64_t uDomainId, uint64_t uIova)
1219{
1220 RT_NOREF(pThis);
1221
1222 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(uDomainId, uIova);
1223 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1224 if ( pIotlbe
1225 && !pIotlbe->fEvictPending)
1226 return pIotlbe;
1227
1228 /*
1229 * Domain Id wildcard invalidations only marks entries for eviction later but doesn't remove
1230 * them from the cache immediately. We found an entry pending eviction, just return that
1231 * nothing was found (rather than evicting now).
1232 */
1233 return NULL;
1234}
1235
1236
1237/**
1238 * Adds an IOTLB entry to the cache.
1239 *
1240 * @param pThis The shared IOMMU device state.
1241 * @param pThis The ring-3 IOMMU device state.
1242 * @param uDomainId The domain ID.
1243 * @param uIova The I/O virtual address.
1244 * @param pPageLookup The I/O page lookup result of the access.
1245 */
1246static void iommuAmdIotlbAdd(PIOMMU pThis, PIOMMUR3 pThisR3, uint16_t uDomainId, uint64_t uIova, PCIOPAGELOOKUP pPageLookup)
1247{
1248 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1249 Assert(pPageLookup);
1250 Assert(pPageLookup->cShift <= 31);
1251 Assert(pPageLookup->fPerm != IOMMU_IO_PERM_NONE);
1252
1253 /*
1254 * If there are no unused IOTLB entries, evict the LRU entry.
1255 * Otherwise, get a new IOTLB entry from the pre-allocated list.
1256 */
1257 if (pThisR3->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
1258 {
1259 /* Grab the least recently used entry. */
1260 PIOTLBE pIotlbe = RTListGetFirst(&pThisR3->LstLruIotlbe, IOTLBE, NdLru);
1261 Assert(pIotlbe);
1262
1263 /* If the entry is in the cache, remove it. */
1264 if (pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL)
1265 iommuAmdIotlbEntryRemove(pThis, pThisR3, pIotlbe->Core.Key);
1266
1267 /* Initialize and insert the IOTLB entry into the cache. */
1268 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, uDomainId, uIova, pPageLookup);
1269
1270 /* Move the entry to the most recently used slot. */
1271 iommuAmdIotlbEntryMoveToMru(pThisR3, pIotlbe);
1272 }
1273 else
1274 {
1275 /* Grab an unused IOTLB entry from the pre-allocated list. */
1276 PIOTLBE pIotlbe = &pThisR3->paIotlbes[pThisR3->idxUnusedIotlbe];
1277 ++pThisR3->idxUnusedIotlbe;
1278
1279 /* Initialize and insert the IOTLB entry into the cache. */
1280 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, uDomainId, uIova, pPageLookup);
1281
1282 /* Add the entry to the most recently used slot. */
1283 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1284 }
1285}
1286
1287
1288/**
1289 * Removes all IOTLB entries from the cache.
1290 *
1291 * @param pDevIns The IOMMU instance data.
1292 */
1293static void iommuAmdIotlbRemoveAll(PPDMDEVINS pDevIns)
1294{
1295 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1296 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1297 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1298
1299 if (pThisR3->cCachedIotlbes > 0)
1300 {
1301 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
1302 RT_BZERO(pThisR3->paIotlbes, cbIotlbes);
1303 pThisR3->idxUnusedIotlbe = 0;
1304 pThisR3->cCachedIotlbes = 0;
1305 STAM_COUNTER_RESET(&pThis->StatIotlbeCached);
1306 RTListInit(&pThisR3->LstLruIotlbe);
1307 }
1308
1309 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1310}
1311
1312
1313/**
1314 * Removes IOTLB entries for the range of I/O virtual addresses and the specified
1315 * domain ID from the cache.
1316 *
1317 * @param pDevIns The IOMMU instance data.
1318 * @param uDomainId The domain ID.
1319 * @param uIova The I/O virtual address to invalidate.
1320 * @param cbInvalidate The size of the invalidation (must be 4K aligned).
1321 */
1322static void iommuAmdIotlbRemoveRange(PPDMDEVINS pDevIns, uint16_t uDomainId, uint64_t uIova, size_t cbInvalidate)
1323{
1324 /* Validate. */
1325 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1326 Assert(!(cbInvalidate & X86_PAGE_4K_OFFSET_MASK));
1327 Assert(cbInvalidate >= X86_PAGE_4K_SIZE);
1328
1329 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1330 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1331 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1332
1333 do
1334 {
1335 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(uDomainId, uIova);
1336 PIOTLBE pIotlbe = iommuAmdIotlbEntryRemove(pThis, pThisR3, uKey);
1337 if (pIotlbe)
1338 iommuAmdIotlbEntryMoveToLru(pThisR3, pIotlbe);
1339 uIova += X86_PAGE_4K_SIZE;
1340 cbInvalidate -= X86_PAGE_4K_SIZE;
1341 } while (cbInvalidate > 0);
1342
1343 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1344}
1345
1346
1347/**
1348 * Removes all IOTLB entries for the specified domain ID.
1349 *
1350 * @param pDevIns The IOMMU instance data.
1351 * @param uDomainId The domain ID.
1352 */
1353static void iommuAmdIotlbRemoveDomainId(PPDMDEVINS pDevIns, uint16_t uDomainId)
1354{
1355 /*
1356 * We need to iterate the tree and search based on the domain ID.
1357 * But it seems we cannot remove items while iterating the tree.
1358 * Thus, we simply mark entries for eviction later but move them to the LRU
1359 * so they will eventually get evicted and re-cycled as the cache gets re-populated.
1360 */
1361 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1362 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1363 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1364
1365 IOTLBEFLUSHARG Args;
1366 Args.pIommuR3 = pThisR3;
1367 Args.uDomainId = uDomainId;
1368 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdIotlbEntryRemoveDomainId, &Args);
1369
1370 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1371}
1372
1373
1374/**
1375 * Adds or updates IOTLB entries for the given range of I/O virtual addresses.
1376 *
1377 * @param pDevIns The IOMMU instance data.
1378 * @param uDomainId The domain ID.
1379 * @param uIova The I/O virtual address.
1380 * @param cbAccess The size of the access (must be 4K aligned).
1381 * @param GCPhysSpa The translated system-physical address.
1382 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
1383 */
1384static void iommuAmdIotlbAddRange(PPDMDEVINS pDevIns, uint16_t uDomainId, uint64_t uIova, size_t cbAccess, RTGCPHYS GCPhysSpa,
1385 uint8_t fPerm)
1386{
1387 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1388 Assert(!(GCPhysSpa & X86_PAGE_4K_OFFSET_MASK));
1389 Assert(!(cbAccess & X86_PAGE_4K_OFFSET_MASK));
1390 Assert(cbAccess >= X86_PAGE_4K_SIZE);
1391
1392 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1393 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1394
1395 /* Add IOTLB entries for every page in the access. */
1396 IOPAGELOOKUP PageLookup;
1397 RT_ZERO(PageLookup);
1398 PageLookup.cShift = X86_PAGE_4K_SHIFT;
1399 PageLookup.fPerm = fPerm;
1400 PageLookup.GCPhysSpa = GCPhysSpa;
1401
1402 size_t cPages = cbAccess / X86_PAGE_4K_SIZE;
1403 cPages = RT_MIN(cPages, IOMMU_IOTLBE_MAX);
1404
1405 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1406 /** @todo Re-check DTE cache? */
1407 do
1408 {
1409 iommuAmdIotlbAdd(pThis, pThisR3, uDomainId, uIova, &PageLookup);
1410 uIova += X86_PAGE_4K_SIZE;
1411 PageLookup.GCPhysSpa += X86_PAGE_4K_SIZE;
1412 --cPages;
1413 } while (cPages > 0);
1414 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1415}
1416#endif /* IOMMU_WITH_IOTLBE_CACHE */
1417
1418
1419#ifdef IOMMU_WITH_IRTE_CACHE
1420/**
1421 * Looks up an IRTE cache entry.
1422 *
1423 * @returns Index of the found entry, or cache capacity if not found.
1424 * @param pThis The shared IOMMU device state.
1425 * @param uDevId The device ID (bus, device, function).
1426 * @param offIrte The offset into the interrupt remap table.
1427 */
1428static uint16_t iommuAmdIrteCacheEntryLookup(PCIOMMU pThis, uint16_t uDevId, uint16_t offIrte)
1429{
1430 /** @todo Consider sorting and binary search when the cache capacity grows.
1431 * For the IRTE cache this should be okay since typically guests do not alter the
1432 * interrupt remapping once programmed, so hopefully sorting shouldn't happen
1433 * often. */
1434 uint32_t const uKey = IOMMU_IRTE_CACHE_KEY_MAKE(uDevId, offIrte);
1435 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1436 for (uint16_t i = 0; i < cIrteCache; i++)
1437 if (pThis->aIrteCache[i].uKey == uKey)
1438 return i;
1439 return cIrteCache;
1440}
1441
1442
1443/**
1444 * Gets a free/unused IRTE cache entry.
1445 *
1446 * @returns The index of an unused entry, or cache capacity if the cache is full.
1447 * @param pThis The shared IOMMU device state.
1448 */
1449static uint16_t iommuAmdIrteCacheEntryGetUnused(PCIOMMU pThis)
1450{
1451 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1452 for (uint16_t i = 0; i < cIrteCache; i++)
1453 if (pThis->aIrteCache[i].uKey == IOMMU_IRTE_CACHE_KEY_NIL)
1454 {
1455 Assert(!pThis->aIrteCache[i].Irte.u32);
1456 return i;
1457 }
1458 return cIrteCache;
1459}
1460
1461
1462/**
1463 * Looks up the IRTE cache for the given MSI.
1464 *
1465 * @returns VBox status code.
1466 * @param pDevIns The IOMMU instance data.
1467 * @param uDevId The device ID (bus, device, function).
1468 * @param enmOp The IOMMU operation being performed.
1469 * @param pMsiIn The source MSI.
1470 * @param pMsiOut Where to store the remapped MSI.
1471 */
1472static int iommuAmdIrteCacheLookup(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1473{
1474 RT_NOREF(enmOp); /* May need it if we have to report errors (currently we fallback to the slower path to do that). */
1475
1476 int rc = VERR_NOT_FOUND;
1477 /* Deal with such cases in the slower/fallback path. */
1478 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
1479 { /* likely */ }
1480 else
1481 return rc;
1482
1483 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1484 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1485
1486 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, uDevId);
1487 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
1488 {
1489 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
1490 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1491 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1492 {
1493 Assert((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE); /* Paranoia. */
1494
1495 /* Currently, we only cache remapping of fixed and arbitrated interrupts. */
1496 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
1497 if (u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
1498 {
1499 uint8_t const uIntrCtrl = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT)
1500 & IOMMU_DTE_CACHE_F_INTR_CTRL_MASK;
1501 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
1502 {
1503 /* Interrupt table length has been verified prior to adding entries to the cache. */
1504 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(pMsiIn->Data.u32);
1505 uint16_t const idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, uDevId, offIrte);
1506 if (idxIrteCache < RT_ELEMENTS(pThis->aIrteCache))
1507 {
1508 PCIRTE_T pIrte = &pThis->aIrteCache[idxIrteCache].Irte;
1509 Assert(pIrte->n.u1RemapEnable);
1510 Assert(pIrte->n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO);
1511 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, pIrte);
1512 rc = VINF_SUCCESS;
1513 }
1514 }
1515 else if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
1516 {
1517 *pMsiOut = *pMsiIn;
1518 rc = VINF_SUCCESS;
1519 }
1520 }
1521 }
1522 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
1523 {
1524 *pMsiOut = *pMsiIn;
1525 rc = VINF_SUCCESS;
1526 }
1527 }
1528
1529 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1530 return rc;
1531}
1532
1533
1534/**
1535 * Adds or updates the IRTE cache for the given IRTE.
1536 *
1537 * @returns VBox status code.
1538 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
1539 *
1540 * @param pDevIns The IOMMU instance data.
1541 * @param uDevId The device ID (bus, device, function).
1542 * @param offIrte The offset into the interrupt remap table.
1543 * @param pIrte The IRTE to cache.
1544 */
1545static int iommuAmdIrteCacheAdd(PPDMDEVINS pDevIns, uint16_t uDevId, uint16_t offIrte, PCIRTE_T pIrte)
1546{
1547 Assert(offIrte != 0xffff); /* Shouldn't be a valid IRTE table offset since sizeof(IRTE) is a multiple of 4. */
1548
1549 int rc = VINF_SUCCESS;
1550 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1551 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1552
1553 /* Find an existing entry or get an unused slot. */
1554 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1555 uint16_t idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, uDevId, offIrte);
1556 if ( idxIrteCache < cIrteCache
1557 || (idxIrteCache = iommuAmdIrteCacheEntryGetUnused(pThis)) < cIrteCache)
1558 {
1559 pThis->aIrteCache[idxIrteCache].uKey = IOMMU_IRTE_CACHE_KEY_MAKE(uDevId, offIrte);
1560 pThis->aIrteCache[idxIrteCache].Irte = *pIrte;
1561 }
1562 else
1563 rc = VERR_OUT_OF_RESOURCES;
1564
1565 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1566 return rc;
1567}
1568
1569
1570/**
1571 * Removes IRTE cache entries for the given device ID.
1572 *
1573 * @param pDevIns The IOMMU instance data.
1574 * @param uDevId The device ID (bus, device, function).
1575 */
1576static void iommuAmdIrteCacheRemove(PPDMDEVINS pDevIns, uint16_t uDevId)
1577{
1578 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1579 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1580 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1581 for (uint16_t i = 0; i < cIrteCache; i++)
1582 {
1583 PIRTECACHE pIrteCache = &pThis->aIrteCache[i];
1584 if (uDevId == IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(pIrteCache->uKey))
1585 {
1586 pIrteCache->uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1587 pIrteCache->Irte.u32 = 0;
1588 /* There could multiple IRTE entries for a device ID, continue searching. */
1589 }
1590 }
1591 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1592}
1593
1594
1595/**
1596 * Removes all IRTE cache entries.
1597 *
1598 * @param pDevIns The IOMMU instance data.
1599 */
1600static void iommuAmdIrteCacheRemoveAll(PPDMDEVINS pDevIns)
1601{
1602 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1603 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1604 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1605 for (uint16_t i = 0; i < cIrteCache; i++)
1606 {
1607 pThis->aIrteCache[i].uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1608 pThis->aIrteCache[i].Irte.u32 = 0;
1609 }
1610 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1611}
1612#endif /* IOMMU_WITH_IRTE_CACHE */
1613
1614
1615/**
1616 * Atomically reads the control register without locking the IOMMU device.
1617 *
1618 * @returns The control register.
1619 * @param pThis The shared IOMMU device state.
1620 */
1621DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrlUnlocked(PCIOMMU pThis)
1622{
1623 IOMMU_CTRL_T Ctrl;
1624 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
1625 return Ctrl;
1626}
1627
1628
1629/**
1630 * Returns whether MSI is enabled for the IOMMU.
1631 *
1632 * @returns Whether MSI is enabled.
1633 * @param pDevIns The IOMMU device instance.
1634 *
1635 * @note There should be a PCIDevXxx function for this.
1636 */
1637static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
1638{
1639 MSI_CAP_HDR_T MsiCapHdr;
1640 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
1641 return MsiCapHdr.n.u1MsiEnable;
1642}
1643
1644
1645/**
1646 * Signals a PCI target abort.
1647 *
1648 * @param pDevIns The IOMMU device instance.
1649 */
1650static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
1651{
1652 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1653 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1654 PDMPciDevSetStatus(pPciDev, u16Status);
1655}
1656
1657
1658/**
1659 * Wakes up the command thread if there are commands to be processed.
1660 *
1661 * @param pDevIns The IOMMU device instance.
1662 *
1663 * @remarks The IOMMU lock must be held while calling this!
1664 */
1665static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1666{
1667 Log4Func(("\n"));
1668
1669 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1670 if ( pThis->Status.n.u1CmdBufRunning
1671 && pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off
1672 && !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true))
1673 {
1674 Log4Func(("Signaling command thread\n"));
1675 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
1676 }
1677}
1678
1679
1680/**
1681 * Reads the Device Table Base Address Register.
1682 */
1683static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1684{
1685 RT_NOREF(pDevIns, offReg);
1686 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
1687 return VINF_SUCCESS;
1688}
1689
1690
1691/**
1692 * Reads the Command Buffer Base Address Register.
1693 */
1694static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1695{
1696 RT_NOREF(pDevIns, offReg);
1697 *pu64Value = pThis->CmdBufBaseAddr.u64;
1698 return VINF_SUCCESS;
1699}
1700
1701
1702/**
1703 * Reads the Event Log Base Address Register.
1704 */
1705static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1706{
1707 RT_NOREF(pDevIns, offReg);
1708 *pu64Value = pThis->EvtLogBaseAddr.u64;
1709 return VINF_SUCCESS;
1710}
1711
1712
1713/**
1714 * Reads the Control Register.
1715 */
1716static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1717{
1718 RT_NOREF(pDevIns, offReg);
1719 *pu64Value = pThis->Ctrl.u64;
1720 return VINF_SUCCESS;
1721}
1722
1723
1724/**
1725 * Reads the Exclusion Range Base Address Register.
1726 */
1727static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1728{
1729 RT_NOREF(pDevIns, offReg);
1730 *pu64Value = pThis->ExclRangeBaseAddr.u64;
1731 return VINF_SUCCESS;
1732}
1733
1734
1735/**
1736 * Reads to the Exclusion Range Limit Register.
1737 */
1738static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1739{
1740 RT_NOREF(pDevIns, offReg);
1741 *pu64Value = pThis->ExclRangeLimit.u64;
1742 return VINF_SUCCESS;
1743}
1744
1745
1746/**
1747 * Reads to the Extended Feature Register.
1748 */
1749static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1750{
1751 RT_NOREF(pDevIns, offReg);
1752 *pu64Value = pThis->ExtFeat.u64;
1753 return VINF_SUCCESS;
1754}
1755
1756
1757/**
1758 * Reads to the PPR Log Base Address Register.
1759 */
1760static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1761{
1762 RT_NOREF(pDevIns, offReg);
1763 *pu64Value = pThis->PprLogBaseAddr.u64;
1764 return VINF_SUCCESS;
1765}
1766
1767
1768/**
1769 * Writes the Hardware Event Register (Hi).
1770 */
1771static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1772{
1773 RT_NOREF(pDevIns, offReg);
1774 *pu64Value = pThis->HwEvtHi.u64;
1775 return VINF_SUCCESS;
1776}
1777
1778
1779/**
1780 * Reads the Hardware Event Register (Lo).
1781 */
1782static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1783{
1784 RT_NOREF(pDevIns, offReg);
1785 *pu64Value = pThis->HwEvtLo;
1786 return VINF_SUCCESS;
1787}
1788
1789
1790/**
1791 * Reads the Hardware Event Status Register.
1792 */
1793static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1794{
1795 RT_NOREF(pDevIns, offReg);
1796 *pu64Value = pThis->HwEvtStatus.u64;
1797 return VINF_SUCCESS;
1798}
1799
1800
1801/**
1802 * Reads to the GA Log Base Address Register.
1803 */
1804static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1805{
1806 RT_NOREF(pDevIns, offReg);
1807 *pu64Value = pThis->GALogBaseAddr.u64;
1808 return VINF_SUCCESS;
1809}
1810
1811
1812/**
1813 * Reads to the PPR Log B Base Address Register.
1814 */
1815static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1816{
1817 RT_NOREF(pDevIns, offReg);
1818 *pu64Value = pThis->PprLogBBaseAddr.u64;
1819 return VINF_SUCCESS;
1820}
1821
1822
1823/**
1824 * Reads to the Event Log B Base Address Register.
1825 */
1826static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1827{
1828 RT_NOREF(pDevIns, offReg);
1829 *pu64Value = pThis->EvtLogBBaseAddr.u64;
1830 return VINF_SUCCESS;
1831}
1832
1833
1834/**
1835 * Reads the Device Table Segment Base Address Register.
1836 */
1837static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1838{
1839 RT_NOREF(pDevIns);
1840
1841 /* Figure out which segment is being written. */
1842 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1843 uint8_t const idxSegment = offSegment + 1;
1844 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1845
1846 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
1847 return VINF_SUCCESS;
1848}
1849
1850
1851/**
1852 * Reads the Device Specific Feature Extension (DSFX) Register.
1853 */
1854static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1855{
1856 RT_NOREF(pDevIns, offReg);
1857 *pu64Value = pThis->DevSpecificFeat.u64;
1858 return VINF_SUCCESS;
1859}
1860
1861/**
1862 * Reads the Device Specific Control Extension (DSCX) Register.
1863 */
1864static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1865{
1866 RT_NOREF(pDevIns, offReg);
1867 *pu64Value = pThis->DevSpecificCtrl.u64;
1868 return VINF_SUCCESS;
1869}
1870
1871
1872/**
1873 * Reads the Device Specific Status Extension (DSSX) Register.
1874 */
1875static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1876{
1877 RT_NOREF(pDevIns, offReg);
1878 *pu64Value = pThis->DevSpecificStatus.u64;
1879 return VINF_SUCCESS;
1880}
1881
1882
1883/**
1884 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1885 */
1886static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1887{
1888 RT_NOREF(pDevIns, offReg);
1889 uint32_t const uLo = pThis->MiscInfo.au32[0];
1890 uint32_t const uHi = pThis->MiscInfo.au32[1];
1891 *pu64Value = RT_MAKE_U64(uLo, uHi);
1892 return VINF_SUCCESS;
1893}
1894
1895
1896/**
1897 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1898 * Register (32-bit).
1899 */
1900static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1901{
1902 RT_NOREF(pThis, offReg);
1903 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1904 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1905 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1906 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1907 *pu64Value = RT_MAKE_U64(uLo, uHi);
1908 return VINF_SUCCESS;
1909}
1910
1911
1912/**
1913 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1914 */
1915static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1916{
1917 RT_NOREF(pThis, offReg);
1918 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1919 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1920 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1921 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1922 *pu64Value = RT_MAKE_U64(uLo, uHi);
1923 return VINF_SUCCESS;
1924}
1925
1926
1927/**
1928 * Reads the Command Buffer Head Pointer Register.
1929 */
1930static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1931{
1932 RT_NOREF(pDevIns, offReg);
1933 *pu64Value = pThis->CmdBufHeadPtr.u64;
1934 return VINF_SUCCESS;
1935}
1936
1937
1938/**
1939 * Reads the Command Buffer Tail Pointer Register.
1940 */
1941static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1942{
1943 RT_NOREF(pDevIns, offReg);
1944 *pu64Value = pThis->CmdBufTailPtr.u64;
1945 return VINF_SUCCESS;
1946}
1947
1948
1949/**
1950 * Reads the Event Log Head Pointer Register.
1951 */
1952static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1953{
1954 RT_NOREF(pDevIns, offReg);
1955 *pu64Value = pThis->EvtLogHeadPtr.u64;
1956 return VINF_SUCCESS;
1957}
1958
1959
1960/**
1961 * Reads the Event Log Tail Pointer Register.
1962 */
1963static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1964{
1965 RT_NOREF(pDevIns, offReg);
1966 *pu64Value = pThis->EvtLogTailPtr.u64;
1967 return VINF_SUCCESS;
1968}
1969
1970
1971/**
1972 * Reads the Status Register.
1973 */
1974static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1975{
1976 RT_NOREF(pDevIns, offReg);
1977 *pu64Value = pThis->Status.u64;
1978 return VINF_SUCCESS;
1979}
1980
1981
1982/**
1983 * Writes the Device Table Base Address Register.
1984 */
1985static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1986{
1987 RT_NOREF(pDevIns, offReg);
1988
1989 /* Mask out all unrecognized bits. */
1990 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
1991
1992 /* Update the register. */
1993 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
1994
1995 /* Paranoia. */
1996 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
1997 return VINF_SUCCESS;
1998}
1999
2000
2001/**
2002 * Writes the Command Buffer Base Address Register.
2003 */
2004static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2005{
2006 RT_NOREF(pDevIns, offReg);
2007
2008 /*
2009 * While this is not explicitly specified like the event log base address register,
2010 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2011 * Inconsistent specs :/
2012 */
2013 if (pThis->Status.n.u1CmdBufRunning)
2014 {
2015 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2016 return VINF_SUCCESS;
2017 }
2018
2019 /* Mask out all unrecognized bits. */
2020 CMD_BUF_BAR_T CmdBufBaseAddr;
2021 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2022
2023 /* Validate the length. */
2024 if (CmdBufBaseAddr.n.u4Len >= 8)
2025 {
2026 /* Update the register. */
2027 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2028
2029 /*
2030 * Writing the command buffer base address, clears the command buffer head and tail pointers.
2031 * See AMD IOMMU spec. 2.4 "Commands".
2032 */
2033 pThis->CmdBufHeadPtr.u64 = 0;
2034 pThis->CmdBufTailPtr.u64 = 0;
2035 }
2036 else
2037 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2038
2039 return VINF_SUCCESS;
2040}
2041
2042
2043/**
2044 * Writes the Event Log Base Address Register.
2045 */
2046static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2047{
2048 RT_NOREF(pDevIns, offReg);
2049
2050 /*
2051 * IOMMU behavior is undefined when software writes this register when event logging is running.
2052 * In our emulation, we ignore the write entirely.
2053 * See AMD IOMMU spec. "Event Log Base Address Register".
2054 */
2055 if (pThis->Status.n.u1EvtLogRunning)
2056 {
2057 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2058 return VINF_SUCCESS;
2059 }
2060
2061 /* Mask out all unrecognized bits. */
2062 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2063 EVT_LOG_BAR_T EvtLogBaseAddr;
2064 EvtLogBaseAddr.u64 = u64Value;
2065
2066 /* Validate the length. */
2067 if (EvtLogBaseAddr.n.u4Len >= 8)
2068 {
2069 /* Update the register. */
2070 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2071
2072 /*
2073 * Writing the event log base address, clears the event log head and tail pointers.
2074 * See AMD IOMMU spec. 2.5 "Event Logging".
2075 */
2076 pThis->EvtLogHeadPtr.u64 = 0;
2077 pThis->EvtLogTailPtr.u64 = 0;
2078 }
2079 else
2080 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2081
2082 return VINF_SUCCESS;
2083}
2084
2085
2086/**
2087 * Writes the Control Register.
2088 */
2089static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2090{
2091 RT_NOREF(pDevIns, offReg);
2092
2093 /* Mask out all unrecognized bits. */
2094 u64Value &= IOMMU_CTRL_VALID_MASK;
2095 IOMMU_CTRL_T NewCtrl;
2096 NewCtrl.u64 = u64Value;
2097
2098 /* Ensure the device table segments are within limits. */
2099 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
2100 {
2101 IOMMU_CTRL_T const OldCtrl = pThis->Ctrl;
2102
2103 /* Update the register. */
2104 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2105
2106 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2107 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
2108
2109 /* Enable or disable event logging when the bit transitions. */
2110 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2111 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2112 if ( fOldEvtLogEn != fNewEvtLogEn
2113 || fOldIommuEn != fNewIommuEn)
2114 {
2115 if ( fNewIommuEn
2116 && fNewEvtLogEn)
2117 {
2118 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2119 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2120 }
2121 else
2122 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2123 }
2124
2125 /* Enable or disable command buffer processing when the bit transitions. */
2126 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2127 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2128 if ( fOldCmdBufEn != fNewCmdBufEn
2129 || fOldIommuEn != fNewIommuEn)
2130 {
2131 if ( fNewCmdBufEn
2132 && fNewIommuEn)
2133 {
2134 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2135 LogFunc(("Command buffer enabled\n"));
2136
2137 /* Wake up the command thread to start processing commands if any. */
2138 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2139 }
2140 else
2141 {
2142 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2143 LogFunc(("Command buffer disabled\n"));
2144 }
2145 }
2146 }
2147 else
2148 {
2149 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
2150 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
2151 }
2152
2153 return VINF_SUCCESS;
2154}
2155
2156
2157/**
2158 * Writes to the Exclusion Range Base Address Register.
2159 */
2160static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2161{
2162 RT_NOREF(pDevIns, offReg);
2163 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2164 return VINF_SUCCESS;
2165}
2166
2167
2168/**
2169 * Writes to the Exclusion Range Limit Register.
2170 */
2171static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2172{
2173 RT_NOREF(pDevIns, offReg);
2174 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2175 u64Value |= UINT64_C(0xfff);
2176 pThis->ExclRangeLimit.u64 = u64Value;
2177 return VINF_SUCCESS;
2178}
2179
2180
2181/**
2182 * Writes the Hardware Event Register (Hi).
2183 */
2184static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2185{
2186 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2187 RT_NOREF(pDevIns, offReg);
2188 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2189 pThis->HwEvtHi.u64 = u64Value;
2190 return VINF_SUCCESS;
2191}
2192
2193
2194/**
2195 * Writes the Hardware Event Register (Lo).
2196 */
2197static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2198{
2199 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2200 RT_NOREF(pDevIns, offReg);
2201 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2202 pThis->HwEvtLo = u64Value;
2203 return VINF_SUCCESS;
2204}
2205
2206
2207/**
2208 * Writes the Hardware Event Status Register.
2209 */
2210static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2211{
2212 RT_NOREF(pDevIns, offReg);
2213
2214 /* Mask out all unrecognized bits. */
2215 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2216
2217 /*
2218 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2219 * If the current status bits or the bits being written are both 0, we've nothing to do.
2220 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2221 */
2222 uint64_t HwStatus = pThis->HwEvtStatus.u64;
2223 if (!(HwStatus & RT_BIT(0)))
2224 return VINF_SUCCESS;
2225 if (u64Value & HwStatus & RT_BIT_64(0))
2226 HwStatus &= ~RT_BIT_64(0);
2227 if (u64Value & HwStatus & RT_BIT_64(1))
2228 HwStatus &= ~RT_BIT_64(1);
2229
2230 /* Update the register. */
2231 pThis->HwEvtStatus.u64 = HwStatus;
2232 return VINF_SUCCESS;
2233}
2234
2235
2236/**
2237 * Writes the Device Table Segment Base Address Register.
2238 */
2239static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2240{
2241 RT_NOREF(pDevIns);
2242
2243 /* Figure out which segment is being written. */
2244 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2245 uint8_t const idxSegment = offSegment + 1;
2246 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2247
2248 /* Mask out all unrecognized bits. */
2249 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2250 DEV_TAB_BAR_T DevTabSegBar;
2251 DevTabSegBar.u64 = u64Value;
2252
2253 /* Validate the size. */
2254 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2255 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2256 if (uSegSize <= uMaxSegSize)
2257 {
2258 /* Update the register. */
2259 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2260 }
2261 else
2262 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2263
2264 return VINF_SUCCESS;
2265}
2266
2267
2268/**
2269 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
2270 */
2271static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2272{
2273 RT_NOREF(pDevIns, offReg);
2274
2275 /* MSI Vector Register 0 is read-only. */
2276 /* MSI Vector Register 1. */
2277 uint32_t const uReg = u64Value >> 32;
2278 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
2279 return VINF_SUCCESS;
2280}
2281
2282
2283/**
2284 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
2285 * Register (32-bit).
2286 */
2287static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2288{
2289 RT_NOREF(pThis, offReg);
2290 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2291 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2292
2293 /* MSI capability header. */
2294 {
2295 uint32_t const uReg = u64Value;
2296 MSI_CAP_HDR_T MsiCapHdr;
2297 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2298 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2299 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2300 }
2301
2302 /* MSI Address Lo. */
2303 {
2304 uint32_t const uReg = u64Value >> 32;
2305 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
2306 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
2307 }
2308
2309 return VINF_SUCCESS;
2310}
2311
2312
2313/**
2314 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
2315 */
2316static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2317{
2318 RT_NOREF(pThis, offReg);
2319 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2320 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2321
2322 /* MSI Address Hi. */
2323 {
2324 uint32_t const uReg = u64Value;
2325 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
2326 }
2327
2328 /* MSI Data. */
2329 {
2330 uint32_t const uReg = u64Value >> 32;
2331 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
2332 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
2333 }
2334
2335 return VINF_SUCCESS;
2336}
2337
2338
2339/**
2340 * Writes the Command Buffer Head Pointer Register.
2341 */
2342static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2343{
2344 RT_NOREF(pDevIns, offReg);
2345
2346 /*
2347 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
2348 * In our emulation, we ignore the write entirely.
2349 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2350 */
2351 if (pThis->Status.n.u1CmdBufRunning)
2352 {
2353 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2354 return VINF_SUCCESS;
2355 }
2356
2357 /*
2358 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2359 * In our emulation, we ignore the write entirely.
2360 */
2361 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2362 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2363 Assert(cbBuf <= _512K);
2364 if (offBuf >= cbBuf)
2365 {
2366 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
2367 return VINF_SUCCESS;
2368 }
2369
2370 /* Update the register. */
2371 pThis->CmdBufHeadPtr.au32[0] = offBuf;
2372
2373 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2374
2375 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
2376 return VINF_SUCCESS;
2377}
2378
2379
2380/**
2381 * Writes the Command Buffer Tail Pointer Register.
2382 */
2383static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2384{
2385 RT_NOREF(pDevIns, offReg);
2386
2387 /*
2388 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2389 * In our emulation, we ignore the write entirely.
2390 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2391 */
2392 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2393 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2394 Assert(cbBuf <= _512K);
2395 if (offBuf >= cbBuf)
2396 {
2397 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2398 return VINF_SUCCESS;
2399 }
2400
2401 /*
2402 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2403 * head pointer after adding one or more commands to the buffer.
2404 *
2405 * However, we cannot enforce this strictly because it's legal for software to shrink the
2406 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2407 * at 0). Software might even make the queue empty by making head and tail equal which is
2408 * allowed. I don't think we can or should try too hard to prevent software shooting itself
2409 * in the foot here. As long as we make sure the offset value is within the circular buffer
2410 * bounds (which we do by masking bits above) it should be sufficient.
2411 */
2412 pThis->CmdBufTailPtr.au32[0] = offBuf;
2413
2414 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2415
2416 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
2417 return VINF_SUCCESS;
2418}
2419
2420
2421/**
2422 * Writes the Event Log Head Pointer Register.
2423 */
2424static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2425{
2426 RT_NOREF(pDevIns, offReg);
2427
2428 /*
2429 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2430 * In our emulation, we ignore the write entirely.
2431 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2432 */
2433 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
2434 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2435 Assert(cbBuf <= _512K);
2436 if (offBuf >= cbBuf)
2437 {
2438 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2439 return VINF_SUCCESS;
2440 }
2441
2442 /* Update the register. */
2443 pThis->EvtLogHeadPtr.au32[0] = offBuf;
2444
2445 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
2446 return VINF_SUCCESS;
2447}
2448
2449
2450/**
2451 * Writes the Event Log Tail Pointer Register.
2452 */
2453static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2454{
2455 RT_NOREF(pDevIns, offReg);
2456 NOREF(pThis);
2457
2458 /*
2459 * IOMMU behavior is undefined when software writes this register when the event log is running.
2460 * In our emulation, we ignore the write entirely.
2461 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2462 */
2463 if (pThis->Status.n.u1EvtLogRunning)
2464 {
2465 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
2466 return VINF_SUCCESS;
2467 }
2468
2469 /*
2470 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2471 * In our emulation, we ignore the write entirely.
2472 */
2473 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
2474 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2475 Assert(cbBuf <= _512K);
2476 if (offBuf >= cbBuf)
2477 {
2478 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2479 return VINF_SUCCESS;
2480 }
2481
2482 /* Update the register. */
2483 pThis->EvtLogTailPtr.au32[0] = offBuf;
2484
2485 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
2486 return VINF_SUCCESS;
2487}
2488
2489
2490/**
2491 * Writes the Status Register.
2492 */
2493static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2494{
2495 RT_NOREF(pDevIns, offReg);
2496
2497 /* Mask out all unrecognized bits. */
2498 u64Value &= IOMMU_STATUS_VALID_MASK;
2499
2500 /*
2501 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
2502 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
2503 */
2504 IOMMU_STATUS_T const OldStatus = pThis->Status;
2505 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
2506 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
2507 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
2508
2509 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
2510
2511 /* Update the register. */
2512 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
2513 return VINF_SUCCESS;
2514}
2515
2516
2517/**
2518 * Register access table 0.
2519 * The MMIO offset of each entry must be a multiple of 8!
2520 */
2521static const IOMMUREGACC g_aRegAccess0[] =
2522{
2523 /* MMIO off. Register name Read function Write function */
2524 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
2525 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
2526 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
2527 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
2528 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
2529 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
2530 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
2531 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
2532 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
2533 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
2534 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
2535 { /* 0x58 */ NULL, NULL, NULL },
2536
2537 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
2538 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
2539 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
2540 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
2541 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
2542 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
2543 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
2544 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
2545 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
2546 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
2547 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
2548 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
2549 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
2550 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
2551 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
2552 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
2553
2554 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
2555 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
2556 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
2557 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
2558
2559 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2560 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2561 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2562 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2563 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2564 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2565 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2566
2567 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
2568 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
2569 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
2570
2571 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
2572 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
2573 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
2574 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
2575
2576 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
2577 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
2578 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
2579};
2580AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
2581
2582/**
2583 * Register access table 1.
2584 * The MMIO offset of each entry must be a multiple of 8!
2585 */
2586static const IOMMUREGACC g_aRegAccess1[] =
2587{
2588 /* MMIO offset Register name Read function Write function */
2589 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
2590 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
2591 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
2592 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
2593 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
2594 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
2595 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
2596 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
2597 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
2598 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
2599 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
2600 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
2601};
2602AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
2603
2604/**
2605 * Register access table 2.
2606 * The MMIO offset of each entry must be a multiple of 8!
2607 */
2608static const IOMMUREGACC g_aRegAccess2[] =
2609{
2610 /* MMIO offset Register name Read Function Write function */
2611 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
2612
2613 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
2614 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
2615 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
2616 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
2617
2618 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
2619 { /* 0x2028 */ NULL, NULL, NULL },
2620
2621 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
2622 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
2623
2624 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
2625 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
2626
2627 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
2628 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
2629
2630 { /* 0x2060 */ NULL, NULL, NULL },
2631 { /* 0x2068 */ NULL, NULL, NULL },
2632
2633 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
2634 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
2635
2636 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
2637 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
2638 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
2639};
2640AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
2641
2642
2643/**
2644 * Gets the register access structure given its MMIO offset.
2645 *
2646 * @returns The register access structure, or NULL if the offset is invalid.
2647 * @param off The MMIO offset of the register being accessed.
2648 */
2649static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
2650{
2651 /* Figure out which table the register belongs to and validate its index. */
2652 PCIOMMUREGACC pReg;
2653 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
2654 {
2655 uint32_t const idxReg = off >> 3;
2656 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
2657 pReg = &g_aRegAccess0[idxReg];
2658 }
2659 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
2660 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
2661 {
2662 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
2663 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
2664 pReg = &g_aRegAccess1[idxReg];
2665 }
2666 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
2667 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
2668 {
2669 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
2670 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
2671 pReg = &g_aRegAccess2[idxReg];
2672 }
2673 else
2674 return NULL;
2675 return pReg;
2676}
2677
2678
2679/**
2680 * Writes an IOMMU register (32-bit and 64-bit).
2681 *
2682 * @returns Strict VBox status code.
2683 * @param pDevIns The IOMMU device instance.
2684 * @param off MMIO byte offset to the register.
2685 * @param cb The size of the write access.
2686 * @param uValue The value being written.
2687 *
2688 * @thread EMT.
2689 */
2690static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2691{
2692 /*
2693 * Validate the access in case of IOM bug or incorrect assumption.
2694 */
2695 Assert(off < IOMMU_MMIO_REGION_SIZE);
2696 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
2697 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
2698
2699 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
2700
2701 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2702 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2703 if (pReg)
2704 { /* likely */ }
2705 else
2706 {
2707 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
2708 return VINF_SUCCESS;
2709 }
2710
2711 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
2712 if (pReg->pfnWrite)
2713 { /* likely */ }
2714 else
2715 {
2716 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2717 return VINF_SUCCESS;
2718 }
2719
2720 /*
2721 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
2722 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
2723 * consecutive 32-bit registers.
2724 */
2725 if (cb == 8)
2726 {
2727 if (!(off & 7))
2728 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
2729
2730 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2731 return VINF_SUCCESS;
2732 }
2733
2734 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
2735 Assert(cb == 4);
2736 if (!(off & 7))
2737 {
2738 /*
2739 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
2740 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2741 */
2742 uint64_t u64Read;
2743 if (pReg->pfnRead)
2744 {
2745 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
2746 if (RT_FAILURE(rcStrict))
2747 {
2748 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2749 return rcStrict;
2750 }
2751 }
2752 else
2753 u64Read = 0;
2754
2755 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
2756 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
2757 }
2758
2759 /*
2760 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
2761 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2762 */
2763 Assert(!(off & 3));
2764 Assert(off & 7);
2765 Assert(off >= 4);
2766 uint64_t u64Read;
2767 if (pReg->pfnRead)
2768 {
2769 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
2770 if (RT_FAILURE(rcStrict))
2771 {
2772 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2773 return rcStrict;
2774 }
2775 }
2776 else
2777 u64Read = 0;
2778
2779 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
2780 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
2781}
2782
2783
2784/**
2785 * Reads an IOMMU register (64-bit) given its MMIO offset.
2786 *
2787 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2788 * boundary include the lower half of the subsequent register.
2789 *
2790 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
2791 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2792 * software will only perform 32-bit reads on those 32-bit registers that are
2793 * aligned on 8-byte boundaries.
2794 *
2795 * @returns Strict VBox status code.
2796 * @param pDevIns The IOMMU device instance.
2797 * @param off The MMIO offset of the register in bytes.
2798 * @param puResult Where to store the value being read.
2799 *
2800 * @thread EMT.
2801 */
2802static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2803{
2804 Assert(off < IOMMU_MMIO_REGION_SIZE);
2805 Assert(!(off & 7) || !(off & 3));
2806
2807 Log4Func(("off=%#x\n", off));
2808
2809 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2810 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2811 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
2812
2813 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2814 if (pReg)
2815 { /* likely */ }
2816 else
2817 {
2818 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2819 return VINF_IOM_MMIO_UNUSED_FF;
2820 }
2821
2822 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2823 if (pReg->pfnRead)
2824 { /* likely */ }
2825 else
2826 {
2827 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2828 return VINF_IOM_MMIO_UNUSED_00;
2829 }
2830
2831 /*
2832 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2833 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2834 */
2835 if (!(off & 7))
2836 return pReg->pfnRead(pDevIns, pThis, off, puResult);
2837
2838 /*
2839 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2840 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2841 */
2842 Assert(!(off & 3));
2843 Assert(off & 7);
2844 Assert(off >= 4);
2845 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2846 if (RT_SUCCESS(rcStrict))
2847 *puResult >>= 32;
2848 else
2849 {
2850 *puResult = 0;
2851 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2852 }
2853
2854 return rcStrict;
2855}
2856
2857
2858/**
2859 * Raises the MSI interrupt for the IOMMU device.
2860 *
2861 * @param pDevIns The IOMMU device instance.
2862 *
2863 * @thread Any.
2864 * @remarks The IOMMU lock may or may not be held.
2865 */
2866static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2867{
2868 LogFlowFunc(("\n"));
2869 if (iommuAmdIsMsiEnabled(pDevIns))
2870 {
2871 LogFunc(("Raising MSI\n"));
2872 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2873 }
2874}
2875
2876#if 0
2877/**
2878 * Clears the MSI interrupt for the IOMMU device.
2879 *
2880 * @param pDevIns The IOMMU device instance.
2881 *
2882 * @thread Any.
2883 * @remarks The IOMMU lock may or may not be held.
2884 */
2885static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2886{
2887 if (iommuAmdIsMsiEnabled(pDevIns))
2888 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2889}
2890#endif
2891
2892/**
2893 * Writes an entry to the event log in memory.
2894 *
2895 * @returns VBox status code.
2896 * @param pDevIns The IOMMU device instance.
2897 * @param pEvent The event to log.
2898 *
2899 * @thread Any.
2900 * @remarks The IOMMU lock must be held while calling this function.
2901 */
2902static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2903{
2904 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2905 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2906
2907 IOMMU_LOCK_NORET(pDevIns, pThisCC);
2908
2909 /* Check if event logging is active and the log has not overflowed. */
2910 IOMMU_STATUS_T const Status = pThis->Status;
2911 if ( Status.n.u1EvtLogRunning
2912 && !Status.n.u1EvtOverflow)
2913 {
2914 uint32_t const cbEvt = sizeof(*pEvent);
2915
2916 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2917 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2918 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2919
2920 /* Ensure we have space in the event log. */
2921 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2922 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2923 if (cEvts + 1 < cMaxEvts)
2924 {
2925 /* Write the event log entry to memory. */
2926 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2927 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2928 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2929 if (RT_FAILURE(rc))
2930 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2931
2932 /* Increment the event log tail pointer. */
2933 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2934 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2935
2936 /* Indicate that an event log entry was written. */
2937 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2938
2939 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2940 if (pThis->Ctrl.n.u1EvtIntrEn)
2941 iommuAmdMsiInterruptRaise(pDevIns);
2942 }
2943 else
2944 {
2945 /* Indicate that the event log has overflowed. */
2946 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2947
2948 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2949 if (pThis->Ctrl.n.u1EvtIntrEn)
2950 iommuAmdMsiInterruptRaise(pDevIns);
2951 }
2952 }
2953
2954 IOMMU_UNLOCK(pDevIns, pThisCC);
2955
2956 return VINF_SUCCESS;
2957}
2958
2959
2960/**
2961 * Sets an event in the hardware error registers.
2962 *
2963 * @param pDevIns The IOMMU device instance.
2964 * @param pEvent The event.
2965 *
2966 * @thread Any.
2967 */
2968static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2969{
2970 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2971 if (pThis->ExtFeat.n.u1HwErrorSup)
2972 {
2973 if (pThis->HwEvtStatus.n.u1Valid)
2974 pThis->HwEvtStatus.n.u1Overflow = 1;
2975 pThis->HwEvtStatus.n.u1Valid = 1;
2976 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
2977 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
2978 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
2979 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
2980 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2981 }
2982}
2983
2984
2985/**
2986 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
2987 *
2988 * @param uDevId The device ID (bus, device, function).
2989 * @param uDomainId The domain ID.
2990 * @param GCPhysPtEntity The system physical address of the page table
2991 * entity.
2992 * @param enmOp The IOMMU operation being performed.
2993 * @param pEvtPageTabHwErr Where to store the initialized event.
2994 */
2995static void iommuAmdPageTabHwErrorEventInit(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
2996 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2997{
2998 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
2999 pEvtPageTabHwErr->n.u16DevId = uDevId;
3000 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
3001 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3002 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3003 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3004 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3005 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3006 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3007 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3008}
3009
3010
3011/**
3012 * Raises a PAGE_TAB_HARDWARE_ERROR event.
3013 *
3014 * @param pDevIns The IOMMU device instance.
3015 * @param enmOp The IOMMU operation being performed.
3016 * @param pEvtPageTabHwErr The page table hardware error event.
3017 *
3018 * @thread Any.
3019 */
3020static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3021{
3022 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3023 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3024
3025 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3026 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3027
3028 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3029 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3030 if (enmOp != IOMMUOP_CMD)
3031 iommuAmdSetPciTargetAbort(pDevIns);
3032
3033 IOMMU_UNLOCK(pDevIns, pThisCC);
3034
3035 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3036 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3037 pEvtPageTabHwErr->n.u2Type));
3038}
3039
3040
3041#ifdef IN_RING3
3042/**
3043 * Initializes a COMMAND_HARDWARE_ERROR event.
3044 *
3045 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
3046 * @param pEvtCmdHwErr Where to store the initialized event.
3047 */
3048static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3049{
3050 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3051 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3052 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3053 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3054}
3055
3056
3057/**
3058 * Raises a COMMAND_HARDWARE_ERROR event.
3059 *
3060 * @param pDevIns The IOMMU device instance.
3061 * @param pEvtCmdHwErr The command hardware error event.
3062 *
3063 * @thread Any.
3064 */
3065static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3066{
3067 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3068 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3069 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3070
3071 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3072 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3073
3074 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3075 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3076 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3077
3078 IOMMU_UNLOCK(pDevIns, pThisCC);
3079
3080 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
3081}
3082#endif /* IN_RING3 */
3083
3084
3085/**
3086 * Initializes a DEV_TAB_HARDWARE_ERROR event.
3087 *
3088 * @param uDevId The device ID (bus, device, function).
3089 * @param GCPhysDte The system physical address of the failed device table
3090 * access.
3091 * @param enmOp The IOMMU operation being performed.
3092 * @param pEvtDevTabHwErr Where to store the initialized event.
3093 */
3094static void iommuAmdDevTabHwErrorEventInit(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3095 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3096{
3097 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3098 pEvtDevTabHwErr->n.u16DevId = uDevId;
3099 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3100 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
3101 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3102 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3103 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3104 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3105 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3106}
3107
3108
3109/**
3110 * Raises a DEV_TAB_HARDWARE_ERROR event.
3111 *
3112 * @param pDevIns The IOMMU device instance.
3113 * @param enmOp The IOMMU operation being performed.
3114 * @param pEvtDevTabHwErr The device table hardware error event.
3115 *
3116 * @thread Any.
3117 */
3118static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3119{
3120 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3121 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3122
3123 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3124 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3125
3126 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3127 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3128 if (enmOp != IOMMUOP_CMD)
3129 iommuAmdSetPciTargetAbort(pDevIns);
3130
3131 IOMMU_UNLOCK(pDevIns, pThisCC);
3132
3133 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
3134 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3135}
3136
3137
3138#ifdef IN_RING3
3139/**
3140 * Initializes an ILLEGAL_COMMAND_ERROR event.
3141 *
3142 * @param GCPhysCmd The system physical address of the failed command
3143 * access.
3144 * @param pEvtIllegalCmd Where to store the initialized event.
3145 */
3146static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3147{
3148 Assert(!(GCPhysCmd & UINT64_C(0xf)));
3149 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3150 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3151 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3152}
3153
3154
3155/**
3156 * Raises an ILLEGAL_COMMAND_ERROR event.
3157 *
3158 * @param pDevIns The IOMMU device instance.
3159 * @param pEvtIllegalCmd The illegal command error event.
3160 */
3161static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3162{
3163 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3164 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3165 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3166
3167 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3168 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3169
3170 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3171}
3172#endif /* IN_RING3 */
3173
3174
3175/**
3176 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3177 *
3178 * @param uDevId The device ID (bus, device, function).
3179 * @param uIova The I/O virtual address.
3180 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3181 * event was caused by an invalid level encoding in the
3182 * DTE.
3183 * @param enmOp The IOMMU operation being performed.
3184 * @param pEvtIllegalDte Where to store the initialized event.
3185 */
3186static void iommuAmdIllegalDteEventInit(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3187 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3188{
3189 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3190 pEvtIllegalDte->n.u16DevId = uDevId;
3191 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3192 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3193 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3194 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3195 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3196 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3197 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3198 * IOMMU spec here but not for this field for I/O page fault event. */
3199 Assert(!(uIova & UINT64_C(0x3)));
3200}
3201
3202
3203/**
3204 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3205 *
3206 * @param pDevIns The IOMMU instance data.
3207 * @param enmOp The IOMMU operation being performed.
3208 * @param pEvtIllegalDte The illegal device table entry event.
3209 * @param enmEvtType The illegal device table entry event type.
3210 *
3211 * @thread Any.
3212 */
3213static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3214 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3215{
3216 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3217 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3218
3219 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3220 if (enmOp != IOMMUOP_CMD)
3221 iommuAmdSetPciTargetAbort(pDevIns);
3222
3223 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3224 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3225 NOREF(enmEvtType);
3226}
3227
3228
3229/**
3230 * Initializes an IO_PAGE_FAULT event.
3231 *
3232 * @param uDevId The device ID (bus, device, function).
3233 * @param uDomainId The domain ID.
3234 * @param uIova The I/O virtual address being accessed.
3235 * @param fPresent Transaction to a page marked as present (including
3236 * DTE.V=1) or interrupt marked as remapped
3237 * (IRTE.RemapEn=1).
3238 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3239 * the I/O page fault was caused by invalid level
3240 * encoding.
3241 * @param fPermDenied Permission denied for the address being accessed.
3242 * @param enmOp The IOMMU operation being performed.
3243 * @param pEvtIoPageFault Where to store the initialized event.
3244 */
3245static void iommuAmdIoPageFaultEventInit(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3246 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3247{
3248 Assert(!fPermDenied || fPresent);
3249 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3250 pEvtIoPageFault->n.u16DevId = uDevId;
3251 //pEvtIoPageFault->n.u4PasidHi = 0;
3252 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
3253 //pEvtIoPageFault->n.u1GuestOrNested = 0;
3254 //pEvtIoPageFault->n.u1NoExecute = 0;
3255 //pEvtIoPageFault->n.u1User = 0;
3256 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3257 pEvtIoPageFault->n.u1Present = fPresent;
3258 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3259 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3260 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3261 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3262 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3263 pEvtIoPageFault->n.u64Addr = uIova;
3264}
3265
3266
3267/**
3268 * Raises an IO_PAGE_FAULT event.
3269 *
3270 * @param pDevIns The IOMMU instance data.
3271 * @param fIoDevFlags The I/O device flags, see IOMMU_DTE_CACHE_F_XXX.
3272 * @param pIrte The interrupt remapping table entry, can be NULL.
3273 * @param enmOp The IOMMU operation being performed.
3274 * @param pEvtIoPageFault The I/O page fault event.
3275 * @param enmEvtType The I/O page fault event type.
3276 *
3277 * @thread Any.
3278 */
3279static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, uint16_t fIoDevFlags, PCIRTE_T pIrte, IOMMUOP enmOp,
3280 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3281{
3282 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3283 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3284
3285#ifdef IOMMU_WITH_DTE_CACHE
3286# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) iommuAmdDteCacheAddFlags((a_pDevIns), (a_DevId), \
3287 IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED)
3288#else
3289# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) do { } while (0)
3290#endif
3291
3292 bool fSuppressEvtLogging = false;
3293 if ( enmOp == IOMMUOP_MEM_READ
3294 || enmOp == IOMMUOP_MEM_WRITE)
3295 {
3296 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_VALID
3297 | IOMMU_DTE_CACHE_F_SUPPRESS_IOPF | IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED;
3298 uint16_t const fSuppressAllIopf = IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
3299 if ( (fIoDevFlags & fSuppressAllIopf) == fSuppressAllIopf
3300 || (fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3301 {
3302 fSuppressEvtLogging = true;
3303 }
3304 }
3305 else if (enmOp == IOMMUOP_INTR_REQ)
3306 {
3307 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_INTR_MAP_VALID | IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
3308 if ((fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3309 fSuppressEvtLogging = true;
3310 else if (pIrte) /** @todo Make this compulsary and assert if it isn't provided. */
3311 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
3312 }
3313 /* else: Events are never suppressed for commands. */
3314
3315 switch (enmEvtType)
3316 {
3317 case kIoPageFaultType_PermDenied:
3318 {
3319 /* Cannot be triggered by a command. */
3320 Assert(enmOp != IOMMUOP_CMD);
3321 RT_FALL_THRU();
3322 }
3323 case kIoPageFaultType_DteRsvdPagingMode:
3324 case kIoPageFaultType_PteInvalidPageSize:
3325 case kIoPageFaultType_PteInvalidLvlEncoding:
3326 case kIoPageFaultType_SkippedLevelIovaNotZero:
3327 case kIoPageFaultType_PteRsvdNotZero:
3328 case kIoPageFaultType_PteValidNotSet:
3329 case kIoPageFaultType_DteTranslationDisabled:
3330 case kIoPageFaultType_PasidInvalidRange:
3331 {
3332 /*
3333 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3334 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
3335 */
3336 if (enmOp != IOMMUOP_TRANSLATE_REQ)
3337 {
3338 if (!fSuppressEvtLogging)
3339 {
3340 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3341 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3342 }
3343 if (enmOp != IOMMUOP_CMD)
3344 iommuAmdSetPciTargetAbort(pDevIns);
3345 }
3346 break;
3347 }
3348
3349 case kIoPageFaultType_UserSupervisor:
3350 {
3351 /* Access is blocked and only creates an event log entry. */
3352 if (!fSuppressEvtLogging)
3353 {
3354 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3355 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3356 }
3357 break;
3358 }
3359
3360 case kIoPageFaultType_IrteAddrInvalid:
3361 case kIoPageFaultType_IrteRsvdNotZero:
3362 case kIoPageFaultType_IrteRemapEn:
3363 case kIoPageFaultType_IrteRsvdIntType:
3364 case kIoPageFaultType_IntrReqAborted:
3365 case kIoPageFaultType_IntrWithPasid:
3366 {
3367 /* Only trigerred by interrupt requests. */
3368 Assert(enmOp == IOMMUOP_INTR_REQ);
3369 if (!fSuppressEvtLogging)
3370 {
3371 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3372 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3373 }
3374 iommuAmdSetPciTargetAbort(pDevIns);
3375 break;
3376 }
3377
3378 case kIoPageFaultType_SmiFilterMismatch:
3379 {
3380 /* Not supported and probably will never be, assert. */
3381 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3382 break;
3383 }
3384
3385 case kIoPageFaultType_DevId_Invalid:
3386 {
3387 /* Cannot be triggered by a command. */
3388 Assert(enmOp != IOMMUOP_CMD);
3389 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3390 if (!fSuppressEvtLogging)
3391 {
3392 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3393 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3394 }
3395 if ( enmOp == IOMMUOP_MEM_READ
3396 || enmOp == IOMMUOP_MEM_WRITE)
3397 iommuAmdSetPciTargetAbort(pDevIns);
3398 break;
3399 }
3400 }
3401
3402#undef IOMMU_DTE_CACHE_SET_PF_RAISED
3403}
3404
3405
3406/**
3407 * Raises an IO_PAGE_FAULT event given the DTE.
3408 *
3409 * @param pDevIns The IOMMU instance data.
3410 * @param pDte The device table entry.
3411 * @param pIrte The interrupt remapping table entry, can be NULL.
3412 * @param enmOp The IOMMU operation being performed.
3413 * @param pEvtIoPageFault The I/O page fault event.
3414 * @param enmEvtType The I/O page fault event type.
3415 *
3416 * @thread Any.
3417 */
3418static void iommuAmdIoPageFaultEventRaiseWithDte(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3419 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3420{
3421 Assert(pDte);
3422 uint16_t const fIoDevFlags = iommuAmdGetBasicDevFlags(pDte);
3423 return iommuAmdIoPageFaultEventRaise(pDevIns, fIoDevFlags, pIrte, enmOp, pEvtIoPageFault, enmEvtType);
3424}
3425
3426
3427/**
3428 * Reads a device table entry for the given the device ID.
3429 *
3430 * @returns VBox status code.
3431 * @param pDevIns The IOMMU device instance.
3432 * @param uDevId The device ID (bus, device, function).
3433 * @param enmOp The IOMMU operation being performed.
3434 * @param pDte Where to store the device table entry.
3435 *
3436 * @thread Any.
3437 */
3438static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
3439{
3440 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3441 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3442
3443 IOMMU_LOCK(pDevIns, pThisCC);
3444
3445 /* Figure out which device table segment is being accessed. */
3446 uint8_t const idxSegsEn = pThis->Ctrl.n.u3DevTabSegEn;
3447 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
3448
3449 uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
3450 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3451 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
3452
3453 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3454 uint32_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
3455 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3456
3457 /* Ensure the DTE falls completely within the device table segment. */
3458 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
3459
3460 IOMMU_UNLOCK(pDevIns, pThisCC);
3461
3462 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
3463 {
3464 /* Read the device table entry from guest memory. */
3465 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3466 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3467 if (RT_SUCCESS(rc))
3468 return rc;
3469
3470 /* Raise a device table hardware error. */
3471 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3472
3473 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3474 iommuAmdDevTabHwErrorEventInit(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
3475 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
3476 return VERR_IOMMU_DTE_READ_FAILED;
3477 }
3478
3479 /* Raise an I/O page fault for out-of-bounds acccess. */
3480 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3481 iommuAmdIoPageFaultEventInit(uDevId, 0 /* uDomainId */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
3482 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3483 iommuAmdIoPageFaultEventRaise(pDevIns, 0 /* fIoDevFlags */, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3484 kIoPageFaultType_DevId_Invalid);
3485 return VERR_IOMMU_DTE_BAD_OFFSET;
3486}
3487
3488
3489/**
3490 * Performs pre-translation checks for the given device table entry.
3491 *
3492 * @returns VBox status code.
3493 * @retval VINF_SUCCESS if the DTE is valid and supports address translation.
3494 * @retval VINF_IOMMU_ADDR_TRANSLATION_DISABLED if the DTE is valid but address
3495 * translation is disabled.
3496 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED if an error occurred and any
3497 * corresponding event was raised.
3498 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the DTE denies the requested
3499 * permissions.
3500 *
3501 * @param pDevIns The IOMMU device instance.
3502 * @param uIova The I/O virtual address to translate.
3503 * @param uDevId The device ID (bus, device, function).
3504 * @param fPerm The I/O permissions for this access, see
3505 * IOMMU_IO_PERM_XXX.
3506 * @param pDte The device table entry.
3507 * @param enmOp The IOMMU operation being performed.
3508 *
3509 * @thread Any.
3510 */
3511static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3512 IOMMUOP enmOp)
3513{
3514 /*
3515 * Check if the translation is valid, otherwise raise an I/O page fault.
3516 */
3517 if (pDte->n.u1TranslationValid)
3518 { /* likely */ }
3519 else
3520 {
3521 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3522 * doesn't explicitly say whether an I/O page fault is raised. From other
3523 * places in the spec. it seems early page walk terminations (starting with
3524 * the DTE) return the state computed so far and raises an I/O page fault. So
3525 * returning an invalid translation rather than skipping translation. */
3526 LogFunc(("Translation valid bit not set -> IOPF\n"));
3527 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3528 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3529 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3530 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3531 kIoPageFaultType_DteTranslationDisabled);
3532 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3533 }
3534
3535 /*
3536 * Check permissions bits in the DTE.
3537 * Note: This MUST be checked prior to checking the root page table level below!
3538 */
3539 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3540 if ((fPerm & fDtePerm) == fPerm)
3541 { /* likely */ }
3542 else
3543 {
3544 LogFunc(("Permission denied by DTE (fPerm=%#x fDtePerm=%#x) -> IOPF\n", fPerm, fDtePerm));
3545 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3546 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3547 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3548 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3549 kIoPageFaultType_PermDenied);
3550 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3551 }
3552
3553 /*
3554 * If the root page table level is 0, translation is disabled and GPA=SPA and
3555 * the DTE.IR and DTE.IW bits control permissions (verified above).
3556 */
3557 uint8_t const uMaxLevel = pDte->n.u3Mode;
3558 if (uMaxLevel != 0)
3559 { /* likely */ }
3560 else
3561 {
3562 Assert((fPerm & fDtePerm) == fPerm); /* Verify we've checked permissions. */
3563 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
3564 }
3565
3566 /*
3567 * If the root page table level exceeds the allowed host-address translation level,
3568 * page walk is terminated and translation fails.
3569 */
3570 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3571 { /* likely */ }
3572 else
3573 {
3574 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3575 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3576 * I'm just going with I/O page fault. */
3577 LogFunc(("Invalid root page table level %#x (uDevId=%#x) -> IOPF\n", uMaxLevel, uDevId));
3578 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3579 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3580 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3581 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3582 kIoPageFaultType_PteInvalidLvlEncoding);
3583 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3584 }
3585
3586 /* The DTE allows translations for this device. */
3587 return VINF_SUCCESS;
3588}
3589
3590
3591/**
3592 * Walks the I/O page table to translate the I/O virtual address to a system
3593 * physical address.
3594 *
3595 * @returns VBox status code.
3596 * @param pDevIns The IOMMU device instance.
3597 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
3598 * @param fPerm The I/O permissions for this access, see
3599 * IOMMU_IO_PERM_XXX.
3600 * @param uDevId The device ID (bus, device, function).
3601 * @param pDte The device table entry.
3602 * @param enmOp The IOMMU operation being performed.
3603 * @param pPageLookup Where to store the results of the I/O page lookup. This
3604 * is only updated when VINF_SUCCESS is returned.
3605 *
3606 * @thread Any.
3607 */
3608static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint64_t uIova, uint8_t fPerm, uint16_t uDevId, PCDTE_T pDte,
3609 IOMMUOP enmOp, PIOPAGELOOKUP pPageLookup)
3610{
3611 Assert(pDte->n.u1Valid);
3612 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
3613
3614 /* The virtual address bits indexing table. */
3615 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
3616 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
3617 UINT64_C(0x00000000001ff000),
3618 UINT64_C(0x000000003fe00000),
3619 UINT64_C(0x0000007fc0000000),
3620 UINT64_C(0x0000ff8000000000),
3621 UINT64_C(0x01ff000000000000),
3622 UINT64_C(0xfe00000000000000),
3623 UINT64_C(0x0000000000000000) };
3624 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
3625 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
3626
3627 /* Traverse the I/O page table starting with the page directory in the DTE. */
3628 IOPTENTITY_T PtEntity;
3629 PtEntity.u64 = pDte->au64[0];
3630 for (;;)
3631 {
3632 /* Figure out the system physical address of the page table at the current level. */
3633 uint8_t const uLevel = PtEntity.n.u3NextLevel;
3634
3635 /* Read the page table entity at the current level. */
3636 {
3637 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
3638 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3639 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
3640 uint64_t const offPte = idxPte << 3;
3641 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
3642 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
3643 if (RT_FAILURE(rc))
3644 {
3645 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
3646 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
3647 iommuAmdPageTabHwErrorEventInit(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
3648 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
3649 return VERR_IOMMU_IPE_2;
3650 }
3651 }
3652
3653 /* Check present bit. */
3654 if (PtEntity.n.u1Present)
3655 { /* likely */ }
3656 else
3657 {
3658 LogFunc(("Page table entry not present (uDevId=%#x) -> IOPF\n", uDevId));
3659 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3660 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3661 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3662 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3663 kIoPageFaultType_PermDenied);
3664 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3665 }
3666
3667 /* Check permission bits. */
3668 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3669 if ((fPerm & fPtePerm) == fPerm)
3670 { /* likely */ }
3671 else
3672 {
3673 LogFunc(("Page table entry access denied (uDevId=%#x fPerm=%#x fPtePerm=%#x) -> IOPF\n", uDevId, fPerm, fPtePerm));
3674 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3675 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3676 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3677 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3678 kIoPageFaultType_PermDenied);
3679 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3680 }
3681
3682 /* If this is a PTE, we're at the final level and we're done. */
3683 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
3684 if (uNextLevel == 0)
3685 {
3686 /* The page size of the translation is the default (4K). */
3687 pPageLookup->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3688 pPageLookup->cShift = X86_PAGE_4K_SHIFT;
3689 pPageLookup->fPerm = fPtePerm;
3690 return VINF_SUCCESS;
3691 }
3692 if (uNextLevel == 7)
3693 {
3694 /* The default page size of the translation is overridden. */
3695 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3696 uint8_t cShift = X86_PAGE_4K_SHIFT;
3697 while (GCPhysPte & RT_BIT_64(cShift++))
3698 ;
3699
3700 /* The page size must be larger than the default size and lower than the default size of the higher level. */
3701 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
3702 if ( cShift > s_acIovaLevelShifts[uLevel]
3703 && cShift < s_acIovaLevelShifts[uLevel + 1])
3704 {
3705 pPageLookup->GCPhysSpa = GCPhysPte;
3706 pPageLookup->cShift = cShift;
3707 pPageLookup->fPerm = fPtePerm;
3708 return VINF_SUCCESS;
3709 }
3710
3711 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
3712 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3713 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3714 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3715 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3716 kIoPageFaultType_PteInvalidPageSize);
3717 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3718 }
3719
3720 /* Validate the next level encoding of the PDE. */
3721#if IOMMU_MAX_HOST_PT_LEVEL < 6
3722 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3723 { /* likely */ }
3724 else
3725 {
3726 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
3727 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3728 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3729 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3730 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3731 kIoPageFaultType_PteInvalidLvlEncoding);
3732 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3733 }
3734#else
3735 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3736#endif
3737
3738 /* Validate level transition. */
3739 if (uNextLevel < uLevel)
3740 { /* likely */ }
3741 else
3742 {
3743 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
3744 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3745 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3746 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3747 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3748 kIoPageFaultType_PteInvalidLvlEncoding);
3749 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3750 }
3751
3752 /* Ensure IOVA bits of skipped levels are zero. */
3753 Assert(uLevel > 0);
3754 uint64_t uIovaSkipMask = 0;
3755 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
3756 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
3757 if (!(uIova & uIovaSkipMask))
3758 { /* likely */ }
3759 else
3760 {
3761 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
3762 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3763 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3764 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3765 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3766 kIoPageFaultType_SkippedLevelIovaNotZero);
3767 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3768 }
3769
3770 /* Continue with traversing the page directory at this level. */
3771 }
3772}
3773
3774
3775/**
3776 * Page lookup callback for finding an I/O page from guest memory.
3777 *
3778 * @returns VBox status code.
3779 * @retval VINF_SUCCESS when the page is found and has the right permissions.
3780 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED when address translation fails.
3781 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
3782 * insufficient to what is requested.
3783 *
3784 * @param pDevIns The IOMMU instance data.
3785 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
3786 * 4K aligned).
3787 * @param fPerm The I/O permissions for this access, see
3788 * IOMMU_IO_PERM_XXX.
3789 * @param pAux The auxiliary information required during lookup.
3790 * @param pPageLookup Where to store the looked up I/O page.
3791 */
3792static DECLCALLBACK(int) iommuAmdDteLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
3793 PIOPAGELOOKUP pPageLookup)
3794{
3795 AssertPtr(pAux);
3796 AssertPtr(pPageLookup);
3797 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
3798
3799 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3800 STAM_PROFILE_ADV_START(&pThis->StatProfDteLookup, a);
3801 int rc = iommuAmdIoPageTableWalk(pDevIns, uIovaPage, fPerm, pAux->uDeviceId, pAux->pDte, pAux->enmOp, pPageLookup);
3802 STAM_PROFILE_ADV_STOP(&pThis->StatProfDteLookup, a); NOREF(pThis);
3803 return rc;
3804}
3805
3806
3807/**
3808 * Looks up a range of I/O virtual addresses.
3809 *
3810 * @returns VBox status code.
3811 * @param pDevIns The IOMMU instance data.
3812 * @param pfnIoPageLookup The lookup function to use.
3813 * @param pAddrIn The I/O address range to lookup.
3814 * @param pAux The auxiliary information required by the lookup
3815 * function.
3816 * @param pAddrOut Where to store the translated I/O address range.
3817 * @param pcbPages Where to store the size of the access (round up to
3818 * the page size). Optional, can be NULL.
3819 */
3820static int iommuAmdLookupIoAddrRange(PPDMDEVINS pDevIns, PFNIOPAGELOOKUP pfnIoPageLookup, PCIOADDRRANGE pAddrIn,
3821 PCIOMMUOPAUX pAux, PIOADDRRANGE pAddrOut, size_t *pcbPages)
3822{
3823 AssertPtr(pfnIoPageLookup);
3824 AssertPtr(pAddrIn);
3825 AssertPtr(pAddrOut);
3826
3827 int rc;
3828 size_t const cbAccess = pAddrIn->cb;
3829 uint8_t const fPerm = pAddrIn->fPerm;
3830 uint64_t const uIova = pAddrIn->uAddr;
3831 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3832 size_t cbRemaining = cbAccess;
3833 uint64_t uIovaPage = pAddrIn->uAddr & X86_PAGE_4K_BASE_MASK;
3834 uint64_t offIova = pAddrIn->uAddr & X86_PAGE_4K_OFFSET_MASK;
3835 uint64_t cbPages = 0;
3836
3837 IOPAGELOOKUP PageLookupPrev;
3838 RT_ZERO(PageLookupPrev);
3839 for (;;)
3840 {
3841 IOPAGELOOKUP PageLookup;
3842 rc = pfnIoPageLookup(pDevIns, uIovaPage, fPerm, pAux, &PageLookup);
3843 if (RT_SUCCESS(rc))
3844 {
3845 Assert(PageLookup.cShift >= X86_PAGE_4K_SHIFT);
3846
3847 /* Store the translated address before continuing to access more pages. */
3848 if (cbRemaining == cbAccess)
3849 {
3850 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(PageLookup.cShift);
3851 uint64_t const offSpa = uIova & offMask;
3852 Assert(!(PageLookup.GCPhysSpa & offMask));
3853 GCPhysSpa = PageLookup.GCPhysSpa | offSpa;
3854 }
3855 /* Check if addresses translated so far result in a physically contiguous region. */
3856 else if (!iommuAmdLookupIsAccessContig(&PageLookupPrev, &PageLookup))
3857 {
3858 rc = VERR_OUT_OF_RANGE;
3859 break;
3860 }
3861
3862 /* Store the page lookup result from the first/previous page. */
3863 PageLookupPrev = PageLookup;
3864
3865 /* Update size of all pages read thus far. */
3866 uint64_t const cbPage = RT_BIT_64(PageLookup.cShift);
3867 cbPages += cbPage;
3868
3869 /* Check if we need to access more pages. */
3870 if (cbRemaining > cbPage - offIova)
3871 {
3872 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3873 uIovaPage += cbPage; /* Update address of the next access. */
3874 offIova = 0; /* After first page, all pages are accessed from off 0. */
3875 }
3876 else
3877 {
3878 cbRemaining = 0;
3879 break;
3880 }
3881 }
3882 else
3883 break;
3884 }
3885
3886 pAddrOut->uAddr = GCPhysSpa; /* Update the translated address. */
3887 pAddrOut->cb = cbAccess - cbRemaining; /* Update the size of the contiguous memory region. */
3888 pAddrOut->fPerm = PageLookupPrev.fPerm; /* Update the allowed permissions for this access. */
3889 if (pcbPages)
3890 *pcbPages = cbPages; /* Update the size of the pages accessed. */
3891 return rc;
3892}
3893
3894
3895/**
3896 * Looks up an I/O virtual address from the device table.
3897 *
3898 * @returns VBox status code.
3899 * @param pDevIns The IOMMU instance data.
3900 * @param uDevId The device ID (bus, device, function).
3901 * @param uIova The I/O virtual address to lookup.
3902 * @param cbAccess The size of the access.
3903 * @param fPerm The I/O permissions for this access, see
3904 * IOMMU_IO_PERM_XXX.
3905 * @param enmOp The IOMMU operation being performed.
3906 * @param pGCPhysSpa Where to store the translated system physical address.
3907 * @param pcbContiguous Where to store the number of contiguous bytes translated
3908 * and permission-checked.
3909 *
3910 * @thread Any.
3911 */
3912static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fPerm, IOMMUOP enmOp,
3913 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3914{
3915 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3916 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3917 size_t cbContiguous = 0;
3918
3919 /* Read the device table entry from memory. */
3920 DTE_T Dte;
3921 int rc = iommuAmdDteRead(pDevIns, uDevId, enmOp, &Dte);
3922 if (RT_SUCCESS(rc))
3923 {
3924 if (Dte.n.u1Valid)
3925 {
3926 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
3927 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
3928 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
3929 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
3930 {
3931 /*
3932 * Check if the DTE is configured for translating addresses.
3933 * Note: Addresses cannot be subject to exclusion as we do -not- support remote IOTLBs,
3934 * so there's no need to check the address exclusion base/limit here.
3935 */
3936 rc = iommuAmdPreTranslateChecks(pDevIns, uDevId, uIova, fPerm, &Dte, enmOp);
3937 if (rc == VINF_SUCCESS)
3938 {
3939 IOADDRRANGE AddrIn;
3940 AddrIn.uAddr = uIova;
3941 AddrIn.cb = cbAccess;
3942 AddrIn.fPerm = fPerm;
3943
3944 IOMMUOPAUX Aux;
3945 Aux.enmOp = enmOp;
3946 Aux.pDte = &Dte;
3947 Aux.uDeviceId = uDevId;
3948 Aux.uDomainId = Dte.n.u16DomainId;
3949
3950 IOADDRRANGE AddrOut;
3951
3952 /* Lookup the address from the DTE and I/O page tables.*/
3953 size_t cbPages = 0;
3954 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdDteLookupPage, &AddrIn, &Aux, &AddrOut, &cbPages);
3955 GCPhysSpa = AddrOut.uAddr;
3956 cbContiguous = AddrOut.cb;
3957
3958 /* If we stopped since translation resulted in non-contiguous physical addresses,
3959 what we translated so far is still valid. */
3960 if (rc == VERR_OUT_OF_RANGE)
3961 {
3962 Assert(cbContiguous > 0 && cbContiguous < cbAccess);
3963 rc = VINF_SUCCESS;
3964 STAM_COUNTER_INC(&pThis->StatAccessDteNonContig); NOREF(pThis);
3965 }
3966
3967 if (rc == VERR_IOMMU_ADDR_ACCESS_DENIED)
3968 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
3969
3970#ifdef IOMMU_WITH_IOTLBE_CACHE
3971 if (RT_SUCCESS(rc))
3972 {
3973 /* Update that addresses requires translation (cumulative permissions of DTE and I/O page tables). */
3974 iommuAmdDteCacheAdd(pDevIns, uDevId, &Dte, IOMMU_DTE_CACHE_F_ADDR_TRANSLATE);
3975 /* Update IOTLB for the contiguous range of I/O virtual addresses. */
3976 iommuAmdIotlbAddRange(pDevIns, Dte.n.u16DomainId, uIova & X86_PAGE_4K_BASE_MASK, cbPages,
3977 GCPhysSpa & X86_PAGE_4K_BASE_MASK, AddrOut.fPerm);
3978 }
3979#endif
3980 }
3981 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
3982 {
3983 /*
3984 * Translation is disabled for this device (root paging mode is 0).
3985 * GPA=SPA, but the permission bits are important and controls accesses.
3986 */
3987 GCPhysSpa = uIova;
3988 cbContiguous = cbAccess;
3989 rc = VINF_SUCCESS;
3990
3991#ifdef IOMMU_WITH_IOTLBE_CACHE
3992 /* Update that addresses permissions of DTE apply (but omit address translation). */
3993 iommuAmdDteCacheAdd(pDevIns, uDevId, &Dte, IOMMU_DTE_CACHE_F_IO_PERM);
3994#endif
3995 }
3996 else
3997 {
3998 /* Address translation failed or access is denied. */
3999 Assert(rc == VERR_IOMMU_ADDR_ACCESS_DENIED || rc == VERR_IOMMU_ADDR_TRANSLATION_FAILED);
4000 GCPhysSpa = NIL_RTGCPHYS;
4001 cbContiguous = 0;
4002 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4003 }
4004 }
4005 else
4006 {
4007 /* Invalid reserved bits in the DTE, raise an error event. */
4008 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4009 EVT_ILLEGAL_DTE_T Event;
4010 iommuAmdIllegalDteEventInit(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4011 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4012 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4013 }
4014 }
4015 else
4016 {
4017 /*
4018 * The DTE is not valid, forward addresses untranslated.
4019 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
4020 */
4021 GCPhysSpa = uIova;
4022 cbContiguous = cbAccess;
4023
4024#ifdef IOMMU_WITH_IOTLBE_CACHE
4025 /* Update that addresses don't require translation (nor permission checks) but a DTE is present. */
4026 iommuAmdDteCacheAdd(pDevIns, uDevId, &Dte, 0 /* fFlags */);
4027#endif
4028 }
4029 }
4030 else
4031 {
4032 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4033 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4034 }
4035
4036 *pGCPhysSpa = GCPhysSpa;
4037 *pcbContiguous = cbContiguous;
4038 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
4039 return rc;
4040}
4041
4042
4043#ifdef IOMMU_WITH_IOTLBE_CACHE
4044/**
4045 * I/O page lookup callback for finding an I/O page from the IOTLB.
4046 *
4047 * @returns VBox status code.
4048 * @retval VINF_SUCCESS when the page is found and has the right permissions.
4049 * @retval VERR_NOT_FOUND when the page is not found.
4050 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
4051 * insufficient to what is requested.
4052 *
4053 * @param pDevIns The IOMMU instance data.
4054 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
4055 * 4K aligned).
4056 * @param fPerm The I/O permissions for this access, see
4057 * IOMMU_IO_PERM_XXX.
4058 * @param pAux The auxiliary information required during lookup.
4059 * @param pPageLookup Where to store the looked up I/O page.
4060 */
4061static DECLCALLBACK(int) iommuAmdCacheLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
4062 PIOPAGELOOKUP pPageLookup)
4063{
4064 Assert(pAux);
4065 Assert(pPageLookup);
4066 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
4067
4068 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4069 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4070
4071 STAM_PROFILE_ADV_START(&pThis->StatProfIotlbeLookup, a);
4072 PCIOTLBE pIotlbe = iommuAmdIotlbLookup(pThis, pThisR3, pAux->uDomainId, uIovaPage);
4073 STAM_PROFILE_ADV_STOP(&pThis->StatProfIotlbeLookup, a);
4074 if (pIotlbe)
4075 {
4076 *pPageLookup = pIotlbe->PageLookup;
4077 if ((pPageLookup->fPerm & fPerm) == fPerm)
4078 {
4079 STAM_COUNTER_INC(&pThis->StatAccessCacheHit);
4080 return VINF_SUCCESS;
4081 }
4082 return VERR_IOMMU_ADDR_ACCESS_DENIED;
4083 }
4084 return VERR_NOT_FOUND;
4085}
4086
4087
4088/**
4089 * Lookups a memory access from the IOMMU cache.
4090 *
4091 * @returns VBox status code.
4092 * @retval VINF_SUCCESS if the access was cached and permissions are verified.
4093 * @retval VERR_OUT_OF_RANGE if the access resulted in a non-contiguous physical
4094 * address region.
4095 * @retval VERR_NOT_FOUND if the access was not cached.
4096 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the access was cached but permissions
4097 * are insufficient.
4098 *
4099 * @param pDevIns The IOMMU instance data.
4100 * @param uDevId The device ID (bus, device, function).
4101 * @param uIova The I/O virtual address to lookup.
4102 * @param cbAccess The size of the access.
4103 * @param fPerm The I/O permissions for this access, see
4104 * IOMMU_IO_PERM_XXX.
4105 * @param enmOp The IOMMU operation being performed.
4106 * @param pGCPhysSpa Where to store the translated system physical address.
4107 * @param pcbContiguous Where to store the number of contiguous bytes translated
4108 * and permission-checked.
4109 */
4110static int iommuAmdCacheLookup(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fPerm, IOMMUOP enmOp,
4111 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4112{
4113 int rc;
4114 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4115
4116#define IOMMU_IOTLB_LOOKUP_FAILED(a_rc) \
4117 do { \
4118 *pGCPhysSpa = NIL_RTGCPHYS; \
4119 *pcbContiguous = 0; \
4120 rc = (a_rc); \
4121 } while (0)
4122
4123 /*
4124 * We hold the cache lock across both the DTE and the IOTLB lookups (if any) because
4125 * we don't want the DTE cache to be invalidate while we perform IOTBL lookups.
4126 */
4127 IOMMU_LOCK_CACHE(pDevIns, pThis);
4128
4129 /* Lookup the DTE cache entry. */
4130 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, uDevId);
4131 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
4132 {
4133 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
4134 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4135 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4136 {
4137 /* Lookup IOTLB entries. */
4138 IOADDRRANGE AddrIn;
4139 AddrIn.uAddr = uIova;
4140 AddrIn.cb = cbAccess;
4141 AddrIn.fPerm = fPerm;
4142
4143 IOMMUOPAUX Aux;
4144 Aux.enmOp = enmOp;
4145 Aux.pDte = NULL;
4146 Aux.uDeviceId = uDevId;
4147 Aux.uDomainId = pDteCache->uDomainId;
4148
4149 IOADDRRANGE AddrOut;
4150 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdCacheLookupPage, &AddrIn, &Aux, &AddrOut, NULL /* pcbPages */);
4151 Assert(AddrOut.cb <= cbAccess);
4152 *pGCPhysSpa = AddrOut.uAddr;
4153 *pcbContiguous = AddrOut.cb;
4154 }
4155 else if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4156 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4157 {
4158 /* Address translation is disabled, but DTE permissions apply. */
4159 Assert(!(pDteCache->fFlags & IOMMU_DTE_CACHE_F_ADDR_TRANSLATE));
4160 uint8_t const fDtePerm = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_IO_PERM_SHIFT) & IOMMU_DTE_CACHE_F_IO_PERM_MASK;
4161 if ((fDtePerm & fPerm) == fPerm)
4162 {
4163 *pGCPhysSpa = uIova;
4164 *pcbContiguous = cbAccess;
4165 rc = VINF_SUCCESS;
4166 }
4167 else
4168 IOMMU_IOTLB_LOOKUP_FAILED(VERR_IOMMU_ADDR_ACCESS_DENIED);
4169 }
4170 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
4171 {
4172 /* Forward addresses untranslated, without checking permissions. */
4173 *pGCPhysSpa = uIova;
4174 *pcbContiguous = cbAccess;
4175 rc = VINF_SUCCESS;
4176 }
4177 else
4178 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4179 }
4180 else
4181 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4182
4183 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
4184
4185 return rc;
4186
4187#undef IOMMU_IOTLB_LOOKUP_FAILED
4188}
4189#endif /* IOMMU_WITH_IOTLBE_CACHE */
4190
4191
4192/**
4193 * Gets the I/O permission and IOMMU operation type for the given access flags.
4194 *
4195 * @param pThis The shared IOMMU device state.
4196 * @param fFlags The PDM IOMMU flags, PDMIOMMU_MEM_F_XXX.
4197 * @param penmOp Where to store the IOMMU operation.
4198 * @param pfPerm Where to store the IOMMU I/O permission.
4199 * @param fBulk Whether this is a bulk read or write.
4200 */
4201DECLINLINE(void) iommuAmdMemAccessGetPermAndOp(PIOMMU pThis, uint32_t fFlags, PIOMMUOP penmOp, uint8_t *pfPerm, bool fBulk)
4202{
4203 if (fFlags & PDMIOMMU_MEM_F_WRITE)
4204 {
4205 *penmOp = IOMMUOP_MEM_WRITE;
4206 *pfPerm = IOMMU_IO_PERM_WRITE;
4207#ifdef VBOX_WITH_STATISTICS
4208 if (!fBulk)
4209 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
4210 else
4211 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
4212#else
4213 RT_NOREF2(pThis, fBulk);
4214#endif
4215 }
4216 else
4217 {
4218 Assert(fFlags & PDMIOMMU_MEM_F_READ);
4219 *penmOp = IOMMUOP_MEM_READ;
4220 *pfPerm = IOMMU_IO_PERM_READ;
4221#ifdef VBOX_WITH_STATISTICS
4222 if (!fBulk)
4223 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
4224 else
4225 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
4226#else
4227 RT_NOREF2(pThis, fBulk);
4228#endif
4229 }
4230}
4231
4232
4233/**
4234 * Memory access transaction from a device.
4235 *
4236 * @returns VBox status code.
4237 * @param pDevIns The IOMMU device instance.
4238 * @param uDevId The device ID (bus, device, function).
4239 * @param uIova The I/O virtual address being accessed.
4240 * @param cbAccess The number of bytes being accessed.
4241 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4242 * @param pGCPhysSpa Where to store the translated system physical address.
4243 * @param pcbContiguous Where to store the number of contiguous bytes translated
4244 * and permission-checked.
4245 *
4246 * @thread Any.
4247 */
4248static DECLCALLBACK(int) iommuAmdMemAccess(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint32_t fFlags,
4249 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4250{
4251 /* Validate. */
4252 AssertPtr(pDevIns);
4253 AssertPtr(pGCPhysSpa);
4254 Assert(cbAccess > 0);
4255 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4256
4257 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4258 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4259 if (Ctrl.n.u1IommuEn)
4260 {
4261 IOMMUOP enmOp;
4262 uint8_t fPerm;
4263 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, false /* fBulk */);
4264 LogFlowFunc(("%s: uDevId=%#x uIova=%#RX64 cb=%zu\n", iommuAmdMemAccessGetPermName(fPerm), uDevId, uIova, cbAccess));
4265
4266 int rc;
4267#ifdef IOMMU_WITH_IOTLBE_CACHE
4268 /* Lookup the IOVA from the cache. */
4269 rc = iommuAmdCacheLookup(pDevIns, uDevId, uIova, cbAccess, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4270 if (rc == VINF_SUCCESS)
4271 {
4272 /* All pages in the access were found in the cache with sufficient permissions. */
4273 Assert(*pcbContiguous == cbAccess);
4274 Assert(*pGCPhysSpa != NIL_RTGCPHYS);
4275 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4276 return rc;
4277 }
4278 if (rc != VERR_OUT_OF_RANGE)
4279 { /* likely */ }
4280 else
4281 {
4282 /* Access stopped since translations resulted in non-contiguous memory, let caller resume access. */
4283 Assert(*pcbContiguous > 0 && *pcbContiguous < cbAccess);
4284 STAM_COUNTER_INC(&pThis->StatAccessCacheNonContig);
4285 return VINF_SUCCESS;
4286 }
4287
4288 /*
4289 * Access incomplete as not all pages were in the cache.
4290 * Or permissions were denied for the access (which typically doesn't happen)
4291 * so go through the slower path and raise the required event.
4292 */
4293 AssertMsg(*pcbContiguous < cbAccess, ("Invalid size: cbContiguous=%zu cbAccess=%zu\n", *pcbContiguous, cbAccess));
4294 uIova += *pcbContiguous;
4295 cbAccess -= *pcbContiguous;
4296 /* We currently are including any permission denied pages as cache misses too.*/
4297 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4298#endif
4299
4300 /* Lookup the IOVA from the device table. */
4301 rc = iommuAmdDteLookup(pDevIns, uDevId, uIova, cbAccess, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4302 if (RT_SUCCESS(rc))
4303 { /* likely */ }
4304 else
4305 {
4306 Assert(rc != VERR_OUT_OF_RANGE);
4307 LogFunc(("DTE lookup failed! uDevId=%#x uIova=%#RX64 fPerm=%u cbAccess=%zu rc=%#Rrc\n", uDevId, uIova, fPerm,
4308 cbAccess, rc));
4309 }
4310
4311 return rc;
4312 }
4313
4314 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4315 *pGCPhysSpa = uIova;
4316 *pcbContiguous = cbAccess;
4317 return VINF_SUCCESS;
4318}
4319
4320
4321/**
4322 * Memory access bulk (one or more 4K pages) request from a device.
4323 *
4324 * @returns VBox status code.
4325 * @param pDevIns The IOMMU device instance.
4326 * @param uDevId The device ID (bus, device, function).
4327 * @param cIovas The number of addresses being accessed.
4328 * @param pauIovas The I/O virtual addresses for each page being accessed.
4329 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4330 * @param paGCPhysSpa Where to store the translated physical addresses.
4331 *
4332 * @thread Any.
4333 */
4334static DECLCALLBACK(int) iommuAmdMemBulkAccess(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
4335 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
4336{
4337 /* Validate. */
4338 AssertPtr(pDevIns);
4339 Assert(cIovas > 0);
4340 AssertPtr(pauIovas);
4341 AssertPtr(paGCPhysSpa);
4342 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4343
4344 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4345 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4346 if (Ctrl.n.u1IommuEn)
4347 {
4348 IOMMUOP enmOp;
4349 uint8_t fPerm;
4350 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, true /* fBulk */);
4351 LogFlowFunc(("%s: uDevId=%#x cIovas=%zu\n", iommuAmdMemAccessGetPermName(fPerm), uDevId, cIovas));
4352
4353 /** @todo IOMMU: IOTLB cache lookup. */
4354
4355 /* Lookup each IOVA from the device table. */
4356 for (size_t i = 0; i < cIovas; i++)
4357 {
4358 size_t cbContig;
4359 int rc = iommuAmdDteLookup(pDevIns, uDevId, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i], &cbContig);
4360 if (RT_SUCCESS(rc))
4361 { /* likely */ }
4362 else
4363 {
4364 LogFunc(("Failed! uDevId=%#x uIova=%#RX64 fPerm=%u rc=%Rrc\n", uDevId, pauIovas[i], fPerm, rc));
4365 return rc;
4366 }
4367 Assert(cbContig == X86_PAGE_SIZE);
4368 }
4369 }
4370 else
4371 {
4372 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4373 for (size_t i = 0; i < cIovas; i++)
4374 paGCPhysSpa[i] = pauIovas[i];
4375 }
4376
4377 return VINF_SUCCESS;
4378}
4379
4380
4381/**
4382 * Reads an interrupt remapping table entry from guest memory given its DTE.
4383 *
4384 * @returns VBox status code.
4385 * @param pDevIns The IOMMU device instance.
4386 * @param uDevId The device ID (bus, device, function).
4387 * @param pDte The device table entry.
4388 * @param GCPhysIn The source MSI address (used for reporting errors).
4389 * @param uDataIn The source MSI data.
4390 * @param enmOp The IOMMU operation being performed.
4391 * @param pIrte Where to store the interrupt remapping table entry.
4392 *
4393 * @thread Any.
4394 */
4395static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4396 IOMMUOP enmOp, PIRTE_T pIrte)
4397{
4398 /* Ensure the IRTE length is valid. */
4399 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
4400
4401 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4402 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
4403 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(uDataIn);
4404 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4405
4406 /* Ensure the IRTE falls completely within the interrupt table. */
4407 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
4408 { /* likely */ }
4409 else
4410 {
4411 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
4412 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
4413
4414 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4415 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
4416 false /* fPermDenied */, enmOp, &EvtIoPageFault);
4417 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4418 kIoPageFaultType_IrteAddrInvalid);
4419 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4420 }
4421
4422 /* Read the IRTE from memory. */
4423 Assert(!(GCPhysIrte & 3));
4424 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4425 if (RT_SUCCESS(rc))
4426 return VINF_SUCCESS;
4427
4428 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
4429 * situation. Is it an I/O page fault or a device table hardware error?
4430 * There's no interrupt table hardware error event, but it's unclear what
4431 * we should do here. */
4432 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4433 return VERR_IOMMU_IPE_4;
4434}
4435
4436
4437/**
4438 * Remaps the interrupt using the interrupt remapping table.
4439 *
4440 * @returns VBox status code.
4441 * @param pDevIns The IOMMU instance data.
4442 * @param uDevId The device ID (bus, device, function).
4443 * @param pDte The device table entry.
4444 * @param enmOp The IOMMU operation being performed.
4445 * @param pMsiIn The source MSI.
4446 * @param pMsiOut Where to store the remapped MSI.
4447 *
4448 * @thread Any.
4449 */
4450static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4451 PMSIMSG pMsiOut)
4452{
4453 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4454
4455 IRTE_T Irte;
4456 uint32_t const uMsiInData = pMsiIn->Data.u32;
4457 int rc = iommuAmdIrteRead(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, uMsiInData, enmOp, &Irte);
4458 if (RT_SUCCESS(rc))
4459 {
4460 if (Irte.n.u1RemapEnable)
4461 {
4462 if (!Irte.n.u1GuestMode)
4463 {
4464 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4465 {
4466 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, &Irte);
4467#ifdef IOMMU_WITH_IRTE_CACHE
4468 iommuAmdIrteCacheAdd(pDevIns, uDevId, IOMMU_GET_IRTE_OFF(uMsiInData), &Irte);
4469#endif
4470 return VINF_SUCCESS;
4471 }
4472
4473 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
4474 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4475 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4476 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4477 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault,
4478 kIoPageFaultType_IrteRsvdIntType);
4479 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4480 }
4481
4482 LogFunc(("Guest mode not supported -> IOPF\n"));
4483 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4484 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4485 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4486 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4487 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4488 }
4489
4490 LogFunc(("Remapping disabled -> IOPF\n"));
4491 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4492 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4493 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4494 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4495 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4496 }
4497
4498 return rc;
4499}
4500
4501
4502/**
4503 * Looks up an MSI interrupt from the interrupt remapping table.
4504 *
4505 * @returns VBox status code.
4506 * @param pDevIns The IOMMU instance data.
4507 * @param uDevId The device ID (bus, device, function).
4508 * @param enmOp The IOMMU operation being performed.
4509 * @param pMsiIn The source MSI.
4510 * @param pMsiOut Where to store the remapped MSI.
4511 *
4512 * @thread Any.
4513 */
4514static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4515{
4516 LogFlowFunc(("uDevId=%#x (%#x:%#x:%#x) enmOp=%u\n", uDevId,
4517 ((uDevId >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
4518 ((uDevId >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (uDevId & VBOX_PCI_DEVFN_FUN_MASK), enmOp));
4519
4520 /* Read the device table entry from memory. */
4521 DTE_T Dte;
4522 int rc = iommuAmdDteRead(pDevIns, uDevId, enmOp, &Dte);
4523 if (RT_SUCCESS(rc))
4524 {
4525#ifdef IOMMU_WITH_IRTE_CACHE
4526 iommuAmdDteCacheAdd(pDevIns, uDevId, &Dte, 0 /* fFlags */);
4527#endif
4528 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
4529 if (Dte.n.u1IntrMapValid)
4530 {
4531 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4532 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4533 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4534 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4535 { /* likely */ }
4536 else
4537 {
4538 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4539 EVT_ILLEGAL_DTE_T Event;
4540 iommuAmdIllegalDteEventInit(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4541 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4542 return VERR_IOMMU_INTR_REMAP_FAILED;
4543 }
4544
4545 /*
4546 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4547 * that's connected through HyperTransport it might be possible; but for us, it
4548 * doesn't seem we need to specially handle these pins.
4549 */
4550
4551 /*
4552 * Validate the MSI source address.
4553 *
4554 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4555 * CPU is concerned, the MSI region is fixed and we must ensure no other device
4556 * claims the region as I/O space.
4557 *
4558 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4559 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4560 * See Intel spec. 10.11.1 "Message Address Register Format".
4561 */
4562 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4563 {
4564 /*
4565 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4566 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4567 */
4568 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4569 bool fPassThru = false;
4570 switch (u8DeliveryMode)
4571 {
4572 case VBOX_MSI_DELIVERY_MODE_FIXED:
4573 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4574 {
4575 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4576 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4577 {
4578 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4579 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
4580 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4581 {
4582 /*
4583 * We don't support guest interrupt remapping yet. When we do, we'll need to
4584 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4585 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4586 * already reads the control register, add that as a parameter when we eventually
4587 * support guest interrupt remapping. For now, just assert.
4588 */
4589 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4590 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4591 NOREF(pThis);
4592
4593 return iommuAmdIntrRemap(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
4594 }
4595
4596 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
4597 EVT_ILLEGAL_DTE_T Event;
4598 iommuAmdIllegalDteEventInit(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4599 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4600 return VERR_IOMMU_INTR_REMAP_FAILED;
4601 }
4602
4603 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4604 {
4605 fPassThru = true;
4606 break;
4607 }
4608
4609 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4610 {
4611 LogFunc(("IntCtl=0: Remapping disallowed for fixed/arbitrated interrupt (%#x) -> Target abort\n",
4612 pMsiIn->Data.n.u8Vector));
4613 iommuAmdSetPciTargetAbort(pDevIns);
4614 return VERR_IOMMU_INTR_REMAP_DENIED;
4615 }
4616
4617 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
4618 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
4619 EVT_ILLEGAL_DTE_T Event;
4620 iommuAmdIllegalDteEventInit(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4621 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4622 return VERR_IOMMU_INTR_REMAP_FAILED;
4623 }
4624
4625 /* SMIs are passed through unmapped. We don't implement SMI filters. */
4626 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4627 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4628 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4629 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4630 default:
4631 {
4632 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
4633 iommuAmdSetPciTargetAbort(pDevIns);
4634 return VERR_IOMMU_INTR_REMAP_FAILED;
4635 }
4636 }
4637
4638 /*
4639 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
4640 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
4641 */
4642 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
4643 || !pMsiIn->Addr.n.u1DestMode)
4644 {
4645 if (fPassThru)
4646 {
4647 *pMsiOut = *pMsiIn;
4648 return VINF_SUCCESS;
4649 }
4650 LogFunc(("Remapping/passthru disallowed for interrupt %#x -> Target abort\n", pMsiIn->Data.n.u8Vector));
4651 }
4652 else
4653 LogFunc(("Logical destination mode invalid for delivery mode %#x\n -> Target abort\n", u8DeliveryMode));
4654
4655 iommuAmdSetPciTargetAbort(pDevIns);
4656 return VERR_IOMMU_INTR_REMAP_DENIED;
4657 }
4658 else
4659 {
4660 /** @todo should be cause a PCI target abort here? */
4661 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
4662 return VERR_IOMMU_INTR_REMAP_FAILED;
4663 }
4664 }
4665 else
4666 {
4667 LogFlowFunc(("DTE interrupt map not valid\n"));
4668 *pMsiOut = *pMsiIn;
4669 return VINF_SUCCESS;
4670 }
4671 }
4672
4673 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4674 return VERR_IOMMU_INTR_REMAP_FAILED;
4675}
4676
4677
4678/**
4679 * Interrupt remap request from a device.
4680 *
4681 * @returns VBox status code.
4682 * @param pDevIns The IOMMU device instance.
4683 * @param uDevId The device ID (bus, device, function).
4684 * @param pMsiIn The source MSI.
4685 * @param pMsiOut Where to store the remapped MSI.
4686 */
4687static DECLCALLBACK(int) iommuAmdMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4688{
4689 /* Validate. */
4690 Assert(pDevIns);
4691 Assert(pMsiIn);
4692 Assert(pMsiOut);
4693
4694 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4695
4696 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4697 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4698 if (Ctrl.n.u1IommuEn)
4699 {
4700 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
4701
4702 int rc;
4703#ifdef IOMMU_WITH_IRTE_CACHE
4704 STAM_PROFILE_ADV_START(&pThis->StatProfIrteCacheLookup, a);
4705 rc = iommuAmdIrteCacheLookup(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4706 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteCacheLookup, a);
4707 if (RT_SUCCESS(rc))
4708 {
4709 STAM_COUNTER_INC(&pThis->StatIntrCacheHit);
4710 return VINF_SUCCESS;
4711 }
4712 STAM_COUNTER_INC(&pThis->StatIntrCacheMiss);
4713#endif
4714
4715 STAM_PROFILE_ADV_START(&pThis->StatProfIrteLookup, a);
4716 rc = iommuAmdIntrTableLookup(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4717 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteLookup, a);
4718 return rc;
4719 }
4720
4721 *pMsiOut = *pMsiIn;
4722 return VINF_SUCCESS;
4723}
4724
4725
4726/**
4727 * @callback_method_impl{FNIOMMMIONEWWRITE}
4728 */
4729static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
4730{
4731 NOREF(pvUser);
4732 Assert(cb == 4 || cb == 8);
4733 Assert(!(off & (cb - 1)));
4734
4735 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4736 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
4737
4738 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
4739 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
4740}
4741
4742
4743/**
4744 * @callback_method_impl{FNIOMMMIONEWREAD}
4745 */
4746static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
4747{
4748 NOREF(pvUser);
4749 Assert(cb == 4 || cb == 8);
4750 Assert(!(off & (cb - 1)));
4751
4752 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4753 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
4754
4755 uint64_t uResult;
4756 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
4757 if (cb == 8)
4758 *(uint64_t *)pv = uResult;
4759 else
4760 *(uint32_t *)pv = (uint32_t)uResult;
4761
4762 return rcStrict;
4763}
4764
4765
4766#ifdef IN_RING3
4767/**
4768 * Processes an IOMMU command.
4769 *
4770 * @returns VBox status code.
4771 * @param pDevIns The IOMMU device instance.
4772 * @param pCmd The command to process.
4773 * @param GCPhysCmd The system physical address of the command.
4774 * @param pEvtError Where to store the error event in case of failures.
4775 *
4776 * @thread Command thread.
4777 */
4778static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4779{
4780 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4781 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4782
4783 STAM_COUNTER_INC(&pThis->StatCmd);
4784
4785 uint8_t const bCmd = pCmd->n.u4Opcode;
4786 switch (bCmd)
4787 {
4788 case IOMMU_CMD_COMPLETION_WAIT:
4789 {
4790 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
4791
4792 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4793 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
4794
4795 /* Validate reserved bits in the command. */
4796 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4797 {
4798 /* If Completion Store is requested, write the StoreData to the specified address. */
4799 if (pCmdComWait->n.u1Store)
4800 {
4801 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4802 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4803 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4804 if (RT_FAILURE(rc))
4805 {
4806 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4807 GCPhysStore, rc));
4808 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4809 return VERR_IOMMU_CMD_HW_ERROR;
4810 }
4811 }
4812
4813 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4814 if (pCmdComWait->n.u1Interrupt)
4815 {
4816 IOMMU_LOCK(pDevIns, pThisR3);
4817 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4818 bool const fRaiseInt = pThis->Ctrl.n.u1CompWaitIntrEn;
4819 IOMMU_UNLOCK(pDevIns, pThisR3);
4820
4821 if (fRaiseInt)
4822 iommuAmdMsiInterruptRaise(pDevIns);
4823 }
4824 return VINF_SUCCESS;
4825 }
4826 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4827 return VERR_IOMMU_CMD_INVALID_FORMAT;
4828 }
4829
4830 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4831 {
4832 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
4833 PCCMD_INV_DTE_T pCmdInvDte = (PCCMD_INV_DTE_T)pCmd;
4834 AssertCompile(sizeof(*pCmdInvDte) == sizeof(*pCmd));
4835
4836 /* Validate reserved bits in the command. */
4837 if ( !(pCmdInvDte->au64[0] & ~IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK)
4838 && !(pCmdInvDte->au64[1] & ~IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK))
4839 {
4840#ifdef IOMMU_WITH_DTE_CACHE
4841 iommuAmdDteCacheRemove(pDevIns, pCmdInvDte->n.u16DevId);
4842#endif
4843 return VINF_SUCCESS;
4844 }
4845 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4846 return VERR_IOMMU_CMD_INVALID_FORMAT;
4847 }
4848
4849 case IOMMU_CMD_INV_IOMMU_PAGES:
4850 {
4851 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
4852 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
4853 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
4854
4855 /* Validate reserved bits in the command. */
4856 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
4857 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
4858 {
4859#ifdef IOMMU_WITH_IOTLBE_CACHE
4860 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
4861 uint16_t const uDomainId = pCmdInvPages->n.u16DomainId;
4862 bool const fFlushPde = pCmdInvPages->n.u1PageDirEntries;
4863 uint8_t cShift;
4864 if (!pCmdInvPages->n.u1Size)
4865 cShift = X86_PAGE_4K_SHIFT;
4866 else
4867 {
4868 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
4869 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
4870 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
4871
4872 /*
4873 * For the address 0x7ffffffffffff000, cShift would be 76 (12+64) and the code below
4874 * would do the right thing by clearing the entire cache for the specified domain ID.
4875 *
4876 * However, for the address 0xfffffffffffff000, cShift would be computed as 12.
4877 * IOMMU behavior is undefined in this case, so it's safe to invalidate just one page.
4878 * A debug-time assert is in place here to let us know if any software tries this.
4879 *
4880 * See AMD IOMMU spec. 2.4.3 "INVALIDATE_IOMMU_PAGES".
4881 * See AMD IOMMU spec. Table 14: "Example Page Size Encodings".
4882 */
4883 Assert(uIova != UINT64_C(0xfffffffffffff000));
4884 }
4885
4886 /*
4887 * Validate invalidation size.
4888 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
4889 */
4890 if ( cShift == 12 /* 4K */ || cShift == 13 /* 8K */
4891 || cShift == 14 /* 16K */ || cShift == 20 /* 1M */
4892 || cShift == 22 /* 4M */ || cShift == 32 /* 4G */)
4893 {
4894 /* Remove the range of I/O virtual addresses requesting to be invalidated. */
4895 size_t const cbAccess = RT_BIT_64(cShift);
4896 iommuAmdIotlbRemoveRange(pDevIns, uDomainId, uIova, cbAccess);
4897 }
4898 else
4899 {
4900 /*
4901 * The guest provided size is invalid or exceeds the largest, meaningful page size.
4902 * In such situations we must remove all ranges for the specified domain ID.
4903 */
4904 iommuAmdIotlbRemoveDomainId(pDevIns, uDomainId);
4905 }
4906#endif
4907 return VINF_SUCCESS;
4908 }
4909 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4910 return VERR_IOMMU_CMD_INVALID_FORMAT;
4911 }
4912
4913 case IOMMU_CMD_INV_IOTLB_PAGES:
4914 {
4915 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
4916
4917 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
4918 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
4919 {
4920 /** @todo IOMMU: Implement remote IOTLB invalidation. */
4921 return VERR_NOT_IMPLEMENTED;
4922 }
4923 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4924 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4925 }
4926
4927 case IOMMU_CMD_INV_INTR_TABLE:
4928 {
4929 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
4930
4931 PCCMD_INV_INTR_TABLE_T pCmdInvIntrTable = (PCCMD_INV_INTR_TABLE_T)pCmd;
4932 AssertCompile(sizeof(*pCmdInvIntrTable) == sizeof(*pCmd));
4933
4934 /* Validate reserved bits in the command. */
4935 if ( !(pCmdInvIntrTable->au64[0] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_0_VALID_MASK)
4936 && !(pCmdInvIntrTable->au64[1] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_1_VALID_MASK))
4937 {
4938#ifdef IOMMU_WITH_IRTE_CACHE
4939 iommuAmdIrteCacheRemove(pDevIns, pCmdInvIntrTable->u.u16DevId);
4940#endif
4941 return VINF_SUCCESS;
4942 }
4943 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4944 return VERR_IOMMU_CMD_INVALID_FORMAT;
4945 }
4946
4947 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
4948 {
4949 /* Linux doesn't use prefetching of IOMMU pages, so we don't bother for now. */
4950 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
4951 Assert(!pThis->ExtFeat.n.u1PrefetchSup);
4952 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4953 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4954 }
4955
4956 case IOMMU_CMD_COMPLETE_PPR_REQ:
4957 {
4958 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
4959
4960 /* We don't support PPR requests yet. */
4961 Assert(!pThis->ExtFeat.n.u1PprSup);
4962 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4963 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4964 }
4965
4966 case IOMMU_CMD_INV_IOMMU_ALL:
4967 {
4968 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
4969 if (pThis->ExtFeat.n.u1InvAllSup)
4970 {
4971 PCCMD_INV_IOMMU_ALL_T pCmdInvAll = (PCCMD_INV_IOMMU_ALL_T)pCmd;
4972 AssertCompile(sizeof(*pCmdInvAll) == sizeof(*pCmd));
4973
4974 /* Validate reserved bits in the command. */
4975 if ( !(pCmdInvAll->au64[0] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK)
4976 && !(pCmdInvAll->au64[1] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK))
4977 {
4978#ifdef IOMMU_WITH_DTE_CACHE
4979 iommuAmdDteCacheRemoveAll(pDevIns);
4980#endif
4981#ifdef IOMMU_WITH_IOTLBE_CACHE
4982 iommuAmdIotlbRemoveAll(pDevIns);
4983#endif
4984 return VINF_SUCCESS;
4985 }
4986 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4987 return VERR_IOMMU_CMD_INVALID_FORMAT;
4988 }
4989 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4990 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4991 }
4992 }
4993
4994 STAM_COUNTER_DEC(&pThis->StatCmd);
4995 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
4996 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4997 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4998}
4999
5000
5001/**
5002 * The IOMMU command thread.
5003 *
5004 * @returns VBox status code.
5005 * @param pDevIns The IOMMU device instance.
5006 * @param pThread The command thread.
5007 */
5008static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5009{
5010 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5011 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5012
5013 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5014 return VINF_SUCCESS;
5015
5016 /*
5017 * Pre-allocate the maximum command buffer size supported by the IOMMU.
5018 * This avoid trashing the heap as well as not wasting time allocating
5019 * and freeing buffers while processing commands.
5020 */
5021 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
5022 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
5023 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
5024
5025 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5026 {
5027 /*
5028 * Sleep perpetually until we are woken up to process commands.
5029 */
5030 bool const fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
5031 if (!fSignaled)
5032 {
5033 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5034 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
5035 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5036 break;
5037 Log4Func(("Woken up with rc=%Rrc\n", rc));
5038 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5039 }
5040
5041 /*
5042 * Fetch and process IOMMU commands.
5043 */
5044 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
5045 * temporary host buffer before processing them as a batch. If we want to
5046 * save on host memory a bit, we could (once PGM has the necessary APIs)
5047 * lock the page mappings page mappings and access them directly. */
5048 IOMMU_LOCK(pDevIns, pThisR3);
5049
5050 if (pThis->Status.n.u1CmdBufRunning)
5051 {
5052 /* Get the offsets we need to read commands from memory (circular buffer offset). */
5053 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5054 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
5055 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5056
5057 /* Validate. */
5058 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5059 Assert(offHead < cbCmdBuf);
5060 Assert(cbCmdBuf <= cbMaxCmdBuf);
5061
5062 if (offHead != offTail)
5063 {
5064 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
5065 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
5066
5067 IOMMU_UNLOCK(pDevIns, pThisR3);
5068 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
5069 IOMMU_LOCK(pDevIns, pThisR3);
5070
5071 if (RT_SUCCESS(rc))
5072 {
5073 /* Indicate to software we've fetched all commands from the buffer. */
5074 pThis->CmdBufHeadPtr.n.off = offTail;
5075
5076 /* Allow IOMMU to do other work while we process commands. */
5077 IOMMU_UNLOCK(pDevIns, pThisR3);
5078
5079 /* Process the fetched commands. */
5080 EVT_GENERIC_T EvtError;
5081 do
5082 {
5083 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
5084 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
5085 if (RT_FAILURE(rc))
5086 {
5087 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5088 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5089 {
5090 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5091 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5092 }
5093 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5094 {
5095 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5096 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
5097 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5098 }
5099 break;
5100 }
5101
5102 /* Move to the next command in the circular buffer. */
5103 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5104 } while (offHead != offTail);
5105 }
5106 else
5107 {
5108 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
5109 EVT_CMD_HW_ERR_T EvtCmdHwErr;
5110 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
5111 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
5112
5113 IOMMU_UNLOCK(pDevIns, pThisR3);
5114 }
5115 }
5116 else
5117 IOMMU_UNLOCK(pDevIns, pThisR3);
5118 }
5119 else
5120 IOMMU_UNLOCK(pDevIns, pThisR3);
5121 }
5122
5123 RTMemFree(pvCmds);
5124 LogFlowFunc(("Command thread terminating\n"));
5125 return VINF_SUCCESS;
5126}
5127
5128
5129/**
5130 * Wakes up the command thread so it can respond to a state change.
5131 *
5132 * @returns VBox status code.
5133 * @param pDevIns The IOMMU device instance.
5134 * @param pThread The command thread.
5135 */
5136static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5137{
5138 RT_NOREF(pThread);
5139 LogFlowFunc(("\n"));
5140 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5141 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5142}
5143
5144
5145/**
5146 * @callback_method_impl{FNPCICONFIGREAD}
5147 */
5148static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5149 unsigned cb, uint32_t *pu32Value)
5150{
5151 /** @todo IOMMU: PCI config read stat counter. */
5152 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5153 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
5154 return rcStrict;
5155}
5156
5157
5158/**
5159 * Sets up the IOMMU MMIO region (usually in response to an IOMMU base address
5160 * register write).
5161 *
5162 * @returns VBox status code.
5163 * @param pDevIns The IOMMU instance data.
5164 *
5165 * @remarks Call this function only when the IOMMU BAR is enabled.
5166 */
5167static int iommuAmdR3MmioSetup(PPDMDEVINS pDevIns)
5168{
5169 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5170 Assert(pThis->IommuBar.n.u1Enable);
5171 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
5172 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5173 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5174 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
5175
5176 /* If the MMIO region is already mapped at the specified address, we're done. */
5177 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
5178 if (GCPhysMmioBasePrev == GCPhysMmioBase)
5179 return VINF_SUCCESS;
5180
5181 /* Unmap the previous MMIO region (which is at a different address). */
5182 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
5183 {
5184 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
5185 int rc = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
5186 if (RT_FAILURE(rc))
5187 {
5188 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", rc));
5189 return rc;
5190 }
5191 }
5192
5193 /* Map the newly specified MMIO region. */
5194 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
5195 int rc = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5196 if (RT_FAILURE(rc))
5197 {
5198 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", rc));
5199 return rc;
5200 }
5201
5202 return VINF_SUCCESS;
5203}
5204
5205
5206/**
5207 * @callback_method_impl{FNPCICONFIGWRITE}
5208 */
5209static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5210 unsigned cb, uint32_t u32Value)
5211{
5212 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5213
5214 /*
5215 * Discard writes to read-only registers that are specific to the IOMMU.
5216 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5217 * See PCI spec. 6.1. "Configuration Space Organization".
5218 */
5219 switch (uAddress)
5220 {
5221 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5222 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5223 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5224 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5225 {
5226 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5227 return VINF_SUCCESS;
5228 }
5229 }
5230
5231 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5232 IOMMU_LOCK(pDevIns, pThisR3);
5233
5234 VBOXSTRICTRC rcStrict;
5235 switch (uAddress)
5236 {
5237 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5238 {
5239 if (!pThis->IommuBar.n.u1Enable)
5240 {
5241 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5242 if (pThis->IommuBar.n.u1Enable)
5243 rcStrict = iommuAmdR3MmioSetup(pDevIns);
5244 else
5245 rcStrict = VINF_SUCCESS;
5246 }
5247 else
5248 {
5249 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5250 rcStrict = VINF_SUCCESS;
5251 }
5252 break;
5253 }
5254
5255 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5256 {
5257 if (!pThis->IommuBar.n.u1Enable)
5258 {
5259 AssertCompile((IOMMU_BAR_VALID_MASK >> 32) == 0xffffffff);
5260 pThis->IommuBar.au32[1] = u32Value;
5261 }
5262 else
5263 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5264 rcStrict = VINF_SUCCESS;
5265 break;
5266 }
5267
5268 case IOMMU_PCI_OFF_MSI_CAP_HDR:
5269 {
5270 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5271 RT_FALL_THRU();
5272 }
5273 default:
5274 {
5275 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5276 break;
5277 }
5278 }
5279
5280 IOMMU_UNLOCK(pDevIns, pThisR3);
5281
5282 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
5283 return rcStrict;
5284}
5285
5286
5287/**
5288 * @callback_method_impl{FNDBGFHANDLERDEV}
5289 */
5290static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5291{
5292 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5293 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5294 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5295
5296 bool fVerbose;
5297 if ( pszArgs
5298 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
5299 fVerbose = true;
5300 else
5301 fVerbose = false;
5302
5303 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5304 /* Device Table Base Addresses (all segments). */
5305 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5306 {
5307 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5308 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
5309 if (fVerbose)
5310 {
5311 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5312 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
5313 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5314 DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5315 }
5316 }
5317 /* Command Buffer Base Address Register. */
5318 {
5319 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5320 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5321 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5322 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5323 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
5324 if (fVerbose)
5325 {
5326 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5327 CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5328 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5329 cEntries, cbBuffer);
5330 }
5331 }
5332 /* Event Log Base Address Register. */
5333 {
5334 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5335 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5336 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5337 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5338 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
5339 if (fVerbose)
5340 {
5341 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5342 EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5343 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5344 cEntries, cbBuffer);
5345 }
5346 }
5347 /* IOMMU Control Register. */
5348 {
5349 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5350 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5351 if (fVerbose)
5352 {
5353 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5354 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5355 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5356 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5357 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5358 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5359 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5360 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5361 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5362 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5363 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5364 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5365 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5366 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5367 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5368 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5369 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5370 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5371 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5372 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5373 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5374 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5375 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5376 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5377 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5378 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5379 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5380 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5381 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5382 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5383 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5384 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5385 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5386 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5387 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5388 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5389 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5390 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5391 }
5392 }
5393 /* Exclusion Base Address Register. */
5394 {
5395 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5396 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5397 if (fVerbose)
5398 {
5399 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5400 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5401 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5402 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5403 }
5404 }
5405 /* Exclusion Range Limit Register. */
5406 {
5407 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5408 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5409 if (fVerbose)
5410 {
5411 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n",
5412 (ExclRangeLimit.n.u40ExclRangeLimit << X86_PAGE_4K_SHIFT) | X86_PAGE_4K_OFFSET_MASK);
5413 }
5414 }
5415 /* Extended Feature Register. */
5416 {
5417 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5418 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5419 if (fVerbose)
5420 {
5421 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5422 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5423 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5424 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5425 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5426 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5427 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5428 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5429 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5430 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5431 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5432 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5433 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5434 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5435 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5436 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5437 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5438 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5439 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5440 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5441 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5442 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5443 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5444 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5445 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5446 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5447 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5448 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5449 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5450 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5451 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5452 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5453 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5454 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5455 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5456 }
5457 }
5458 /* PPR Log Base Address Register. */
5459 {
5460 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5461 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5462 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5463 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5464 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5465 if (fVerbose)
5466 {
5467 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5468 PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5469 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5470 cEntries, cbBuffer);
5471 }
5472 }
5473 /* Hardware Event (Hi) Register. */
5474 {
5475 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5476 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5477 if (fVerbose)
5478 {
5479 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5480 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5481 }
5482 }
5483 /* Hardware Event (Lo) Register. */
5484 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5485 /* Hardware Event Status. */
5486 {
5487 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5488 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5489 if (fVerbose)
5490 {
5491 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5492 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5493 }
5494 }
5495 /* Guest Virtual-APIC Log Base Address Register. */
5496 {
5497 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5498 uint8_t const uEncodedLen = GALogBar.n.u4Len;
5499 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5500 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5501 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5502 if (fVerbose)
5503 {
5504 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5505 GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5506 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5507 cEntries, cbBuffer);
5508 }
5509 }
5510 /* Guest Virtual-APIC Log Tail Address Register. */
5511 {
5512 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5513 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5514 if (fVerbose)
5515 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5516 }
5517 /* PPR Log B Base Address Register. */
5518 {
5519 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5520 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5521 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5522 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5523 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5524 if (fVerbose)
5525 {
5526 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5527 PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5528 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5529 cEntries, cbBuffer);
5530 }
5531 }
5532 /* Event Log B Base Address Register. */
5533 {
5534 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5535 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5536 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5537 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5538 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5539 if (fVerbose)
5540 {
5541 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5542 EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5543 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5544 cEntries, cbBuffer);
5545 }
5546 }
5547 /* Device-Specific Feature Extension Register. */
5548 {
5549 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5550 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5551 if (fVerbose)
5552 {
5553 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5554 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5555 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5556 }
5557 }
5558 /* Device-Specific Control Extension Register. */
5559 {
5560 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5561 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5562 if (fVerbose)
5563 {
5564 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5565 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5566 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5567 }
5568 }
5569 /* Device-Specific Status Extension Register. */
5570 {
5571 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5572 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
5573 if (fVerbose)
5574 {
5575 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5576 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5577 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5578 }
5579 }
5580 /* Miscellaneous Information Register (Lo and Hi). */
5581 {
5582 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5583 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5584 if (fVerbose)
5585 {
5586 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5587 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5588 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5589 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5590 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5591 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5592 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5593 }
5594 }
5595 /* MSI Capability Header. */
5596 {
5597 MSI_CAP_HDR_T MsiCapHdr;
5598 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5599 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5600 if (fVerbose)
5601 {
5602 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5603 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5604 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5605 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5606 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5607 }
5608 }
5609 /* MSI Address Register (Lo and Hi). */
5610 {
5611 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5612 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5613 MSIADDR MsiAddr;
5614 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5615 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5616 if (fVerbose)
5617 {
5618 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5619 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5620 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5621 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
5622 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
5623 }
5624 }
5625 /* MSI Data. */
5626 {
5627 MSIDATA MsiData;
5628 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5629 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5630 if (fVerbose)
5631 {
5632 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5633 MsiData.n.u8Vector);
5634 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5635 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5636 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5637 "level" : "edge");
5638 }
5639 }
5640 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5641 {
5642 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5643 MsiMapCapHdr.u32 = 0;
5644 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5645 if (fVerbose)
5646 {
5647 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5648 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5649 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5650 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5651 }
5652 }
5653 /* Performance Optimization Control Register. */
5654 {
5655 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5656 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5657 if (fVerbose)
5658 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5659 }
5660 /* XT (x2APIC) General Interrupt Control Register. */
5661 {
5662 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5663 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5664 if (fVerbose)
5665 {
5666 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5667 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5668 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5669 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5670 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5671 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5672 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5673 }
5674 }
5675 /* XT (x2APIC) PPR Interrupt Control Register. */
5676 {
5677 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5678 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5679 if (fVerbose)
5680 {
5681 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5682 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5683 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5684 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5685 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5686 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5687 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5688 }
5689 }
5690 /* XT (X2APIC) GA Log Interrupt Control Register. */
5691 {
5692 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5693 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5694 if (fVerbose)
5695 {
5696 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5697 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5698 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5699 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5700 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5701 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5702 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5703 }
5704 }
5705 /* MARC Registers. */
5706 {
5707 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5708 {
5709 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5710 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5711 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5712
5713 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5714 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5715 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5716 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5717
5718 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5719 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5720 }
5721 }
5722 /* Reserved Register. */
5723 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5724 /* Command Buffer Head Pointer Register. */
5725 {
5726 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5727 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
5728 CmdBufHeadPtr.n.off);
5729 }
5730 /* Command Buffer Tail Pointer Register. */
5731 {
5732 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5733 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
5734 CmdBufTailPtr.n.off);
5735 }
5736 /* Event Log Head Pointer Register. */
5737 {
5738 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5739 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
5740 EvtLogHeadPtr.n.off);
5741 }
5742 /* Event Log Tail Pointer Register. */
5743 {
5744 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5745 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
5746 EvtLogTailPtr.n.off);
5747 }
5748 /* Status Register. */
5749 {
5750 IOMMU_STATUS_T const Status = pThis->Status;
5751 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5752 if (fVerbose)
5753 {
5754 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5755 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5756 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5757 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5758 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5759 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5760 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5761 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5762 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5763 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5764 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5765 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5766 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5767 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5768 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5769 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5770 }
5771 }
5772 /* PPR Log Head Pointer. */
5773 {
5774 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5775 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
5776 PprLogHeadPtr.n.off);
5777 }
5778 /* PPR Log Tail Pointer. */
5779 {
5780 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5781 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
5782 PprLogTailPtr.n.off);
5783 }
5784 /* Guest Virtual-APIC Log Head Pointer. */
5785 {
5786 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5787 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
5788 GALogHeadPtr.n.u12GALogPtr);
5789 }
5790 /* Guest Virtual-APIC Log Tail Pointer. */
5791 {
5792 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5793 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
5794 GALogTailPtr.n.u12GALogPtr);
5795 }
5796 /* PPR Log B Head Pointer. */
5797 {
5798 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5799 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
5800 PprLogBHeadPtr.n.off);
5801 }
5802 /* PPR Log B Tail Pointer. */
5803 {
5804 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5805 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
5806 PprLogBTailPtr.n.off);
5807 }
5808 /* Event Log B Head Pointer. */
5809 {
5810 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5811 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
5812 EvtLogBHeadPtr.n.off);
5813 }
5814 /* Event Log B Tail Pointer. */
5815 {
5816 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5817 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
5818 EvtLogBTailPtr.n.off);
5819 }
5820 /* PPR Log Auto Response Register. */
5821 {
5822 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5823 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5824 if (fVerbose)
5825 {
5826 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5827 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5828 }
5829 }
5830 /* PPR Log Overflow Early Warning Indicator Register. */
5831 {
5832 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5833 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5834 if (fVerbose)
5835 {
5836 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5837 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5838 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5839 }
5840 }
5841 /* PPR Log Overflow Early Warning Indicator Register. */
5842 {
5843 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5844 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5845 if (fVerbose)
5846 {
5847 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5848 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5849 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5850 }
5851 }
5852}
5853
5854
5855/**
5856 * Dumps the DTE via the info callback helper.
5857 *
5858 * @param pHlp The info helper.
5859 * @param pDte The device table entry.
5860 * @param pszPrefix The string prefix.
5861 */
5862static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
5863{
5864 AssertReturnVoid(pHlp);
5865 AssertReturnVoid(pDte);
5866 AssertReturnVoid(pszPrefix);
5867
5868 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
5869 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
5870 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
5871 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
5872 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
5873 pDte->n.u40PageTableRootPtrLo << 12);
5874 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
5875 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
5876 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
5877 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
5878 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
5879 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
5880 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
5881 (pDte->n.u21GstCr3TableRootPtrHi << 31)
5882 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
5883 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
5884 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
5885 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
5886 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
5887 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
5888 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
5889 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
5890 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
5891 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
5892 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
5893 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
5894 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
5895 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
5896 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
5897 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
5898 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
5899 {
5900 uint16_t const cEntries = IOMMU_DTE_GET_INTR_TAB_ENTRIES(pDte);
5901 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
5902 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
5903 cbIntrTable);
5904 }
5905 else
5906 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
5907 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
5908 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
5909 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
5910 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
5911 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
5912 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
5913 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
5914 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
5915 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
5916 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
5917 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
5918 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
5919 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
5920 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
5921 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
5922 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
5923 pHlp->pfnPrintf(pHlp, "\n");
5924}
5925
5926
5927/**
5928 * @callback_method_impl{FNDBGFHANDLERDEV}
5929 */
5930static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5931{
5932 if (pszArgs)
5933 {
5934 uint16_t uDevId = 0;
5935 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDevId);
5936 if (RT_SUCCESS(rc))
5937 {
5938 DTE_T Dte;
5939 rc = iommuAmdDteRead(pDevIns, uDevId, IOMMUOP_TRANSLATE_REQ, &Dte);
5940 if (RT_SUCCESS(rc))
5941 {
5942 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", uDevId);
5943 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
5944 return;
5945 }
5946 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", uDevId, uDevId, rc);
5947 }
5948 else
5949 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
5950 }
5951 else
5952 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
5953}
5954
5955
5956# ifdef IOMMU_WITH_DTE_CACHE
5957/**
5958 * @callback_method_impl{FNDBGFHANDLERDEV}
5959 */
5960static DECLCALLBACK(void) iommuAmdR3DbgInfoDteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5961{
5962 RT_NOREF(pszArgs);
5963 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5964 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
5965
5966 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDeviceIds);
5967 pHlp->pfnPrintf(pHlp, "DTE Cache: Capacity=%u entries\n", cDteCache);
5968 for (uint16_t i = 0; i < cDteCache; i++)
5969 {
5970 uint16_t const uDeviceId = pThis->aDeviceIds[i];
5971 if (uDeviceId)
5972 {
5973 pHlp->pfnPrintf(pHlp, " Entry[%u]: Device=%#x (BDF %02x:%02x.%d)\n", i, uDeviceId,
5974 (uDeviceId >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
5975 (uDeviceId >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
5976 uDeviceId & VBOX_PCI_DEVFN_FUN_MASK);
5977
5978 PCDTECACHE pDteCache = &pThis->aDteCache[i];
5979 pHlp->pfnPrintf(pHlp, " Flags = %#x\n", pDteCache->fFlags);
5980 pHlp->pfnPrintf(pHlp, " Domain Id = %u\n", pDteCache->uDomainId);
5981 pHlp->pfnPrintf(pHlp, "\n");
5982 }
5983 }
5984 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
5985}
5986# endif /* IOMMU_WITH_DTE_CACHE */
5987
5988
5989# ifdef IOMMU_WITH_IOTLBE_CACHE
5990/**
5991 * @callback_method_impl{FNDBGFHANDLERDEV}
5992 */
5993static DECLCALLBACK(void) iommuAmdR3DbgInfoIotlb(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5994{
5995 if (pszArgs)
5996 {
5997 uint16_t uDomainId = 0;
5998 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDomainId);
5999 if (RT_SUCCESS(rc))
6000 {
6001 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", uDomainId, uDomainId);
6002 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6003 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6004 IOTLBEINFOARG Args;
6005 Args.pIommuR3 = pThisR3;
6006 Args.pHlp = pHlp;
6007 Args.uDomainId = uDomainId;
6008
6009 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
6010 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdR3IotlbEntryInfo, &Args);
6011 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
6012 }
6013 else
6014 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit domain ID. rc=%Rrc\n", rc);
6015 }
6016 else
6017 pHlp->pfnPrintf(pHlp, "Missing domain ID.\n");
6018}
6019# endif /* IOMMU_WITH_IOTLBE_CACHE */
6020
6021
6022# ifdef IOMMU_WITH_IRTE_CACHE
6023/**
6024 * Gets the interrupt type name for an interrupt type in the IRTE.
6025 *
6026 * @returns The interrupt type name.
6027 * @param uIntrType The interrupt type (as specified in the IRTE).
6028 */
6029static const char *iommuAmdIrteGetIntrTypeName(uint8_t uIntrType)
6030{
6031 switch (uIntrType)
6032 {
6033 case VBOX_MSI_DELIVERY_MODE_FIXED: return "Fixed";
6034 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO: return "Arbitrated";
6035 default: return "<Reserved>";
6036 }
6037}
6038
6039
6040/**
6041 * @callback_method_impl{FNDBGFHANDLERDEV}
6042 */
6043static DECLCALLBACK(void) iommuAmdR3DbgInfoIrteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6044{
6045 RT_NOREF(pszArgs);
6046
6047 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6048 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
6049
6050 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
6051 pHlp->pfnPrintf(pHlp, "IRTE Cache: Capacity=%u entries\n", cIrteCache);
6052 for (uint16_t idxIrte = 0; idxIrte < cIrteCache; idxIrte++)
6053 {
6054 PCIRTECACHE pIrteCache = &pThis->aIrteCache[idxIrte];
6055 uint32_t const uKey = pIrteCache->uKey;
6056 if (uKey != IOMMU_IRTE_CACHE_KEY_NIL)
6057 {
6058 uint16_t const uDeviceId = IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(uKey);
6059 uint16_t const offIrte = IOMMU_IRTE_CACHE_KEY_GET_OFF(uKey);
6060 pHlp->pfnPrintf(pHlp, " Entry[%u]: Offset=%#x Device=%#x (BDF %02x:%02x.%d)\n",
6061 idxIrte, offIrte, uDeviceId,
6062 (uDeviceId >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6063 (uDeviceId >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6064 uDeviceId & VBOX_PCI_DEVFN_FUN_MASK);
6065
6066 PCIRTE_T pIrte = &pIrteCache->Irte;
6067 pHlp->pfnPrintf(pHlp, " Remap Enable = %RTbool\n", pIrte->n.u1RemapEnable);
6068 pHlp->pfnPrintf(pHlp, " Suppress IOPF = %RTbool\n", pIrte->n.u1SuppressIoPf);
6069 pHlp->pfnPrintf(pHlp, " Interrupt Type = %#x (%s)\n", pIrte->n.u3IntrType,
6070 iommuAmdIrteGetIntrTypeName(pIrte->n.u3IntrType));
6071 pHlp->pfnPrintf(pHlp, " Request EOI = %RTbool\n", pIrte->n.u1ReqEoi);
6072 pHlp->pfnPrintf(pHlp, " Destination mode = %s\n", pIrte->n.u1DestMode ? "Logical" : "Physical");
6073 pHlp->pfnPrintf(pHlp, " Destination Id = %u\n", pIrte->n.u8Dest);
6074 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", pIrte->n.u8Vector, pIrte->n.u8Vector);
6075 pHlp->pfnPrintf(pHlp, "\n");
6076 }
6077 }
6078 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
6079}
6080# endif /* IOMMU_WITH_IRTE_CACHE */
6081
6082
6083/**
6084 * @callback_method_impl{FNDBGFHANDLERDEV}
6085 */
6086static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6087{
6088 RT_NOREF(pszArgs);
6089
6090 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6091 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6092 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6093 NOREF(pPciDev);
6094
6095 uint8_t cSegments = 0;
6096 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6097 {
6098 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6099 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6100 if (GCPhysDevTab)
6101 ++cSegments;
6102 }
6103
6104 pHlp->pfnPrintf(pHlp, "AMD-IOMMU device tables with address translations enabled:\n");
6105 pHlp->pfnPrintf(pHlp, " DTE Segments=%u\n", cSegments);
6106 if (!cSegments)
6107 return;
6108
6109 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6110 {
6111 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6112 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6113 if (GCPhysDevTab)
6114 {
6115 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
6116 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
6117
6118 void *pvDevTab = RTMemAllocZ(cbDevTab);
6119 if (RT_LIKELY(pvDevTab))
6120 {
6121 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
6122 if (RT_SUCCESS(rc))
6123 {
6124 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
6125 {
6126 PCDTE_T pDte = (PCDTE_T)((uintptr_t)pvDevTab + idxDte * sizeof(DTE_T));
6127 if ( pDte->n.u1Valid
6128 && pDte->n.u1TranslationValid
6129 && pDte->n.u3Mode != 0)
6130 {
6131 pHlp->pfnPrintf(pHlp, " DTE %u (BDF %02x:%02x.%d)\n", idxDte,
6132 (idxDte >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6133 (idxDte >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6134 idxDte & VBOX_PCI_DEVFN_FUN_MASK);
6135 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
6136 pHlp->pfnPrintf(pHlp, "\n");
6137 }
6138 }
6139 pHlp->pfnPrintf(pHlp, "\n");
6140 }
6141 else
6142 {
6143 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %zu bytes. rc=%Rrc!\n", GCPhysDevTab,
6144 cbDevTab, rc);
6145 }
6146
6147 RTMemFree(pvDevTab);
6148 }
6149 else
6150 {
6151 pHlp->pfnPrintf(pHlp, " Allocating %zu bytes for reading the device table failed!\n", cbDevTab);
6152 return;
6153 }
6154 }
6155 }
6156}
6157
6158
6159/**
6160 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6161 */
6162static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6163{
6164 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6165 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6166 LogFlowFunc(("\n"));
6167
6168 /* First, save ExtFeat and other registers that cannot be modified by the guest. */
6169 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64);
6170 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64);
6171 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64);
6172 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64);
6173 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64);
6174 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg);
6175
6176 /* Next, save all registers that can be modified by the guest. */
6177 pHlp->pfnSSMPutU64(pSSM, pThis->IommuBar.u64);
6178
6179 uint8_t const cDevTabBaseAddrs = RT_ELEMENTS(pThis->aDevTabBaseAddrs);
6180 pHlp->pfnSSMPutU8(pSSM, cDevTabBaseAddrs);
6181 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6182 pHlp->pfnSSMPutU64(pSSM, pThis->aDevTabBaseAddrs[i].u64);
6183
6184 AssertReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8, VERR_IOMMU_IPE_4);
6185 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufBaseAddr.u64);
6186 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64);
6187 pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64);
6188 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeBaseAddr.u64);
6189 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeLimit.u64);
6190#if 0
6191 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); /* read-only, done already (above). */
6192#endif
6193
6194 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBaseAddr.u64);
6195 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtHi.u64);
6196 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtLo);
6197 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtStatus.u64);
6198
6199 pHlp->pfnSSMPutU64(pSSM, pThis->GALogBaseAddr.u64);
6200 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailAddr.u64);
6201
6202 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBBaseAddr.u64);
6203 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBBaseAddr.u64);
6204
6205#if 0
6206 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6207 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6208 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6209
6210 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); /* read-only, done already (above). */
6211#endif
6212 pHlp->pfnSSMPutU32(pSSM, pThis->PerfOptCtrl.u32);
6213
6214 pHlp->pfnSSMPutU64(pSSM, pThis->XtGenIntrCtrl.u64);
6215 pHlp->pfnSSMPutU64(pSSM, pThis->XtPprIntrCtrl.u64);
6216 pHlp->pfnSSMPutU64(pSSM, pThis->XtGALogIntrCtrl.u64);
6217
6218 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers);
6219 pHlp->pfnSSMPutU8(pSSM, cMarcApers);
6220 for (size_t i = 0; i < cMarcApers; i++)
6221 {
6222 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64);
6223 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64);
6224 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64);
6225 }
6226
6227#if 0
6228 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done already (above). */
6229#endif
6230
6231 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufHeadPtr.u64);
6232 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufTailPtr.u64);
6233 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogHeadPtr.u64);
6234 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogTailPtr.u64);
6235
6236 pHlp->pfnSSMPutU64(pSSM, pThis->Status.u64);
6237
6238 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogHeadPtr.u64);
6239 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogTailPtr.u64);
6240
6241 pHlp->pfnSSMPutU64(pSSM, pThis->GALogHeadPtr.u64);
6242 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailPtr.u64);
6243
6244 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBHeadPtr.u64);
6245 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBTailPtr.u64);
6246
6247 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBHeadPtr.u64);
6248 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBTailPtr.u64);
6249
6250 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogAutoResp.u64);
6251 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogOverflowEarly.u64);
6252 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBOverflowEarly.u64);
6253
6254 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
6255}
6256
6257
6258/**
6259 * @callback_method_impl{FNSSMDEVLOADEXEC}
6260 */
6261static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6262{
6263 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6264 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6265 int const rcErr = VERR_SSM_UNEXPECTED_DATA;
6266 LogFlowFunc(("\n"));
6267
6268 /* Validate. */
6269 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
6270 if (uVersion != IOMMU_SAVED_STATE_VERSION)
6271 {
6272 LogRel(("%s: Invalid saved-state version %#x\n", IOMMU_LOG_PFX, uVersion));
6273 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6274 }
6275
6276 /* Load ExtFeat and other read-only registers first. */
6277 int rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64);
6278 AssertRCReturn(rc, rc);
6279 AssertLogRelMsgReturn(pThis->ExtFeat.n.u2HostAddrTranslateSize < 0x3,
6280 ("ExtFeat.HATS register invalid %#RX64\n", pThis->ExtFeat.u64), rcErr);
6281 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64);
6282 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64);
6283 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64);
6284 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64);
6285 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg);
6286
6287 /* IOMMU base address register. */
6288 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->IommuBar.u64);
6289 AssertRCReturn(rc, rc);
6290 pThis->IommuBar.u64 &= IOMMU_BAR_VALID_MASK;
6291
6292 /* Device table base address registers. */
6293 uint8_t cDevTabBaseAddrs;
6294 rc = pHlp->pfnSSMGetU8(pSSM, &cDevTabBaseAddrs);
6295 AssertRCReturn(rc, rc);
6296 AssertLogRelMsgReturn(cDevTabBaseAddrs > 0 && cDevTabBaseAddrs <= RT_ELEMENTS(pThis->aDevTabBaseAddrs),
6297 ("Device table segment count invalid %#x\n", cDevTabBaseAddrs), rcErr);
6298 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6299 {
6300 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aDevTabBaseAddrs[i].u64);
6301 AssertRCReturn(rc, rc);
6302 pThis->aDevTabBaseAddrs[i].u64 &= IOMMU_DEV_TAB_BAR_VALID_MASK;
6303 AssertLogRelMsgReturn(pThis->aDevTabBaseAddrs[i].n.u9Size <= g_auDevTabSegMaxSizes[0],
6304 ("Device table segment size invalid %#x\n", pThis->aDevTabBaseAddrs[i].n.u9Size), rcErr);
6305 }
6306
6307 /* Command buffer base address register. */
6308 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufBaseAddr.u64);
6309 AssertRCReturn(rc, rc);
6310 pThis->CmdBufBaseAddr.u64 &= IOMMU_CMD_BUF_BAR_VALID_MASK;
6311 AssertLogRelMsgReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8,
6312 ("Command buffer base address invalid %#RX64\n", pThis->CmdBufBaseAddr.u64), rcErr);
6313
6314 /* Event log base address register. */
6315 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBaseAddr.u64);
6316 AssertRCReturn(rc, rc);
6317 pThis->EvtLogBaseAddr.u64 &= IOMMU_EVT_LOG_BAR_VALID_MASK;
6318 AssertLogRelMsgReturn(pThis->EvtLogBaseAddr.n.u4Len >= 8,
6319 ("Event log base address invalid %#RX64\n", pThis->EvtLogBaseAddr.u64), rcErr);
6320
6321 /* Control register. */
6322 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Ctrl.u64);
6323 AssertRCReturn(rc, rc);
6324 pThis->Ctrl.u64 &= IOMMU_CTRL_VALID_MASK;
6325 AssertLogRelMsgReturn(pThis->Ctrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup,
6326 ("Control register invalid %#RX64\n", pThis->Ctrl.u64), rcErr);
6327
6328 /* Exclusion range base address register. */
6329 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeBaseAddr.u64);
6330 AssertRCReturn(rc, rc);
6331 pThis->ExclRangeBaseAddr.u64 &= IOMMU_EXCL_RANGE_BAR_VALID_MASK;
6332
6333 /* Exclusion range limit register. */
6334 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeLimit.u64);
6335 AssertRCReturn(rc, rc);
6336 pThis->ExclRangeLimit.u64 &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
6337 pThis->ExclRangeLimit.u64 |= UINT64_C(0xfff);
6338
6339#if 0
6340 pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64); /* read-only, done already (above). */
6341#endif
6342
6343 /* PPR log base address register. */
6344 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBaseAddr.u64);
6345 AssertRCReturn(rc, rc);
6346 Assert(!pThis->ExtFeat.n.u1PprSup);
6347
6348 /* Hardware event (Hi) register. */
6349 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtHi.u64);
6350 AssertRCReturn(rc, rc);
6351
6352 /* Hardware event (Lo) register. */
6353 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtLo);
6354 AssertRCReturn(rc, rc);
6355
6356 /* Hardware event status register. */
6357 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtStatus.u64);
6358 AssertRCReturn(rc, rc);
6359 pThis->HwEvtStatus.u64 &= IOMMU_HW_EVT_STATUS_VALID_MASK;
6360
6361 /* Guest Virtual-APIC log base address register. */
6362 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogBaseAddr.u64);
6363 AssertRCReturn(rc, rc);
6364 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6365
6366 /* Guest Virtual-APIC log tail address register. */
6367 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailAddr.u64);
6368 AssertRCReturn(rc, rc);
6369 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6370
6371 /* PPR log-B base address register. */
6372 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBBaseAddr.u64);
6373 AssertRCReturn(rc, rc);
6374 Assert(!pThis->ExtFeat.n.u1PprSup);
6375
6376 /* Event log-B base address register. */
6377 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBBaseAddr.u64);
6378 AssertRCReturn(rc, rc);
6379 Assert(!pThis->ExtFeat.n.u2DualPprLogSup);
6380
6381#if 0
6382 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6383 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6384 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6385
6386 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64); /* read-only, done already (above). */
6387#endif
6388
6389 /* Performance optimization control register. */
6390 rc = pHlp->pfnSSMGetU32(pSSM, &pThis->PerfOptCtrl.u32);
6391 AssertRCReturn(rc, rc);
6392 Assert(!pThis->ExtFeat.n.u1PerfOptSup);
6393
6394 /* x2APIC registers. */
6395 {
6396 Assert(!pThis->ExtFeat.n.u1X2ApicSup);
6397
6398 /* x2APIC general interrupt control register. */
6399 pHlp->pfnSSMGetU64(pSSM, &pThis->XtGenIntrCtrl.u64);
6400 AssertRCReturn(rc, rc);
6401
6402 /* x2APIC PPR interrupt control register. */
6403 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtPprIntrCtrl.u64);
6404 AssertRCReturn(rc, rc);
6405
6406 /* x2APIC GA log interrupt control register. */
6407 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtGALogIntrCtrl.u64);
6408 AssertRCReturn(rc, rc);
6409 }
6410
6411 /* MARC (Memory access and routing) registers. */
6412 {
6413 uint8_t cMarcApers;
6414 rc = pHlp->pfnSSMGetU8(pSSM, &cMarcApers);
6415 AssertRCReturn(rc, rc);
6416 AssertLogRelMsgReturn(cMarcApers > 0 && cMarcApers <= RT_ELEMENTS(pThis->aMarcApers),
6417 ("MARC register count invalid %#x\n", cMarcApers), rcErr);
6418 for (uint8_t i = 0; i < cMarcApers; i++)
6419 {
6420 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Base.u64);
6421 AssertRCReturn(rc, rc);
6422
6423 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Reloc.u64);
6424 AssertRCReturn(rc, rc);
6425
6426 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Length.u64);
6427 AssertRCReturn(rc, rc);
6428 }
6429 Assert(!pThis->ExtFeat.n.u2MarcSup);
6430 }
6431
6432#if 0
6433 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg); /* read-only, done already (above). */
6434#endif
6435
6436 /* Command buffer head pointer register. */
6437 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufHeadPtr.u64);
6438 AssertRCReturn(rc, rc);
6439 {
6440 /*
6441 * IOMMU behavior is undefined when software writes a value outside the buffer length.
6442 * In our emulation, since we ignore the write entirely (see iommuAmdCmdBufHeadPtr_w)
6443 * we shouldn't see such values in the saved state.
6444 */
6445 uint32_t const offBuf = pThis->CmdBufHeadPtr.u64 & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
6446 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6447 Assert(cbBuf <= _512K);
6448 AssertLogRelMsgReturn(offBuf < cbBuf,
6449 ("Command buffer head pointer invalid %#x\n", pThis->CmdBufHeadPtr.u64), rcErr);
6450 }
6451
6452 /* Command buffer tail pointer register. */
6453 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufTailPtr.u64);
6454 AssertRCReturn(rc, rc);
6455 {
6456 uint32_t const offBuf = pThis->CmdBufTailPtr.u64 & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
6457 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6458 Assert(cbBuf <= _512K);
6459 AssertLogRelMsgReturn(offBuf < cbBuf,
6460 ("Command buffer tail pointer invalid %#x\n", pThis->CmdBufTailPtr.u64), rcErr);
6461 }
6462
6463 /* Event log head pointer register. */
6464 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogHeadPtr.u64);
6465 AssertRCReturn(rc, rc);
6466 {
6467 uint32_t const offBuf = pThis->EvtLogHeadPtr.u64 & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
6468 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6469 Assert(cbBuf <= _512K);
6470 AssertLogRelMsgReturn(offBuf < cbBuf,
6471 ("Event log head pointer invalid %#x\n", pThis->EvtLogHeadPtr.u64), rcErr);
6472 }
6473
6474 /* Event log tail pointer register. */
6475 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogTailPtr.u64);
6476 AssertRCReturn(rc, rc);
6477 {
6478 uint32_t const offBuf = pThis->EvtLogTailPtr.u64 & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
6479 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6480 Assert(cbBuf <= _512K);
6481 AssertLogRelMsgReturn(offBuf < cbBuf,
6482 ("Event log tail pointer invalid %#x\n", pThis->EvtLogTailPtr.u64), rcErr);
6483 }
6484
6485 /* Status register. */
6486 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Status.u64);
6487 AssertRCReturn(rc, rc);
6488 pThis->Status.u64 &= IOMMU_STATUS_VALID_MASK;
6489
6490 /* PPR log head pointer register. */
6491 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogHeadPtr.u64);
6492 AssertRCReturn(rc, rc);
6493 Assert(!pThis->ExtFeat.n.u1PprSup);
6494
6495 /* PPR log tail pointer register. */
6496 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogTailPtr.u64);
6497 AssertRCReturn(rc, rc);
6498 Assert(!pThis->ExtFeat.n.u1PprSup);
6499
6500 /* Guest Virtual-APIC log head pointer register. */
6501 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogHeadPtr.u64);
6502 AssertRCReturn(rc, rc);
6503 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6504
6505 /* Guest Virtual-APIC log tail pointer register. */
6506 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailPtr.u64);
6507 AssertRCReturn(rc, rc);
6508 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6509
6510 /* PPR log-B head pointer register. */
6511 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBHeadPtr.u64);
6512 AssertRCReturn(rc, rc);
6513 Assert(!pThis->ExtFeat.n.u1PprSup);
6514
6515 /* PPR log-B head pointer register. */
6516 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBTailPtr.u64);
6517 AssertRCReturn(rc, rc);
6518 Assert(!pThis->ExtFeat.n.u1PprSup);
6519
6520 /* Event log-B head pointer register. */
6521 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBHeadPtr.u64);
6522 AssertRCReturn(rc, rc);
6523 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6524
6525 /* Event log-B tail pointer register. */
6526 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBTailPtr.u64);
6527 AssertRCReturn(rc, rc);
6528 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6529
6530 /* PPR log auto response register. */
6531 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogAutoResp.u64);
6532 AssertRCReturn(rc, rc);
6533 Assert(!pThis->ExtFeat.n.u1PprAutoRespSup);
6534
6535 /* PPR log overflow early indicator register. */
6536 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogOverflowEarly.u64);
6537 AssertRCReturn(rc, rc);
6538 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6539
6540 /* PPR log-B overflow early indicator register. */
6541 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBOverflowEarly.u64);
6542 AssertRCReturn(rc, rc);
6543 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6544
6545 /* End marker. */
6546 {
6547 uint32_t uEndMarker;
6548 rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
6549 AssertLogRelMsgRCReturn(rc, ("Failed to read end marker. rc=%Rrc\n", rc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6550 AssertLogRelMsgReturn(uEndMarker == UINT32_MAX, ("End marker invalid (%#x expected %#x)\n", uEndMarker, UINT32_MAX),
6551 rcErr);
6552 }
6553
6554 return rc;
6555}
6556
6557
6558/**
6559 * @callback_method_impl{FNSSMDEVLOADDONE}
6560 */
6561static DECLCALLBACK(int) iommuAmdR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6562{
6563 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6564 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6565 RT_NOREF(pSSM);
6566 LogFlowFunc(("\n"));
6567
6568 /* Sanity. */
6569 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6570 AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
6571
6572 IOMMU_LOCK(pDevIns, pThisR3);
6573
6574 /* Map MMIO regions if the IOMMU BAR is enabled. */
6575 if (pThis->IommuBar.n.u1Enable)
6576 iommuAmdR3MmioSetup(pDevIns);
6577
6578 /* Wake up the command thread if commands need processing. */
6579 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
6580
6581 IOMMU_UNLOCK(pDevIns, pThisR3);
6582 return VINF_SUCCESS;
6583}
6584
6585
6586/**
6587 * @interface_method_impl{PDMDEVREG,pfnReset}
6588 */
6589static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
6590{
6591 /*
6592 * Resets read-write portion of the IOMMU state.
6593 *
6594 * NOTE! State not initialized here is expected to be initialized during
6595 * device construction and remain read-only through the lifetime of the VM.
6596 */
6597 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6598 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6599 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6600 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6601 LogFlowFunc(("\n"));
6602
6603 IOMMU_LOCK_NORET(pDevIns, pThisR3);
6604
6605 RT_ZERO(pThis->aDevTabBaseAddrs);
6606
6607 pThis->CmdBufBaseAddr.u64 = 0;
6608 pThis->CmdBufBaseAddr.n.u4Len = 8;
6609
6610 pThis->EvtLogBaseAddr.u64 = 0;
6611 pThis->EvtLogBaseAddr.n.u4Len = 8;
6612
6613 pThis->Ctrl.u64 = 0;
6614 pThis->Ctrl.n.u1Coherent = 1;
6615 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
6616
6617 pThis->ExclRangeBaseAddr.u64 = 0;
6618 pThis->ExclRangeLimit.u64 = 0;
6619
6620 pThis->PprLogBaseAddr.u64 = 0;
6621 pThis->PprLogBaseAddr.n.u4Len = 8;
6622
6623 pThis->HwEvtHi.u64 = 0;
6624 pThis->HwEvtLo = 0;
6625 pThis->HwEvtStatus.u64 = 0;
6626
6627 pThis->GALogBaseAddr.u64 = 0;
6628 pThis->GALogBaseAddr.n.u4Len = 8;
6629 pThis->GALogTailAddr.u64 = 0;
6630
6631 pThis->PprLogBBaseAddr.u64 = 0;
6632 pThis->PprLogBBaseAddr.n.u4Len = 8;
6633
6634 pThis->EvtLogBBaseAddr.u64 = 0;
6635 pThis->EvtLogBBaseAddr.n.u4Len = 8;
6636
6637 pThis->PerfOptCtrl.u32 = 0;
6638
6639 pThis->XtGenIntrCtrl.u64 = 0;
6640 pThis->XtPprIntrCtrl.u64 = 0;
6641 pThis->XtGALogIntrCtrl.u64 = 0;
6642
6643 RT_ZERO(pThis->aMarcApers);
6644
6645 pThis->CmdBufHeadPtr.u64 = 0;
6646 pThis->CmdBufTailPtr.u64 = 0;
6647 pThis->EvtLogHeadPtr.u64 = 0;
6648 pThis->EvtLogTailPtr.u64 = 0;
6649
6650 pThis->Status.u64 = 0;
6651
6652 pThis->PprLogHeadPtr.u64 = 0;
6653 pThis->PprLogTailPtr.u64 = 0;
6654
6655 pThis->GALogHeadPtr.u64 = 0;
6656 pThis->GALogTailPtr.u64 = 0;
6657
6658 pThis->PprLogBHeadPtr.u64 = 0;
6659 pThis->PprLogBTailPtr.u64 = 0;
6660
6661 pThis->EvtLogBHeadPtr.u64 = 0;
6662 pThis->EvtLogBTailPtr.u64 = 0;
6663
6664 pThis->PprLogAutoResp.u64 = 0;
6665 pThis->PprLogOverflowEarly.u64 = 0;
6666 pThis->PprLogBOverflowEarly.u64 = 0;
6667
6668 pThis->IommuBar.u64 = 0;
6669 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
6670 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
6671
6672 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
6673
6674 IOMMU_UNLOCK(pDevIns, pThisR3);
6675
6676#ifdef IOMMU_WITH_DTE_CACHE
6677 iommuAmdDteCacheRemoveAll(pDevIns);
6678#endif
6679#ifdef IOMMU_WITH_IOTLBE_CACHE
6680 iommuAmdIotlbRemoveAll(pDevIns);
6681#endif
6682#ifdef IOMMU_WITH_IRTE_CACHE
6683 iommuAmdIrteCacheRemoveAll(pDevIns);
6684#endif
6685}
6686
6687
6688/**
6689 * @interface_method_impl{PDMDEVREG,pfnDestruct}
6690 */
6691static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
6692{
6693 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6694 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6695 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6696 LogFlowFunc(("\n"));
6697
6698 IOMMU_LOCK_NORET(pDevIns, pThisR3);
6699
6700 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
6701 {
6702 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
6703 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
6704 }
6705
6706#ifdef IOMMU_WITH_IOTLBE_CACHE
6707 if (pThisR3->paIotlbes)
6708 {
6709 PDMDevHlpMMHeapFree(pDevIns, pThisR3->paIotlbes);
6710 pThisR3->paIotlbes = NULL;
6711 pThisR3->idxUnusedIotlbe = 0;
6712 }
6713#endif
6714
6715 IOMMU_UNLOCK(pDevIns, pThisR3);
6716 return VINF_SUCCESS;
6717}
6718
6719
6720/**
6721 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6722 */
6723static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6724{
6725 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6726 RT_NOREF(pCfg);
6727
6728 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6729 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6730 pThis->u32Magic = IOMMU_MAGIC;
6731 pThisR3->pDevInsR3 = pDevIns;
6732
6733 LogFlowFunc(("iInstance=%d\n", iInstance));
6734
6735 /*
6736 * Register the IOMMU with PDM.
6737 */
6738 PDMIOMMUREGR3 IommuReg;
6739 RT_ZERO(IommuReg);
6740 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6741 IommuReg.pfnMemAccess = iommuAmdMemAccess;
6742 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
6743 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
6744 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6745 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
6746 if (RT_FAILURE(rc))
6747 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
6748 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
6749 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6750 N_("IOMMU helper version mismatch; got %#x expected %#x"),
6751 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
6752 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
6753 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6754 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
6755 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
6756
6757 /*
6758 * We will use PDM's critical section (via helpers) for the IOMMU device.
6759 */
6760 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6761 AssertRCReturn(rc, rc);
6762
6763 /*
6764 * Initialize read-only PCI configuration space.
6765 */
6766 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6767 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6768
6769 /* Header. */
6770 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
6771 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
6772 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
6773 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
6774 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
6775 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
6776 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
6777 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
6778 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
6779 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
6780 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
6781 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
6782 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
6783 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
6784
6785 /* Capability Header. */
6786 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
6787 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
6788 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
6789 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
6790 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
6791 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
6792 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
6793 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
6794 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
6795 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
6796 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
6797
6798 /* Base Address Register. */
6799 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
6800 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
6801
6802 /* IOMMU Range Register. */
6803 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
6804
6805 /* Misc. Information Register. */
6806 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
6807 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
6808 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
6809 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
6810 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
6811 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
6812 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
6813 uint32_t const uMiscInfoReg1 = 0;
6814 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
6815 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
6816
6817 /* MSI Capability Header register. */
6818 PDMMSIREG MsiReg;
6819 RT_ZERO(MsiReg);
6820 MsiReg.cMsiVectors = 1;
6821 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
6822 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
6823 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
6824
6825 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
6826#if 0
6827 /* MSI Address Lo. */
6828 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
6829 /* MSI Address Hi. */
6830 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
6831 /* MSI Data. */
6832 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
6833#endif
6834
6835#if 0
6836 /** @todo IOMMU: I don't know if we need to support this, enable later if
6837 * required. */
6838 /* MSI Mapping Capability Header register. */
6839 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
6840 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
6841 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
6842 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
6843 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
6844 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
6845 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
6846#endif
6847
6848 /*
6849 * Register the PCI function with PDM.
6850 */
6851 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
6852 AssertLogRelRCReturn(rc, rc);
6853
6854 /*
6855 * Register MSI support for the PCI device.
6856 * This must be done -after- registering it as a PCI device!
6857 */
6858 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6859 AssertRCReturn(rc, rc);
6860
6861 /*
6862 * Intercept PCI config. space accesses.
6863 */
6864 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
6865 AssertLogRelRCReturn(rc, rc);
6866
6867 /*
6868 * Create the MMIO region.
6869 * Mapping of the region is done when software configures it via PCI config space.
6870 */
6871 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
6872 NULL /* pvUser */,
6873 IOMMMIO_FLAGS_READ_DWORD_QWORD
6874 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
6875 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
6876 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
6877 "AMD-IOMMU", &pThis->hMmio);
6878 AssertLogRelRCReturn(rc, rc);
6879
6880 /*
6881 * Register saved state handlers.
6882 */
6883 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL /* pszBefore */,
6884 NULL /* pfnLivePrep */, NULL /* pfnLiveExec */, NULL /* pfnLiveVote */,
6885 NULL /* pfnSavePrep */, iommuAmdR3SaveExec, NULL /* pfnSaveDone */,
6886 NULL /* pfnLoadPrep */, iommuAmdR3LoadExec, iommuAmdR3LoadDone);
6887 AssertLogRelRCReturn(rc, rc);
6888
6889 /*
6890 * Register debugger info items.
6891 */
6892 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
6893 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device (from memory). Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
6894 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display I/O device tables with translation enabled.", iommuAmdR3DbgInfoDevTabs);
6895#ifdef IOMMU_WITH_IOTLBE_CACHE
6896 PDMDevHlpDBGFInfoRegister(pDevIns, "iommutlb", "Display IOTLBs for a domain. Arguments: DomainID.", iommuAmdR3DbgInfoIotlb);
6897#endif
6898#ifdef IOMMU_WITH_DTE_CACHE
6899 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudtecache", "Display the DTE cache.", iommuAmdR3DbgInfoDteCache);
6900#endif
6901#ifdef IOMMU_WITH_IRTE_CACHE
6902 PDMDevHlpDBGFInfoRegister(pDevIns, "iommuirtecache", "Display the IRTE cache.", iommuAmdR3DbgInfoIrteCache);
6903#endif
6904
6905# ifdef VBOX_WITH_STATISTICS
6906 /*
6907 * Statistics.
6908 */
6909 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
6910 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
6911
6912 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
6913 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
6914
6915 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
6916 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
6917
6918 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
6919 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
6920
6921 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
6922 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
6923
6924 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
6925 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
6926
6927 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
6928 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
6929
6930 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
6931 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
6932 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
6933 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
6934 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
6935 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
6936 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
6937 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
6938 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
6939
6940
6941 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCached, STAMTYPE_COUNTER, "IOTLB/Cached", STAMUNIT_OCCURENCES, "Number of IOTLB entries in the cache.");
6942 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLazyEvictReuse, STAMTYPE_COUNTER, "IOTLB/LazyEvictReuse", STAMUNIT_OCCURENCES, "Number of IOTLB entries reused after lazy eviction.");
6943
6944 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfDteLookup, STAMTYPE_PROFILE, "Profile/DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling DTE lookup.");
6945 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIotlbeLookup, STAMTYPE_PROFILE, "Profile/IotlbeLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IOTLBE lookup.");
6946
6947 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteLookup, STAMTYPE_PROFILE, "Profile/IrteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE lookup.");
6948 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteCacheLookup, STAMTYPE_PROFILE, "Profile/IrteCacheLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE cache lookup.");
6949
6950 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHit, STAMTYPE_COUNTER, "MemAccess/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
6951 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheMiss, STAMTYPE_COUNTER, "MemAccess/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
6952 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHitFull, STAMTYPE_COUNTER, "MemAccess/CacheHitFull", STAMUNIT_OCCURENCES, "Number of accesses that was entirely in the cache.");
6953 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheNonContig, STAMTYPE_COUNTER, "MemAccess/CacheNonContig", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in non-contiguous translated regions.");
6954 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCachePermDenied, STAMTYPE_COUNTER, "MemAccess/CacheAddrDenied", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in denied permissions.");
6955 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDteNonContig, STAMTYPE_COUNTER, "MemAccess/DteNonContig", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in non-contiguous translated regions.");
6956 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDtePermDenied, STAMTYPE_COUNTER, "MemAccess/DtePermDenied", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in denied permissions.");
6957
6958 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheHit, STAMTYPE_COUNTER, "Interrupt/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
6959 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheMiss, STAMTYPE_COUNTER, "Interrupt/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
6960# endif
6961
6962 /*
6963 * Create the command thread and its event semaphore.
6964 */
6965 char szDevIommu[64];
6966 RT_ZERO(szDevIommu);
6967 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
6968 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
6969 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
6970 AssertLogRelRCReturn(rc, rc);
6971
6972 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
6973 AssertLogRelRCReturn(rc, rc);
6974
6975#ifdef IOMMU_WITH_DTE_CACHE
6976 /*
6977 * Initialize the critsect of the cache.
6978 */
6979 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectCache, RT_SRC_POS, "IOMMUCache-#%u", pDevIns->iInstance);
6980 AssertLogRelRCReturn(rc, rc);
6981
6982 /* Several places in this code relies on this basic assumption - assert it! */
6983 AssertCompile(RT_ELEMENTS(pThis->aDeviceIds) == RT_ELEMENTS(pThis->aDteCache));
6984#endif
6985
6986#ifdef IOMMU_WITH_IOTLBE_CACHE
6987 /*
6988 * Allocate IOTLB entries.
6989 * This is allocated upfront since we expect a relatively small number of entries,
6990 * is more cache-line efficient and easier to track least recently used entries for
6991 * eviction when the cache is full. This also avoids unpredictable behavior during
6992 * the lifetime of the VM if the hyperheap gets full.
6993 */
6994 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
6995 pThisR3->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
6996 if (!pThisR3->paIotlbes)
6997 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
6998 N_("Failed to allocate %zu bytes from the hyperheap for the IOTLB cache."), cbIotlbes);
6999 RTListInit(&pThisR3->LstLruIotlbe);
7000 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbIotlbes));
7001#endif
7002
7003 /*
7004 * Initialize read-only registers.
7005 * NOTE! Fields here must match their corresponding field in the ACPI tables.
7006 */
7007 /* Don't remove the commented lines below as it lets us see all features at a glance. */
7008 pThis->ExtFeat.u64 = 0;
7009 //pThis->ExtFeat.n.u1PrefetchSup = 0;
7010 //pThis->ExtFeat.n.u1PprSup = 0;
7011 //pThis->ExtFeat.n.u1X2ApicSup = 0;
7012 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
7013 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
7014 pThis->ExtFeat.n.u1InvAllSup = 1;
7015 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
7016 pThis->ExtFeat.n.u1HwErrorSup = 1;
7017 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
7018 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
7019 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
7020 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
7021 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
7022 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
7023 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
7024 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
7025 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
7026 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
7027 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
7028 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
7029 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
7030 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
7031 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
7032 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
7033 //pThis->ExtFeat.n.u2MarcSup = 0;
7034 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
7035 //pThis->ExtFeat.n.u1PerfOptSup = 0;
7036 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
7037 //pThis->ExtFeat.n.u1GstIoSup = 0;
7038 //pThis->ExtFeat.n.u1HostAccessSup = 0;
7039 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
7040 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
7041 //pThis->ExtFeat.n.u1HostDirtySup = 0;
7042 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
7043 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
7044 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
7045
7046 pThis->DevSpecificFeat.u64 = 0;
7047 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
7048 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
7049
7050 pThis->DevSpecificCtrl.u64 = 0;
7051 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
7052 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
7053
7054 pThis->DevSpecificStatus.u64 = 0;
7055 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
7056 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
7057
7058 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
7059
7060 pThis->RsvdReg = 0;
7061
7062 /*
7063 * Initialize parts of the IOMMU state as it would during reset.
7064 * Also initializes non-zero initial values like IRTE cache keys.
7065 * Must be called -after- initializing PCI config. space registers.
7066 */
7067 iommuAmdR3Reset(pDevIns);
7068
7069 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
7070 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
7071 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
7072 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
7073 pThis->ExtFeat.u64));
7074 return VINF_SUCCESS;
7075}
7076
7077#else
7078
7079/**
7080 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7081 */
7082static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
7083{
7084 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7085 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
7086 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
7087 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
7088
7089 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
7090 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7091 AssertRCReturn(rc, rc);
7092
7093 /* Set up the MMIO RZ handlers. */
7094 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
7095 AssertRCReturn(rc, rc);
7096
7097 /* Set up the IOMMU RZ callbacks. */
7098 PDMIOMMUREGCC IommuReg;
7099 RT_ZERO(IommuReg);
7100 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
7101 IommuReg.idxIommu = pThis->idxIommu;
7102 IommuReg.pfnMemAccess = iommuAmdMemAccess;
7103 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
7104 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
7105 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
7106 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
7107 AssertRCReturn(rc, rc);
7108 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
7109 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
7110 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
7111 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
7112 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
7113 return VINF_SUCCESS;
7114}
7115#endif
7116
7117
7118/**
7119 * The device registration structure.
7120 */
7121const PDMDEVREG g_DeviceIommuAmd =
7122{
7123 /* .u32Version = */ PDM_DEVREG_VERSION,
7124 /* .uReserved0 = */ 0,
7125 /* .szName = */ "iommu-amd",
7126 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
7127 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
7128 /* .cMaxInstances = */ ~0U,
7129 /* .uSharedVersion = */ 42,
7130 /* .cbInstanceShared = */ sizeof(IOMMU),
7131 /* .cbInstanceCC = */ sizeof(IOMMUCC),
7132 /* .cbInstanceRC = */ sizeof(IOMMURC),
7133 /* .cMaxPciDevices = */ 1,
7134 /* .cMaxMsixVectors = */ 0,
7135 /* .pszDescription = */ "IOMMU (AMD)",
7136#if defined(IN_RING3)
7137 /* .pszRCMod = */ "VBoxDDRC.rc",
7138 /* .pszR0Mod = */ "VBoxDDR0.r0",
7139 /* .pfnConstruct = */ iommuAmdR3Construct,
7140 /* .pfnDestruct = */ iommuAmdR3Destruct,
7141 /* .pfnRelocate = */ NULL,
7142 /* .pfnMemSetup = */ NULL,
7143 /* .pfnPowerOn = */ NULL,
7144 /* .pfnReset = */ iommuAmdR3Reset,
7145 /* .pfnSuspend = */ NULL,
7146 /* .pfnResume = */ NULL,
7147 /* .pfnAttach = */ NULL,
7148 /* .pfnDetach = */ NULL,
7149 /* .pfnQueryInterface = */ NULL,
7150 /* .pfnInitComplete = */ NULL,
7151 /* .pfnPowerOff = */ NULL,
7152 /* .pfnSoftReset = */ NULL,
7153 /* .pfnReserved0 = */ NULL,
7154 /* .pfnReserved1 = */ NULL,
7155 /* .pfnReserved2 = */ NULL,
7156 /* .pfnReserved3 = */ NULL,
7157 /* .pfnReserved4 = */ NULL,
7158 /* .pfnReserved5 = */ NULL,
7159 /* .pfnReserved6 = */ NULL,
7160 /* .pfnReserved7 = */ NULL,
7161#elif defined(IN_RING0)
7162 /* .pfnEarlyConstruct = */ NULL,
7163 /* .pfnConstruct = */ iommuAmdRZConstruct,
7164 /* .pfnDestruct = */ NULL,
7165 /* .pfnFinalDestruct = */ NULL,
7166 /* .pfnRequest = */ NULL,
7167 /* .pfnReserved0 = */ NULL,
7168 /* .pfnReserved1 = */ NULL,
7169 /* .pfnReserved2 = */ NULL,
7170 /* .pfnReserved3 = */ NULL,
7171 /* .pfnReserved4 = */ NULL,
7172 /* .pfnReserved5 = */ NULL,
7173 /* .pfnReserved6 = */ NULL,
7174 /* .pfnReserved7 = */ NULL,
7175#elif defined(IN_RC)
7176 /* .pfnConstruct = */ iommuAmdRZConstruct,
7177 /* .pfnReserved0 = */ NULL,
7178 /* .pfnReserved1 = */ NULL,
7179 /* .pfnReserved2 = */ NULL,
7180 /* .pfnReserved3 = */ NULL,
7181 /* .pfnReserved4 = */ NULL,
7182 /* .pfnReserved5 = */ NULL,
7183 /* .pfnReserved6 = */ NULL,
7184 /* .pfnReserved7 = */ NULL,
7185#else
7186# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7187#endif
7188 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
7189};
7190
7191#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7192
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