DevPciIch9.cpp@ 64387

Last change on this file since 64387 was 64387, checked in by vboxsync, 8 years ago
PDM,Devices: Some PCI device type cleanup.
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1	/* $Id: DevPciIch9.cpp 64387 2016-10-24 14:06:02Z vboxsync $ */
2	/** @file
3	* DevPCI - ICH9 southbridge PCI bus emulation device.
4	*
5	* @note bird: I've cleaned up DevPCI.cpp to some extent, this file has not
6	* be cleaned up and because of pending code merge.
7	*/
8
9	/*
10	* Copyright (C) 2010-2016 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/*********************************************************************************************************************************
23	* Header Files *
24	*********************************************************************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PCI
26	#define PCIBus ICH9PCIBus /*< HACK ALERT! Real ugly type hack! /
27	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
28	#include <VBox/vmm/pdmpcidev.h>
29
30	#include <VBox/msi.h>
31	#include <VBox/vmm/pdmdev.h>
32	#include <VBox/vmm/mm.h>
33	#include <iprt/asm.h>
34	#include <iprt/assert.h>
35	#include <iprt/string.h>
36	#ifdef IN_RING3
37	# include <iprt/mem.h>
38	#endif
39
40	#include "PciInline.h"
41	#include "VBoxDD.h"
42	#include "MsiCommon.h"
43
44
45	/*********************************************************************************************************************************
46	* Structures and Typedefs *
47	*********************************************************************************************************************************/
48	/**
49	* PCI Bus instance.
50	*/
51	typedef struct ICH9PCIBus
52	{
53	/** Bus number. */
54	int32_t iBus;
55	/** Number of bridges attached to the bus. */
56	uint32_t cBridges;
57
58	/** Array of PCI devices. We assume 32 slots, each with 8 functions. */
59	R3PTRTYPE(PPDMPCIDEV) apDevices[256];
60	/** Array of bridges attached to the bus. */
61	R3PTRTYPE(PPDMPCIDEV *) papBridgesR3;
62
63	/** R3 pointer to the device instance. */
64	PPDMDEVINSR3 pDevInsR3;
65	/** Pointer to the PCI R3 helpers. */
66	PCPDMPCIHLPR3 pPciHlpR3;
67
68	/** R0 pointer to the device instance. */
69	PPDMDEVINSR0 pDevInsR0;
70	/** Pointer to the PCI R0 helpers. */
71	PCPDMPCIHLPR0 pPciHlpR0;
72
73	/** RC pointer to the device instance. */
74	PPDMDEVINSRC pDevInsRC;
75	/** Pointer to the PCI RC helpers. */
76	PCPDMPCIHLPRC pPciHlpRC;
77
78	/** The PCI device for the PCI bridge. */
79	PDMPCIDEV aPciDev;
80
81	/** Start device number - always zero (only for DevPCI source compat). */
82	uint32_t iDevSearch;
83	/** Size alignemnt padding. */
84	uint32_t u32Alignment;
85	} ICH9PCIBUS, *PICH9PCIBUS;
86
87
88	/** @def PCI_APIC_IRQ_PINS
89	* Number of pins for interrupts if the APIC is used.
90	*/
91	#define PCI_APIC_IRQ_PINS 8
92
93	/**
94	* PCI Globals - This is the host-to-pci bridge and the root bus.
95	*/
96	typedef struct
97	{
98	/** R3 pointer to the device instance. */
99	PPDMDEVINSR3 pDevInsR3;
100	/** R0 pointer to the device instance. */
101	PPDMDEVINSR0 pDevInsR0;
102	/** RC pointer to the device instance. */
103	PPDMDEVINSRC pDevInsRC;
104
105	/** Value latched in Configuration Address Port (0CF8h) */
106	uint32_t uConfigReg;
107
108	/** I/O APIC irq levels */
109	volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
110
111	#if 1 /* Will be moved into the BIOS soon. */
112	/** The next I/O port address which the PCI BIOS will use. */
113	uint32_t uPciBiosIo;
114	/** The next MMIO address which the PCI BIOS will use. */
115	uint32_t uPciBiosMmio;
116	/** The next 64-bit MMIO address which the PCI BIOS will use. */
117	uint64_t uPciBiosMmio64;
118	/** Actual bus number. */
119	uint8_t uBus;
120	uint8_t Alignment0[7];
121	#endif
122	/** Physical address of PCI config space MMIO region. */
123	uint64_t u64PciConfigMMioAddress;
124	/** Length of PCI config space MMIO region. */
125	uint64_t u64PciConfigMMioLength;
126
127	/** PCI bus which is attached to the host-to-PCI bridge. */
128	ICH9PCIBUS aPciBus;
129	} ICH9PCIGLOBALS, *PICH9PCIGLOBALS;
130
131
132	/**
133	* PCI configuration space address.
134	*/
135	typedef struct
136	{
137	uint8_t iBus;
138	uint8_t iDeviceFunc;
139	uint16_t iRegister;
140	} PciAddress;
141
142	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
143
144
145	/*********************************************************************************************************************************
146	* Defined Constants And Macros *
147	*********************************************************************************************************************************/
148
149	/** @def VBOX_ICH9PCI_SAVED_STATE_VERSION
150	* Saved state version of the ICH9 PCI bus device.
151	*/
152	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI 1
153	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI 2
154	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI
155
156	/** Converts a bus instance pointer to a device instance pointer. */
157	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
158	/** Converts a device instance pointer to a ICH9PCIGLOBALS pointer. */
159	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PICH9PCIGLOBALS)(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)))
160	/** Converts a device instance pointer to a PCIBUS pointer. */
161	#define DEVINS_2_PCIBUS(pDevIns) ((PICH9PCIBUS)(&PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS)->aPciBus))
162	/** Converts a pointer to a PCI root bus instance to a PCIGLOBALS pointer. */
163	#define PCIROOTBUS_2_PCIGLOBALS(pPciBus) ( (PICH9PCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(ICH9PCIGLOBALS, aPciBus)) )
164
165	/** @def PCI_LOCK
166	* Acquires the PDM lock. This is a NOP if locking is disabled. */
167	/** @def PCI_UNLOCK
168	* Releases the PDM lock. This is a NOP if locking is disabled. */
169	#define PCI_LOCK(pDevIns, rc) \
170	do { \
171	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
172	if (rc2 != VINF_SUCCESS) \
173	return rc2; \
174	} while (0)
175	#define PCI_UNLOCK(pDevIns) \
176	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
177
178	/* Prototypes */
179	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev,
180	int iIrq, int iLevel, uint32_t uTagSrc);
181	#ifdef IN_RING3
182	static void ich9pcibridgeReset(PPDMDEVINS pDevIns);
183	static void ich9pciUpdateMappings(PDMPCIDEV *pDev);
184	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t u32Address, unsigned len);
185	static DECLCALLBACK(void) ich9pciConfigWriteDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t u32Address, uint32_t val, unsigned len);
186	DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);
187	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn);
188	#endif
189
190	// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
191	// mapping, we take n=6 approach
192	DECLINLINE(void) ich9pciPhysToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
193	{
194	NOREF(pGlobals);
195	pPciAddr->iBus = (GCPhysAddr >> 20) & ((1<<6) - 1);
196	pPciAddr->iDeviceFunc = (GCPhysAddr >> 12) & ((1<<(5+3)) - 1); // 5 bits - device, 3 bits - function
197	pPciAddr->iRegister = (GCPhysAddr >> 0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
198	}
199
200	DECLINLINE(void) ich9pciStateToPciAddr(PICH9PCIGLOBALS pGlobals, RTGCPHYS addr, PciAddress* pPciAddr)
201	{
202	pPciAddr->iBus = (pGlobals->uConfigReg >> 16) & 0xff;
203	pPciAddr->iDeviceFunc = (pGlobals->uConfigReg >> 8) & 0xff;
204	pPciAddr->iRegister = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
205	}
206
207	PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
208	{
209	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
210	ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
211	}
212
213	PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
214	{
215	/*
216	* The PCI-to-PCI bridge specification defines how the interrupt pins
217	* are routed from the secondary to the primary bus (see chapter 9).
218	* iIrq gives the interrupt pin the pci device asserted.
219	* We change iIrq here according to the spec and call the SetIrq function
220	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
221	*/
222	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
223	PPDMPCIDEV pPciDevBus = pPciDev;
224	int iIrqPinBridge = iIrq;
225	uint8_t uDevFnBridge = 0;
226
227	/* Walk the chain until we reach the host bus. */
228	do
229	{
230	uDevFnBridge = pBus->aPciDev.devfn;
231	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
232
233	/* Get the parent. */
234	pBus = pBus->aPciDev.Int.s.CTX_SUFF(pBus);
235	pPciDevBus = &pBus->aPciDev;
236	} while (pBus->iBus != 0);
237
238	AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
239	ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
240	}
241
242
243	/**
244	* Port I/O Handler for PCI address OUT operations.
245	*
246	* Emulates writes to Configuration Address Port at 0CF8h for
247	* Configuration Mechanism #1.
248	*
249	* @returns VBox status code.
250	*
251	* @param pDevIns ICH9 device instance.
252	* @param pvUser User argument - ignored.
253	* @param uPort Port number used for the OUT operation.
254	* @param u32 The value to output.
255	* @param cb The value size in bytes.
256	*/
257	PDMBOTHCBDECL(int) ich9pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
258	{
259	LogFlow(("ich9pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
260	RT_NOREF2(Port, pvUser);
261	if (cb == 4)
262	{
263	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
264
265	/*
266	* bits [1:0] are hard-wired, read-only and must return zeroes
267	* when read.
268	*/
269	u32 &= ~3;
270
271	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
272	pThis->uConfigReg = u32;
273	PCI_UNLOCK(pDevIns);
274	}
275
276	return VINF_SUCCESS;
277	}
278
279
280	/**
281	* Port I/O Handler for PCI address IN operations.
282	*
283	* Emulates reads from Configuration Address Port at 0CF8h for
284	* Configuration Mechanism #1.
285	*
286	* @returns VBox status code.
287	*
288	* @param pDevIns ICH9 device instance.
289	* @param pvUser User argument - ignored.
290	* @param uPort Port number used for the IN operation.
291	* @param pu32 Where to store the result.
292	* @param cb Number of bytes read.
293	*/
294	PDMBOTHCBDECL(int) ich9pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
295	{
296	RT_NOREF2(Port, pvUser);
297	if (cb == 4)
298	{
299	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
300
301	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
302	*pu32 = pThis->uConfigReg;
303	PCI_UNLOCK(pDevIns);
304
305	LogFlow(("ich9pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
306	return VINF_SUCCESS;
307	}
308
309	Log(("ich9pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
310	return VERR_IOM_IOPORT_UNUSED;
311	}
312
313
314	/*
315	* Perform configuration space write.
316	*/
317	static int ich9pciDataWriteAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pAddr,
318	uint32_t val, int cb, int rcReschedule)
319	{
320	int rc = VINF_SUCCESS;
321	#ifdef IN_RING3
322	NOREF(rcReschedule);
323	#else
324	RT_NOREF2(val, cb);
325	#endif
326
327	if (pAddr->iBus != 0) /* forward to subordinate bus */
328	{
329	if (pGlobals->aPciBus.cBridges)
330	{
331	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
332	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);
333	if (pBridgeDevice)
334	{
335	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
336	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc,
337	pAddr->iRegister, val, cb);
338	}
339	#else
340	rc = rcReschedule;
341	#endif
342	}
343	}
344	else /* forward to directly connected device */
345	{
346	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];
347	if (pPciDev)
348	{
349	#ifdef IN_RING3
350	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, pAddr->iRegister, val, cb);
351	#else
352	rc = rcReschedule;
353	#endif
354	}
355	}
356
357	Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n",
358	pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister,
359	cb, val, rc));
360	return rc;
361	}
362
363
364	/*
365	* Decode value latched in Configuration Address Port and perform
366	* requsted write to the target configuration space register.
367	*
368	* XXX: This code should be probably moved to its only caller
369	* (ich9pciIOPortDataWrite) to avoid prolifiration of confusingly
370	* similarly named functions.
371	*/
372	static int ich9pciDataWrite(PICH9PCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
373	{
374	LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
375
376	/* Configuration space mapping enabled? */
377	if (!(pGlobals->uConfigReg & (1 << 31)))
378	return VINF_SUCCESS;
379
380	/* Decode target device and configuration space register */
381	PciAddress aPciAddr;
382	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
383
384	/* Perform configuration space write */
385	return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_R3_IOPORT_WRITE);
386	}
387
388
389	/**
390	* Port I/O Handler for PCI data OUT operations.
391	*
392	* Emulates writes to Configuration Data Port at 0CFCh for
393	* Configuration Mechanism #1.
394	*
395	* @returns VBox status code.
396	*
397	* @param pDevIns ICH9 device instance.
398	* @param pvUser User argument - ignored.
399	* @param uPort Port number used for the OUT operation.
400	* @param u32 The value to output.
401	* @param cb The value size in bytes.
402	*/
403	PDMBOTHCBDECL(int) ich9pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
404	{
405	LogFlow(("ich9pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
406	NOREF(pvUser);
407	int rc = VINF_SUCCESS;
408	if (!(Port % cb))
409	{
410	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
411
412	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
413	rc = ich9pciDataWrite(pThis, Port, u32, cb);
414	PCI_UNLOCK(pDevIns);
415	}
416	else
417	AssertMsgFailed(("Unaligned write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
418	return rc;
419	}
420
421
422	static void ich9pciNoMem(void* ptr, int cb)
423	{
424	for (int i = 0; i < cb; i++)
425	((uint8_t*)ptr)[i] = 0xff;
426	}
427
428
429	/*
430	* Perform configuration space read.
431	*/
432	static int ich9pciDataReadAddr(PICH9PCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb,
433	uint32_t *pu32, int rcReschedule)
434	{
435	int rc = VINF_SUCCESS;
436	#ifdef IN_RING3
437	NOREF(rcReschedule);
438	#endif
439
440	if (pPciAddr->iBus != 0) /* forward to subordinate bus */
441	{
442	if (pGlobals->aPciBus.cBridges)
443	{
444	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
445	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);
446	if (pBridgeDevice)
447	{
448	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
449	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb);
450	}
451	else
452	ich9pciNoMem(pu32, cb);
453	#else
454	rc = rcReschedule;
455	#endif
456	}
457	else
458	ich9pciNoMem(pu32, cb);
459	}
460	else /* forward to directly connected device */
461	{
462	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];
463	if (pPciDev)
464	{
465	#ifdef IN_RING3
466	*pu32 = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, pPciAddr->iRegister, cb);
467	#else
468	rc = rcReschedule;
469	#endif
470	}
471	else
472	ich9pciNoMem(pu32, cb);
473	}
474
475	Log3(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",
476	pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister,
477	cb, *pu32, rc));
478	return rc;
479	}
480
481
482	/*
483	* Decode value latched in Configuration Address Port and perform
484	* requsted read from the target configuration space register.
485	*
486	* XXX: This code should be probably moved to its only caller
487	* (ich9pciIOPortDataRead) to avoid prolifiration of confusingly
488	* similarly named functions.
489	*/
490	static int ich9pciDataRead(PICH9PCIGLOBALS pGlobals, uint32_t addr, int cb, uint32_t *pu32)
491	{
492	LogFlow(("ich9pciDataRead: config=%x cb=%d\n", pGlobals->uConfigReg, cb));
493
494	*pu32 = 0xffffffff;
495
496	/* Configuration space mapping enabled? */
497	if (!(pGlobals->uConfigReg & (1 << 31)))
498	return VINF_SUCCESS;
499
500	/* Decode target device and configuration space register */
501	PciAddress aPciAddr;
502	ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
503
504	/* Perform configuration space read */
505	return ich9pciDataReadAddr(pGlobals, &aPciAddr, cb, pu32, VINF_IOM_R3_IOPORT_READ);
506	}
507
508
509	/**
510	* Port I/O Handler for PCI data IN operations.
511	*
512	* Emulates reads from Configuration Data Port at 0CFCh for
513	* Configuration Mechanism #1.
514	*
515	* @returns VBox status code.
516	*
517	* @param pDevIns ICH9 device instance.
518	* @param pvUser User argument - ignored.
519	* @param uPort Port number used for the IN operation.
520	* @param pu32 Where to store the result.
521	* @param cb Number of bytes read.
522	*/
523	PDMBOTHCBDECL(int) ich9pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
524	{
525	NOREF(pvUser);
526	if (!(Port % cb))
527	{
528	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
529
530	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
531	int rc = ich9pciDataRead(pThis, Port, cb, pu32);
532	PCI_UNLOCK(pDevIns);
533
534	LogFlow(("ich9pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
535	return rc;
536	}
537	AssertMsgFailed(("Unaligned read from port %#x cb=%d\n", Port, cb));
538	return VERR_IOM_IOPORT_UNUSED;
539	}
540
541
542	/* Compute mapping of PCI slot and IRQ number to APIC interrupt line */
543	DECLINLINE(int) ich9pciSlot2ApicIrq(uint8_t uSlot, int irq_num)
544	{
545	return (irq_num + uSlot) & 7;
546	}
547
548	#ifdef IN_RING3
549
550	/* return the global irq number corresponding to a given device irq
551	pin. We could also use the bus number to have a more precise
552	mapping. This is the implementation note described in the PCI spec chapter 2.2.6 */
553	DECLINLINE(int) ich9pciSlotGetPirq(uint8_t uBus, uint8_t uDevFn, int iIrqNum)
554	{
555	NOREF(uBus);
556	int iSlotAddend = (uDevFn >> 3) - 1;
557	return (iIrqNum + iSlotAddend) & 3;
558	}
559
560	/* irqs corresponding to PCI irqs A-D, must match pci_irq_list in rombios.c */
561	static const uint8_t aPciIrqs[4] = { 11, 10, 9, 5 };
562
563	#endif /* IN_RING3 */
564
565	/* Add one more level up request on APIC input line */
566	DECLINLINE(void) ich9pciApicLevelUp(PICH9PCIGLOBALS pGlobals, int irq_num)
567	{
568	ASMAtomicIncU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
569	}
570
571	/* Remove one level up request on APIC input line */
572	DECLINLINE(void) ich9pciApicLevelDown(PICH9PCIGLOBALS pGlobals, int irq_num)
573	{
574	ASMAtomicDecU32(&pGlobals->uaPciApicIrqLevels[irq_num]);
575	}
576
577	static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel,
578	uint32_t uTagSrc, int iForcedIrq)
579	{
580	/* This is only allowed to be called with a pointer to the root bus. */
581	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
582
583	if (iForcedIrq == -1)
584	{
585	int apic_irq, apic_level;
586	PICH9PCIGLOBALS pGlobals = PCIROOTBUS_2_PCIGLOBALS(pBus);
587	int irq_num = ich9pciSlot2ApicIrq(uDevFn >> 3, irq_num1);
588
589	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
590	ich9pciApicLevelUp(pGlobals, irq_num);
591	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
592	ich9pciApicLevelDown(pGlobals, irq_num);
593
594	apic_irq = irq_num + 0x10;
595	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
596	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n",
597	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
598	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
599
600	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
601	{
602	/*
603	* we raised it few lines above, as PDM_IRQ_LEVEL_FLIP_FLOP has
604	* PDM_IRQ_LEVEL_HIGH bit set
605	*/
606	ich9pciApicLevelDown(pGlobals, irq_num);
607	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
608	apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0;
609	Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n",
610	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc));
611	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
612	}
613	} else {
614	Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n",
615	R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq, uTagSrc));
616	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc);
617	}
618	}
619
620	static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev,
621	int iIrq, int iLevel, uint32_t uTagSrc)
622	{
623	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
624	* register interrupt bit state.
625	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
626	* that undefined behavior. We check for MSI first, then MSI-X.
627	*/
628	if (MsiIsEnabled(pPciDev))
629	{
630	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
631	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
632	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
633	MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
634	return;
635	}
636
637	if (MsixIsEnabled(pPciDev))
638	{
639	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
640	PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns);
641	MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
642	return;
643	}
644
645	PICH9PCIBUS pBus = &pGlobals->aPciBus;
646	const bool fIsAcpiDevice = PCIDevGetDeviceId(pPciDev) == 0x7113;
647
648	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
649	/* Check if the state changed. */
650	if (pPciDev->Int.s.uIrqPinState != iLevel)
651	{
652	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
653
654	/* Send interrupt to I/O APIC only now. */
655	if (fIsAcpiDevice)
656	/*
657	* ACPI needs special treatment since SCI is hardwired and
658	* should not be affected by PCI IRQ routing tables at the
659	* same time SCI IRQ is shared in PCI sense hence this
660	* kludge (i.e. we fetch the hardwired value from ACPIs
661	* PCI device configuration space).
662	*/
663	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev));
664	else
665	ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1);
666	}
667	}
668
669
670	/**
671	* Memory mapped I/O Handler for write operations.
672	*
673	* Emulates writes to configuration space.
674	*
675	* @returns VBox status code.
676	*
677	* @param pDevIns The device instance.
678	* @param pvUser User argument.
679	* @param GCPhysAddr Physical address (in GC) where the read starts.
680	* @param pv Where to fetch the result.
681	* @param cb Number of bytes to write.
682	* @remarks Caller enters the device critical section.
683	*/
684	PDMBOTHCBDECL(int) ich9pciMcfgMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
685	{
686	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
687	uint32_t u32 = 0;
688	NOREF(pvUser);
689
690	Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
691
692	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_WRITE);
693
694	/* Decode target device and configuration space register */
695	PciAddress aDest;
696	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
697
698	switch (cb)
699	{
700	case 1:
701	u32 = (uint8_t)pv;
702	break;
703	case 2:
704	u32 = (uint16_t)pv;
705	break;
706	case 4:
707	u32 = (uint32_t)pv;
708	break;
709	default:
710	Assert(false);
711	break;
712	}
713
714	/* Perform configuration space write */
715	int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE);
716	PCI_UNLOCK(pDevIns);
717
718	return rc;
719	}
720
721
722	/**
723	* Memory mapped I/O Handler for read operations.
724	*
725	* Emulates reads from configuration space.
726	*
727	* @returns VBox status code.
728	*
729	* @param pDevIns The device instance.
730	* @param pvUser User argument.
731	* @param GCPhysAddr Physical address (in GC) where the read starts.
732	* @param pv Where to store the result.
733	* @param cb Number of bytes read.
734	* @remarks Caller enters the device critical section.
735	*/
736	PDMBOTHCBDECL(int) ich9pciMcfgMMIORead (PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
737	{
738	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
739	uint32_t rv;
740	NOREF(pvUser);
741
742	LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
743
744	PCI_LOCK(pDevIns, VINF_IOM_R3_MMIO_READ);
745
746	/* Decode target device and configuration space register */
747	PciAddress aDest;
748	ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
749
750	/* Perform configuration space read */
751	int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_R3_MMIO_READ);
752
753	if (RT_SUCCESS(rc))
754	{
755	switch (cb)
756	{
757	case 1:
758	(uint8_t)pv = (uint8_t)rv;
759	break;
760	case 2:
761	(uint16_t)pv = (uint16_t)rv;
762	break;
763	case 4:
764	(uint32_t)pv = (uint32_t)rv;
765	break;
766	default:
767	Assert(false);
768	break;
769	}
770	}
771	PCI_UNLOCK(pDevIns);
772
773	return rc;
774	}
775
776	#ifdef IN_RING3
777
778	/*
779	* Include code we share with the other PCI bus implementation.
780	*
781	* Note! No #ifdefs, use instant data booleans/flags/whatever. Goal is to
782	* completely merge these files! File #1 contains code we write, where
783	* as a possible file #2 contains external code if there's any left.
784	*/
785	typedef PICH9PCIBUS PPCIMERGEDBUS;
786	# define pciR3UnmergedConfigReadDev ich9pciConfigReadDev
787	# define pciR3UnmergedConfigWriteDev ich9pciConfigWriteDev
788	# include "DevPciMerge1.cpp.h"
789
790
791	DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)
792	{
793	/* Search for a fitting bridge. */
794	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
795	{
796	/*
797	* Examine secondary and subordinate bus number.
798	* If the target bus is in the range we pass the request on to the bridge.
799	*/
800	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
801	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
802	("Device is not a PCI bridge but on the list of PCI bridges\n"));
803	uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS);
804	uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS);
805	Log3(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate));
806	if (iBus >= uSecondary && iBus <= uSubordinate)
807	return pBridge;
808	}
809
810	/* Nothing found. */
811	return NULL;
812	}
813
814	static uint32_t ich9pciGetCfg(PPDMPCIDEV pPciDev, int32_t iRegister, int cb)
815	{
816	return pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, iRegister, cb);
817	}
818
819	static uint8_t ich9pciGetByte(PPDMPCIDEV pPciDev, int32_t iRegister)
820	{
821	return (uint8_t)ich9pciGetCfg(pPciDev, iRegister, 1);
822	}
823
824	static uint16_t ich9pciGetWord(PPDMPCIDEV pPciDev, int32_t iRegister)
825	{
826	return (uint16_t)ich9pciGetCfg(pPciDev, iRegister, 2);
827	}
828
829	static uint32_t ich9pciGetDWord(PPDMPCIDEV pPciDev, int32_t iRegister)
830	{
831	return (uint32_t)ich9pciGetCfg(pPciDev, iRegister, 4);
832	}
833
834	DECLINLINE(uint32_t) ich9pciGetRegionReg(int iRegion)
835	{
836	return (iRegion == VBOX_PCI_ROM_SLOT) ?
837	VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
838	}
839
840	#define INVALID_PCI_ADDRESS ~0U
841
842	static int ich9pciUnmapRegion(PPDMPCIDEV pDev, int iRegion)
843	{
844	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
845	int rc = VINF_SUCCESS;
846	PICH9PCIBUS pBus = pDev->Int.s.CTX_SUFF(pBus);
847
848	Assert (pRegion->size != 0);
849
850	if (pRegion->addr != INVALID_PCI_ADDRESS)
851	{
852	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
853	{
854	/* Port IO */
855	rc = PDMDevHlpIOPortDeregister(pDev->Int.s.pDevInsR3, pRegion->addr, pRegion->size);
856	AssertRC(rc);
857	}
858	else
859	{
860	RTGCPHYS GCPhysBase = pRegion->addr;
861	if (pBus->pPciHlpR3->pfnIsMMIOExBase(pBus->pDevInsR3, pDev->Int.s.pDevInsR3, GCPhysBase))
862	{
863	/* unmap it. */
864	rc = pRegion->map_func(pDev->Int.s.pDevInsR3, pDev, iRegion,
865	NIL_RTGCPHYS, pRegion->size, (PCIADDRESSSPACE)(pRegion->type));
866	AssertRC(rc);
867	rc = PDMDevHlpMMIOExUnmap(pDev->Int.s.pDevInsR3, pDev, iRegion, GCPhysBase);
868	}
869	else
870	rc = PDMDevHlpMMIODeregister(pDev->Int.s.pDevInsR3, GCPhysBase, pRegion->size);
871	}
872
873	pRegion->addr = INVALID_PCI_ADDRESS;
874	}
875
876	return rc;
877	}
878
879	static void ich9pciUpdateMappings(PDMPCIDEV* pDev)
880	{
881	uint64_t uLast, uNew;
882
883	int iCmd = ich9pciGetWord(pDev, VBOX_PCI_COMMAND);
884	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
885	{
886	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
887	uint32_t uConfigReg = ich9pciGetRegionReg(iRegion);
888	int64_t iRegionSize = pRegion->size;
889	int rc;
890
891	if (iRegionSize == 0)
892	continue;
893
894	bool f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
895	== PCI_ADDRESS_SPACE_BAR64;
896
897	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
898	{
899	/* port IO region */
900	if (iCmd & PCI_COMMAND_IOACCESS)
901	{
902	/* IO access allowed */
903	uNew = ich9pciGetDWord(pDev, uConfigReg);
904	uNew &= ~(iRegionSize - 1);
905	uLast = uNew + iRegionSize - 1;
906	/* only 64K ioports on PC */
907	if (uLast <= uNew \|\| uNew == 0 \|\| uLast >= 0x10000)
908	uNew = INVALID_PCI_ADDRESS;
909	} else
910	uNew = INVALID_PCI_ADDRESS;
911	}
912	else
913	{
914	/* MMIO region */
915	if (iCmd & PCI_COMMAND_MEMACCESS)
916	{
917	uNew = ich9pciGetDWord(pDev, uConfigReg);
918	if (f64Bit)
919	uNew \|= (uint64_t)ich9pciGetDWord(pDev, uConfigReg + 4) << 32;
920
921	/* the ROM slot has a specific enable bit */
922	if (iRegion == PCI_ROM_SLOT && !(uNew & 1))
923	uNew = INVALID_PCI_ADDRESS;
924	else
925	{
926	uNew &= ~(iRegionSize - 1);
927	uLast = uNew + iRegionSize - 1;
928	/* NOTE: we do not support wrapping */
929	/* XXX: as we cannot support really dynamic
930	mappings, we handle specific values as invalid
931	mappings. */
932	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
933	if (uLast <= uNew \|\| uNew == 0 \|\| (uNew <= UINT32_C(0xffffffff) && uLast >= UINT32_C(0xfec00000)))
934	uNew = INVALID_PCI_ADDRESS;
935	}
936	} else
937	uNew = INVALID_PCI_ADDRESS;
938	}
939	LogRel2(("PCI: config dev %u/%u BAR%i uOld=%#018llx uNew=%#018llx size=%llu\n", pDev->devfn >> 3, pDev->devfn & 7, iRegion, pRegion->addr, uNew, pRegion->size));
940	/* now do the real mapping */
941	if (uNew != pRegion->addr)
942	{
943	if (pRegion->addr != INVALID_PCI_ADDRESS)
944	ich9pciUnmapRegion(pDev, iRegion);
945
946	pRegion->addr = uNew;
947	if (pRegion->addr != INVALID_PCI_ADDRESS)
948	{
949
950	/* finally, map the region */
951	rc = pRegion->map_func(pDev->Int.s.pDevInsR3, pDev, iRegion,
952	pRegion->addr, pRegion->size,
953	(PCIADDRESSSPACE)(pRegion->type));
954	AssertRC(rc);
955	}
956	}
957
958	if (f64Bit)
959	iRegion++;
960	}
961	}
962
963
964	static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
965	{
966	NOREF(pDevIns);
967	int rc;
968
969	rc = MsiInit(pPciDev, pMsiReg);
970	if (RT_FAILURE(rc))
971	return rc;
972
973	rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
974	if (RT_FAILURE(rc))
975	return rc;
976
977	return VINF_SUCCESS;
978	}
979
980
981	static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion,
982	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
983	{
984	NOREF(pDevIns);
985
986	/*
987	* Validate.
988	*/
989	AssertMsgReturn( enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR32)
990	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR32)
991	\|\| enmType == (PCI_ADDRESS_SPACE_MEM \| PCI_ADDRESS_SPACE_BAR64)
992	\|\| enmType == (PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_BAR64)
993	\|\| enmType == PCI_ADDRESS_SPACE_IO
994	,
995	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
996	VERR_INVALID_PARAMETER);
997	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
998	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
999	VERR_INVALID_PARAMETER);
1000	int iLastSet = ASMBitLastSetU64(cbRegion);
1001	AssertMsgReturn( iLastSet != 0
1002	&& RT_BIT_64(iLastSet - 1) == cbRegion,
1003	("Invalid cbRegion=%RGp iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1004	VERR_INVALID_PARAMETER);
1005
1006	Log(("ich9pciIORegionRegister: %s region %d size %RGp type %x\n",
1007	pPciDev->name, iRegion, cbRegion, enmType));
1008
1009	/* Make sure that we haven't marked this region as continuation of 64-bit region. */
1010	Assert(pPciDev->Int.s.aIORegions[iRegion].type != 0xff);
1011
1012	/*
1013	* Register the I/O region.
1014	*/
1015	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1016	pRegion->addr = INVALID_PCI_ADDRESS;
1017	pRegion->size = cbRegion;
1018	pRegion->type = enmType;
1019	pRegion->map_func = pfnCallback;
1020
1021	if ((enmType & PCI_ADDRESS_SPACE_BAR64) != 0)
1022	{
1023	/* VBOX_PCI_BASE_ADDRESS_5 and VBOX_PCI_ROM_ADDRESS are excluded. */
1024	AssertMsgReturn(iRegion < PCI_NUM_REGIONS - 2,
1025	("Region %d cannot be 64-bit\n", iRegion),
1026	VERR_INVALID_PARAMETER);
1027	/* Mark next region as continuation of this one. */
1028	pPciDev->Int.s.aIORegions[iRegion + 1].type = 0xff;
1029	}
1030
1031	/* Set type in the PCI config space. */
1032	uint32_t u32Value = (uint32_t)enmType & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH);
1033	PCIDevSetDWord(pPciDev, ich9pciGetRegionReg(iRegion), u32Value);
1034
1035	return VINF_SUCCESS;
1036	}
1037
1038	static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1039	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1040	{
1041	NOREF(pDevIns);
1042
1043	if (ppfnReadOld)
1044	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1045	pPciDev->Int.s.pfnConfigRead = pfnRead;
1046
1047	if (ppfnWriteOld)
1048	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1049	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1050	}
1051
1052	static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
1053	{
1054	/*
1055	* Iterate thru all the devices.
1056	*/
1057	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1058	{
1059	PPDMPCIDEV pDev = pBus->apDevices[i];
1060	if (pDev)
1061	{
1062	/* Device position */
1063	SSMR3PutU32(pSSM, i);
1064	/* PCI config registers */
1065	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1066
1067	/* Device flags */
1068	int rc = SSMR3PutU32(pSSM, pDev->Int.s.fFlags);
1069	if (RT_FAILURE(rc))
1070	return rc;
1071
1072	/* IRQ pin state */
1073	rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1074	if (RT_FAILURE(rc))
1075	return rc;
1076
1077	/* MSI info */
1078	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapOffset);
1079	if (RT_FAILURE(rc))
1080	return rc;
1081	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsiCapSize);
1082	if (RT_FAILURE(rc))
1083	return rc;
1084
1085	/* MSI-X info */
1086	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapOffset);
1087	if (RT_FAILURE(rc))
1088	return rc;
1089	rc = SSMR3PutU8(pSSM, pDev->Int.s.u8MsixCapSize);
1090	if (RT_FAILURE(rc))
1091	return rc;
1092	/* Save MSI-X page state */
1093	if (pDev->Int.s.u8MsixCapOffset != 0)
1094	{
1095	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1096	SSMR3PutMem(pSSM, pDev->Int.s.pMsixPageR3, 0x1000);
1097	if (RT_FAILURE(rc))
1098	return rc;
1099	}
1100	}
1101	}
1102	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1103	}
1104
1105	static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1106	{
1107	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1108
1109	/*
1110	* Bus state data.
1111	*/
1112	SSMR3PutU32(pSSM, pThis->uConfigReg);
1113
1114	/*
1115	* Save IRQ states.
1116	*/
1117	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1118	SSMR3PutU32(pSSM, pThis->uaPciApicIrqLevels[i]);
1119
1120	SSMR3PutU32(pSSM, UINT32_MAX); /* separator */
1121
1122	return ich9pciR3CommonSaveExec(&pThis->aPciBus, pSSM);
1123	}
1124
1125
1126	static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1127	{
1128	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1129	return ich9pciR3CommonSaveExec(pThis, pSSM);
1130	}
1131
1132
1133	static DECLCALLBACK(void) ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1134	{
1135	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1136
1137	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1138
1139	/* If the current bus is not the target bus search for the bus which contains the device. */
1140	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1141	{
1142	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1143	if (pBridgeDevice)
1144	{
1145	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1146	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
1147	}
1148	}
1149	else
1150	{
1151	/* This is the target bus, pass the write to the device. */
1152	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1153	if (pPciDev)
1154	{
1155	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1156	pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, u32Value, cb);
1157	}
1158	}
1159	}
1160
1161	static DECLCALLBACK(uint32_t) ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
1162	{
1163	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1164	uint32_t u32Value;
1165
1166	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1167
1168	/* If the current bus is not the target bus search for the bus which contains the device. */
1169	if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
1170	{
1171	PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, iBus);
1172	if (pBridgeDevice)
1173	{
1174	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
1175	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
1176	}
1177	else
1178	ich9pciNoMem(&u32Value, 4);
1179	}
1180	else
1181	{
1182	/* This is the target bus, pass the read to the device. */
1183	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1184	if (pPciDev)
1185	{
1186	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb);
1187	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
1188	}
1189	else
1190	ich9pciNoMem(&u32Value, 4);
1191	}
1192
1193	return u32Value;
1194	}
1195
1196
1197	/**
1198	* Common routine for restoring the config registers of a PCI device.
1199	*
1200	* @param pDev The PCI device.
1201	* @param pbSrcConfig The configuration register values to be loaded.
1202	* @param fIsBridge Whether this is a bridge device or not.
1203	*/
1204	static void pciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1205	{
1206	/*
1207	* This table defines the fields for normal devices and bridge devices, and
1208	* the order in which they need to be restored.
1209	*/
1210	static const struct PciField
1211	{
1212	uint8_t off;
1213	uint8_t cb;
1214	uint8_t fWritable;
1215	uint8_t fBridge;
1216	const char *pszName;
1217	} s_aFields[] =
1218	{
1219	/* off,cb,fW,fB, pszName */
1220	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1221	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1222	{ 0x06, 2, 1, 3, "STATUS" },
1223	{ 0x08, 1, 0, 3, "REVISION_ID" },
1224	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1225	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1226	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1227	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1228	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1229	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1230	{ 0x0f, 1, 1, 3, "BIST" },
1231	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1232	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1233	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1234	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1235	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1236	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1237	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1238	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1239	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1240	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1241	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1242	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1243	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1244	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1245	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1246	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1247	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1248	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1249	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1250	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1251	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1252	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1253	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1254	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1255	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1256	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1257	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1258	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1259	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1260	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1261	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1262	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1263	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1264	/* The COMMAND register must come last as it requires the ADDRESS
1265	registers to be restored before we pretent to change it from 0 to
1266	whatever value the guest assigned it. */
1267	{ 0x04, 2, 1, 3, "COMMAND" },
1268	};
1269
1270	#ifdef RT_STRICT
1271	/* Check that we've got full register coverage. */
1272	uint32_t bmDevice[0x40 / 32];
1273	uint32_t bmBridge[0x40 / 32];
1274	RT_ZERO(bmDevice);
1275	RT_ZERO(bmBridge);
1276	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1277	{
1278	uint8_t off = s_aFields[i].off;
1279	uint8_t cb = s_aFields[i].cb;
1280	uint8_t f = s_aFields[i].fBridge;
1281	while (cb-- > 0)
1282	{
1283	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1284	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1285	if (f & 1) ASMBitSet(bmDevice, off);
1286	if (f & 2) ASMBitSet(bmBridge, off);
1287	off++;
1288	}
1289	}
1290	for (uint32_t off = 0; off < 0x40; off++)
1291	{
1292	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1293	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1294	}
1295	#endif
1296
1297	/*
1298	* Loop thru the fields covering the 64 bytes of standard registers.
1299	*/
1300	uint8_t const fBridge = fIsBridge ? 2 : 1;
1301	Assert(!pciDevIsPassthrough(pDev));
1302	uint8_t *pbDstConfig = &pDev->config[0];
1303
1304	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1305	if (s_aFields[i].fBridge & fBridge)
1306	{
1307	uint8_t const off = s_aFields[i].off;
1308	uint8_t const cb = s_aFields[i].cb;
1309	uint32_t u32Src;
1310	uint32_t u32Dst;
1311	switch (cb)
1312	{
1313	case 1:
1314	u32Src = pbSrcConfig[off];
1315	u32Dst = pbDstConfig[off];
1316	break;
1317	case 2:
1318	u32Src = (uint16_t const )&pbSrcConfig[off];
1319	u32Dst = (uint16_t const )&pbDstConfig[off];
1320	break;
1321	case 4:
1322	u32Src = (uint32_t const )&pbSrcConfig[off];
1323	u32Dst = (uint32_t const )&pbDstConfig[off];
1324	break;
1325	default:
1326	AssertFailed();
1327	continue;
1328	}
1329
1330	if ( u32Src != u32Dst
1331	\|\| off == VBOX_PCI_COMMAND)
1332	{
1333	if (u32Src != u32Dst)
1334	{
1335	if (!s_aFields[i].fWritable)
1336	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1337	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1338	else
1339	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1340	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1341	}
1342	if (off == VBOX_PCI_COMMAND)
1343	PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
1344	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, off, u32Src, cb);
1345	}
1346	}
1347
1348	/*
1349	* The device dependent registers.
1350	*
1351	* We will not use ConfigWrite here as we have no clue about the size
1352	* of the registers, so the device is responsible for correctly
1353	* restoring functionality governed by these registers.
1354	*/
1355	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1356	if (pbDstConfig[off] != pbSrcConfig[off])
1357	{
1358	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1359	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1360	pbDstConfig[off] = pbSrcConfig[off];
1361	}
1362	}
1363
1364	/**
1365	* Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
1366	*
1367	* @returns VBox status code.
1368	* @param pBus The bus which data is being loaded.
1369	* @param pSSM The saved state handle.
1370	* @param uVersion The data version.
1371	* @param uPass The pass.
1372	*/
1373	static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1374	{
1375	uint32_t u32;
1376	uint32_t i;
1377	int rc;
1378
1379	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1380	if (uVersion != VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT)
1381	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1382
1383	/*
1384	* Iterate thru all the devices and write 0 to the COMMAND register so
1385	* that all the memory is unmapped before we start restoring the saved
1386	* mapping locations.
1387	*
1388	* The register value is restored afterwards so we can do proper
1389	* LogRels in pciR3CommonRestoreConfig.
1390	*/
1391	for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
1392	{
1393	PPDMPCIDEV pDev = pBus->apDevices[i];
1394	if (pDev)
1395	{
1396	uint16_t u16 = PCIDevGetCommand(pDev);
1397	pDev->Int.s.pfnConfigWrite(pDev->Int.s.CTX_SUFF(pDevIns), pDev, VBOX_PCI_COMMAND, 0, 2);
1398	PCIDevSetCommand(pDev, u16);
1399	Assert(PCIDevGetCommand(pDev) == u16);
1400	}
1401	}
1402
1403	void *pvMsixPage = RTMemTmpAllocZ(0x1000);
1404	AssertReturn(pvMsixPage, VERR_NO_TMP_MEMORY);
1405
1406	/*
1407	* Iterate all the devices.
1408	*/
1409	for (i = 0;; i++)
1410	{
1411	PPDMPCIDEV pDev;
1412	PDMPCIDEV DevTmp;
1413
1414	/* index / terminator */
1415	rc = SSMR3GetU32(pSSM, &u32);
1416	if (RT_FAILURE(rc))
1417	break;
1418	if (u32 == (uint32_t)~0)
1419	break;
1420	AssertMsgBreak(u32 < RT_ELEMENTS(pBus->apDevices) && u32 >= i, ("u32=%#x i=%#x\n", u32, i));
1421
1422	/* skip forward to the device checking that no new devices are present. */
1423	for (; i < u32; i++)
1424	{
1425	pDev = pBus->apDevices[i];
1426	if (pDev)
1427	{
1428	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pDev->name,
1429	PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev)));
1430	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1431	{
1432	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1433	i, pDev->name, PCIDevGetVendorId(pDev), PCIDevGetDeviceId(pDev));
1434	break;
1435	}
1436	}
1437	}
1438	if (RT_FAILURE(rc))
1439	break;
1440
1441	/* get the data */
1442	DevTmp.Int.s.fFlags = 0;
1443	DevTmp.Int.s.u8MsiCapOffset = 0;
1444	DevTmp.Int.s.u8MsiCapSize = 0;
1445	DevTmp.Int.s.u8MsixCapOffset = 0;
1446	DevTmp.Int.s.u8MsixCapSize = 0;
1447	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1448	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1449
1450	SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags);
1451	SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1452	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapOffset);
1453	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsiCapSize);
1454	SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapOffset);
1455	rc = SSMR3GetU8(pSSM, &DevTmp.Int.s.u8MsixCapSize);
1456	if (RT_FAILURE(rc))
1457	break;
1458
1459	/* Load MSI-X page state */
1460	if (DevTmp.Int.s.u8MsixCapOffset != 0)
1461	{
1462	Assert(pvMsixPage != NULL);
1463	rc = SSMR3GetMem(pSSM, pvMsixPage, 0x1000);
1464	if (RT_FAILURE(rc))
1465	break;
1466	}
1467
1468	/* check that it's still around. */
1469	pDev = pBus->apDevices[i];
1470	if (!pDev)
1471	{
1472	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1473	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1474	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1475	{
1476	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1477	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1478	break;
1479	}
1480	continue;
1481	}
1482
1483	/* match the vendor id assuming that this will never be changed. */
1484	if (PCIDevGetVendorId(&DevTmp) != PCIDevGetVendorId(pDev))
1485	{
1486	rc = SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1487	i, pDev->name, PCIDevGetVendorId(&DevTmp), PCIDevGetVendorId(pDev));
1488	break;
1489	}
1490
1491	/* commit the loaded device config. */
1492	Assert(!pciDevIsPassthrough(pDev));
1493	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1494
1495	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1496	pDev->Int.s.u8MsiCapOffset = DevTmp.Int.s.u8MsiCapOffset;
1497	pDev->Int.s.u8MsiCapSize = DevTmp.Int.s.u8MsiCapSize;
1498	pDev->Int.s.u8MsixCapOffset = DevTmp.Int.s.u8MsixCapOffset;
1499	pDev->Int.s.u8MsixCapSize = DevTmp.Int.s.u8MsixCapSize;
1500	if (DevTmp.Int.s.u8MsixCapSize != 0)
1501	{
1502	Assert(pDev->Int.s.pMsixPageR3 != NULL);
1503	memcpy(pDev->Int.s.pMsixPageR3, pvMsixPage, 0x1000);
1504	}
1505	}
1506
1507	RTMemTmpFree(pvMsixPage);
1508
1509	return rc;
1510	}
1511
1512	static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1513	{
1514	PICH9PCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1515	PICH9PCIBUS pBus = &pThis->aPciBus;
1516	uint32_t u32;
1517	int rc;
1518
1519	/* We ignore this version as there's no saved state with it anyway */
1520	if (uVersion == VBOX_ICH9PCI_SAVED_STATE_VERSION_NOMSI)
1521	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1522	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1523	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1524
1525	/*
1526	* Bus state data.
1527	*/
1528	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1529
1530	/*
1531	* Load IRQ states.
1532	*/
1533	for (int i = 0; i < PCI_APIC_IRQ_PINS; i++)
1534	SSMR3GetU32(pSSM, (uint32_t*)&pThis->uaPciApicIrqLevels[i]);
1535
1536	/* separator */
1537	rc = SSMR3GetU32(pSSM, &u32);
1538	if (RT_FAILURE(rc))
1539	return rc;
1540	if (u32 != (uint32_t)~0)
1541	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1542
1543	return ich9pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1544	}
1545
1546	static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1547	{
1548	PICH9PCIBUS pThis = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
1549	if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION_MSI)
1550	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1551	return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
1552	}
1553
1554
1555	/*
1556	* Perform imeediate read of configuration space register.
1557	* Cannot be rescheduled, as already in R3.
1558	*/
1559	static uint32_t ich9pciConfigRead(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len)
1560	{
1561	PciAddress aPciAddr;
1562	aPciAddr.iBus = uBus;
1563	aPciAddr.iDeviceFunc = uDevFn;
1564	aPciAddr.iRegister = addr;
1565
1566	uint32_t u32Val;
1567	int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
1568	AssertRC(rc);
1569
1570	return u32Val;
1571	}
1572
1573
1574	/*
1575	* Perform imeediate write to configuration space register.
1576	* Cannot be rescheduled, as already in R3.
1577	*/
1578	static void ich9pciConfigWrite(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val, uint32_t len)
1579	{
1580	PciAddress aPciAddr;
1581	aPciAddr.iBus = uBus;
1582	aPciAddr.iDeviceFunc = uDevFn;
1583	aPciAddr.iRegister = addr;
1584
1585	int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
1586	AssertRC(rc);
1587	}
1588
1589
1590	static void ich9pciSetRegionAddress(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int iRegion, uint64_t addr)
1591	{
1592	uint32_t uReg = ich9pciGetRegionReg(iRegion);
1593
1594	/* Read memory type first. */
1595	uint8_t uResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, uReg, 1);
1596	bool f64Bit = (uResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1597	== PCI_ADDRESS_SPACE_BAR64;
1598
1599	Log(("Set region address: %02x:%02x.%d region %d address=%RX64%s\n",
1600	uBus, uDevFn >> 3, uDevFn & 7, iRegion, addr, f64Bit ? " (64-bit)" : ""));
1601
1602	/* Write address of the device. */
1603	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg, (uint32_t)addr, 4);
1604	if (f64Bit)
1605	ich9pciConfigWrite(pGlobals, uBus, uDevFn, uReg + 4, (uint32_t)(addr >> 32), 4);
1606	}
1607
1608
1609	static void ich9pciBiosInitBridge(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1610	{
1611	Log(("BIOS init bridge: %02x::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1612
1613	/*
1614	* The I/O range for the bridge must be aligned to a 4KB boundary.
1615	* This does not change anything really as the access to the device is not going
1616	* through the bridge but we want to be compliant to the spec.
1617	*/
1618	if ((pGlobals->uPciBiosIo % 4096) != 0)
1619	{
1620	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1621	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosIo));
1622	}
1623	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0, 1);
1624
1625	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1626	if ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0)
1627	{
1628	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1629	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->uPciBiosMmio));
1630	}
1631	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0), 2);
1632
1633	/* Save values to compare later to. */
1634	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
1635	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
1636	uint8_t uBridgeBus = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, 1);
1637
1638	/* Init devices behind the bridge and possibly other bridges as well. */
1639	for (int iDev = 0; iDev <= 255; iDev++)
1640	ich9pciBiosInitDevice(pGlobals, uBridgeBus, iDev);
1641
1642	/*
1643	* Set I/O limit register. If there is no device with I/O space behind the bridge
1644	* we set a lower value than in the base register.
1645	* The result with a real bridge is that no I/O transactions are passed to the secondary
1646	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1647	*/
1648	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % 4096) != 0))
1649	{
1650	/* The upper boundary must be one byte less than a 4KB boundary. */
1651	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, 4*1024);
1652	}
1653
1654	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1, 1);
1655
1656	/* Same with the MMIO limit register but with 1MB boundary here. */
1657	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % (1024 * 1024)) != 0))
1658	{
1659	/* The upper boundary must be one byte less than a 1MB boundary. */
1660	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, 1024*1024);
1661	}
1662	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1, 2);
1663
1664	/*
1665	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1666	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1667	* the base register than in the limit register.
1668	*/
1669	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0, 2);
1670	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0, 2);
1671	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00, 4);
1672	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00, 4);
1673	}
1674
1675	static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn)
1676	{
1677	uint16_t uDevClass, uVendor, uDevice;
1678	uint8_t uCmd;
1679
1680	uDevClass = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_CLASS_DEVICE, 2);
1681	uVendor = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_VENDOR_ID, 2);
1682	uDevice = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_DEVICE_ID, 2);
1683
1684	/* If device is present */
1685	if (uVendor == 0xffff)
1686	return;
1687
1688	Log(("BIOS init device: %02x:%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7));
1689
1690	switch (uDevClass)
1691	{
1692	case 0x0101:
1693	/* IDE controller */
1694	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x40, 0x8000, 2); /* enable IDE0 */
1695	ich9pciConfigWrite(pGlobals, uBus, uDevFn, 0x42, 0x8000, 2); /* enable IDE1 */
1696	goto default_map;
1697	break;
1698	case 0x0300:
1699	/* VGA controller */
1700
1701	/* NB: Default Bochs VGA LFB address is 0xE0000000. Old guest
1702	* software may break if the framebuffer isn't mapped there.
1703	*/
1704
1705	/*
1706	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
1707	* only the framebuffer (i.e., a memory region) is explicitly registered via
1708	* ich9pciSetRegionAddress, so don't forget to enable I/O decoding.
1709	*/
1710	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 1);
1711	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND,
1712	uCmd \| PCI_COMMAND_IOACCESS,
1713	1);
1714	goto default_map;
1715	break;
1716	case 0x0604:
1717	/* PCI-to-PCI bridge. */
1718	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1719	ich9pciBiosInitBridge(pGlobals, uBus, uDevFn);
1720	break;
1721	default:
1722	default_map:
1723	{
1724	/* default memory mappings */
1725	bool fActiveMemRegion = false;
1726	bool fActiveIORegion = false;
1727	/*
1728	* We ignore ROM region here.
1729	*/
1730	for (int iRegion = 0; iRegion < (PCI_NUM_REGIONS-1); iRegion++)
1731	{
1732	uint32_t u32Address = ich9pciGetRegionReg(iRegion);
1733
1734	/* Calculate size - we write all 1s into the BAR, and then evaluate which bits
1735	are cleared. */
1736	uint8_t u8ResourceType = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 1);
1737
1738	bool f64Bit = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
1739	== PCI_ADDRESS_SPACE_BAR64;
1740	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
1741	uint64_t cbRegSize64 = 0;
1742
1743	if (f64Bit)
1744	{
1745	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1746	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address+4, UINT32_C(0xffffffff), 4);
1747	cbRegSize64 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1748	cbRegSize64 \|= ((uint64_t)ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address+4, 4) << 32);
1749	cbRegSize64 &= ~UINT64_C(0x0f);
1750	cbRegSize64 = (~cbRegSize64) + 1;
1751
1752	/* No 64-bit PIO regions possible. */
1753	#ifndef DEBUG_bird /* EFI triggers this for DevAHCI. */
1754	AssertMsg((u8ResourceType & PCI_COMMAND_IOACCESS) == 0, ("type=%#x rgn=%d\n", u8ResourceType, iRegion));
1755	#endif
1756	}
1757	else
1758	{
1759	uint32_t cbRegSize32;
1760	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff), 4);
1761	cbRegSize32 = ich9pciConfigRead(pGlobals, uBus, uDevFn, u32Address, 4);
1762
1763	/* Clear resource information depending on resource type. */
1764	if (fIsPio) /* PIO */
1765	cbRegSize32 &= ~UINT32_C(0x01);
1766	else /* MMIO */
1767	cbRegSize32 &= ~UINT32_C(0x0f);
1768
1769	/*
1770	* Invert all bits and add 1 to get size of the region.
1771	* (From PCI implementation note)
1772	*/
1773	if (fIsPio && (cbRegSize32 & UINT32_C(0xffff0000)) == 0)
1774	cbRegSize32 = (~(cbRegSize32 \| UINT32_C(0xffff0000))) + 1;
1775	else
1776	cbRegSize32 = (~cbRegSize32) + 1;
1777
1778	cbRegSize64 = cbRegSize32;
1779	}
1780	Log2(("%s: Size of region %u for device %d on bus %d is %lld\n", __FUNCTION__, iRegion, uDevFn, uBus, cbRegSize64));
1781
1782	if (cbRegSize64)
1783	{
1784	/* Try 32-bit base first. */
1785	uint32_t* paddr = fIsPio ? &pGlobals->uPciBiosIo : &pGlobals->uPciBiosMmio;
1786	uint64_t uNew = *paddr;
1787	/* Align starting address to region size. */
1788	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1789	if (fIsPio)
1790	uNew &= UINT32_C(0xffff);
1791	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
1792	if ( !uNew
1793	\|\| (uNew <= UINT32_C(0xffffffff) && uNew + cbRegSize64 - 1 >= UINT32_C(0xfec00000))
1794	\|\| uNew >= _4G)
1795	{
1796	if (f64Bit)
1797	{
1798	/* Map a 64-bit region above 4GB. */
1799	Assert(!fIsPio);
1800	uNew = pGlobals->uPciBiosMmio64;
1801	/* Align starting address to region size. */
1802	uNew = (uNew + cbRegSize64 - 1) & ~(cbRegSize64 - 1);
1803	LogFunc(("Start address of 64-bit MMIO region %u/%u is %#llx\n", iRegion, iRegion + 1, uNew));
1804	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1805	fActiveMemRegion = true;
1806	pGlobals->uPciBiosMmio64 = uNew + cbRegSize64;
1807	Log2Func(("New 64-bit address is %#llx\n", pGlobals->uPciBiosMmio64));
1808	}
1809	else
1810	{
1811	LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n",
1812	iRegion, uBus, uDevFn >> 3, uDevFn & 7, uVendor, uDevice)); /** @todo make this a VM start failure later. */
1813	/* Undo the mapping mess caused by the size probing. */
1814	ich9pciConfigWrite(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0), 4);
1815	}
1816	}
1817	else
1818	{
1819	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), iRegion, uNew));
1820	ich9pciSetRegionAddress(pGlobals, uBus, uDevFn, iRegion, uNew);
1821	if (fIsPio)
1822	fActiveIORegion = true;
1823	else
1824	fActiveMemRegion = true;
1825	*paddr = uNew + cbRegSize64;
1826	Log2Func(("New 32-bit address is %#x\n", *paddr));
1827	}
1828
1829	if (f64Bit)
1830	iRegion++; /* skip next region */
1831	}
1832	}
1833
1834	/* Update the command word appropriately. */
1835	uCmd = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, 2);
1836	if (fActiveMemRegion)
1837	uCmd \|= PCI_COMMAND_MEMACCESS; /* Enable MMIO access. */
1838	if (fActiveIORegion)
1839	uCmd \|= PCI_COMMAND_IOACCESS; /* Enable I/O space access. */
1840	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_COMMAND, uCmd, 2);
1841	break;
1842	}
1843	}
1844
1845	/* map the interrupt */
1846	uint32_t iPin = ich9pciConfigRead(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_PIN, 1);
1847	if (iPin != 0)
1848	{
1849	iPin--;
1850
1851	if (uBus != 0)
1852	{
1853	/* Find bus this device attached to. */
1854	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1855	while (1)
1856	{
1857	PPDMPCIDEV pBridge = ich9pciFindBridge(pBus, uBus);
1858	if (!pBridge)
1859	{
1860	Assert(false);
1861	break;
1862	}
1863	if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS))
1864	{
1865	/* OK, found bus this device attached to. */
1866	break;
1867	}
1868	pBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1869	}
1870
1871	/* We need to go up to the host bus to see which irq pin this
1872	* device will use there. See logic in ich9pcibridgeSetIrq().
1873	*/
1874	while (pBus->iBus != 0)
1875	{
1876	/* Get the pin the device would assert on the bridge. */
1877	iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3;
1878	pBus = pBus->aPciDev.Int.s.pBusR3;
1879	};
1880	}
1881
1882	int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)];
1883	Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n",
1884	iPin, iIrq, uBus, uDevFn>>3, uDevFn&7));
1885	ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1);
1886	}
1887	}
1888
1889	/**
1890	* Initializes bridges registers used for routing.
1891	*
1892	* @returns nothing.
1893	* @param pGlobals Global device instance data used to generate unique bus numbers.
1894	* @param pBus The PCI bus to initialize.
1895	* @param uBusPrimary The primary bus number the bus is connected to.
1896	* @param uBusSecondary The secondary bus number, i.e. the bus number behind the bridge.
1897	*/
1898	static void ich9pciInitBridgeTopology(PICH9PCIGLOBALS pGlobals, PICH9PCIBUS pBus, unsigned uBusPrimary,
1899	unsigned uBusSecondary)
1900	{
1901	PPDMPCIDEV pBridgeDev = &pBus->aPciDev;
1902
1903	/* Set only if we are not on the root bus, it has no primary bus attached. */
1904	if (uBusSecondary != 0)
1905	{
1906	PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, uBusPrimary);
1907	PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, uBusSecondary);
1908	}
1909
1910	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
1911	{
1912	PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge];
1913	AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge),
1914	("Device is not a PCI bridge but on the list of PCI bridges\n"));
1915	PICH9PCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PICH9PCIBUS);
1916	pGlobals->uBus++;
1917	ich9pciInitBridgeTopology(pGlobals, pChildBus, uBusSecondary, pGlobals->uBus);
1918	}
1919	PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1920	Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n",
1921	pBus,
1922	PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS),
1923	PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS),
1924	PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS)
1925	));
1926	}
1927
1928
1929	static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns)
1930	{
1931	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
1932	PVM pVM = PDMDevHlpGetVM(pDevIns);
1933	uint32_t const cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
1934	uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
1935
1936	/*
1937	* Set the start addresses.
1938	*/
1939	pGlobals->uPciBiosIo = 0xd000;
1940	pGlobals->uPciBiosMmio = cbBelow4GB;
1941	pGlobals->uPciBiosMmio64 = cbAbove4GB + _4G;
1942	pGlobals->uBus = 0;
1943
1944	/* NB: Assume that if MMIO range is enabled, it is at the bottom of the memory hole. */
1945	if (pGlobals->u64PciConfigMMioAddress)
1946	{
1947	AssertRelease(pGlobals->u64PciConfigMMioAddress >= cbBelow4GB);
1948	pGlobals->uPciBiosMmio = pGlobals->u64PciConfigMMioAddress + pGlobals->u64PciConfigMMioLength;
1949	}
1950	Log(("cbBelow4GB: %lX, uPciBiosMmio: %lX, cbAbove4GB: %llX\n", cbBelow4GB, pGlobals->uPciBiosMmio, cbAbove4GB));
1951
1952	/*
1953	* Assign bridge topology, for further routing to work.
1954	*/
1955	PICH9PCIBUS pBus = &pGlobals->aPciBus;
1956	ich9pciInitBridgeTopology(pGlobals, pBus, 0, 0);
1957
1958	/*
1959	* Init the devices.
1960	*/
1961	for (int i = 0; i < 256; i++)
1962	ich9pciBiosInitDevice(pGlobals, 0, i);
1963
1964	return VINF_SUCCESS;
1965	}
1966
1967
1968	/*
1969	* Configuration space read callback (PCIDEVICEINT::pfnConfigRead) for
1970	* connected devices.
1971	*/
1972	static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t u32Address, unsigned len)
1973	{
1974	NOREF(pDevIns);
1975	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
1976	{
1977	LogRel(("PCI: %8s/%u: Read from extended register %d fallen back to generic code\n",
1978	pPciDev->name, pPciDev->pDevIns->iInstance, u32Address));
1979	return 0;
1980	}
1981
1982	AssertMsgReturn(u32Address + len <= 256, ("Read after the end of PCI config space\n"),
1983	0);
1984	if ( pciDevIsMsiCapable(pPciDev)
1985	&& (u32Address >= pPciDev->Int.s.u8MsiCapOffset)
1986	&& (u32Address < (unsigned)(pPciDev->Int.s.u8MsiCapOffset + pPciDev->Int.s.u8MsiCapSize))
1987	)
1988	{
1989	return MsiPciConfigRead(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), pPciDev, u32Address, len);
1990	}
1991
1992	if ( pciDevIsMsixCapable(pPciDev)
1993	&& (u32Address >= pPciDev->Int.s.u8MsixCapOffset)
1994	&& (u32Address < (unsigned)(pPciDev->Int.s.u8MsixCapOffset + pPciDev->Int.s.u8MsixCapSize))
1995	)
1996	{
1997	return MsixPciConfigRead(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns), pPciDev, u32Address, len);
1998	}
1999
2000	AssertMsgReturn(u32Address + len <= 256, ("Read after end of PCI config space\n"),
2001	0);
2002	switch (len)
2003	{
2004	case 1:
2005	return PCIDevGetByte(pPciDev, u32Address);
2006	case 2:
2007	return PCIDevGetWord(pPciDev, u32Address);
2008	case 4:
2009	return PCIDevGetDWord(pPciDev, u32Address);
2010	default:
2011	Assert(false);
2012	return 0;
2013	}
2014	}
2015
2016
2017	DECLINLINE(void) ich9pciWriteBarByte(PPDMPCIDEV pPciDev, int iRegion, int iOffset, uint8_t u8Val)
2018	{
2019	PCIIORegion * pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2020	int64_t iRegionSize = pRegion->size;
2021
2022	Log3(("ich9pciWriteBarByte: region=%d off=%d val=%x size=%d\n",
2023	iRegion, iOffset, u8Val, iRegionSize));
2024
2025	if (iOffset > 3)
2026	Assert((pRegion->type & PCI_ADDRESS_SPACE_BAR64) != 0);
2027
2028	/* Check if we're writing to upper part of 64-bit BAR. */
2029	if (pRegion->type == 0xff)
2030	{
2031	ich9pciWriteBarByte(pPciDev, iRegion-1, iOffset+4, u8Val);
2032	return;
2033	}
2034
2035	/* Region doesn't exist */
2036	if (iRegionSize == 0)
2037	return;
2038
2039	uint32_t uAddr = ich9pciGetRegionReg(iRegion) + iOffset;
2040	/* Region size must be power of two */
2041	Assert((iRegionSize & (iRegionSize - 1)) == 0);
2042	uint8_t uMask = ((iRegionSize - 1) >> (iOffset*8) ) & 0xff;
2043
2044	if (iOffset == 0)
2045	{
2046	uMask \|= (pRegion->type & PCI_ADDRESS_SPACE_IO) ?
2047	(1 << 2) - 1 /* 2 lowest bits for IO region */ :
2048	(1 << 4) - 1 /* 4 lowest bits for memory region, also ROM enable bit for ROM region */;
2049
2050	}
2051
2052	uint8_t u8Old = PCIDevGetByte(pPciDev, uAddr) & uMask;
2053	u8Val = (u8Old & uMask) \| (u8Val & ~uMask);
2054
2055	Log3(("ich9pciWriteBarByte: was %x writing %x\n", u8Old, u8Val));
2056
2057	PCIDevSetByte(pPciDev, uAddr, u8Val);
2058	}
2059
2060
2061	/**
2062	* Configuration space write callback (PCIDEVICEINT::pfnConfigWrite)
2063	* for connected devices.
2064	*
2065	* See paragraph 7.5 of PCI Express specification (p. 349) for
2066	* definition of registers and their writability policy.
2067	*/
2068	static DECLCALLBACK(void) ich9pciConfigWriteDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
2069	uint32_t u32Address, uint32_t val, unsigned len)
2070	{
2071	NOREF(pDevIns);
2072	Assert(len <= 4);
2073
2074	if ((u32Address + len) > 256 && (u32Address + len) < 4096)
2075	{
2076	LogRel(("PCI: %8s/%u: Write to extended register %d fallen back to generic code\n",
2077	pPciDev->name, pPciDev->pDevIns->iInstance, u32Address));
2078	return;
2079	}
2080
2081	AssertMsgReturnVoid(u32Address + len <= 256, ("Write after end of PCI config space\n"));
2082
2083	if ( pciDevIsMsiCapable(pPciDev)
2084	&& (u32Address >= pPciDev->Int.s.u8MsiCapOffset)
2085	&& (u32Address < (unsigned)(pPciDev->Int.s.u8MsiCapOffset + pPciDev->Int.s.u8MsiCapSize))
2086	)
2087	{
2088	MsiPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2089	pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2090	pPciDev, u32Address, val, len);
2091	return;
2092	}
2093
2094	if ( pciDevIsMsixCapable(pPciDev)
2095	&& (u32Address >= pPciDev->Int.s.u8MsixCapOffset)
2096	&& (u32Address < (unsigned)(pPciDev->Int.s.u8MsixCapOffset + pPciDev->Int.s.u8MsixCapSize))
2097	)
2098	{
2099	MsixPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
2100	pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
2101	pPciDev, u32Address, val, len);
2102	return;
2103	}
2104
2105	uint32_t addr = u32Address;
2106	bool fUpdateMappings = false;
2107	bool fP2PBridge = false;
2108	/bool fPassthrough = pciDevIsPassthrough(pPciDev);/
2109	uint8_t u8HeaderType = ich9pciGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
2110
2111	for (uint32_t i = 0; i < len; i++)
2112	{
2113	bool fWritable = false;
2114	bool fRom = false;
2115	switch (u8HeaderType)
2116	{
2117	case 0x00: /* normal device */
2118	case 0x80: /* multi-function device */
2119	switch (addr)
2120	{
2121	/* Read-only registers */
2122	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2123	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2124	case VBOX_PCI_REVISION_ID:
2125	case VBOX_PCI_CLASS_PROG:
2126	case VBOX_PCI_CLASS_SUB:
2127	case VBOX_PCI_CLASS_BASE:
2128	case VBOX_PCI_HEADER_TYPE:
2129	case VBOX_PCI_SUBSYSTEM_VENDOR_ID: case VBOX_PCI_SUBSYSTEM_VENDOR_ID+1:
2130	case VBOX_PCI_SUBSYSTEM_ID: case VBOX_PCI_SUBSYSTEM_ID+1:
2131	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS+1: case VBOX_PCI_ROM_ADDRESS+2: case VBOX_PCI_ROM_ADDRESS+3:
2132	case VBOX_PCI_CAPABILITY_LIST:
2133	case VBOX_PCI_INTERRUPT_PIN:
2134	fWritable = false;
2135	break;
2136	/* Others can be written */
2137	default:
2138	fWritable = true;
2139	break;
2140	}
2141	break;
2142	case 0x01: /* PCI-PCI bridge */
2143	fP2PBridge = true;
2144	switch (addr)
2145	{
2146	/* Read-only registers */
2147	case VBOX_PCI_VENDOR_ID: case VBOX_PCI_VENDOR_ID+1:
2148	case VBOX_PCI_DEVICE_ID: case VBOX_PCI_DEVICE_ID+1:
2149	case VBOX_PCI_REVISION_ID:
2150	case VBOX_PCI_CLASS_PROG:
2151	case VBOX_PCI_CLASS_SUB:
2152	case VBOX_PCI_CLASS_BASE:
2153	case VBOX_PCI_HEADER_TYPE:
2154	case VBOX_PCI_ROM_ADDRESS_BR: case VBOX_PCI_ROM_ADDRESS_BR+1: case VBOX_PCI_ROM_ADDRESS_BR+2: case VBOX_PCI_ROM_ADDRESS_BR+3:
2155	case VBOX_PCI_INTERRUPT_PIN:
2156	fWritable = false;
2157	break;
2158	default:
2159	fWritable = true;
2160	break;
2161	}
2162	break;
2163	default:
2164	AssertMsgFailed(("Unknown header type %x\n", PCIDevGetHeaderType(pPciDev)));
2165	fWritable = false;
2166	break;
2167	}
2168
2169	uint8_t u8Val = (uint8_t)val;
2170	switch (addr)
2171	{
2172	case VBOX_PCI_COMMAND: /* Command register, bits 0-7. */
2173	fUpdateMappings = true;
2174	goto default_case;
2175	case VBOX_PCI_COMMAND+1: /* Command register, bits 8-15. */
2176	/* don't change reserved bits (11-15) */
2177	u8Val &= ~UINT32_C(0xf8);
2178	fUpdateMappings = true;
2179	goto default_case;
2180	case VBOX_PCI_STATUS: /* Status register, bits 0-7. */
2181	/* don't change read-only bits => actually all lower bits are read-only */
2182	u8Val &= ~UINT32_C(0xff);
2183	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
2184	pPciDev->config[addr] &= ~u8Val;
2185	break;
2186	case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */
2187	/* don't change read-only bits */
2188	u8Val &= ~UINT32_C(0x06);
2189	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
2190	pPciDev->config[addr] &= ~u8Val;
2191	break;
2192	case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3:
2193	fRom = true;
2194	case VBOX_PCI_BASE_ADDRESS_0: case VBOX_PCI_BASE_ADDRESS_0+1: case VBOX_PCI_BASE_ADDRESS_0+2: case VBOX_PCI_BASE_ADDRESS_0+3:
2195	case VBOX_PCI_BASE_ADDRESS_1: case VBOX_PCI_BASE_ADDRESS_1+1: case VBOX_PCI_BASE_ADDRESS_1+2: case VBOX_PCI_BASE_ADDRESS_1+3:
2196	case VBOX_PCI_BASE_ADDRESS_2: case VBOX_PCI_BASE_ADDRESS_2+1: case VBOX_PCI_BASE_ADDRESS_2+2: case VBOX_PCI_BASE_ADDRESS_2+3:
2197	case VBOX_PCI_BASE_ADDRESS_3: case VBOX_PCI_BASE_ADDRESS_3+1: case VBOX_PCI_BASE_ADDRESS_3+2: case VBOX_PCI_BASE_ADDRESS_3+3:
2198	case VBOX_PCI_BASE_ADDRESS_4: case VBOX_PCI_BASE_ADDRESS_4+1: case VBOX_PCI_BASE_ADDRESS_4+2: case VBOX_PCI_BASE_ADDRESS_4+3:
2199	case VBOX_PCI_BASE_ADDRESS_5: case VBOX_PCI_BASE_ADDRESS_5+1: case VBOX_PCI_BASE_ADDRESS_5+2: case VBOX_PCI_BASE_ADDRESS_5+3:
2200	{
2201	/* We check that, as same PCI register numbers as BARs may mean different registers for bridges */
2202	if (fP2PBridge)
2203	goto default_case;
2204	else
2205	{
2206	int iRegion = fRom ? VBOX_PCI_ROM_SLOT : (addr - VBOX_PCI_BASE_ADDRESS_0) >> 2;
2207	int iOffset = addr & 0x3;
2208	ich9pciWriteBarByte(pPciDev, iRegion, iOffset, u8Val);
2209	fUpdateMappings = true;
2210	}
2211	break;
2212	}
2213	default:
2214	default_case:
2215	if (fWritable)
2216	PCIDevSetByte(pPciDev, addr, u8Val);
2217	}
2218	addr++;
2219	val >>= 8;
2220	}
2221
2222	if (fUpdateMappings)
2223	/* if the command/base address register is modified, we must modify the mappings */
2224	ich9pciUpdateMappings(pPciDev);
2225	}
2226
2227
2228	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2229	{
2230	for (int i = 0; i < iIndent; i++)
2231	{
2232	pHlp->pfnPrintf(pHlp, " ");
2233	}
2234	}
2235
2236	static void ich9pciBusInfo(PICH9PCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2237	{
2238	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++)
2239	{
2240	PPDMPCIDEV pPciDev = pBus->apDevices[iDev];
2241	if (pPciDev != NULL)
2242	{
2243	printIndent(pHlp, iIndent);
2244
2245	/*
2246	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2247	* as host driver handles real devices interrupts.
2248	*/
2249	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x",
2250	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2251	pPciDev->name,
2252	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2253	ich9pciGetWord(pPciDev, VBOX_PCI_VENDOR_ID), ich9pciGetWord(pPciDev, VBOX_PCI_DEVICE_ID)
2254	);
2255	if (ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2256	{
2257	pHlp->pfnPrintf(pHlp, " IRQ%d", ich9pciGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2258	pHlp->pfnPrintf(pHlp, " (INTA#->IRQ%d)", 0x10 + ich9pciSlot2ApicIrq(iDev >> 3, 0));
2259	}
2260	pHlp->pfnPrintf(pHlp, "\n");
2261
2262	if (pciDevIsMsiCapable(pPciDev) \|\| pciDevIsMsixCapable(pPciDev))
2263	{
2264	printIndent(pHlp, iIndent + 2);
2265
2266	if (pciDevIsMsiCapable(pPciDev))
2267	pHlp->pfnPrintf(pHlp, "MSI:%s ", MsiIsEnabled(pPciDev) ? "on" : "off");
2268
2269	if (pciDevIsMsixCapable(pPciDev))
2270	pHlp->pfnPrintf(pHlp, "MSI-X:%s ", MsixIsEnabled(pPciDev) ? "on" : "off");
2271
2272	pHlp->pfnPrintf(pHlp, "\n");
2273	}
2274
2275	uint16_t iCmd = ich9pciGetWord(pPciDev, VBOX_PCI_COMMAND);
2276	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2277	{
2278	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2279	{
2280	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2281	uint64_t iRegionSize = pRegion->size;
2282
2283	if (iRegionSize == 0)
2284	continue;
2285
2286	uint32_t u32Addr = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion));
2287	const char * pszDesc;
2288	char szDescBuf[128];
2289
2290	bool f64Bit = (pRegion->type & ((uint8_t)(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_IO)))
2291	== PCI_ADDRESS_SPACE_BAR64;
2292	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2293	{
2294	pszDesc = "IO";
2295	u32Addr &= ~0x3;
2296	}
2297	else
2298	{
2299	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2300	f64Bit ? "64" : "32",
2301	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2302	pszDesc = szDescBuf;
2303	u32Addr &= ~0xf;
2304	}
2305
2306	printIndent(pHlp, iIndent + 2);
2307	pHlp->pfnPrintf(pHlp, "%s region #%d: ",pszDesc, iRegion);
2308	if (f64Bit)
2309	{
2310	uint32_t u32High = ich9pciGetDWord(pPciDev, ich9pciGetRegionReg(iRegion+1));
2311	uint64_t u64Addr = RT_MAKE_U64(u32Addr, u32High);
2312	pHlp->pfnPrintf(pHlp, "%RX64..%RX64\n", u64Addr, u64Addr+iRegionSize);
2313	iRegion++;
2314	}
2315	else
2316	pHlp->pfnPrintf(pHlp, "%x..%x\n", u32Addr, u32Addr+iRegionSize);
2317	}
2318	}
2319
2320	printIndent(pHlp, iIndent + 2);
2321	uint16_t iStatus = ich9pciGetWord(pPciDev, VBOX_PCI_STATUS);
2322	pHlp->pfnPrintf(pHlp, "Command: %04X, Status: %04X\n",
2323	iCmd, iStatus);
2324	printIndent(pHlp, iIndent + 2);
2325	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2326	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2327
2328	if (fRegisters)
2329	{
2330	printIndent(pHlp, iIndent + 2);
2331	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2332	for (int iReg = 0; iReg < 0x100; )
2333	{
2334	int iPerLine = 0x10;
2335	Assert (0x100 % iPerLine == 0);
2336	printIndent(pHlp, iIndent + 3);
2337
2338	while (iPerLine-- > 0)
2339	{
2340	pHlp->pfnPrintf(pHlp, "%02x ", ich9pciGetByte(pPciDev, iReg++));
2341	}
2342	pHlp->pfnPrintf(pHlp, "\n");
2343	}
2344	}
2345	}
2346	}
2347
2348	if (pBus->cBridges > 0)
2349	{
2350	printIndent(pHlp, iIndent);
2351	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2352	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2353	{
2354	PICH9PCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PICH9PCIBUS);
2355	ich9pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2356	}
2357	}
2358	}
2359
2360	/**
2361	* Info handler, device version.
2362	*
2363	* @param pDevIns Device instance which registered the info.
2364	* @param pHlp Callback functions for doing output.
2365	* @param pszArgs Argument string. Optional and specific to the handler.
2366	*/
2367	static DECLCALLBACK(void) ich9pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2368	{
2369	PICH9PCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2370
2371	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2372	{
2373	ich9pciBusInfo(pBus, pHlp, 0, false);
2374	}
2375	else if (!strcmp(pszArgs, "verbose"))
2376	{
2377	ich9pciBusInfo(pBus, pHlp, 0, true);
2378	}
2379	else
2380	{
2381	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2382	}
2383	}
2384
2385
2386	static DECLCALLBACK(int) ich9pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2387	{
2388	RT_NOREF1(iInstance);
2389	Assert(iInstance == 0);
2390	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2391
2392	/*
2393	* Validate and read configuration.
2394	*/
2395	if (!CFGMR3AreValuesValid(pCfg,
2396	"IOAPIC\0"
2397	"GCEnabled\0"
2398	"R0Enabled\0"
2399	"McfgBase\0"
2400	"McfgLength\0"
2401	))
2402	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2403
2404	/* query whether we got an IOAPIC */
2405	bool fUseIoApic;
2406	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2407	if (RT_FAILURE(rc))
2408	return PDMDEV_SET_ERROR(pDevIns, rc,
2409	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2410
2411	/* check if RC code is enabled. */
2412	bool fGCEnabled;
2413	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2414	if (RT_FAILURE(rc))
2415	return PDMDEV_SET_ERROR(pDevIns, rc,
2416	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2417	/* check if R0 code is enabled. */
2418	bool fR0Enabled;
2419	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2420	if (RT_FAILURE(rc))
2421	return PDMDEV_SET_ERROR(pDevIns, rc,
2422	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2423
2424	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2425
2426	/*
2427	* Init data.
2428	*/
2429	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2430	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2431	/* Zero out everything */
2432	memset(pGlobals, 0, sizeof(*pGlobals));
2433	/* And fill values */
2434	if (!fUseIoApic)
2435	return PDMDEV_SET_ERROR(pDevIns, rc,
2436	N_("Must use IO-APIC with ICH9 chipset"));
2437	rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pGlobals->u64PciConfigMMioAddress, 0);
2438	if (RT_FAILURE(rc))
2439	return PDMDEV_SET_ERROR(pDevIns, rc,
2440	N_("Configuration error: Failed to read \"McfgBase\""));
2441	rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pGlobals->u64PciConfigMMioLength, 0);
2442	if (RT_FAILURE(rc))
2443	return PDMDEV_SET_ERROR(pDevIns, rc,
2444	N_("Configuration error: Failed to read \"McfgLength\""));
2445
2446	pGlobals->pDevInsR3 = pDevIns;
2447	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2448	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2449
2450	pGlobals->aPciBus.pDevInsR3 = pDevIns;
2451	pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2452	pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2453	pGlobals->aPciBus.papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pGlobals->aPciBus.apDevices));
2454
2455	/*
2456	* Register bus
2457	*/
2458	PDMPCIBUSREG PciBusReg;
2459	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2460	PciBusReg.pfnRegisterR3 = pciR3MergedRegister;
2461	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2462	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2463	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2464	PciBusReg.pfnSetIrqR3 = ich9pciSetIrq;
2465	PciBusReg.pfnFakePCIBIOSR3 = ich9pciFakePCIBIOS;
2466	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pciSetIrq" : NULL;
2467	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pciSetIrq" : NULL;
2468	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2469	if (RT_FAILURE(rc))
2470	return PDMDEV_SET_ERROR(pDevIns, rc,
2471	N_("Failed to register ourselves as a PCI Bus"));
2472	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2473	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2474	N_("PCI helper version mismatch; got %#x expected %#x"),
2475	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2476
2477	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2478	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2479
2480	/*
2481	* Fill in PCI configs and add them to the bus.
2482	*/
2483	/** @todo Disabled for now because this causes error messages with Linux guests.
2484	* The guest loads the x38_edac device which tries to map a memory region
2485	* using an address given at place 0x48 - 0x4f in the PCi config space.
2486	* This fails. because we don't register such a region.
2487	*/
2488	#if 0
2489	/* Host bridge device */
2490	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2491	PCIDevSetDeviceId( &pBus->aPciDev, 0x29e0); /* Desktop */
2492	PCIDevSetRevisionId(&pBus->aPciDev, 0x01); /* rev. 01 */
2493	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* bridge */
2494	PCIDevSetClassSub( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2495	PCIDevSetClassProg( &pBus->aPciDev, 0x00); /* Host/PCI bridge */
2496	PCIDevSetHeaderType(&pBus->aPciDev, 0x00); /* bridge */
2497	PCIDevSetWord(&pBus->aPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
2498
2499	pBus->aPciDev.pDevIns = pDevIns;
2500	/* We register Host<->PCI controller on the bus */
2501	ich9pciRegisterInternal(pBus, 0, &pBus->aPciDev, "dram");
2502	#endif
2503
2504	/*
2505	* Register I/O ports and save state.
2506	*/
2507	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, ich9pciIOPortAddressWrite, ich9pciIOPortAddressRead, NULL, NULL, "ICH9 (PCI)");
2508	if (RT_FAILURE(rc))
2509	return rc;
2510	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, ich9pciIOPortDataWrite, ich9pciIOPortDataRead, NULL, NULL, "ICH9 (PCI)");
2511	if (RT_FAILURE(rc))
2512	return rc;
2513	if (fGCEnabled)
2514	{
2515	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2516	if (RT_FAILURE(rc))
2517	return rc;
2518	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2519	if (RT_FAILURE(rc))
2520	return rc;
2521	}
2522	if (fR0Enabled)
2523	{
2524	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "ich9pciIOPortAddressWrite", "ich9pciIOPortAddressRead", NULL, NULL, "ICH9 (PCI)");
2525	if (RT_FAILURE(rc))
2526	return rc;
2527	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "ich9pciIOPortDataWrite", "ich9pciIOPortDataRead", NULL, NULL, "ICH9 (PCI)");
2528	if (RT_FAILURE(rc))
2529	return rc;
2530	}
2531
2532	if (pGlobals->u64PciConfigMMioAddress != 0)
2533	{
2534	rc = PDMDevHlpMMIORegister(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength, NULL /pvUser/,
2535	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
2536	ich9pciMcfgMMIOWrite, ich9pciMcfgMMIORead, "MCFG ranges");
2537	AssertMsgRCReturn(rc, ("rc=%Rrc %#llx/%#llx\n", rc, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength), rc);
2538
2539	if (fGCEnabled)
2540	{
2541	rc = PDMDevHlpMMIORegisterRC(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2542	NIL_RTRCPTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2543	AssertRCReturn(rc, rc);
2544	}
2545
2546
2547	if (fR0Enabled)
2548	{
2549	rc = PDMDevHlpMMIORegisterR0(pDevIns, pGlobals->u64PciConfigMMioAddress, pGlobals->u64PciConfigMMioLength,
2550	NIL_RTR0PTR /pvUser/, "ich9pciMcfgMMIOWrite", "ich9pciMcfgMMIORead");
2551	AssertRCReturn(rc, rc);
2552	}
2553	}
2554
2555	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2556	sizeof(pBus) + 16128, "pgm",
2557	NULL, NULL, NULL,
2558	NULL, ich9pciR3SaveExec, NULL,
2559	NULL, ich9pciR3LoadExec, NULL);
2560	if (RT_FAILURE(rc))
2561	return rc;
2562
2563
2564	/** @todo other chipset devices shall be registered too */
2565
2566	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. Recognizes 'basic' or 'verbose' "
2567	"as arguments, defaults to 'basic'.", ich9pciInfo);
2568
2569	return VINF_SUCCESS;
2570	}
2571
2572	static void ich9pciResetDevice(PPDMPCIDEV pDev)
2573	{
2574	/* Clear regions */
2575	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2576	{
2577	PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion];
2578	if (pRegion->size == 0)
2579	continue;
2580
2581	ich9pciUnmapRegion(pDev, iRegion);
2582	}
2583
2584	if (pciDevIsPassthrough(pDev))
2585	{
2586	// no reset handler - we can do what we need in PDM reset handler
2587	/// @todo is it correct?
2588	}
2589	else
2590	{
2591	PCIDevSetCommand(pDev,
2592	PCIDevGetCommand(pDev)
2593	&
2594	~(VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY \|
2595	VBOX_PCI_COMMAND_MASTER \| VBOX_PCI_COMMAND_SPECIAL \|
2596	VBOX_PCI_COMMAND_PARITY \| VBOX_PCI_COMMAND_SERR \|
2597	VBOX_PCI_COMMAND_FAST_BACK \| VBOX_PCI_COMMAND_INTX_DISABLE));
2598
2599	/* Bridge device reset handlers processed later */
2600	if (!pciDevIsPci2PciBridge(pDev))
2601	{
2602	PCIDevSetByte(pDev, VBOX_PCI_CACHE_LINE_SIZE, 0x0);
2603	PCIDevSetInterruptLine(pDev, 0x0);
2604	}
2605
2606	/* Reset MSI message control. */
2607	if (pciDevIsMsiCapable(pDev))
2608	{
2609	/* Extracted from MsiPciConfigWrite(). */
2610	pDev->config[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;
2611	}
2612
2613	/* Reset MSI-X message control. */
2614	if (pciDevIsMsixCapable(pDev))
2615	{
2616	/* Extracted from MsixPciConfigWrite(); no side effects. */
2617	pDev->config[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;
2618	}
2619	}
2620	}
2621
2622
2623	/**
2624	* @copydoc FNPDMDEVRESET
2625	*/
2626	static DECLCALLBACK(void) ich9pciReset(PPDMDEVINS pDevIns)
2627	{
2628	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2629	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2630
2631	/* PCI-specific reset for each device. */
2632	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2633	{
2634	if (pBus->apDevices[i])
2635	ich9pciResetDevice(pBus->apDevices[i]);
2636	}
2637
2638	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2639	{
2640	if (pBus->papBridgesR3[iBridge])
2641	ich9pcibridgeReset(pBus->papBridgesR3[iBridge]->pDevIns);
2642	}
2643
2644	ich9pciFakePCIBIOS(pDevIns);
2645	}
2646
2647	static void ich9pciRelocateDevice(PPDMPCIDEV pDev, RTGCINTPTR offDelta)
2648	{
2649	if (pDev)
2650	{
2651	pDev->Int.s.pBusRC += offDelta;
2652	if (pDev->Int.s.pMsixPageRC)
2653	pDev->Int.s.pMsixPageRC += offDelta;
2654	}
2655	}
2656
2657	/**
2658	* @copydoc FNPDMDEVRELOCATE
2659	*/
2660	static DECLCALLBACK(void) ich9pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2661	{
2662	PICH9PCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS);
2663	PICH9PCIBUS pBus = &pGlobals->aPciBus;
2664	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2665
2666	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2667	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2668
2669	/* Relocate RC pointers for the attached pci devices. */
2670	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2671	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2672
2673	}
2674
2675	/**
2676	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2677	*/
2678	static DECLCALLBACK(int) ich9pcibridgeConstruct(PPDMDEVINS pDevIns,
2679	int iInstance,
2680	PCFGMNODE pCfg)
2681	{
2682	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2683
2684	/*
2685	* Validate and read configuration.
2686	*/
2687	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2688	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2689
2690	/* check if RC code is enabled. */
2691	bool fGCEnabled;
2692	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2693	if (RT_FAILURE(rc))
2694	return PDMDEV_SET_ERROR(pDevIns, rc,
2695	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2696
2697	/* check if R0 code is enabled. */
2698	bool fR0Enabled;
2699	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2700	if (RT_FAILURE(rc))
2701	return PDMDEV_SET_ERROR(pDevIns, rc,
2702	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2703	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2704
2705	/*
2706	* Init data and register the PCI bus.
2707	*/
2708	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2709	pBus->pDevInsR3 = pDevIns;
2710	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2711	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2712	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
2713
2714	PDMPCIBUSREG PciBusReg;
2715	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2716	PciBusReg.pfnRegisterR3 = pcibridgeR3MergedRegisterDevice;
2717	PciBusReg.pfnRegisterMsiR3 = ich9pciRegisterMsi;
2718	PciBusReg.pfnIORegionRegisterR3 = ich9pciIORegionRegister;
2719	PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
2720	PciBusReg.pfnSetIrqR3 = ich9pcibridgeSetIrq;
2721	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2722	PciBusReg.pszSetIrqRC = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
2723	PciBusReg.pszSetIrqR0 = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
2724	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2725	if (RT_FAILURE(rc))
2726	return PDMDEV_SET_ERROR(pDevIns, rc,
2727	N_("Failed to register ourselves as a PCI Bus"));
2728	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2729	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2730	N_("PCI helper version mismatch; got %#x expected %#x"),
2731	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2732
2733	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2734	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2735
2736	/* Disable default device locking. */
2737	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2738	AssertRCReturn(rc, rc);
2739
2740	/*
2741	* Fill in PCI configs and add them to the bus.
2742	*/
2743	PCIDevSetVendorId( &pBus->aPciDev, 0x8086); /* Intel */
2744	PCIDevSetDeviceId( &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2745	PCIDevSetRevisionId(&pBus->aPciDev, 0xf2);
2746	PCIDevSetClassSub( &pBus->aPciDev, 0x04); /* pci2pci */
2747	PCIDevSetClassBase( &pBus->aPciDev, 0x06); /* PCI_bridge */
2748	PCIDevSetClassProg( &pBus->aPciDev, 0x01); /* Supports subtractive decoding. */
2749	PCIDevSetHeaderType(&pBus->aPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2750	PCIDevSetCommand( &pBus->aPciDev, 0x00);
2751	PCIDevSetStatus( &pBus->aPciDev, 0x20); /* 66MHz Capable. */
2752	PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
2753
2754	/*
2755	* This device does not generate interrupts. Interrupt delivery from
2756	* devices attached to the bus is unaffected.
2757	*/
2758	PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
2759
2760	/*
2761	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2762	*/
2763	rc = PDMDevHlpPCIRegisterEx(pDevIns, &pBus->aPciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_PCI_BRIDGE,
2764	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "ich9pcibridge");
2765	if (RT_FAILURE(rc))
2766	return rc;
2767	pBus->aPciDev.Int.s.pfnBridgeConfigRead = ich9pcibridgeConfigRead;
2768	pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
2769
2770	/*
2771	* The iBus property doesn't really represent the bus number
2772	* because the guest and the BIOS can choose different bus numbers
2773	* for them.
2774	* The bus number is mainly for the setIrq function to indicate
2775	* when the host bus is reached which will have iBus = 0.
2776	* That's why the + 1.
2777	*/
2778	pBus->iBus = iInstance + 1;
2779
2780	/*
2781	* Register SSM handlers. We use the same saved state version as for the host bridge
2782	* to make changes easier.
2783	*/
2784	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION_CURRENT,
2785	sizeof(pBus) + 16128,
2786	"pgm" /* before */,
2787	NULL, NULL, NULL,
2788	NULL, ich9pcibridgeR3SaveExec, NULL,
2789	NULL, ich9pcibridgeR3LoadExec, NULL);
2790	if (RT_FAILURE(rc))
2791	return rc;
2792
2793
2794	return VINF_SUCCESS;
2795	}
2796
2797	/**
2798	* @copydoc FNPDMDEVRESET
2799	*/
2800	static void ich9pcibridgeReset(PPDMDEVINS pDevIns)
2801	{
2802	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2803
2804	/* Reset config space to default values. */
2805	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_PRIMARY_BUS, 0);
2806	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS, 0);
2807	PCIDevSetByte(&pBus->aPciDev, VBOX_PCI_SUBORDINATE_BUS, 0);
2808
2809	/* PCI-specific reset for each device. */
2810	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2811	{
2812	if (pBus->apDevices[i])
2813	ich9pciResetDevice(pBus->apDevices[i]);
2814	}
2815	}
2816
2817
2818	/**
2819	* @copydoc FNPDMDEVRELOCATE
2820	*/
2821	static DECLCALLBACK(void) ich9pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2822	{
2823	PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS);
2824	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2825
2826	/* Relocate RC pointers for the attached pci devices. */
2827	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++)
2828	ich9pciRelocateDevice(pBus->apDevices[i], offDelta);
2829	}
2830
2831	/**
2832	* The PCI bus device registration structure.
2833	*/
2834	const PDMDEVREG g_DevicePciIch9 =
2835	{
2836	/* u32Version */
2837	PDM_DEVREG_VERSION,
2838	/* szName */
2839	"ich9pci",
2840	/* szRCMod */
2841	"VBoxDDRC.rc",
2842	/* szR0Mod */
2843	"VBoxDDR0.r0",
2844	/* pszDescription */
2845	"ICH9 PCI bridge",
2846	/* fFlags */
2847	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2848	/* fClass */
2849	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2850	/* cMaxInstances */
2851	1,
2852	/* cbInstance */
2853	sizeof(ICH9PCIGLOBALS),
2854	/* pfnConstruct */
2855	ich9pciConstruct,
2856	/* pfnDestruct */
2857	NULL,
2858	/* pfnRelocate */
2859	ich9pciRelocate,
2860	/* pfnMemSetup */
2861	NULL,
2862	/* pfnPowerOn */
2863	NULL,
2864	/* pfnReset */
2865	ich9pciReset,
2866	/* pfnSuspend */
2867	NULL,
2868	/* pfnResume */
2869	NULL,
2870	/* pfnAttach */
2871	NULL,
2872	/* pfnDetach */
2873	NULL,
2874	/* pfnQueryInterface */
2875	NULL,
2876	/* pfnInitComplete */
2877	NULL,
2878	/* pfnPowerOff */
2879	NULL,
2880	/* pfnSoftReset */
2881	NULL,
2882	/* u32VersionEnd */
2883	PDM_DEVREG_VERSION
2884	};
2885
2886	/**
2887	* The device registration structure
2888	* for the PCI-to-PCI bridge.
2889	*/
2890	const PDMDEVREG g_DevicePciIch9Bridge =
2891	{
2892	/* u32Version */
2893	PDM_DEVREG_VERSION,
2894	/* szName */
2895	"ich9pcibridge",
2896	/* szRCMod */
2897	"VBoxDDRC.rc",
2898	/* szR0Mod */
2899	"VBoxDDR0.r0",
2900	/* pszDescription */
2901	"ICH9 PCI to PCI bridge",
2902	/* fFlags */
2903	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2904	/* fClass */
2905	PDM_DEVREG_CLASS_BUS_PCI,
2906	/* cMaxInstances */
2907	~0U,
2908	/* cbInstance */
2909	sizeof(ICH9PCIBUS),
2910	/* pfnConstruct */
2911	ich9pcibridgeConstruct,
2912	/* pfnDestruct */
2913	NULL,
2914	/* pfnRelocate */
2915	ich9pcibridgeRelocate,
2916	/* pfnMemSetup */
2917	NULL,
2918	/* pfnPowerOn */
2919	NULL,
2920	/* pfnReset */
2921	NULL, /* Must be NULL, to make sure only bus driver handles reset */
2922	/* pfnSuspend */
2923	NULL,
2924	/* pfnResume */
2925	NULL,
2926	/* pfnAttach */
2927	NULL,
2928	/* pfnDetach */
2929	NULL,
2930	/* pfnQueryInterface */
2931	NULL,
2932	/* pfnInitComplete */
2933	NULL,
2934	/* pfnPowerOff */
2935	NULL,
2936	/* pfnSoftReset */
2937	NULL,
2938	/* u32VersionEnd */
2939	PDM_DEVREG_VERSION
2940	};
2941
2942	#endif /* IN_RING3 */
2943	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciIch9.cpp@ 64387

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