Changeset 64387 in vbox
- Timestamp:
- Oct 24, 2016 2:06:02 PM (8 years ago)
- svn:sync-xref-src-repo-rev:
- 111495
- Location:
- trunk
- Files:
-
- 35 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/pdmdev.h
r64373 r64387 547 547 * @remarks Caller enters the PDM critical section. 548 548 */ 549 DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t fFlags,549 DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags, 550 550 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)); 551 551 … … 3163 3163 * The pointer is saved, so don't free or changed. 3164 3164 */ 3165 DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t idxDevCfg, uint32_t fFlags,3165 DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t idxDevCfg, uint32_t fFlags, 3166 3166 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)); 3167 3167 … … 5195 5195 * @copydoc PDMDEVHLPR3::pfnPCIRegister 5196 5196 */ 5197 DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t idxDevCfg, uint32_t fFlags,5197 DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t idxDevCfg, uint32_t fFlags, 5198 5198 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName) 5199 5199 { -
trunk/include/VBox/vmm/pdmpcidev.h
r64373 r64387 36 36 */ 37 37 38 /** @deprecated. */39 typedef PPDMPCIDEV PPCIDEVICE;40 /** @deprecated. */41 typedef struct PDMPCIDEV PCIDEVICE;42 /** Legacy type name.43 * @deprecated */44 #define PCIDevice PDMPCIDEV45 46 47 38 /** 48 39 * Callback function for reading from the PCI configuration space. … … 111 102 * @todo add pDevIns parameter and fix iRegion type. 112 103 */ 113 typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,104 typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 114 105 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType); 115 106 /** Pointer to a FNPCIIOREGIONMAP() function. */ -
trunk/include/VBox/vmm/pdmpcidevint.h
r64376 r64387 1 1 /* $Id$ */ 2 2 /** @file 3 * DevPCI - PDM PCI Internal header - Only for hiding bits of P CIDEVICE.3 * DevPCI - PDM PCI Internal header - Only for hiding bits of PDMPCIDEV. 4 4 */ 5 5 … … 108 108 * PDM PCI Device - Internal data. 109 109 * 110 * @sa PDMPCIDEV ICE110 * @sa PDMPCIDEV 111 111 */ 112 112 typedef struct PDMPCIDEVICEINT … … 209 209 AssertCompileSize(PDMPCIDEVICEINT, HC_ARCH_BITS == 32 ? 264 : 384); 210 210 211 /** Indicate that P CIDEVICE::Int.s can be declared. */211 /** Indicate that PDMPCIDEV::Int.s can be declared. */ 212 212 #define PDMPCIDEVICEINT_DECLARED 213 213 -
trunk/src/VBox/Devices/Audio/DevHDA.cpp
r64373 r64387 769 769 { 770 770 /** The PCI device structure. */ 771 P CIDevicePciDev;771 PDMPCIDEV PciDev; 772 772 /** R3 Pointer to the device instance. */ 773 773 PPDMDEVINSR3 pDevInsR3; … … 4769 4769 * @callback_method_impl{FNPCIIOREGIONMAP} 4770 4770 */ 4771 static DECLCALLBACK(int) hdaPciIoRegionMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,4771 static DECLCALLBACK(int) hdaPciIoRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 4772 4772 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 4773 4773 { -
trunk/src/VBox/Devices/Audio/DevIchAc97.cpp
r64385 r64387 355 355 { 356 356 /** The PCI device state. */ 357 P CIDevicePciDev;357 PDMPCIDEV PciDev; 358 358 /** R3 Pointer to the device instance. */ 359 359 PPDMDEVINSR3 pDevInsR3; … … 2297 2297 * @callback_method_impl{FNPCIIOREGIONMAP} 2298 2298 */ 2299 static DECLCALLBACK(int) ichac97IOPortMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,2299 static DECLCALLBACK(int) ichac97IOPortMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 2300 2300 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 2301 2301 { -
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r64373 r64387 67 67 { 68 68 /** The PCI device of the bridge. */ 69 P CIDEVICEdev;69 PDMPCIDEV dev; 70 70 } PIIX3State, PIIX3, *PPIIX3; 71 71 … … 87 87 { 88 88 /** Array of PCI devices. */ 89 R3PTRTYPE(PP CIDEVICE) apDevices[256];89 R3PTRTYPE(PPDMPCIDEV) apDevices[256]; 90 90 /** @deprecated */ 91 R3PTRTYPE(PP CIDEVICE) devices[256];91 R3PTRTYPE(PPDMPCIDEV) devices[256]; 92 92 }; 93 93 /** Array of bridges attached to the bus. */ 94 R3PTRTYPE(PP CIDEVICE*) papBridgesR3;94 R3PTRTYPE(PPDMPCIDEV *) papBridgesR3; 95 95 96 96 /** R3 pointer to the device instance. */ … … 110 110 111 111 /** The PCI device for the PCI bridge. */ 112 P CIDEVICEPciDev;112 PDMPCIDEV PciDev; 113 113 114 114 } PCIBUS; … … 223 223 RT_C_DECLS_BEGIN 224 224 225 PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel, uint32_t uTag);226 PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel, uint32_t uTag);225 PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag); 226 PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag); 227 227 PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb); 228 228 PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb); … … 231 231 232 232 #ifdef IN_RING3 233 DECLINLINE(PP CIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus);233 DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus); 234 234 #endif 235 235 … … 252 252 #ifdef IN_RING3 253 253 254 static void pci_update_mappings(P CIDevice*d)254 static void pci_update_mappings(PDMPCIDEV *d) 255 255 { 256 256 PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus); … … 349 349 350 350 351 static DECLCALLBACK(uint32_t) pci_default_read_config(PPDMDEVINS pDevIns, P CIDevice*d, uint32_t address, unsigned len)351 static DECLCALLBACK(uint32_t) pci_default_read_config(PPDMDEVINS pDevIns, PDMPCIDEV *d, uint32_t address, unsigned len) 352 352 { 353 353 NOREF(pDevIns); … … 368 368 } 369 369 370 static DECLCALLBACK(void) pci_default_write_config(PPDMDEVINS pDevIns, P CIDevice*d, uint32_t address, uint32_t val, unsigned len)370 static DECLCALLBACK(void) pci_default_write_config(PPDMDEVINS pDevIns, PDMPCIDEV *d, uint32_t address, uint32_t val, unsigned len) 371 371 { 372 372 NOREF(pDevIns); … … 515 515 { 516 516 #ifdef IN_RING3 /** @todo do lookup in R0/RC too! */ 517 PP CIDEVICEpBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);517 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus); 518 518 if (pBridgeDevice) 519 519 { … … 529 529 else 530 530 { 531 R3PTRTYPE(P CIDevice*) pci_dev = pGlobals->PciBus.devices[iDevice];531 R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.devices[iDevice]; 532 532 if (pci_dev) 533 533 { … … 562 562 { 563 563 #ifdef IN_RING3 /** @todo do lookup in R0/RC too! */ 564 PP CIDEVICEpBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);564 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus); 565 565 if (pBridgeDevice) 566 566 { … … 576 576 else 577 577 { 578 R3PTRTYPE(P CIDevice*) pci_dev = pGlobals->PciBus.devices[iDevice];578 R3PTRTYPE(PDMPCIDEV *) pci_dev = pGlobals->PciBus.devices[iDevice]; 579 579 if (pci_dev) 580 580 { … … 615 615 } 616 616 617 static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, P CIDevice*pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc)617 static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc) 618 618 { 619 619 /* This is only allowed to be called with a pointer to the host bus. */ … … 669 669 * PIRQ value. 670 670 */ 671 static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PP CIDEVICEpPciDev, int iIrq, int iLevel, uint32_t uTagSrc)671 static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 672 672 { 673 673 PPCIBUS pBus = &pGlobals->PciBus; … … 761 761 * @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3} 762 762 */ 763 PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel, uint32_t uTagSrc)763 PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 764 764 { 765 765 pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc); … … 776 776 * @param iBus Destination bus number. 777 777 */ 778 DECLINLINE(PP CIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus)778 DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus) 779 779 { 780 780 /* Search for a fitting bridge. */ … … 785 785 * If the target bus is in the range we pass the request on to the bridge. 786 786 */ 787 PP CIDEVICEpBridgeTemp = pBus->papBridgesR3[iBridge];787 PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge]; 788 788 AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp), 789 789 ("Device is not a PCI bridge but on the list of PCI bridges\n")); … … 1271 1271 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++) 1272 1272 { 1273 PP CIDEVICEpDev = pBus->devices[i];1273 PPDMPCIDEV pDev = pBus->devices[i]; 1274 1274 if (pDev) 1275 1275 { … … 1327 1327 * @param fIsBridge Whether this is a bridge device or not. 1328 1328 */ 1329 static void pciR3CommonRestoreConfig(PP CIDEVICEpDev, uint8_t const *pbSrcConfig, bool fIsBridge)1329 static void pciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig, bool fIsBridge) 1330 1330 { 1331 1331 /* … … 1513 1513 for (i = 0; i < RT_ELEMENTS(pBus->devices); i++) 1514 1514 { 1515 PP CIDEVICEpDev = pBus->devices[i];1515 PPDMPCIDEV pDev = pBus->devices[i]; 1516 1516 if (pDev) 1517 1517 { … … 1528 1528 for (i = 0;; i++) 1529 1529 { 1530 P CIDEVICEDevTmp;1531 PP CIDEVICEpDev;1530 PDMPCIDEV DevTmp; 1531 PPDMPCIDEV pDev; 1532 1532 1533 1533 /* index / terminator */ … … 1659 1659 * @interface_method_impl{PDMPCIBUSREG,pfnIORegionRegisterR3} 1660 1660 */ 1661 static DECLCALLBACK(int) pciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iRegion, RTGCPHYS cbRegion,1661 static DECLCALLBACK(int) pciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion, 1662 1662 PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback) 1663 1663 { … … 1704 1704 */ 1705 1705 static DECLCALLBACK(void) 1706 pciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,1706 pciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld, 1707 1707 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld) 1708 1708 { … … 1843 1843 for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->devices); iDev++) 1844 1844 { 1845 PP CIDEVICEpPciDev = pBus->devices[iDev];1845 PPDMPCIDEV pPciDev = pBus->devices[iDev]; 1846 1846 if (pPciDev != NULL) 1847 1847 { … … 2049 2049 pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 2050 2050 pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 2051 pGlobals->PciBus.papBridgesR3 = (PP CIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE)2051 pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) 2052 2052 * RT_ELEMENTS(pGlobals->PciBus.devices)); 2053 2053 … … 2215 2215 * @interface_method_impl{PDMPCIBUSREG,pfnSetIrqR3} 2216 2216 */ 2217 PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel, uint32_t uTagSrc)2217 PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 2218 2218 { 2219 2219 /* … … 2225 2225 */ 2226 2226 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS); 2227 PP CIDEVICEpPciDevBus = pPciDev;2227 PPDMPCIDEV pPciDevBus = pPciDev; 2228 2228 int iIrqPinBridge = iIrq; 2229 2229 uint8_t uDevFnBridge = 0; … … 2258 2258 if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS]) 2259 2259 { 2260 PP CIDEVICEpBridgeDevice = pciR3FindBridge(pBus, iBus);2260 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus); 2261 2261 if (pBridgeDevice) 2262 2262 { … … 2268 2268 { 2269 2269 /* This is the target bus, pass the write to the device. */ 2270 PP CIDEVICEpPciDev = pBus->devices[iDevice];2270 PPDMPCIDEV pPciDev = pBus->devices[iDevice]; 2271 2271 if (pPciDev) 2272 2272 { … … 2291 2291 if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS]) 2292 2292 { 2293 PP CIDEVICEpBridgeDevice = pciR3FindBridge(pBus, iBus);2293 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus); 2294 2294 if (pBridgeDevice) 2295 2295 { … … 2301 2301 { 2302 2302 /* This is the target bus, pass the read to the device. */ 2303 PP CIDEVICEpPciDev = pBus->devices[iDevice];2303 PPDMPCIDEV pPciDev = pBus->devices[iDevice]; 2304 2304 if (pPciDev) 2305 2305 { … … 2401 2401 pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 2402 2402 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 2403 pBus->papBridgesR3 = (PP CIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pBus->devices));2403 pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->devices)); 2404 2404 2405 2405 PDMPCIBUSREG PciBusReg; -
trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r64373 r64387 57 57 58 58 /** Array of PCI devices. We assume 32 slots, each with 8 functions. */ 59 R3PTRTYPE(PP CIDEVICE) apDevices[256];59 R3PTRTYPE(PPDMPCIDEV) apDevices[256]; 60 60 /** Array of bridges attached to the bus. */ 61 R3PTRTYPE(PP CIDEVICE*) papBridgesR3;61 R3PTRTYPE(PPDMPCIDEV *) papBridgesR3; 62 62 63 63 /** R3 pointer to the device instance. */ … … 77 77 78 78 /** The PCI device for the PCI bridge. */ 79 P CIDEVICEaPciDev;79 PDMPCIDEV aPciDev; 80 80 81 81 /** Start device number - always zero (only for DevPCI source compat). */ … … 177 177 178 178 /* Prototypes */ 179 static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PP CIDEVICEpPciDev,179 static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, 180 180 int iIrq, int iLevel, uint32_t uTagSrc); 181 181 #ifdef IN_RING3 182 182 static void ich9pcibridgeReset(PPDMDEVINS pDevIns); 183 static void ich9pciUpdateMappings(P CIDevice*pDev);183 static void ich9pciUpdateMappings(PDMPCIDEV *pDev); 184 184 static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t u32Address, unsigned len); 185 185 static DECLCALLBACK(void) ich9pciConfigWriteDev(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t u32Address, uint32_t val, unsigned len); 186 DECLINLINE(PP CIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus);186 DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus); 187 187 static void ich9pciBiosInitDevice(PICH9PCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn); 188 188 #endif … … 205 205 } 206 206 207 PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel, uint32_t uTagSrc)207 PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 208 208 { 209 209 LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc)); … … 211 211 } 212 212 213 PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel, uint32_t uTagSrc)213 PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 214 214 { 215 215 /* … … 221 221 */ 222 222 PICH9PCIBUS pBus = PDMINS_2_DATA(pDevIns, PICH9PCIBUS); 223 PP CIDEVICEpPciDevBus = pPciDev;223 PPDMPCIDEV pPciDevBus = pPciDev; 224 224 int iIrqPinBridge = iIrq; 225 225 uint8_t uDevFnBridge = 0; … … 330 330 { 331 331 #ifdef IN_RING3 /** @todo do lookup in R0/RC too! */ 332 PP CIDEVICEpBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus);332 PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pAddr->iBus); 333 333 if (pBridgeDevice) 334 334 { … … 344 344 else /* forward to directly connected device */ 345 345 { 346 R3PTRTYPE(P CIDevice*) pPciDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc];346 R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc]; 347 347 if (pPciDev) 348 348 { … … 443 443 { 444 444 #ifdef IN_RING3 /** @todo do lookup in R0/RC too! */ 445 PP CIDEVICEpBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus);445 PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(&pGlobals->aPciBus, pPciAddr->iBus); 446 446 if (pBridgeDevice) 447 447 { … … 460 460 else /* forward to directly connected device */ 461 461 { 462 R3PTRTYPE(P CIDevice*) pPciDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc];462 R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc]; 463 463 if (pPciDev) 464 464 { … … 575 575 } 576 576 577 static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, P CIDevice*pPciDev, int irq_num1, int iLevel,577 static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, 578 578 uint32_t uTagSrc, int iForcedIrq) 579 579 { … … 618 618 } 619 619 620 static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PP CIDEVICEpPciDev,620 static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPDMPCIDEV pPciDev, 621 621 int iIrq, int iLevel, uint32_t uTagSrc) 622 622 { … … 789 789 790 790 791 DECLINLINE(PP CIDEVICE) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus)791 DECLINLINE(PPDMPCIDEV) ich9pciFindBridge(PICH9PCIBUS pBus, uint8_t iBus) 792 792 { 793 793 /* Search for a fitting bridge. */ … … 798 798 * If the target bus is in the range we pass the request on to the bridge. 799 799 */ 800 PP CIDEVICEpBridge = pBus->papBridgesR3[iBridge];800 PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge]; 801 801 AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge), 802 802 ("Device is not a PCI bridge but on the list of PCI bridges\n")); … … 840 840 #define INVALID_PCI_ADDRESS ~0U 841 841 842 static int ich9pciUnmapRegion(PP CIDEVICEpDev, int iRegion)842 static int ich9pciUnmapRegion(PPDMPCIDEV pDev, int iRegion) 843 843 { 844 844 PCIIORegion* pRegion = &pDev->Int.s.aIORegions[iRegion]; … … 877 877 } 878 878 879 static void ich9pciUpdateMappings(P CIDevice* pDev)879 static void ich9pciUpdateMappings(PDMPCIDEV* pDev) 880 880 { 881 881 uint64_t uLast, uNew; … … 962 962 963 963 964 static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, PPDMMSIREG pMsiReg)964 static DECLCALLBACK(int) ich9pciRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg) 965 965 { 966 966 NOREF(pDevIns); … … 979 979 980 980 981 static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iRegion, RTGCPHYS cbRegion,981 static DECLCALLBACK(int) ich9pciIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion, 982 982 PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback) 983 983 { … … 1036 1036 } 1037 1037 1038 static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,1038 static DECLCALLBACK(void) ich9pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld, 1039 1039 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld) 1040 1040 { … … 1057 1057 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->apDevices); i++) 1058 1058 { 1059 PP CIDEVICEpDev = pBus->apDevices[i];1059 PPDMPCIDEV pDev = pBus->apDevices[i]; 1060 1060 if (pDev) 1061 1061 { … … 1140 1140 if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS)) 1141 1141 { 1142 PP CIDEVICEpBridgeDevice = ich9pciFindBridge(pBus, iBus);1142 PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, iBus); 1143 1143 if (pBridgeDevice) 1144 1144 { … … 1150 1150 { 1151 1151 /* This is the target bus, pass the write to the device. */ 1152 PP CIDEVICEpPciDev = pBus->apDevices[iDevice];1152 PPDMPCIDEV pPciDev = pBus->apDevices[iDevice]; 1153 1153 if (pPciDev) 1154 1154 { … … 1169 1169 if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS)) 1170 1170 { 1171 PP CIDEVICEpBridgeDevice = ich9pciFindBridge(pBus, iBus);1171 PPDMPCIDEV pBridgeDevice = ich9pciFindBridge(pBus, iBus); 1172 1172 if (pBridgeDevice) 1173 1173 { … … 1181 1181 { 1182 1182 /* This is the target bus, pass the read to the device. */ 1183 PP CIDEVICEpPciDev = pBus->apDevices[iDevice];1183 PPDMPCIDEV pPciDev = pBus->apDevices[iDevice]; 1184 1184 if (pPciDev) 1185 1185 { … … 1202 1202 * @param fIsBridge Whether this is a bridge device or not. 1203 1203 */ 1204 static void pciR3CommonRestoreConfig(PP CIDEVICEpDev, uint8_t const *pbSrcConfig, bool fIsBridge)1204 static void pciR3CommonRestoreConfig(PPDMPCIDEV pDev, uint8_t const *pbSrcConfig, bool fIsBridge) 1205 1205 { 1206 1206 /* … … 1391 1391 for (i = 0; i < RT_ELEMENTS(pBus->apDevices); i++) 1392 1392 { 1393 PP CIDEVICEpDev = pBus->apDevices[i];1393 PPDMPCIDEV pDev = pBus->apDevices[i]; 1394 1394 if (pDev) 1395 1395 { … … 1409 1409 for (i = 0;; i++) 1410 1410 { 1411 PP CIDEVICEpDev;1412 P CIDEVICEDevTmp;1411 PPDMPCIDEV pDev; 1412 PDMPCIDEV DevTmp; 1413 1413 1414 1414 /* index / terminator */ … … 1855 1855 while (1) 1856 1856 { 1857 PP CIDEVICEpBridge = ich9pciFindBridge(pBus, uBus);1857 PPDMPCIDEV pBridge = ich9pciFindBridge(pBus, uBus); 1858 1858 if (!pBridge) 1859 1859 { … … 1899 1899 unsigned uBusSecondary) 1900 1900 { 1901 PP CIDEVICEpBridgeDev = &pBus->aPciDev;1901 PPDMPCIDEV pBridgeDev = &pBus->aPciDev; 1902 1902 1903 1903 /* Set only if we are not on the root bus, it has no primary bus attached. */ … … 1910 1910 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++) 1911 1911 { 1912 PP CIDEVICEpBridge = pBus->papBridgesR3[iBridge];1912 PPDMPCIDEV pBridge = pBus->papBridgesR3[iBridge]; 1913 1913 AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge), 1914 1914 ("Device is not a PCI bridge but on the list of PCI bridges\n")); … … 2238 2238 for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->apDevices); iDev++) 2239 2239 { 2240 PP CIDEVICEpPciDev = pBus->apDevices[iDev];2240 PPDMPCIDEV pPciDev = pBus->apDevices[iDev]; 2241 2241 if (pPciDev != NULL) 2242 2242 { … … 2451 2451 pGlobals->aPciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 2452 2452 pGlobals->aPciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 2453 pGlobals->aPciBus.papBridgesR3 = (PP CIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pGlobals->aPciBus.apDevices));2453 pGlobals->aPciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pGlobals->aPciBus.apDevices)); 2454 2454 2455 2455 /* … … 2570 2570 } 2571 2571 2572 static void ich9pciResetDevice(PP CIDEVICEpDev)2572 static void ich9pciResetDevice(PPDMPCIDEV pDev) 2573 2573 { 2574 2574 /* Clear regions */ … … 2645 2645 } 2646 2646 2647 static void ich9pciRelocateDevice(PP CIDEVICEpDev, RTGCINTPTR offDelta)2647 static void ich9pciRelocateDevice(PPDMPCIDEV pDev, RTGCINTPTR offDelta) 2648 2648 { 2649 2649 if (pDev) … … 2710 2710 pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 2711 2711 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 2712 pBus->papBridgesR3 = (PP CIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pBus->apDevices));2712 pBus->papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) * RT_ELEMENTS(pBus->apDevices)); 2713 2713 2714 2714 PDMPCIBUSREG PciBusReg; -
trunk/src/VBox/Devices/Bus/MsiCommon.cpp
r64373 r64387 27 27 #include "PciInline.h" 28 28 29 DECLINLINE(uint16_t) msiGetMessageControl(PP CIDEVICEpDev)29 DECLINLINE(uint16_t) msiGetMessageControl(PPDMPCIDEV pDev) 30 30 { 31 31 uint32_t idxMessageControl = pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL; … … 38 38 } 39 39 40 DECLINLINE(bool) msiIs64Bit(PP CIDEVICEpDev)40 DECLINLINE(bool) msiIs64Bit(PPDMPCIDEV pDev) 41 41 { 42 42 return pciDevIsMsi64Capable(pDev); 43 43 } 44 44 45 DECLINLINE(uint32_t*) msiGetMaskBits(PP CIDEVICEpDev)45 DECLINLINE(uint32_t*) msiGetMaskBits(PPDMPCIDEV pDev) 46 46 { 47 47 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MASK_BITS_64 : VBOX_MSI_CAP_MASK_BITS_32; … … 53 53 } 54 54 55 DECLINLINE(uint32_t*) msiGetPendingBits(PP CIDEVICEpDev)55 DECLINLINE(uint32_t*) msiGetPendingBits(PPDMPCIDEV pDev) 56 56 { 57 57 uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_PENDING_BITS_64 : VBOX_MSI_CAP_PENDING_BITS_32; … … 63 63 } 64 64 65 DECLINLINE(bool) msiIsEnabled(PP CIDEVICEpDev)65 DECLINLINE(bool) msiIsEnabled(PPDMPCIDEV pDev) 66 66 { 67 67 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_ENABLE) != 0; 68 68 } 69 69 70 DECLINLINE(uint8_t) msiGetMme(PP CIDEVICEpDev)70 DECLINLINE(uint8_t) msiGetMme(PPDMPCIDEV pDev) 71 71 { 72 72 return (msiGetMessageControl(pDev) & VBOX_PCI_MSI_FLAGS_QSIZE) >> 4; 73 73 } 74 74 75 DECLINLINE(RTGCPHYS) msiGetMsiAddress(PP CIDEVICEpDev)75 DECLINLINE(RTGCPHYS) msiGetMsiAddress(PPDMPCIDEV pDev) 76 76 { 77 77 if (msiIs64Bit(pDev)) … … 87 87 } 88 88 89 DECLINLINE(uint32_t) msiGetMsiData(PP CIDEVICEpDev, int32_t iVector)89 DECLINLINE(uint32_t) msiGetMsiData(PPDMPCIDEV pDev, int32_t iVector) 90 90 { 91 91 int16_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MESSAGE_DATA_64 : VBOX_MSI_CAP_MESSAGE_DATA_32; … … 117 117 } 118 118 119 void MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev,119 void MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, 120 120 uint32_t u32Address, uint32_t val, unsigned len) 121 121 { … … 202 202 } 203 203 204 uint32_t MsiPciConfigRead (PPDMDEVINS pDevIns, PP CIDEVICEpDev, uint32_t u32Address, unsigned len)204 uint32_t MsiPciConfigRead (PPDMDEVINS pDevIns, PPDMPCIDEV pDev, uint32_t u32Address, unsigned len) 205 205 { 206 206 RT_NOREF1(pDevIns); … … 231 231 } 232 232 233 int MsiInit(PP CIDEVICEpDev, PPDMMSIREG pMsiReg)233 int MsiInit(PPDMPCIDEV pDev, PPDMMSIREG pMsiReg) 234 234 { 235 235 if (pMsiReg->cMsiVectors == 0) … … 284 284 285 285 286 bool MsiIsEnabled(PP CIDEVICEpDev)286 bool MsiIsEnabled(PPDMPCIDEV pDev) 287 287 { 288 288 return pciDevIsMsiCapable(pDev) && msiIsEnabled(pDev); 289 289 } 290 290 291 void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev, int iVector, int iLevel, uint32_t uTagSrc)291 void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, int iVector, int iLevel, uint32_t uTagSrc) 292 292 { 293 293 AssertMsg(msiIsEnabled(pDev), ("Must be enabled to use that")); -
trunk/src/VBox/Devices/Bus/MsiCommon.h
r62518 r64387 30 30 #ifdef IN_RING3 31 31 /* Init MSI support in the device. */ 32 int MsiInit(PP CIDEVICEpDev, PPDMMSIREG pMsiReg);32 int MsiInit(PPDMPCIDEV pDev, PPDMMSIREG pMsiReg); 33 33 #endif 34 34 35 35 /* If MSI is enabled, so that MSINotify() shall be used for notifications. */ 36 bool MsiIsEnabled(PP CIDEVICEpDev);36 bool MsiIsEnabled(PPDMPCIDEV pDev); 37 37 38 38 /* Device notification (aka interrupt). */ 39 void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev, int iVector, int iLevel, uint32_t uTagSrc);39 void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, int iVector, int iLevel, uint32_t uTagSrc); 40 40 41 41 #ifdef IN_RING3 42 42 /* PCI config space accessors for MSI registers */ 43 void MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev, uint32_t u32Address, uint32_t val, unsigned len);44 uint32_t MsiPciConfigRead (PPDMDEVINS pDevIns, PP CIDEVICEpDev, uint32_t u32Address, unsigned len);43 void MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len); 44 uint32_t MsiPciConfigRead (PPDMDEVINS pDevIns, PPDMPCIDEV pDev, uint32_t u32Address, unsigned len); 45 45 #endif 46 46 47 47 #ifdef IN_RING3 48 48 /* Init MSI-X support in the device. */ 49 int MsixInit(PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev, PPDMMSIREG pMsiReg);49 int MsixInit(PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, PPDMMSIREG pMsiReg); 50 50 #endif 51 51 52 52 /* If MSI-X is enabled, so that MSIXNotify() shall be used for notifications. */ 53 bool MsixIsEnabled(PP CIDEVICEpDev);53 bool MsixIsEnabled(PPDMPCIDEV pDev); 54 54 55 55 /* Device notification (aka interrupt). */ 56 void MsixNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev, int iVector, int iLevel, uint32_t uTagSrc);56 void MsixNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, int iVector, int iLevel, uint32_t uTagSrc); 57 57 58 58 #ifdef IN_RING3 59 59 /* PCI config space accessors for MSI-X */ 60 void MsixPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev, uint32_t u32Address, uint32_t val, unsigned len);61 uint32_t MsixPciConfigRead (PPDMDEVINS pDevIns, PP CIDEVICEpDev, uint32_t u32Address, unsigned len);60 void MsixPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len); 61 uint32_t MsixPciConfigRead (PPDMDEVINS pDevIns, PPDMPCIDEV pDev, uint32_t u32Address, unsigned len); 62 62 #endif -
trunk/src/VBox/Devices/Bus/MsixCommon.cpp
r64373 r64387 40 40 41 41 /** @todo use accessors so that raw PCI devices work correctly with MSI-X. */ 42 DECLINLINE(uint16_t) msixGetMessageControl(PP CIDEVICEpDev)42 DECLINLINE(uint16_t) msixGetMessageControl(PPDMPCIDEV pDev) 43 43 { 44 44 return PCIDevGetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL); 45 45 } 46 46 47 DECLINLINE(bool) msixIsEnabled(PP CIDEVICEpDev)47 DECLINLINE(bool) msixIsEnabled(PPDMPCIDEV pDev) 48 48 { 49 49 return (msixGetMessageControl(pDev) & VBOX_PCI_MSIX_FLAGS_ENABLE) != 0; 50 50 } 51 51 52 DECLINLINE(bool) msixIsMasked(PP CIDEVICEpDev)52 DECLINLINE(bool) msixIsMasked(PPDMPCIDEV pDev) 53 53 { 54 54 return (msixGetMessageControl(pDev) & VBOX_PCI_MSIX_FLAGS_FUNCMASK) != 0; 55 55 } 56 56 57 DECLINLINE(uint16_t) msixTableSize(PP CIDEVICEpDev)57 DECLINLINE(uint16_t) msixTableSize(PPDMPCIDEV pDev) 58 58 { 59 59 return (msixGetMessageControl(pDev) & 0x3ff) + 1; 60 60 } 61 61 62 DECLINLINE(uint8_t*) msixGetPageOffset(PP CIDEVICEpDev, uint32_t off)62 DECLINLINE(uint8_t*) msixGetPageOffset(PPDMPCIDEV pDev, uint32_t off) 63 63 { 64 64 return (uint8_t*)pDev->Int.s.CTX_SUFF(pMsixPage) + off; 65 65 } 66 66 67 DECLINLINE(MsixTableRecord*) msixGetVectorRecord(PP CIDEVICEpDev, uint32_t iVector)67 DECLINLINE(MsixTableRecord*) msixGetVectorRecord(PPDMPCIDEV pDev, uint32_t iVector) 68 68 { 69 69 return (MsixTableRecord*)msixGetPageOffset(pDev, iVector * VBOX_MSIX_ENTRY_SIZE); 70 70 } 71 71 72 DECLINLINE(RTGCPHYS) msixGetMsiAddress(PP CIDEVICEpDev, uint32_t iVector)72 DECLINLINE(RTGCPHYS) msixGetMsiAddress(PPDMPCIDEV pDev, uint32_t iVector) 73 73 { 74 74 MsixTableRecord* pRec = msixGetVectorRecord(pDev, iVector); … … 76 76 } 77 77 78 DECLINLINE(uint32_t) msixGetMsiData(PP CIDEVICEpDev, uint32_t iVector)78 DECLINLINE(uint32_t) msixGetMsiData(PPDMPCIDEV pDev, uint32_t iVector) 79 79 { 80 80 return msixGetVectorRecord(pDev, iVector)->u32MsgData; 81 81 } 82 82 83 DECLINLINE(uint32_t) msixIsVectorMasked(PP CIDEVICEpDev, uint32_t iVector)83 DECLINLINE(uint32_t) msixIsVectorMasked(PPDMPCIDEV pDev, uint32_t iVector) 84 84 { 85 85 return (msixGetVectorRecord(pDev, iVector)->u32VectorControl & 0x1) != 0; 86 86 } 87 87 88 DECLINLINE(uint8_t*) msixPendingByte(PP CIDEVICEpDev, uint32_t iVector)88 DECLINLINE(uint8_t*) msixPendingByte(PPDMPCIDEV pDev, uint32_t iVector) 89 89 { 90 90 return msixGetPageOffset(pDev, 0x800 + iVector / 8); 91 91 } 92 92 93 DECLINLINE(void) msixSetPending(PP CIDEVICEpDev, uint32_t iVector)93 DECLINLINE(void) msixSetPending(PPDMPCIDEV pDev, uint32_t iVector) 94 94 { 95 95 *msixPendingByte(pDev, iVector) |= (1 << (iVector & 0x7)); 96 96 } 97 97 98 DECLINLINE(void) msixClearPending(PP CIDEVICEpDev, uint32_t iVector)98 DECLINLINE(void) msixClearPending(PPDMPCIDEV pDev, uint32_t iVector) 99 99 { 100 100 *msixPendingByte(pDev, iVector) &= ~(1 << (iVector & 0x7)); 101 101 } 102 102 103 DECLINLINE(bool) msixIsPending(PP CIDEVICEpDev, uint32_t iVector)103 DECLINLINE(bool) msixIsPending(PPDMPCIDEV pDev, uint32_t iVector) 104 104 { 105 105 return (*msixPendingByte(pDev, iVector) & (1 << (iVector & 0x7))) != 0; 106 106 } 107 107 108 static void msixCheckPendingVector(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev, uint32_t iVector)108 static void msixCheckPendingVector(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t iVector) 109 109 { 110 110 if (msixIsPending(pDev, iVector) && !msixIsVectorMasked(pDev, iVector)) … … 123 123 124 124 uint32_t off = (uint32_t)(GCPhysAddr & 0xfff); 125 PP CIDEVICE pPciDev = (PPCIDEVICE)pvUser;125 PPDMPCIDEV pPciDev = (PPDMPCIDEV)pvUser; 126 126 127 127 *(uint32_t*)pv = *(uint32_t*)msixGetPageOffset(pPciDev, off); … … 136 136 ("MSI-X must be accessed with 4-byte reads"), 137 137 VERR_INTERNAL_ERROR); 138 PP CIDEVICE pPciDev = (PPCIDEVICE)pvUser;138 PPDMPCIDEV pPciDev = (PPDMPCIDEV)pvUser; 139 139 140 140 uint32_t off = (uint32_t)(GCPhysAddr & 0xfff); … … 152 152 * @callback_method_impl{FNPCIIOREGIONMAP} 153 153 */ 154 static DECLCALLBACK(int) msixMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,154 static DECLCALLBACK(int) msixMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 155 155 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 156 156 { … … 168 168 } 169 169 170 int MsixInit(PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev, PPDMMSIREG pMsiReg)170 int MsixInit(PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, PPDMMSIREG pMsiReg) 171 171 { 172 172 if (pMsiReg->cMsixVectors == 0) … … 236 236 #endif 237 237 238 bool MsixIsEnabled(PP CIDEVICEpDev)238 bool MsixIsEnabled(PPDMPCIDEV pDev) 239 239 { 240 240 return pciDevIsMsixCapable(pDev) && msixIsEnabled(pDev); 241 241 } 242 242 243 void MsixNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev, int iVector, int iLevel, uint32_t uTagSrc)243 void MsixNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, int iVector, int iLevel, uint32_t uTagSrc) 244 244 { 245 245 AssertMsg(msixIsEnabled(pDev), ("Must be enabled to use that")); … … 277 277 } 278 278 279 static void msixCheckPendingVectors(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev)279 static void msixCheckPendingVectors(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev) 280 280 { 281 281 for (uint32_t i = 0; i < msixTableSize(pDev); i++) … … 284 284 285 285 286 void MsixPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PP CIDEVICEpDev, uint32_t u32Address, uint32_t val, unsigned len)286 void MsixPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len) 287 287 { 288 288 int32_t iOff = u32Address - pDev->Int.s.u8MsixCapOffset; … … 330 330 331 331 332 uint32_t MsixPciConfigRead(PPDMDEVINS pDevIns, PP CIDEVICEpDev, uint32_t u32Address, unsigned len)332 uint32_t MsixPciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pDev, uint32_t u32Address, unsigned len) 333 333 { 334 334 NOREF(pDevIns); -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp
r64373 r64387 3762 3762 * @callback_method_impl{FNPCIIOREGIONMAP} 3763 3763 */ 3764 DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,3764 DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 3765 3765 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 3766 3766 { -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.h
r64373 r64387 43 43 #define VMSVGA_ACTION_CHANGEMODE RT_BIT(VMSVGA_ACTION_CHANGEMODE_BIT) 44 44 45 DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,45 DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 46 46 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType); 47 47 -
trunk/src/VBox/Devices/Graphics/DevVGA.cpp
r64373 r64387 5400 5400 * @callback_method_impl{FNPCIIOREGIONMAP, Mapping/unmapping the VRAM MMI2 region} 5401 5401 */ 5402 static DECLCALLBACK(int) vgaR3IORegionMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,5402 static DECLCALLBACK(int) vgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 5403 5403 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 5404 5404 { -
trunk/src/VBox/Devices/Graphics/DevVGA.h
r62951 r64387 502 502 PDMCRITSECT CritSect; 503 503 /** The PCI device. */ 504 P CIDEVICEDev;504 PDMPCIDEV Dev; 505 505 506 506 STAMPROFILE StatRZMemoryRead; -
trunk/src/VBox/Devices/Network/DevE1000.cpp
r64373 r64387 1079 1079 RTIOPORT IOPortBase; 1080 1080 /** EMT: */ 1081 P CIDEVICEpciDevice;1081 PDMPCIDEV pciDevice; 1082 1082 /** EMT: Last time the interrupt was acknowledged. */ 1083 1083 uint64_t u64AckedAt; … … 6104 6104 * @callback_method_impl{FNPCIIOREGIONMAP} 6105 6105 */ 6106 static DECLCALLBACK(int) e1kMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,6106 static DECLCALLBACK(int) e1kMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 6107 6107 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 6108 6108 { … … 7422 7422 * @thread EMT 7423 7423 */ 7424 static DECLCALLBACK(void) e1kConfigurePciDev(PP CIDEVICEpPciDev, E1KCHIP eChip)7424 static DECLCALLBACK(void) e1kConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip) 7425 7425 { 7426 7426 Assert(eChip < RT_ELEMENTS(g_aChips)); -
trunk/src/VBox/Devices/Network/DevPCNet.cpp
r64373 r64387 247 247 * PCNET state. 248 248 * 249 * @extends P CIDEVICE249 * @extends PDMPCIDEV 250 250 * @implements PDMIBASE 251 251 * @implements PDMINETWORKDOWN … … 255 255 typedef struct PCNETSTATE 256 256 { 257 P CIDEVICEPciDev;257 PDMPCIDEV PciDev; 258 258 259 259 /** Pointer to the device instance - R3. */ … … 3867 3867 * @callback_method_impl{FNPCIIOREGIONMAP, For the PC-NET I/O Ports.} 3868 3868 */ 3869 static DECLCALLBACK(int) pcnetIOPortMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,3869 static DECLCALLBACK(int) pcnetIOPortMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 3870 3870 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 3871 3871 { … … 3918 3918 * @callback_method_impl{FNPCIIOREGIONMAP, For the PC-Net MMIO region.} 3919 3919 */ 3920 static DECLCALLBACK(int) pcnetMMIOMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,3920 static DECLCALLBACK(int) pcnetMMIOMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 3921 3921 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 3922 3922 { -
trunk/src/VBox/Devices/Network/DevVirtioNet.cpp
r64373 r64387 1778 1778 * @callback_method_impl{FNPCIIOREGIONMAP} 1779 1779 */ 1780 static DECLCALLBACK(int) vnetMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,1780 static DECLCALLBACK(int) vnetMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 1781 1781 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 1782 1782 { -
trunk/src/VBox/Devices/PC/DevACPI.cpp
r64373 r64387 282 282 typedef struct ACPIState 283 283 { 284 P CIDevicedev;284 PDMPCIDEV dev; 285 285 /** Critical section protecting the ACPI state. */ 286 286 PDMCRITSECT CritSect; … … 3266 3266 * @callback_method_impl{FNPCICONFIGREAD} 3267 3267 */ 3268 static DECLCALLBACK(uint32_t) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t Address, unsigned cb)3268 static DECLCALLBACK(uint32_t) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t Address, unsigned cb) 3269 3269 { 3270 3270 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *); … … 3277 3277 * @callback_method_impl{FNPCICONFIGWRITE} 3278 3278 */ 3279 static DECLCALLBACK(void) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t Address,3279 static DECLCALLBACK(void) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t Address, 3280 3280 uint32_t u32Value, unsigned cb) 3281 3281 { -
trunk/src/VBox/Devices/PC/DevLPC.cpp
r64373 r64387 65 65 { 66 66 /** PCI device structure. */ 67 P CIDEVICEdev;67 PDMPCIDEV dev; 68 68 69 69 /** Pointer to the device instance. - R3 ptr. */ -
trunk/src/VBox/Devices/Samples/DevPlayground.cpp
r64373 r64387 96 96 * @callback_method_impl{FNPCIIOREGIONMAP} 97 97 */ 98 static DECLCALLBACK(int) devPlaygroundMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,98 static DECLCALLBACK(int) devPlaygroundMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 99 99 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 100 100 { -
trunk/src/VBox/Devices/Serial/DevSerial.cpp
r64373 r64387 230 230 231 231 #ifdef VBOX_SERIAL_PCI 232 P CIDEVICEPciDev;232 PDMPCIDEV PciDev; 233 233 #endif /* VBOX_SERIAL_PCI */ 234 234 } DEVSERIAL; … … 1051 1051 * @callback_method_impl{FNPCIIOREGIONMAP} 1052 1052 */ 1053 static DECLCALLBACK(int) serialIOPortRegionMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,1053 static DECLCALLBACK(int) serialIOPortRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 1054 1054 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 1055 1055 { -
trunk/src/VBox/Devices/Storage/DevAHCI.cpp
r64373 r64387 482 482 { 483 483 /** The PCI device structure. */ 484 P CIDEVICEdev;484 PDMPCIDEV dev; 485 485 /** Pointer to the device instance - R3 ptr */ 486 486 PPDMDEVINSR3 pDevInsR3; … … 2449 2449 * @callback_method_impl{FNPCIIOREGIONMAP} 2450 2450 */ 2451 static DECLCALLBACK(int) ahciR3MMIOMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,2451 static DECLCALLBACK(int) ahciR3MMIOMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 2452 2452 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 2453 2453 { … … 2493 2493 * controller.} 2494 2494 */ 2495 static DECLCALLBACK(int) ahciR3LegacyFakeIORangeMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,2495 static DECLCALLBACK(int) ahciR3LegacyFakeIORangeMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 2496 2496 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 2497 2497 { … … 2533 2533 * Map the BMDMA I/O port range (used for the Index/Data pair register access)} 2534 2534 */ 2535 static DECLCALLBACK(int) ahciR3IdxDataIORangeMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,2535 static DECLCALLBACK(int) ahciR3IdxDataIORangeMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 2536 2536 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 2537 2537 { -
trunk/src/VBox/Devices/Storage/DevATA.cpp
r64373 r64387 480 480 * The state of the ATA PCI device. 481 481 * 482 * @extends P CIDEVICE482 * @extends PDMPCIDEV 483 483 * @implements PDMILEDPORTS 484 484 */ 485 485 typedef struct PCIATAState 486 486 { 487 P CIDEVICEdev;487 PDMPCIDEV dev; 488 488 /** The controllers. */ 489 489 ATACONTROLLER aCts[2]; … … 6112 6112 * @callback_method_impl{FNPCIIOREGIONMAP} 6113 6113 */ 6114 static DECLCALLBACK(int) ataR3BMDMAIORangeMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,6114 static DECLCALLBACK(int) ataR3BMDMAIORangeMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 6115 6115 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 6116 6116 { -
trunk/src/VBox/Devices/Storage/DevBusLogic.cpp
r64373 r64387 322 322 * Main BusLogic device state. 323 323 * 324 * @extends P CIDEVICE324 * @extends PDMPCIDEV 325 325 * @implements PDMILEDPORTS 326 326 */ … … 328 328 { 329 329 /** The PCI device structure. */ 330 P CIDEVICEdev;330 PDMPCIDEV dev; 331 331 /** Pointer to the device instance - HC ptr */ 332 332 PPDMDEVINSR3 pDevInsR3; … … 2780 2780 * @callback_method_impl{FNPCIIOREGIONMAP} 2781 2781 */ 2782 static DECLCALLBACK(int) buslogicR3MmioMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,2782 static DECLCALLBACK(int) buslogicR3MmioMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 2783 2783 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 2784 2784 { -
trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp
r64373 r64387 189 189 { 190 190 /** PCI device structure. */ 191 P CIDEVICEPciDev;191 PDMPCIDEV PciDev; 192 192 /** Pointer to the device instance. - R3 ptr. */ 193 193 PPDMDEVINSR3 pDevInsR3; … … 3990 3990 * @callback_method_impl{FNPCIIOREGIONMAP} 3991 3991 */ 3992 static DECLCALLBACK(int) lsilogicR3Map(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,3992 static DECLCALLBACK(int) lsilogicR3Map(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 3993 3993 RTGCPHYS GCPhysAddress, RTGCPHYS cb, 3994 3994 PCIADDRESSSPACE enmType) -
trunk/src/VBox/Devices/USB/DevOHCI.cpp
r64373 r64387 264 264 { 265 265 /** The PCI device. */ 266 P CIDEVICEPciDev;266 PDMPCIDEV PciDev; 267 267 268 268 /** Pointer to the device instance - R3 ptr. */ … … 5364 5364 * @callback_method_impl{FNPCIIOREGIONMAP} 5365 5365 */ 5366 static DECLCALLBACK(int) ohciR3Map(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,5366 static DECLCALLBACK(int) ohciR3Map(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 5367 5367 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 5368 5368 { -
trunk/src/VBox/Devices/VMMDev/VMMDev.cpp
r64373 r64387 2879 2879 * @callback_method_impl{FNPCIIOREGIONMAP,MMIO/MMIO2 regions} 2880 2880 */ 2881 static DECLCALLBACK(int) vmmdevIORAMRegionMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,2881 static DECLCALLBACK(int) vmmdevIORAMRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 2882 2882 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 2883 2883 { … … 2947 2947 * @callback_method_impl{FNPCIIOREGIONMAP,I/O Port Region} 2948 2948 */ 2949 static DECLCALLBACK(int) vmmdevIOPortRegionMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,2949 static DECLCALLBACK(int) vmmdevIOPortRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 2950 2950 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType) 2951 2951 { -
trunk/src/VBox/Devices/VMMDev/VMMDevState.h
r62503 r64387 115 115 { 116 116 /** The PCI device structure. */ 117 P CIDevicePciDev;117 PDMPCIDEV PciDev; 118 118 /** The critical section for this device. 119 119 * @remarks We use this rather than the default one, it's simpler with all -
trunk/src/VBox/Devices/VirtIO/Virtio.cpp
r64301 r64387 626 626 * @thread EMT 627 627 */ 628 DECLINLINE(void) vpciCfgSetU8(P CIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)628 DECLINLINE(void) vpciCfgSetU8(PDMPCIDEV& refPciDev, uint32_t uOffset, uint8_t u8Value) 629 629 { 630 630 Assert(uOffset < sizeof(refPciDev.config)); … … 639 639 * @thread EMT 640 640 */ 641 DECLINLINE(void) vpciCfgSetU16(P CIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)641 DECLINLINE(void) vpciCfgSetU16(PDMPCIDEV& refPciDev, uint32_t uOffset, uint16_t u16Value) 642 642 { 643 643 Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config)); … … 653 653 * @thread EMT 654 654 */ 655 DECLINLINE(void) vpciCfgSetU32(P CIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)655 DECLINLINE(void) vpciCfgSetU32(PDMPCIDEV& refPciDev, uint32_t uOffset, uint32_t u32Value) 656 656 { 657 657 Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config)); … … 800 800 * @thread EMT 801 801 */ 802 static DECLCALLBACK(void) vpciConfigure(P CIDEVICE& pci,802 static DECLCALLBACK(void) vpciConfigure(PDMPCIDEV& pci, 803 803 uint16_t uDeviceId, 804 804 uint16_t uClass) -
trunk/src/VBox/Devices/VirtIO/Virtio.h
r62504 r64387 188 188 189 189 /** TODO */ 190 P CIDEVICEpciDevice;190 PDMPCIDEV pciDevice; 191 191 /** Base port of I/O space region. */ 192 192 RTIOPORT IOPortBase; -
trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp
r64351 r64387 281 281 /* Basic alignment checks. */ 282 282 CHECK_MEMBER_ALIGNMENT(PDMDEVINS, achInstanceData, 64); 283 CHECK_MEMBER_ALIGNMENT(P CIDEVICE, Int.s, 16);284 CHECK_MEMBER_ALIGNMENT(P CIDEVICE, Int.s.aIORegions, 16);283 CHECK_MEMBER_ALIGNMENT(PDMPCIDEV, Int.s, 16); 284 CHECK_MEMBER_ALIGNMENT(PDMPCIDEV, Int.s.aIORegions, 16); 285 285 286 286 /* -
trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp
r64373 r64387 151 151 GEN_CHECK_SIZE(PDMPCIDEVICEINT); 152 152 GEN_CHECK_SIZE(PCIIOREGION); 153 GEN_CHECK_OFF(P CIDEVICE, config);154 GEN_CHECK_OFF(P CIDEVICE, devfn);155 GEN_CHECK_OFF(P CIDEVICE, name);156 GEN_CHECK_OFF(P CIDEVICE, pDevIns);157 GEN_CHECK_OFF(P CIDEVICE, Int);158 GEN_CHECK_OFF(P CIDEVICE, Int.s.aIORegions);159 GEN_CHECK_OFF(P CIDEVICE, Int.s.aIORegions[1]);160 GEN_CHECK_OFF(P CIDEVICE, Int.s.aIORegions[VBOX_PCI_NUM_REGIONS - 1]);161 GEN_CHECK_OFF(P CIDEVICE, Int.s.aIORegions[0].addr);162 GEN_CHECK_OFF(P CIDEVICE, Int.s.aIORegions[0].size);163 GEN_CHECK_OFF(P CIDEVICE, Int.s.aIORegions[0].type);164 GEN_CHECK_OFF(P CIDEVICE, Int.s.aIORegions[0].padding);165 GEN_CHECK_OFF(P CIDEVICE, Int.s.pBusR3);166 GEN_CHECK_OFF(P CIDEVICE, Int.s.pBusR0);167 GEN_CHECK_OFF(P CIDEVICE, Int.s.pBusRC);168 GEN_CHECK_OFF(P CIDEVICE, Int.s.pfnConfigRead);169 GEN_CHECK_OFF(P CIDEVICE, Int.s.pfnConfigWrite);170 GEN_CHECK_OFF(P CIDEVICE, Int.s.fFlags);171 GEN_CHECK_OFF(P CIDEVICE, Int.s.uIrqPinState);172 GEN_CHECK_OFF(P CIDEVICE, Int.s.pfnBridgeConfigRead);173 GEN_CHECK_OFF(P CIDEVICE, Int.s.pfnBridgeConfigWrite);174 GEN_CHECK_PADDING(P CIDEVICE, Int, 8);153 GEN_CHECK_OFF(PDMPCIDEV, config); 154 GEN_CHECK_OFF(PDMPCIDEV, devfn); 155 GEN_CHECK_OFF(PDMPCIDEV, name); 156 GEN_CHECK_OFF(PDMPCIDEV, pDevIns); 157 GEN_CHECK_OFF(PDMPCIDEV, Int); 158 GEN_CHECK_OFF(PDMPCIDEV, Int.s.aIORegions); 159 GEN_CHECK_OFF(PDMPCIDEV, Int.s.aIORegions[1]); 160 GEN_CHECK_OFF(PDMPCIDEV, Int.s.aIORegions[VBOX_PCI_NUM_REGIONS - 1]); 161 GEN_CHECK_OFF(PDMPCIDEV, Int.s.aIORegions[0].addr); 162 GEN_CHECK_OFF(PDMPCIDEV, Int.s.aIORegions[0].size); 163 GEN_CHECK_OFF(PDMPCIDEV, Int.s.aIORegions[0].type); 164 GEN_CHECK_OFF(PDMPCIDEV, Int.s.aIORegions[0].padding); 165 GEN_CHECK_OFF(PDMPCIDEV, Int.s.pBusR3); 166 GEN_CHECK_OFF(PDMPCIDEV, Int.s.pBusR0); 167 GEN_CHECK_OFF(PDMPCIDEV, Int.s.pBusRC); 168 GEN_CHECK_OFF(PDMPCIDEV, Int.s.pfnConfigRead); 169 GEN_CHECK_OFF(PDMPCIDEV, Int.s.pfnConfigWrite); 170 GEN_CHECK_OFF(PDMPCIDEV, Int.s.fFlags); 171 GEN_CHECK_OFF(PDMPCIDEV, Int.s.uIrqPinState); 172 GEN_CHECK_OFF(PDMPCIDEV, Int.s.pfnBridgeConfigRead); 173 GEN_CHECK_OFF(PDMPCIDEV, Int.s.pfnBridgeConfigWrite); 174 GEN_CHECK_PADDING(PDMPCIDEV, Int, 8); 175 175 GEN_CHECK_SIZE(PIIX3State); 176 176 GEN_CHECK_SIZE(PCIBUS); -
trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp
r64378 r64387 69 69 70 70 /** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */ 71 static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, RTGCPHYS GCPhys,71 static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, 72 72 void *pvBuf, size_t cbRead) 73 73 { … … 96 96 97 97 /** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */ 98 static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, RTGCPHYS GCPhys,98 static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, 99 99 const void *pvBuf, size_t cbWrite) 100 100 { … … 123 123 124 124 /** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */ 125 static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel)125 static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel) 126 126 { 127 127 PDMDEV_ASSERT_DEVINS(pDevIns); -
trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp
r64378 r64387 428 428 * @copydoc PDMDEVHLPR3::pfnMMIO2Register 429 429 */ 430 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Register(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion, RTGCPHYS cb,430 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Register(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cb, 431 431 uint32_t fFlags, void **ppv, const char *pszDesc) 432 432 { … … 452 452 */ 453 453 static DECLCALLBACK(int) 454 pdmR3DevHlp_MMIOExPreRegister(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion, RTGCPHYS cbRegion, uint32_t fFlags,454 pdmR3DevHlp_MMIOExPreRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion, uint32_t fFlags, 455 455 const char *pszDesc, 456 456 RTHCPTR pvUser, PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill, … … 542 542 * @copydoc PDMDEVHLPR3::pfnMMIOExDeregister 543 543 */ 544 static DECLCALLBACK(int) pdmR3DevHlp_MMIOExDeregister(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion)544 static DECLCALLBACK(int) pdmR3DevHlp_MMIOExDeregister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion) 545 545 { 546 546 PDMDEV_ASSERT_DEVINS(pDevIns); … … 562 562 * @copydoc PDMDEVHLPR3::pfnMMIOExMap 563 563 */ 564 static DECLCALLBACK(int) pdmR3DevHlp_MMIOExMap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion, RTGCPHYS GCPhys)564 static DECLCALLBACK(int) pdmR3DevHlp_MMIOExMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys) 565 565 { 566 566 PDMDEV_ASSERT_DEVINS(pDevIns); … … 580 580 * @copydoc PDMDEVHLPR3::pfnMMIOExUnmap 581 581 */ 582 static DECLCALLBACK(int) pdmR3DevHlp_MMIOExUnmap(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion, RTGCPHYS GCPhys)582 static DECLCALLBACK(int) pdmR3DevHlp_MMIOExUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys) 583 583 { 584 584 PDMDEV_ASSERT_DEVINS(pDevIns); … … 598 598 * @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2 599 599 */ 600 static DECLCALLBACK(int) pdmR3DevHlp_MMHyperMapMMIO2(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion, RTGCPHYS off,600 static DECLCALLBACK(int) pdmR3DevHlp_MMHyperMapMMIO2(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off, 601 601 RTGCPHYS cb, const char *pszDesc, PRTRCPTR pRCPtr) 602 602 { … … 625 625 * @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel 626 626 */ 627 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2MapKernel(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion, RTGCPHYS off,627 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2MapKernel(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off, 628 628 RTGCPHYS cb,const char *pszDesc, PRTR0PTR pR0Ptr) 629 629 { … … 1215 1215 * @interface_method_impl{PDMDEVHLPR3,pfnPCIRegister} 1216 1216 */ 1217 static DECLCALLBACK(int) pdmR3DevHlp_PCIRegister(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t idxDevCfg, uint32_t fFlags,1217 static DECLCALLBACK(int) pdmR3DevHlp_PCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t idxDevCfg, uint32_t fFlags, 1218 1218 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName) 1219 1219 { … … 1459 1459 1460 1460 /** @interface_method_impl{PDMDEVHLPR3,pfnPCIRegisterMsi} */ 1461 static DECLCALLBACK(int) pdmR3DevHlp_PCIRegisterMsi(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, PPDMMSIREG pMsiReg)1461 static DECLCALLBACK(int) pdmR3DevHlp_PCIRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg) 1462 1462 { 1463 1463 PDMDEV_ASSERT_DEVINS(pDevIns); … … 1484 1484 1485 1485 /** @interface_method_impl{PDMDEVHLPR3,pfnPCIIORegionRegister} */ 1486 static DECLCALLBACK(int) pdmR3DevHlp_PCIIORegionRegister(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t iRegion,1486 static DECLCALLBACK(int) pdmR3DevHlp_PCIIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, 1487 1487 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback) 1488 1488 { … … 1584 1584 1585 1585 /** @interface_method_impl{PDMDEVHLPR3,pfnPCISetConfigCallbacks} */ 1586 static DECLCALLBACK(void) pdmR3DevHlp_PCISetConfigCallbacks(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,1586 static DECLCALLBACK(void) pdmR3DevHlp_PCISetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld, 1587 1587 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld) 1588 1588 { … … 1622 1622 /** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysRead} */ 1623 1623 static DECLCALLBACK(int) 1624 pdmR3DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)1624 pdmR3DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead) 1625 1625 { 1626 1626 PDMDEV_ASSERT_DEVINS(pDevIns); … … 1649 1649 /** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysWrite} */ 1650 1650 static DECLCALLBACK(int) 1651 pdmR3DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)1651 pdmR3DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite) 1652 1652 { 1653 1653 PDMDEV_ASSERT_DEVINS(pDevIns); … … 1675 1675 1676 1676 /** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrq} */ 1677 static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel)1677 static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel) 1678 1678 { 1679 1679 PDMDEV_ASSERT_DEVINS(pDevIns); … … 1721 1721 1722 1722 /** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrqNoWait} */ 1723 static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrqNoWait(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel)1723 static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel) 1724 1724 { 1725 1725 pdmR3DevHlp_PCISetIrq(pDevIns, pPciDev, iIrq, iLevel); … … 4212 4212 { 4213 4213 /* Same as pdmR3DevHlp_PCISetIrq, except we've got a tag already. */ 4214 PP CIDEVICEpPciDev = pTask->u.PciSetIRQ.pPciDevR3;4214 PPDMPCIDEV pPciDev = pTask->u.PciSetIRQ.pPciDevR3; 4215 4215 if (pPciDev) 4216 4216 { -
trunk/src/VBox/VMM/include/PDMInternal.h
r64374 r64387 704 704 PPDMDEVINSR3 pDevInsR3; 705 705 /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */ 706 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel, uint32_t uTagSrc));706 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)); 707 707 /** @copydoc PDMPCIBUSREG::pfnRegisterR3 */ 708 DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, uint32_t fFlags,708 DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags, 709 709 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)); 710 710 /** @copydoc PDMPCIBUSREG::pfnRegisterMsiR3 */ 711 DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, PPDMMSIREG pMsiReg));711 DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)); 712 712 /** @copydoc PDMPCIBUSREG::pfnIORegionRegisterR3 */ 713 DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iRegion, RTGCPHYS cbRegion,713 DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iRegion, RTGCPHYS cbRegion, 714 714 PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)); 715 715 /** @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksR3 */ 716 DECLR3CALLBACKMEMBER(void, pfnSetConfigCallbacksR3,(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, PFNPCICONFIGREAD pfnRead,716 DECLR3CALLBACKMEMBER(void, pfnSetConfigCallbacksR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead, 717 717 PPFNPCICONFIGREAD ppfnReadOld, PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)); 718 718 /** @copydoc PDMPCIBUSREG::pfnFakePCIBIOSR3 */ … … 722 722 R0PTRTYPE(PPDMDEVINS) pDevInsR0; 723 723 /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */ 724 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel, uint32_t uTagSrc));724 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)); 725 725 726 726 /** Pointer to PCI Bus device instance. */ 727 727 PPDMDEVINSRC pDevInsRC; 728 728 /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */ 729 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PP CIDEVICEpPciDev, int iIrq, int iLevel, uint32_t uTagSrc));729 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)); 730 730 } PDMPCIBUS; 731 731
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