VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp@ 88787

Last change on this file since 88787 was 88787, checked in by vboxsync, 4 years ago

Devices/Graphics: a few DX commands. bugref:9830
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 257.1 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 88787 2021-04-29 15:51:13Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef IN_RING3
19# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
20#endif
21
22
23#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
24#include <iprt/mem.h>
25#include <VBox/AssertGuest.h>
26#include <VBox/log.h>
27#include <VBox/vmm/pdmdev.h>
28#include <VBoxVideo.h>
29
30/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
31#include "DevVGA.h"
32
33/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
34#ifdef VBOX_WITH_VMSVGA3D
35# include "DevVGA-SVGA3d.h"
36#endif
37#include "DevVGA-SVGA-internal.h"
38
39#ifdef DUMP_BITMAPS
40# include <iprt/formats/bmp.h>
41# include <stdio.h>
42#endif
43
44#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
45# define SVGA_CASE_ID2STR(idx) case idx: return #idx
46
47static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
48{
49 switch (enmCmdId)
50 {
51 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
52 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
53 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
54 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
55 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
56 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
57 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
58 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1);
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
290 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
291 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
292 }
293 return "UNKNOWN_3D";
294}
295
296/**
297 * FIFO command name lookup
298 *
299 * @returns FIFO command string or "UNKNOWN"
300 * @param u32Cmd FIFO command
301 */
302const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
303{
304 switch (u32Cmd)
305 {
306 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
307 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
308 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
309 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
310 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
311 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
312 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
313 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
314 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
315 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
316 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
317 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
318 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
319 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
320 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
321 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
322 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
323 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
324 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
325 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
326 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
327 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
328 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
329 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
330 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
331 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
332 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
333 default:
334 if ( u32Cmd >= SVGA_3D_CMD_BASE
335 && u32Cmd < SVGA_3D_CMD_MAX)
336 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
337 }
338 return "UNKNOWN";
339}
340# undef SVGA_CASE_ID2STR
341#endif /* LOG_ENABLED || VBOX_STRICT */
342
343
344/*
345 *
346 * Guest-Backed Objects (GBO).
347 *
348 */
349
350/**
351 * HC access handler for GBOs which require write protection, i.e. OTables, etc.
352 *
353 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
354 * @param pVM VM Handle.
355 * @param pVCpu The cross context CPU structure for the calling EMT.
356 * @param GCPhys The physical address the guest is writing to.
357 * @param pvPhys The HC mapping of that address.
358 * @param pvBuf What the guest is reading/writing.
359 * @param cbBuf How much it's reading/writing.
360 * @param enmAccessType The access type.
361 * @param enmOrigin Who is making the access.
362 * @param pvUser User argument.
363 */
364DECLCALLBACK(VBOXSTRICTRC)
365vmsvgaR3GboAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
366 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
367{
368 RT_NOREF(pVM, pVCpu, pvPhys, enmAccessType);
369
370 if (RT_LIKELY(enmOrigin == PGMACCESSORIGIN_DEVICE || enmOrigin == PGMACCESSORIGIN_DEBUGGER))
371 return VINF_PGM_HANDLER_DO_DEFAULT;
372
373 PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
374 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
375 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
376 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
377
378 /*
379 * The guest is not allowed to access the memory.
380 * Set the error condition.
381 */
382 ASMAtomicWriteBool(&pThis->svga.fBadGuest, true);
383
384 /* Try to find the GBO which the guest is accessing. */
385 char const *pszTarget = NULL;
386 for (uint32_t i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables) && !pszTarget; ++i)
387 {
388 PVMSVGAGBO pGbo = &pSvgaR3State->aGboOTables[i];
389 if (pGbo->cDescriptors)
390 {
391 for (uint32_t j = 0; j < pGbo->cDescriptors; ++j)
392 {
393 if ( GCPhys >= pGbo->paDescriptors[j].GCPhys
394 && GCPhys < pGbo->paDescriptors[j].GCPhys + pGbo->paDescriptors[j].cPages * PAGE_SIZE)
395 {
396 switch (i)
397 {
398 case SVGA_OTABLE_MOB: pszTarget = "SVGA_OTABLE_MOB"; break;
399 case SVGA_OTABLE_SURFACE: pszTarget = "SVGA_OTABLE_SURFACE"; break;
400 case SVGA_OTABLE_CONTEXT: pszTarget = "SVGA_OTABLE_CONTEXT"; break;
401 case SVGA_OTABLE_SHADER: pszTarget = "SVGA_OTABLE_SHADER"; break;
402 case SVGA_OTABLE_SCREENTARGET: pszTarget = "SVGA_OTABLE_SCREENTARGET"; break;
403 case SVGA_OTABLE_DXCONTEXT: pszTarget = "SVGA_OTABLE_DXCONTEXT"; break;
404 default: pszTarget = "Unknown OTABLE"; break;
405 }
406 break;
407 }
408 }
409 }
410 }
411
412 LogRelMax(8, ("VMSVGA: invalid guest access to page %RGp, target %s:\n"
413 "%.*Rhxd\n",
414 GCPhys, pszTarget ? pszTarget : "unknown", RT_MIN(cbBuf, 256), pvBuf));
415
416 return VINF_PGM_HANDLER_DO_DEFAULT;
417}
418
419
420static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, bool fGCPhys64, bool fWriteProtected, PVMSVGAGBO pGbo)
421{
422 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
423
424 /*
425 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
426 * Content of the root page depends on the ptDepth value:
427 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
428 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
429 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
430 * The code below extracts the page addresses of the GBO.
431 */
432
433 /* Verify and normalize the ptDepth value. */
434 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
435 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
436 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
437 ASSERT_GUEST_RETURN(fGCPhys64, VERR_INVALID_PARAMETER);
438 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
439 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
440 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
441 {
442 ASSERT_GUEST_RETURN(!fGCPhys64, VERR_INVALID_PARAMETER);
443 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
444 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
445 }
446 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
447 { }
448 else
449 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
450
451 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
452
453 pGbo->cbTotal = sizeInBytes;
454 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
455
456 /* Allocate the maximum amount possible (everything non-continuous) */
457 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
458 AssertReturn(paDescriptors, VERR_NO_MEMORY);
459
460 int rc = VINF_SUCCESS;
461 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
462 {
463 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
464 RTMemFree(paDescriptors),
465 VERR_INVALID_PARAMETER);
466
467 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
468 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
469 paDescriptors[0].GCPhys = GCPhys;
470 paDescriptors[0].cPages = 1;
471 }
472 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
473 {
474 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
475 RTMemFree(paDescriptors),
476 VERR_INVALID_PARAMETER);
477
478 /* Read the root page. */
479 uint8_t au8RootPage[X86_PAGE_SIZE];
480 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
481 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
482 if (RT_SUCCESS(rc))
483 {
484 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
485 PPN *paPPN32 = (PPN *)&au8RootPage[0];
486 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
487 {
488 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
489 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
490 paDescriptors[iPPN].GCPhys = GCPhys;
491 paDescriptors[iPPN].cPages = 1;
492 }
493 }
494 }
495 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
496 {
497 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
498 RTMemFree(paDescriptors),
499 VERR_INVALID_PARAMETER);
500
501 /* Read the Level2 root page. */
502 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
503 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
504 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
505 if (RT_SUCCESS(rc))
506 {
507 uint32_t cPagesLeft = pGbo->cTotalPages;
508
509 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
510 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
511
512 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
513 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
514 {
515 /* Read the Level1 root page. */
516 uint8_t au8RootPage[X86_PAGE_SIZE];
517 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
518 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
519 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
520 if (RT_SUCCESS(rc))
521 {
522 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
523 PPN *paPPN32 = (PPN *)&au8RootPage[0];
524
525 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
526 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
527 {
528 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
529 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
530 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
531 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
532 }
533 cPagesLeft -= cPPNs;
534 }
535 }
536 }
537 }
538 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
539 {
540 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
541 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
542 paDescriptors[0].GCPhys = GCPhys;
543 paDescriptors[0].cPages = pGbo->cTotalPages;
544 }
545 else
546 {
547 AssertFailed();
548 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
549 }
550
551 /* Compress the descriptors. */
552 if (ptDepth != SVGA3D_MOBFMT_RANGE)
553 {
554 uint32_t iDescriptor = 0;
555 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
556 {
557 /* Continuous physical memory? */
558 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
559 {
560 Assert(paDescriptors[iDescriptor].cPages);
561 paDescriptors[iDescriptor].cPages++;
562 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
563 }
564 else
565 {
566 iDescriptor++;
567 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
568 paDescriptors[iDescriptor].cPages = 1;
569 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
570 }
571 }
572
573 pGbo->cDescriptors = iDescriptor + 1;
574 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
575 }
576 else
577 pGbo->cDescriptors = 1;
578
579 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
580 {
581 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
582 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
583 }
584 else
585 pGbo->paDescriptors = paDescriptors;
586
587#if 1 /// @todo PGMHandlerPhysicalRegister asserts deep in PGM code with enmKind of a page being out of range.
588fWriteProtected = false;
589#endif
590 if (fWriteProtected)
591 {
592 pGbo->fGboFlags |= VMSVGAGBO_F_WRITE_PROTECTED;
593 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
594 {
595 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pSvgaR3State->pDevIns),
596 pGbo->paDescriptors[i].GCPhys, pGbo->paDescriptors[i].GCPhys + pGbo->paDescriptors[i].cPages * PAGE_SIZE - 1,
597 pSvgaR3State->hGboAccessHandlerType, pSvgaR3State->pDevIns, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GBO");
598 AssertRC(rc);
599 }
600 }
601
602 return VINF_SUCCESS;
603}
604
605
606static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
607{
608 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
609 {
610 if (pGbo->fGboFlags & VMSVGAGBO_F_WRITE_PROTECTED)
611 {
612 for (uint32_t i = 0; i < pGbo->cDescriptors; ++i)
613 {
614 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pSvgaR3State->pDevIns), pGbo->paDescriptors[i].GCPhys);
615 AssertRC(rc);
616 }
617 }
618 RTMemFree(pGbo->paDescriptors);
619 RT_ZERO(pGbo);
620 }
621}
622
623/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
624
625typedef enum VMSVGAGboTransferDirection
626{
627 VMSVGAGboTransferDirection_Read,
628 VMSVGAGboTransferDirection_Write,
629} VMSVGAGboTransferDirection;
630
631static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
632 uint32_t off, void *pvData, uint32_t cbData,
633 VMSVGAGboTransferDirection enmDirection)
634{
635// ASMBreakpoint();
636 int rc = VINF_SUCCESS;
637 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
638
639 /* Find the right descriptor */
640 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
641 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
642 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
643 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
644 {
645 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
646 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
647 ++iDescriptor;
648 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
649 }
650
651 while (cbData)
652 {
653 uint32_t cbToCopy;
654 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
655 cbToCopy = cbData;
656 else
657 {
658 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
659 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
660 }
661
662 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
663 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
664
665 /*
666 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
667 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
668 * see @bugref{9654#c75}.
669 */
670 if (enmDirection == VMSVGAGboTransferDirection_Read)
671 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
672 else
673 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
674 AssertRCBreak(rc);
675
676 cbData -= cbToCopy;
677 off += cbToCopy;
678 pu8CurrentHost += cbToCopy;
679
680 /* Go to the next descriptor if there's anything left. */
681 if (cbData)
682 {
683 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
684 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
685 ++iDescriptor;
686 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
687 }
688 }
689 return rc;
690}
691
692
693static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
694 uint32_t off, void const *pvData, uint32_t cbData)
695{
696 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
697 off, (void *)pvData, cbData,
698 VMSVGAGboTransferDirection_Write);
699}
700
701
702static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
703 uint32_t off, void *pvData, uint32_t cbData)
704{
705 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
706 off, pvData, cbData,
707 VMSVGAGboTransferDirection_Read);
708}
709
710
711static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
712{
713 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
714 vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
715 RTMemFree(pGbo->pvHost);
716 pGbo->pvHost = NULL;
717 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
718}
719
720
721static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
722{
723 int rc;
724
725 /* Just reread the data if pvHost has been allocated already. */
726 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
727 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
728
729 if (pGbo->pvHost)
730 {
731 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
732 }
733 else
734 rc = VERR_NO_MEMORY;
735
736 if (RT_SUCCESS(rc))
737 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
738 else
739 {
740 RTMemFree(pGbo->pvHost);
741 pGbo->pvHost = NULL;
742 }
743 return rc;
744}
745
746
747
748/*
749 *
750 * Object Tables.
751 *
752 */
753
754static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
755 uint32_t idx, uint32_t cbEntry)
756{
757 RT_NOREF(pSvgaR3State);
758
759 /* The table must exist and the index must be within the table. */
760 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
761 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
762 RT_UNTRUSTED_VALIDATED_FENCE();
763 return VINF_SUCCESS;
764}
765
766
767static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
768 uint32_t idx, uint32_t cbEntry,
769 void *pvData, uint32_t cbData)
770{
771 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
772
773 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
774 if (RT_SUCCESS(rc))
775 {
776 uint32_t const off = idx * cbEntry;
777 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
778 }
779 return rc;
780}
781
782static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
783 uint32_t idx, uint32_t cbEntry,
784 void const *pvData, uint32_t cbData)
785{
786 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
787
788 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
789 if (RT_SUCCESS(rc))
790 {
791 uint32_t const off = idx * cbEntry;
792 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
793 }
794 return rc;
795}
796
797
798/*
799 *
800 * The guest's Memory OBjects (MOB).
801 *
802 */
803
804static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
805 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
806 bool fGCPhys64, PVMSVGAMOB pMob)
807{
808 RT_ZERO(*pMob);
809
810 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
811 SVGAOTableMobEntry entry;
812 entry.ptDepth = ptDepth;
813 entry.sizeInBytes = sizeInBytes;
814 entry.base = baseAddress;
815 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
816 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
817 if (RT_SUCCESS(rc))
818 {
819 /* Create the corresponding GBO. */
820 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, fGCPhys64, /* fWriteProtected = */ false, &pMob->Gbo);
821 if (RT_SUCCESS(rc))
822 {
823 /* Add to the tree of known GBOs and the LRU list. */
824 pMob->Core.Key = mobid;
825 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
826 {
827 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
828 return VINF_SUCCESS;
829 }
830
831 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
832 }
833 }
834
835 return rc;
836}
837
838
839static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
840{
841 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
842 SVGAOTableMobEntry entry;
843 RT_ZERO(entry);
844 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
845 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
846
847 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
848 if (pMob)
849 {
850 RTListNodeRemove(&pMob->nodeLRU);
851 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
852 RTMemFree(pMob);
853 return VINF_SUCCESS;
854 }
855
856 return VERR_INVALID_PARAMETER;
857}
858
859
860static PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
861{
862 if (mobid == SVGA_ID_INVALID)
863 return NULL;
864
865 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
866 if (pMob)
867 {
868 /* Move to the head of the LRU list. */
869 RTListNodeRemove(&pMob->nodeLRU);
870 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
871 }
872 else
873 ASSERT_GUEST_FAILED();
874
875 return pMob;
876}
877
878
879/** Create a host ring-3 pointer to the MOB data.
880 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
881 * @param pMob The MOB.
882 * @param cbValid How many bytes of the guest backing memory contain valid data.
883 * @return VBox status.
884 */
885/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
886int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
887{
888 AssertReturn(pMob, VERR_INVALID_PARAMETER);
889 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
890}
891
892
893void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
894{
895 if (pMob)
896 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
897}
898
899
900void *vmsvgaR3MobBackingStoreGet(PVMSVGAMOB pMob, uint32_t off)
901{
902 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
903 {
904 if (off <= pMob->Gbo.cbTotal)
905 return (uint8_t *)pMob->Gbo.pvHost + off;
906 }
907 return NULL;
908}
909
910
911#ifdef VBOX_WITH_VMSVGA3D
912int vmsvgaR3UpdateGBSurface(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBox)
913{
914 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
915
916 SVGAOTableSurfaceEntry entrySurface;
917 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
918 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
919 if (RT_SUCCESS(rc))
920 {
921 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
922 if (pMob)
923 {
924 VMSVGA3D_MAPPED_SURFACE map;
925 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, pImageId, pBox, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
926 if (RT_SUCCESS(rc))
927 {
928 /* Copy MOB -> mapped surface. */
929 uint32_t offSrc = pBox->x * map.cbPixel
930 + pBox->y * entrySurface.size.width * map.cbPixel
931 + pBox->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
932 uint8_t *pu8Dst = (uint8_t *)map.pvData;
933 for (uint32_t z = 0; z < pBox->d; ++z)
934 {
935 for (uint32_t y = 0; y < pBox->h; ++y)
936 {
937 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBox->w * map.cbPixel);
938 if (RT_FAILURE(rc))
939 break;
940
941 pu8Dst += map.cbRowPitch;
942 offSrc += entrySurface.size.width * map.cbPixel;
943 }
944
945 pu8Dst += map.cbDepthPitch;
946 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
947 }
948
949 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
950 }
951 }
952 else
953 rc = VERR_INVALID_STATE;
954 }
955
956 return rc;
957}
958
959
960int vmsvgaR3UpdateGBSurfaceEx(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImageId, SVGA3dBox const *pBoxDst, SVGA3dPoint const *pPtSrc)
961{
962 /* pPtSrc must be verified by the caller. */
963 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
964
965 SVGAOTableSurfaceEntry entrySurface;
966 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
967 pImageId->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
968 if (RT_SUCCESS(rc))
969 {
970 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
971 if (pMob)
972 {
973 VMSVGA3D_MAPPED_SURFACE map;
974 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, pImageId, pBoxDst, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
975 if (RT_SUCCESS(rc))
976 {
977 /* Copy MOB -> mapped surface. */
978 uint32_t offSrc = pPtSrc->x * map.cbPixel
979 + pPtSrc->y * entrySurface.size.width * map.cbPixel
980 + pPtSrc->z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
981 uint8_t *pu8Dst = (uint8_t *)map.pvData;
982 for (uint32_t z = 0; z < pBoxDst->d; ++z)
983 {
984 for (uint32_t y = 0; y < pBoxDst->h; ++y)
985 {
986 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pBoxDst->w * map.cbPixel);
987 if (RT_FAILURE(rc))
988 break;
989
990 pu8Dst += map.cbRowPitch;
991 offSrc += entrySurface.size.width * map.cbPixel;
992 }
993
994 pu8Dst += map.cbDepthPitch;
995 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
996 }
997
998 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, pImageId, &map, /* fWritten= */ true);
999 }
1000 }
1001 else
1002 rc = VERR_INVALID_STATE;
1003 }
1004
1005 return rc;
1006}
1007#endif /* VBOX_WITH_VMSVGA3D */
1008
1009
1010/*
1011 * Screen objects.
1012 */
1013VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
1014{
1015 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1016 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
1017 && pSVGAState
1018 && pSVGAState->aScreens[idScreen].fDefined)
1019 {
1020 return &pSVGAState->aScreens[idScreen];
1021 }
1022 return NULL;
1023}
1024
1025void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
1026{
1027#ifdef VBOX_WITH_VMSVGA3D
1028 if (pThis->svga.f3DEnabled)
1029 {
1030 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
1031 {
1032 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
1033 if (pScreen)
1034 vmsvga3dDestroyScreen(pThisCC, pScreen);
1035 }
1036 }
1037#else
1038 RT_NOREF(pThis, pThisCC);
1039#endif
1040}
1041
1042
1043/**
1044 * Copy a rectangle of pixels within guest VRAM.
1045 */
1046static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1047 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1048{
1049 if (!width || !height)
1050 return; /* Nothing to do, don't even bother. */
1051
1052 /*
1053 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1054 * corresponding to the current display mode.
1055 */
1056 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1057 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1058 uint8_t const *pSrc;
1059 uint8_t *pDst;
1060 unsigned const cbRectWidth = width * cbPixel;
1061 unsigned uMaxOffset;
1062
1063 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1064 if (uMaxOffset >= cbFrameBuffer)
1065 {
1066 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1067 return; /* Just don't listen to a bad guest. */
1068 }
1069
1070 pSrc = pDst = pThisCC->pbVRam;
1071 pSrc += srcY * cbScanline + srcX * cbPixel;
1072 pDst += dstY * cbScanline + dstX * cbPixel;
1073
1074 if (srcY >= dstY)
1075 {
1076 /* Source below destination, copy top to bottom. */
1077 for (; height > 0; height--)
1078 {
1079 memmove(pDst, pSrc, cbRectWidth);
1080 pSrc += cbScanline;
1081 pDst += cbScanline;
1082 }
1083 }
1084 else
1085 {
1086 /* Source above destination, copy bottom to top. */
1087 pSrc += cbScanline * (height - 1);
1088 pDst += cbScanline * (height - 1);
1089 for (; height > 0; height--)
1090 {
1091 memmove(pDst, pSrc, cbRectWidth);
1092 pSrc -= cbScanline;
1093 pDst -= cbScanline;
1094 }
1095 }
1096}
1097
1098
1099/**
1100 * Common worker for changing the pointer shape.
1101 *
1102 * @param pThisCC The VGA/VMSVGA state for ring-3.
1103 * @param pSVGAState The VMSVGA ring-3 instance data.
1104 * @param fAlpha Whether there is alpha or not.
1105 * @param xHot Hotspot x coordinate.
1106 * @param yHot Hotspot y coordinate.
1107 * @param cx Width.
1108 * @param cy Height.
1109 * @param pbData Heap copy of the cursor data. Consumed.
1110 * @param cbData The size of the data.
1111 */
1112static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1113 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1114{
1115 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1116#ifdef LOG_ENABLED
1117 if (LogIs2Enabled())
1118 {
1119 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1120 if (!fAlpha)
1121 {
1122 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1123 for (uint32_t y = 0; y < cy; y++)
1124 {
1125 Log2(("%3u:", y));
1126 uint8_t const *pbLine = &pbData[y * cbAndLine];
1127 for (uint32_t x = 0; x < cx; x += 8)
1128 {
1129 uint8_t b = pbLine[x / 8];
1130 char szByte[12];
1131 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1132 szByte[1] = b & 0x40 ? '*' : ' ';
1133 szByte[2] = b & 0x20 ? '*' : ' ';
1134 szByte[3] = b & 0x10 ? '*' : ' ';
1135 szByte[4] = b & 0x08 ? '*' : ' ';
1136 szByte[5] = b & 0x04 ? '*' : ' ';
1137 szByte[6] = b & 0x02 ? '*' : ' ';
1138 szByte[7] = b & 0x01 ? '*' : ' ';
1139 szByte[8] = '\0';
1140 Log2(("%s", szByte));
1141 }
1142 Log2(("\n"));
1143 }
1144 }
1145
1146 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1147 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1148 for (uint32_t y = 0; y < cy; y++)
1149 {
1150 Log2(("%3u:", y));
1151 uint32_t const *pu32Line = &pu32Xor[y * cx];
1152 for (uint32_t x = 0; x < cx; x++)
1153 Log2((" %08x", pu32Line[x]));
1154 Log2(("\n"));
1155 }
1156 }
1157#endif
1158
1159 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1160 AssertRC(rc);
1161
1162 if (pSVGAState->Cursor.fActive)
1163 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1164
1165 pSVGAState->Cursor.fActive = true;
1166 pSVGAState->Cursor.xHotspot = xHot;
1167 pSVGAState->Cursor.yHotspot = yHot;
1168 pSVGAState->Cursor.width = cx;
1169 pSVGAState->Cursor.height = cy;
1170 pSVGAState->Cursor.cbData = cbData;
1171 pSVGAState->Cursor.pData = pbData;
1172}
1173
1174
1175#ifdef VBOX_WITH_VMSVGA3D
1176
1177/*
1178 * SVGA_3D_CMD_* handlers.
1179 */
1180
1181
1182/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1183 *
1184 * @param pThisCC The VGA/VMSVGA state for the current context.
1185 * @param pCmd The VMSVGA command.
1186 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1187 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1188 */
1189static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1190 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1191{
1192 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1193 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1194 RT_UNTRUSTED_VALIDATED_FENCE();
1195
1196 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1197 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1198 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1199 */
1200 uint32_t cRemainingMipLevels = cMipLevelSizes;
1201 uint32_t cFaces = 0;
1202 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1203 {
1204 if (pCmd->face[i].numMipLevels == 0)
1205 break;
1206
1207 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1208 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1209
1210 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1211 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1212 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1213
1214 ++cFaces;
1215 }
1216 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1217 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1218
1219 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1220 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1221
1222 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1223 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1224 RT_UNTRUSTED_VALIDATED_FENCE();
1225
1226 /* Verify paMipLevelSizes */
1227 uint32_t cWidth = paMipLevelSizes[0].width;
1228 uint32_t cHeight = paMipLevelSizes[0].height;
1229 uint32_t cDepth = paMipLevelSizes[0].depth;
1230 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1231 {
1232 cWidth >>= 1;
1233 if (cWidth == 0) cWidth = 1;
1234 cHeight >>= 1;
1235 if (cHeight == 0) cHeight = 1;
1236 cDepth >>= 1;
1237 if (cDepth == 0) cDepth = 1;
1238 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1239 {
1240 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1241 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1242 && cHeight == paMipLevelSizes[iMipLevelSize].height
1243 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1244 }
1245 }
1246 RT_UNTRUSTED_VALIDATED_FENCE();
1247
1248 /* Create the surface. */
1249 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1250 pCmd->multisampleCount, pCmd->autogenFilter,
1251 pCmd->face[0].numMipLevels, &paMipLevelSizes[0]);
1252}
1253
1254
1255/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1256static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1257{
1258 ASMBreakpoint();
1259 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1260
1261 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1262
1263 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1264 /* Allocate a structure for the MOB. */
1265 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1266 AssertPtrReturnVoid(pMob);
1267
1268 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ false, pMob);
1269 if (RT_SUCCESS(rc))
1270 {
1271 return;
1272 }
1273
1274 AssertFailed();
1275
1276 RTMemFree(pMob);
1277}
1278
1279
1280/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1281static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1282{
1283// ASMBreakpoint();
1284 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1285
1286 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1287
1288 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1289 if (RT_SUCCESS(rc))
1290 {
1291 return;
1292 }
1293
1294 AssertFailed();
1295}
1296
1297
1298/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1299static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1300{
1301// ASMBreakpoint();
1302 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1303
1304 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1305 SVGAOTableSurfaceEntry entry;
1306 RT_ZERO(entry);
1307 entry.format = pCmd->format;
1308 entry.surface1Flags = pCmd->surfaceFlags;
1309 entry.numMipLevels = pCmd->numMipLevels;
1310 entry.multisampleCount = pCmd->multisampleCount;
1311 entry.autogenFilter = pCmd->autogenFilter;
1312 entry.size = pCmd->size;
1313 entry.mobid = SVGA_ID_INVALID;
1314 // entry.arraySize = 0;
1315 // entry.mobPitch = 0;
1316 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1317 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1318 if (RT_SUCCESS(rc))
1319 {
1320 /* Create the host surface. */
1321 /** @todo fGBO = true flag. */
1322 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1323 pCmd->multisampleCount, pCmd->autogenFilter,
1324 pCmd->numMipLevels, &pCmd->size);
1325 }
1326}
1327
1328
1329/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1330static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1331{
1332// ASMBreakpoint();
1333 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1334
1335 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1336 SVGAOTableSurfaceEntry entry;
1337 RT_ZERO(entry);
1338 entry.mobid = SVGA_ID_INVALID;
1339 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1340 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1341
1342 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1343}
1344
1345
1346/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1347static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1348{
1349// ASMBreakpoint();
1350 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1351
1352 /* Assign the mobid to the surface. */
1353 int rc = VINF_SUCCESS;
1354 if (pCmd->mobid != SVGA_ID_INVALID)
1355 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1356 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1357 if (RT_SUCCESS(rc))
1358 {
1359 SVGAOTableSurfaceEntry entry;
1360 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1361 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1362 if (RT_SUCCESS(rc))
1363 {
1364 entry.mobid = pCmd->mobid;
1365 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1366 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1367 if (RT_SUCCESS(rc))
1368 {
1369 /* */
1370 }
1371 }
1372 }
1373}
1374
1375
1376#ifdef DUMP_BITMAPS
1377static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1378{
1379 if (pMap->cbPixel != 4)
1380 return VERR_NOT_SUPPORTED;
1381
1382 int const w = pMap->box.w;
1383 int const h = pMap->box.h;
1384
1385 const int cbBitmap = w * h * 4;
1386
1387 FILE *f = fopen(pszFilename, "wb");
1388 if (!f)
1389 return VERR_FILE_NOT_FOUND;
1390
1391 {
1392 BMPFILEHDR fileHdr;
1393 RT_ZERO(fileHdr);
1394 fileHdr.uType = BMP_HDR_MAGIC;
1395 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1396 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1397
1398 BMPWIN3XINFOHDR coreHdr;
1399 RT_ZERO(coreHdr);
1400 coreHdr.cbSize = sizeof(coreHdr);
1401 coreHdr.uWidth = w;
1402 coreHdr.uHeight = -h;
1403 coreHdr.cPlanes = 1;
1404 coreHdr.cBits = 32;
1405 coreHdr.cbSizeImage = cbBitmap;
1406
1407 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1408 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1409 }
1410
1411 if (pMap->cbPixel == 4)
1412 {
1413 const uint8_t *s = (uint8_t *)pMap->pvData;
1414 for (int32_t y = 0; y < h; ++y)
1415 {
1416 fwrite(s, 1, w * pMap->cbPixel, f);
1417
1418 s += pMap->cbRowPitch;
1419 }
1420 }
1421
1422 fclose(f);
1423
1424 return VINF_SUCCESS;
1425}
1426
1427
1428void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1429{
1430 static int idxBitmap = 0;
1431 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1432 vmsvga3dBmpWrite(pszFilename, pMap);
1433 RTStrFree(pszFilename);
1434}
1435#endif /* DUMP_BITMAPS */
1436
1437
1438/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1439static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1440{
1441// ASMBreakpoint();
1442 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1443
1444 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1445 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1446
1447 /* "update a surface from its backing MOB." */
1448 SVGAOTableSurfaceEntry entrySurface;
1449 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1450 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1451 if (RT_SUCCESS(rc))
1452 {
1453 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1454 if (pMob)
1455 {
1456 VMSVGA3D_MAPPED_SURFACE map;
1457 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, &pCmd->image, &pCmd->box, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
1458 if (RT_SUCCESS(rc))
1459 {
1460 /* Copy MOB -> mapped surface. */
1461 uint32_t offSrc = pCmd->box.x * map.cbPixel
1462 + pCmd->box.y * entrySurface.size.width * map.cbPixel
1463 + pCmd->box.z * entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1464 uint8_t *pu8Dst = (uint8_t *)map.pvData;
1465 for (uint32_t z = 0; z < pCmd->box.d; ++z)
1466 {
1467 for (uint32_t y = 0; y < pCmd->box.h; ++y)
1468 {
1469 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offSrc, pu8Dst, pCmd->box.w * map.cbPixel);
1470 if (RT_FAILURE(rc))
1471 break;
1472
1473 pu8Dst += map.cbRowPitch;
1474 offSrc += entrySurface.size.width * map.cbPixel;
1475 }
1476
1477 pu8Dst += map.cbDepthPitch;
1478 offSrc += entrySurface.size.height * entrySurface.size.width * map.cbPixel;
1479 }
1480
1481 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1482
1483 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &pCmd->image, &map, /* fWritten = */true);
1484 }
1485 }
1486 }
1487}
1488
1489
1490/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1491static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1492{
1493// ASMBreakpoint();
1494 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1495}
1496
1497
1498/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1499static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1500{
1501// ASMBreakpoint();
1502 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1503}
1504
1505
1506/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1507static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1508{
1509 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1510
1511 /*
1512 * Create a GBO for the table.
1513 */
1514 PVMSVGAGBO pGbo;
1515 if (pCmd->type <= RT_ELEMENTS(pSvgaR3State->aGboOTables))
1516 {
1517 RT_UNTRUSTED_VALIDATED_FENCE();
1518 pGbo = &pSvgaR3State->aGboOTables[pCmd->type];
1519 }
1520 else
1521 {
1522 ASSERT_GUEST_FAILED();
1523 pGbo = NULL;
1524 }
1525
1526 if (pGbo)
1527 {
1528 /* Recreate. */
1529 vmsvgaR3GboDestroy(pSvgaR3State, pGbo);
1530 int rc = vmsvgaR3GboCreate(pSvgaR3State, pCmd->ptDepth, pCmd->baseAddress, pCmd->sizeInBytes, /*fGCPhys64=*/ true, /* fWriteProtected = */ true, pGbo);
1531 AssertRC(rc);
1532 }
1533}
1534
1535
1536/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1537static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1538{
1539// ASMBreakpoint();
1540 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1541
1542 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1543 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1544 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1545 RT_UNTRUSTED_VALIDATED_FENCE();
1546
1547 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1548 SVGAOTableScreenTargetEntry entry;
1549 RT_ZERO(entry);
1550 entry.image.sid = SVGA_ID_INVALID;
1551 // entry.image.face = 0;
1552 // entry.image.mipmap = 0;
1553 entry.width = pCmd->width;
1554 entry.height = pCmd->height;
1555 entry.xRoot = pCmd->xRoot;
1556 entry.yRoot = pCmd->yRoot;
1557 entry.flags = pCmd->flags;
1558 entry.dpi = pCmd->dpi;
1559
1560 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1561 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1562 if (RT_SUCCESS(rc))
1563 {
1564 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1565 /** @todo Generic screen object/target interface. */
1566 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1567 pScreen->fDefined = true;
1568 pScreen->fModified = true;
1569 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1570 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1571 pScreen->idScreen = pCmd->stid;
1572
1573 pScreen->xOrigin = pCmd->xRoot;
1574 pScreen->yOrigin = pCmd->yRoot;
1575 pScreen->cWidth = pCmd->width;
1576 pScreen->cHeight = pCmd->height;
1577 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1578 pScreen->cbPitch = pCmd->width * 4;
1579 pScreen->cBpp = 32;
1580
1581 if (RT_LIKELY(pThis->svga.f3DEnabled))
1582 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1583
1584 if (!pScreen->pHwScreen)
1585 {
1586 /* System memory buffer. */
1587 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1588 }
1589
1590 pThis->svga.fGFBRegisters = false;
1591 vmsvgaR3ChangeMode(pThis, pThisCC);
1592 }
1593}
1594
1595
1596/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1597static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1598{
1599// ASMBreakpoint();
1600 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1601
1602 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1603 RT_UNTRUSTED_VALIDATED_FENCE();
1604
1605 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1606 SVGAOTableScreenTargetEntry entry;
1607 RT_ZERO(entry);
1608 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1609 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1610 if (RT_SUCCESS(rc))
1611 {
1612 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1613 /** @todo Generic screen object/target interface. */
1614 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1615 pScreen->fModified = true;
1616 pScreen->fDefined = false;
1617 pScreen->idScreen = pCmd->stid;
1618
1619 if (RT_LIKELY(pThis->svga.f3DEnabled))
1620 vmsvga3dDestroyScreen(pThisCC, pScreen);
1621
1622 vmsvgaR3ChangeMode(pThis, pThisCC);
1623
1624 RTMemFree(pScreen->pvScreenBitmap);
1625 pScreen->pvScreenBitmap = NULL;
1626 }
1627}
1628
1629
1630/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1631static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1632{
1633// ASMBreakpoint();
1634 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1635
1636 /* "Binding a surface to a Screen Target the same as flipping" */
1637
1638 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1639 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1640 RT_UNTRUSTED_VALIDATED_FENCE();
1641
1642 /* Assign the surface to the screen target. */
1643 int rc = VINF_SUCCESS;
1644 if (pCmd->image.sid != SVGA_ID_INVALID)
1645 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1646 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1647 if (RT_SUCCESS(rc))
1648 {
1649 SVGAOTableScreenTargetEntry entry;
1650 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1651 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1652 if (RT_SUCCESS(rc))
1653 {
1654 entry.image = pCmd->image;
1655 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1656 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1657 if (RT_SUCCESS(rc))
1658 {
1659 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1660 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
1661 AssertRC(rc);
1662 }
1663 }
1664 }
1665}
1666
1667
1668/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
1669static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
1670{
1671// ASMBreakpoint();
1672 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1673
1674 /* Update the screen target from its backing surface. */
1675 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1676 RT_UNTRUSTED_VALIDATED_FENCE();
1677
1678 /* Get the screen target info. */
1679 SVGAOTableScreenTargetEntry entryScreenTarget;
1680 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1681 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
1682 if (RT_SUCCESS(rc))
1683 {
1684 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
1685 RT_UNTRUSTED_VALIDATED_FENCE();
1686
1687 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
1688 {
1689 SVGAOTableSurfaceEntry entrySurface;
1690 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1691 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1692 if (RT_SUCCESS(rc))
1693 {
1694 /* Copy entrySurface.mobid content to the screen target. */
1695 if (entrySurface.mobid != SVGA_ID_INVALID)
1696 {
1697 RT_UNTRUSTED_VALIDATED_FENCE();
1698 SVGA3dRect targetRect = pCmd->rect;
1699
1700 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1701 if (pScreen->pHwScreen)
1702 {
1703 /* Copy the screen target surface to the backend's screen. */
1704 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
1705 }
1706 else if (pScreen->pvScreenBitmap)
1707 {
1708 /* Copy the screen target surface to the memory buffer. */
1709 VMSVGA3D_MAPPED_SURFACE map;
1710 rc = pSvgaR3State->pFuncsMap->pfnSurfaceMap(pThisCC, &entryScreenTarget.image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
1711 if (RT_SUCCESS(rc))
1712 {
1713 uint8_t const *pu8Src = (uint8_t *)map.pvData
1714 + targetRect.x * map.cbPixel
1715 + targetRect.y * map.cbRowPitch;
1716 uint8_t *pu8Dst = (uint8_t *)pScreen->pvScreenBitmap
1717 + targetRect.x * map.cbPixel
1718 + targetRect.y * map.box.w * map.cbPixel;
1719 for (uint32_t y = 0; y < targetRect.h; ++y)
1720 {
1721 memcpy(pu8Dst, pu8Src, targetRect.w * map.cbPixel);
1722
1723 pu8Src += map.cbRowPitch;
1724 pu8Dst += map.box.w * map.cbPixel;
1725 }
1726
1727 pSvgaR3State->pFuncsMap->pfnSurfaceUnmap(pThisCC, &entryScreenTarget.image, &map, /* fWritten = */ false);
1728
1729 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->rect.x, pCmd->rect.y, pCmd->rect.w, pCmd->rect.h);
1730 }
1731 else
1732 AssertFailed();
1733 }
1734 }
1735 }
1736 }
1737 }
1738}
1739
1740
1741/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
1742static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
1743{
1744 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1745
1746 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1747 SVGAOTableSurfaceEntry entry;
1748 RT_ZERO(entry);
1749 entry.format = pCmd->format;
1750 entry.surface1Flags = pCmd->surfaceFlags;
1751 entry.numMipLevels = pCmd->numMipLevels;
1752 entry.multisampleCount = pCmd->multisampleCount;
1753 entry.autogenFilter = pCmd->autogenFilter;
1754 entry.size = pCmd->size;
1755 entry.mobid = SVGA_ID_INVALID;
1756 entry.arraySize = pCmd->arraySize;
1757 // entry.mobPitch = 0;
1758 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1759 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1760 if (RT_SUCCESS(rc))
1761 {
1762 /* Create the host surface. */
1763 /** @todo fGBO = true flag. */
1764 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1765 pCmd->multisampleCount, pCmd->autogenFilter,
1766 pCmd->numMipLevels, &pCmd->size);
1767 }
1768}
1769
1770
1771/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
1772static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
1773{
1774// ASMBreakpoint();
1775 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1776
1777 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1778
1779 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1780 /* Allocate a structure for the MOB. */
1781 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1782 AssertPtrReturnVoid(pMob);
1783
1784 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, /*fGCPhys64=*/ true, pMob);
1785 if (RT_SUCCESS(rc))
1786 {
1787 return;
1788 }
1789
1790 RTMemFree(pMob);
1791}
1792
1793
1794/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
1795static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
1796{
1797#ifdef VMSVGA3D_DX
1798//ASMBreakpoint();
1799 RT_NOREF(cbCmd);
1800
1801 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1802
1803 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1804 SVGAOTableDXContextEntry entry;
1805 RT_ZERO(entry);
1806 entry.cid = pCmd->cid;
1807 entry.mobid = SVGA_ID_INVALID;
1808 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1809 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1810 if (RT_SUCCESS(rc))
1811 {
1812 /* Create the host context. */
1813 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
1814 }
1815
1816 return rc;
1817#else
1818 RT_NOREF(pThisCC, pCmd, cbCmd);
1819 return VERR_NOT_SUPPORTED;
1820#endif
1821}
1822
1823
1824/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
1825static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
1826{
1827#ifdef VMSVGA3D_DX
1828//ASMBreakpoint();
1829 RT_NOREF(cbCmd);
1830
1831 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1832
1833 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
1834 SVGAOTableDXContextEntry entry;
1835 RT_ZERO(entry);
1836 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1837 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1838
1839 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
1840#else
1841 RT_NOREF(pThisCC, pCmd, cbCmd);
1842 return VERR_NOT_SUPPORTED;
1843#endif
1844}
1845
1846
1847/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
1848static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
1849{
1850#ifdef VMSVGA3D_DX
1851//ASMBreakpoint();
1852 RT_NOREF(cbCmd);
1853
1854 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1855
1856 /* Assign a mobid to a cid. */
1857 int rc = VINF_SUCCESS;
1858 if (pCmd->mobid != SVGA_ID_INVALID)
1859 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1860 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1861 if (RT_SUCCESS(rc))
1862 {
1863 SVGAOTableDXContextEntry entry;
1864 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1865 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1866 if (RT_SUCCESS(rc))
1867 {
1868 SVGADXContextMobFormat *pSvgaDXContext = NULL;
1869 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
1870 {
1871 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
1872 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
1873 if (pSvgaDXContext)
1874 {
1875 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
1876 if (RT_SUCCESS(rc))
1877 {
1878 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
1879 if (pMob)
1880 {
1881 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
1882 }
1883 }
1884
1885 RTMemFree(pSvgaDXContext);
1886 pSvgaDXContext = NULL;
1887 }
1888 }
1889
1890 if (pCmd->mobid != SVGA_ID_INVALID)
1891 {
1892 /* Bind a new context. Copy existing data from the guyest backing memory. */
1893 if (pCmd->validContents)
1894 {
1895 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
1896 if (pMob)
1897 {
1898 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
1899 if (pSvgaDXContext)
1900 {
1901 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
1902 if (RT_FAILURE(rc))
1903 {
1904 RTMemFree(pSvgaDXContext);
1905 pSvgaDXContext = NULL;
1906 }
1907 }
1908 }
1909 }
1910
1911 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
1912
1913 RTMemFree(pSvgaDXContext);
1914 }
1915
1916 /* Update the object table. */
1917 entry.mobid = pCmd->mobid;
1918 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
1919 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
1920 }
1921 }
1922
1923 return rc;
1924#else
1925 RT_NOREF(pThisCC, pCmd, cbCmd);
1926 return VERR_NOT_SUPPORTED;
1927#endif
1928}
1929
1930
1931/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
1932static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
1933{
1934#ifdef VMSVGA3D_DX
1935ASMBreakpoint();
1936 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1937 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
1938 return vmsvga3dDXReadbackContext(pThisCC, idDXContext);
1939#else
1940 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1941 return VERR_NOT_SUPPORTED;
1942#endif
1943}
1944
1945
1946/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
1947static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
1948{
1949#ifdef VMSVGA3D_DX
1950ASMBreakpoint();
1951 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1952 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
1953 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
1954#else
1955 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1956 return VERR_NOT_SUPPORTED;
1957#endif
1958}
1959
1960
1961/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
1962static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
1963{
1964#ifdef VMSVGA3D_DX
1965//ASMBreakpoint();
1966 RT_NOREF(cbCmd);
1967 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
1968#else
1969 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1970 return VERR_NOT_SUPPORTED;
1971#endif
1972}
1973
1974
1975/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
1976static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
1977{
1978#ifdef VMSVGA3D_DX
1979ASMBreakpoint();
1980 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1981 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
1982 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext);
1983#else
1984 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1985 return VERR_NOT_SUPPORTED;
1986#endif
1987}
1988
1989
1990/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
1991static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
1992{
1993#ifdef VMSVGA3D_DX
1994//ASMBreakpoint();
1995 RT_NOREF(cbCmd);
1996 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
1997#else
1998 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
1999 return VERR_NOT_SUPPORTED;
2000#endif
2001}
2002
2003
2004/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2005static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2006{
2007#ifdef VMSVGA3D_DX
2008//ASMBreakpoint();
2009 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2010 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2011 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd->startSampler, pCmd->type, cSamplerId, paSamplerId);
2012#else
2013 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2014 return VERR_NOT_SUPPORTED;
2015#endif
2016}
2017
2018
2019/* SVGA_3D_CMD_DX_DRAW 1152 */
2020static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2021{
2022#ifdef VMSVGA3D_DX
2023//ASMBreakpoint();
2024 RT_NOREF(cbCmd);
2025 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2026#else
2027 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2028 return VERR_NOT_SUPPORTED;
2029#endif
2030}
2031
2032
2033/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2034static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2035{
2036#ifdef VMSVGA3D_DX
2037ASMBreakpoint();
2038 RT_NOREF(cbCmd);
2039 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2040#else
2041 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2042 return VERR_NOT_SUPPORTED;
2043#endif
2044}
2045
2046
2047/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2048static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2049{
2050#ifdef VMSVGA3D_DX
2051ASMBreakpoint();
2052 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2053 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2054 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext);
2055#else
2056 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2057 return VERR_NOT_SUPPORTED;
2058#endif
2059}
2060
2061
2062/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2063static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2064{
2065#ifdef VMSVGA3D_DX
2066ASMBreakpoint();
2067 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2068 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2069 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext);
2070#else
2071 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2072 return VERR_NOT_SUPPORTED;
2073#endif
2074}
2075
2076
2077/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2078static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2079{
2080#ifdef VMSVGA3D_DX
2081ASMBreakpoint();
2082 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2083 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2084 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2085#else
2086 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2087 return VERR_NOT_SUPPORTED;
2088#endif
2089}
2090
2091
2092/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2093static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2094{
2095#ifdef VMSVGA3D_DX
2096//ASMBreakpoint();
2097 RT_NOREF(cbCmd);
2098 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2099#else
2100 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2101 return VERR_NOT_SUPPORTED;
2102#endif
2103}
2104
2105
2106/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2107static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2108{
2109#ifdef VMSVGA3D_DX
2110//ASMBreakpoint();
2111 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2112 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2113 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2114#else
2115 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2116 return VERR_NOT_SUPPORTED;
2117#endif
2118}
2119
2120
2121/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2122static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2123{
2124#ifdef VMSVGA3D_DX
2125//ASMBreakpoint();
2126 RT_NOREF(cbCmd);
2127 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2128#else
2129 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2130 return VERR_NOT_SUPPORTED;
2131#endif
2132}
2133
2134
2135/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2136static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2137{
2138#ifdef VMSVGA3D_DX
2139//ASMBreakpoint();
2140 RT_NOREF(cbCmd);
2141 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2142#else
2143 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2144 return VERR_NOT_SUPPORTED;
2145#endif
2146}
2147
2148
2149/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2150static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2151{
2152#ifdef VMSVGA3D_DX
2153//ASMBreakpoint();
2154 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2155 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2156 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2157#else
2158 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2159 return VERR_NOT_SUPPORTED;
2160#endif
2161}
2162
2163
2164/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2165static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2166{
2167#ifdef VMSVGA3D_DX
2168//ASMBreakpoint();
2169 RT_NOREF(cbCmd);
2170 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2171#else
2172 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2173 return VERR_NOT_SUPPORTED;
2174#endif
2175}
2176
2177
2178/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2179static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2180{
2181#ifdef VMSVGA3D_DX
2182//ASMBreakpoint();
2183 RT_NOREF(cbCmd);
2184 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2185#else
2186 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2187 return VERR_NOT_SUPPORTED;
2188#endif
2189}
2190
2191
2192/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2193static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2194{
2195#ifdef VMSVGA3D_DX
2196//ASMBreakpoint();
2197 RT_NOREF(cbCmd);
2198 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2199#else
2200 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2201 return VERR_NOT_SUPPORTED;
2202#endif
2203}
2204
2205
2206/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2207static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2208{
2209#ifdef VMSVGA3D_DX
2210ASMBreakpoint();
2211 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2212 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2213 return vmsvga3dDXDefineQuery(pThisCC, idDXContext);
2214#else
2215 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2216 return VERR_NOT_SUPPORTED;
2217#endif
2218}
2219
2220
2221/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2222static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2223{
2224#ifdef VMSVGA3D_DX
2225ASMBreakpoint();
2226 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2227 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2228 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext);
2229#else
2230 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2231 return VERR_NOT_SUPPORTED;
2232#endif
2233}
2234
2235
2236/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2237static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2238{
2239#ifdef VMSVGA3D_DX
2240ASMBreakpoint();
2241 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2242 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2243 return vmsvga3dDXBindQuery(pThisCC, idDXContext);
2244#else
2245 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2246 return VERR_NOT_SUPPORTED;
2247#endif
2248}
2249
2250
2251/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2252static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2253{
2254#ifdef VMSVGA3D_DX
2255ASMBreakpoint();
2256 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2257 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2258 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext);
2259#else
2260 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2261 return VERR_NOT_SUPPORTED;
2262#endif
2263}
2264
2265
2266/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2267static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2268{
2269#ifdef VMSVGA3D_DX
2270ASMBreakpoint();
2271 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2272 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2273 return vmsvga3dDXBeginQuery(pThisCC, idDXContext);
2274#else
2275 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2276 return VERR_NOT_SUPPORTED;
2277#endif
2278}
2279
2280
2281/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2282static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2283{
2284#ifdef VMSVGA3D_DX
2285ASMBreakpoint();
2286 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2287 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2288 return vmsvga3dDXEndQuery(pThisCC, idDXContext);
2289#else
2290 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2291 return VERR_NOT_SUPPORTED;
2292#endif
2293}
2294
2295
2296/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2297static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2298{
2299#ifdef VMSVGA3D_DX
2300ASMBreakpoint();
2301 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2302 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2303 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext);
2304#else
2305 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2306 return VERR_NOT_SUPPORTED;
2307#endif
2308}
2309
2310
2311/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2312static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2313{
2314#ifdef VMSVGA3D_DX
2315ASMBreakpoint();
2316 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2317 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2318 return vmsvga3dDXSetPredication(pThisCC, idDXContext);
2319#else
2320 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2321 return VERR_NOT_SUPPORTED;
2322#endif
2323}
2324
2325
2326/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2327static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2328{
2329#ifdef VMSVGA3D_DX
2330ASMBreakpoint();
2331 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2332 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2333 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext);
2334#else
2335 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2336 return VERR_NOT_SUPPORTED;
2337#endif
2338}
2339
2340
2341/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2342static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2343{
2344#ifdef VMSVGA3D_DX
2345//ASMBreakpoint();
2346 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2347 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2348 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2349#else
2350 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2351 return VERR_NOT_SUPPORTED;
2352#endif
2353}
2354
2355
2356/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2357static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2358{
2359#ifdef VMSVGA3D_DX
2360//ASMBreakpoint();
2361 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2362 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2363 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2364#else
2365 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2366 return VERR_NOT_SUPPORTED;
2367#endif
2368}
2369
2370
2371/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2372static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2373{
2374#ifdef VMSVGA3D_DX
2375ASMBreakpoint();
2376 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2377 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2378 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext);
2379#else
2380 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2381 return VERR_NOT_SUPPORTED;
2382#endif
2383}
2384
2385
2386/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2387static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2388{
2389#ifdef VMSVGA3D_DX
2390ASMBreakpoint();
2391 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2392 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2393 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext);
2394#else
2395 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2396 return VERR_NOT_SUPPORTED;
2397#endif
2398}
2399
2400
2401/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2402static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2403{
2404#ifdef VMSVGA3D_DX
2405ASMBreakpoint();
2406 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2407 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2408 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext);
2409#else
2410 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2411 return VERR_NOT_SUPPORTED;
2412#endif
2413}
2414
2415
2416/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2417static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2418{
2419#ifdef VMSVGA3D_DX
2420ASMBreakpoint();
2421 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2422 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2423 return vmsvga3dDXPredCopy(pThisCC, idDXContext);
2424#else
2425 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2426 return VERR_NOT_SUPPORTED;
2427#endif
2428}
2429
2430
2431/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2432static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2433{
2434#ifdef VMSVGA3D_DX
2435ASMBreakpoint();
2436 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2437 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2438 return vmsvga3dDXPresentBlt(pThisCC, idDXContext);
2439#else
2440 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2441 return VERR_NOT_SUPPORTED;
2442#endif
2443}
2444
2445
2446/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2447static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2448{
2449#ifdef VMSVGA3D_DX
2450ASMBreakpoint();
2451 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2452 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2453 return vmsvga3dDXGenMips(pThisCC, idDXContext);
2454#else
2455 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2456 return VERR_NOT_SUPPORTED;
2457#endif
2458}
2459
2460
2461/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2462static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2463{
2464#ifdef VMSVGA3D_DX
2465ASMBreakpoint();
2466 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2467 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2468 return vmsvga3dDXUpdateSubResource(pThisCC, idDXContext);
2469#else
2470 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2471 return VERR_NOT_SUPPORTED;
2472#endif
2473}
2474
2475
2476/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2477static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2478{
2479#ifdef VMSVGA3D_DX
2480ASMBreakpoint();
2481 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2482 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2483 return vmsvga3dDXReadbackSubResource(pThisCC, idDXContext);
2484#else
2485 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2486 return VERR_NOT_SUPPORTED;
2487#endif
2488}
2489
2490
2491/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2492static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2493{
2494#ifdef VMSVGA3D_DX
2495ASMBreakpoint();
2496 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2497 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2498 return vmsvga3dDXInvalidateSubResource(pThisCC, idDXContext);
2499#else
2500 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2501 return VERR_NOT_SUPPORTED;
2502#endif
2503}
2504
2505
2506/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2507static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2508{
2509#ifdef VMSVGA3D_DX
2510ASMBreakpoint();
2511 RT_NOREF(cbCmd);
2512 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2513#else
2514 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2515 return VERR_NOT_SUPPORTED;
2516#endif
2517}
2518
2519
2520/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2521static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2522{
2523#ifdef VMSVGA3D_DX
2524ASMBreakpoint();
2525 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2526 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2527 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext);
2528#else
2529 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2530 return VERR_NOT_SUPPORTED;
2531#endif
2532}
2533
2534
2535/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2536static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2537{
2538#ifdef VMSVGA3D_DX
2539//ASMBreakpoint();
2540 RT_NOREF(cbCmd);
2541 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2542#else
2543 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2544 return VERR_NOT_SUPPORTED;
2545#endif
2546}
2547
2548
2549/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2550static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2551{
2552#ifdef VMSVGA3D_DX
2553ASMBreakpoint();
2554 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2555 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2556 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext);
2557#else
2558 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2559 return VERR_NOT_SUPPORTED;
2560#endif
2561}
2562
2563
2564/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2565static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2566{
2567#ifdef VMSVGA3D_DX
2568ASMBreakpoint();
2569 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2570 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2571 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext);
2572#else
2573 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2574 return VERR_NOT_SUPPORTED;
2575#endif
2576}
2577
2578
2579/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
2580static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
2581{
2582#ifdef VMSVGA3D_DX
2583ASMBreakpoint();
2584 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2585 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2586 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext);
2587#else
2588 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2589 return VERR_NOT_SUPPORTED;
2590#endif
2591}
2592
2593
2594/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
2595static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
2596{
2597#ifdef VMSVGA3D_DX
2598//ASMBreakpoint();
2599 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
2600 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
2601 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
2602#else
2603 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2604 return VERR_NOT_SUPPORTED;
2605#endif
2606}
2607
2608
2609/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
2610static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
2611{
2612#ifdef VMSVGA3D_DX
2613ASMBreakpoint();
2614 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2615 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2616 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext);
2617#else
2618 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2619 return VERR_NOT_SUPPORTED;
2620#endif
2621}
2622
2623
2624/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
2625static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
2626{
2627#ifdef VMSVGA3D_DX
2628//ASMBreakpoint();
2629 RT_NOREF(cbCmd);
2630 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
2631#else
2632 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2633 return VERR_NOT_SUPPORTED;
2634#endif
2635}
2636
2637
2638/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
2639static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
2640{
2641#ifdef VMSVGA3D_DX
2642ASMBreakpoint();
2643 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2644 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2645 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext);
2646#else
2647 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2648 return VERR_NOT_SUPPORTED;
2649#endif
2650}
2651
2652
2653/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
2654static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
2655{
2656#ifdef VMSVGA3D_DX
2657//ASMBreakpoint();
2658 RT_NOREF(cbCmd);
2659 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
2660#else
2661 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2662 return VERR_NOT_SUPPORTED;
2663#endif
2664}
2665
2666
2667/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
2668static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
2669{
2670#ifdef VMSVGA3D_DX
2671ASMBreakpoint();
2672 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2673 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2674 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext);
2675#else
2676 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2677 return VERR_NOT_SUPPORTED;
2678#endif
2679}
2680
2681
2682/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
2683static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
2684{
2685#ifdef VMSVGA3D_DX
2686//ASMBreakpoint();
2687 RT_NOREF(cbCmd);
2688 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
2689#else
2690 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2691 return VERR_NOT_SUPPORTED;
2692#endif
2693}
2694
2695
2696/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
2697static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
2698{
2699#ifdef VMSVGA3D_DX
2700ASMBreakpoint();
2701 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2702 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2703 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext);
2704#else
2705 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2706 return VERR_NOT_SUPPORTED;
2707#endif
2708}
2709
2710
2711/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
2712static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
2713{
2714#ifdef VMSVGA3D_DX
2715//ASMBreakpoint();
2716 RT_NOREF(cbCmd);
2717 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
2718#else
2719 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2720 return VERR_NOT_SUPPORTED;
2721#endif
2722}
2723
2724
2725/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
2726static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
2727{
2728#ifdef VMSVGA3D_DX
2729ASMBreakpoint();
2730 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2731 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2732 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext);
2733#else
2734 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2735 return VERR_NOT_SUPPORTED;
2736#endif
2737}
2738
2739
2740/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
2741static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
2742{
2743#ifdef VMSVGA3D_DX
2744//ASMBreakpoint();
2745 RT_NOREF(cbCmd);
2746 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
2747#else
2748 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2749 return VERR_NOT_SUPPORTED;
2750#endif
2751}
2752
2753
2754/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
2755static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
2756{
2757#ifdef VMSVGA3D_DX
2758ASMBreakpoint();
2759 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2760 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2761 return vmsvga3dDXDestroyShader(pThisCC, idDXContext);
2762#else
2763 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2764 return VERR_NOT_SUPPORTED;
2765#endif
2766}
2767
2768
2769/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
2770static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
2771{
2772#ifdef VMSVGA3D_DX
2773//ASMBreakpoint();
2774 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2775 RT_NOREF(cbCmd);
2776 ASSERT_GUEST_LOGREL_MSG(idDXContext == pCmd->cid, ("idDXContext = %u, pCmd->cid = %u\n", idDXContext, pCmd->cid));
2777 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2778 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2779 return vmsvga3dDXBindShader(pThisCC, pCmd->cid, pMob, pCmd->shid, pCmd->offsetInBytes);
2780#else
2781 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2782 return VERR_NOT_SUPPORTED;
2783#endif
2784}
2785
2786
2787/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
2788static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
2789{
2790#ifdef VMSVGA3D_DX
2791ASMBreakpoint();
2792 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2793 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2794 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext);
2795#else
2796 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2797 return VERR_NOT_SUPPORTED;
2798#endif
2799}
2800
2801
2802/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
2803static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
2804{
2805#ifdef VMSVGA3D_DX
2806ASMBreakpoint();
2807 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2808 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2809 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext);
2810#else
2811 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2812 return VERR_NOT_SUPPORTED;
2813#endif
2814}
2815
2816
2817/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
2818static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
2819{
2820#ifdef VMSVGA3D_DX
2821ASMBreakpoint();
2822 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2823 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2824 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext);
2825#else
2826 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2827 return VERR_NOT_SUPPORTED;
2828#endif
2829}
2830
2831
2832/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
2833static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
2834{
2835#ifdef VMSVGA3D_DX
2836//ASMBreakpoint();
2837 RT_NOREF(cbCmd);
2838 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2839 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2840 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2841 return vmsvga3dDXSetCOTable(pThisCC, pCmd->cid, pMob, pCmd->type, pCmd->validSizeInBytes);
2842#else
2843 RT_NOREF(pThisCC, pCmd, cbCmd);
2844 return VERR_NOT_SUPPORTED;
2845#endif
2846}
2847
2848
2849/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
2850static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
2851{
2852#ifdef VMSVGA3D_DX
2853ASMBreakpoint();
2854 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2855 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2856 return vmsvga3dDXReadbackCOTable(pThisCC, idDXContext);
2857#else
2858 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2859 return VERR_NOT_SUPPORTED;
2860#endif
2861}
2862
2863
2864/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
2865static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
2866{
2867#ifdef VMSVGA3D_DX
2868ASMBreakpoint();
2869 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2870 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2871 return vmsvga3dDXBufferCopy(pThisCC, idDXContext);
2872#else
2873 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2874 return VERR_NOT_SUPPORTED;
2875#endif
2876}
2877
2878
2879/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
2880static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
2881{
2882#ifdef VMSVGA3D_DX
2883ASMBreakpoint();
2884 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2885 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2886 return vmsvga3dDXTransferFromBuffer(pThisCC, idDXContext);
2887#else
2888 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2889 return VERR_NOT_SUPPORTED;
2890#endif
2891}
2892
2893
2894/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
2895static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
2896{
2897#ifdef VMSVGA3D_DX
2898ASMBreakpoint();
2899 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2900 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2901 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
2902#else
2903 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2904 return VERR_NOT_SUPPORTED;
2905#endif
2906}
2907
2908
2909/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
2910static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
2911{
2912#ifdef VMSVGA3D_DX
2913ASMBreakpoint();
2914 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2915 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2916 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
2917#else
2918 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2919 return VERR_NOT_SUPPORTED;
2920#endif
2921}
2922
2923
2924/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
2925static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
2926{
2927#ifdef VMSVGA3D_DX
2928ASMBreakpoint();
2929 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2930 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2931 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext);
2932#else
2933 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2934 return VERR_NOT_SUPPORTED;
2935#endif
2936}
2937
2938
2939/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
2940static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
2941{
2942#ifdef VMSVGA3D_DX
2943ASMBreakpoint();
2944 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2945 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2946 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext);
2947#else
2948 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2949 return VERR_NOT_SUPPORTED;
2950#endif
2951}
2952
2953
2954/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
2955static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
2956{
2957#ifdef VMSVGA3D_DX
2958ASMBreakpoint();
2959 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2960 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2961 return vmsvga3dDXPredTransferFromBuffer(pThisCC, idDXContext);
2962#else
2963 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2964 return VERR_NOT_SUPPORTED;
2965#endif
2966}
2967
2968
2969/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
2970static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
2971{
2972#ifdef VMSVGA3D_DX
2973ASMBreakpoint();
2974 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2975 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2976 return vmsvga3dDXMobFence64(pThisCC, idDXContext);
2977#else
2978 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2979 return VERR_NOT_SUPPORTED;
2980#endif
2981}
2982
2983
2984/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
2985static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
2986{
2987#ifdef VMSVGA3D_DX
2988ASMBreakpoint();
2989 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2990 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2991 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
2992#else
2993 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2994 return VERR_NOT_SUPPORTED;
2995#endif
2996}
2997
2998
2999/* SVGA_3D_CMD_DX_HINT 1218 */
3000static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3001{
3002#ifdef VMSVGA3D_DX
3003ASMBreakpoint();
3004 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3005 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3006 return vmsvga3dDXHint(pThisCC, idDXContext);
3007#else
3008 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3009 return VERR_NOT_SUPPORTED;
3010#endif
3011}
3012
3013
3014/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3015static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3016{
3017#ifdef VMSVGA3D_DX
3018ASMBreakpoint();
3019 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3020 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3021 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3022#else
3023 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3024 return VERR_NOT_SUPPORTED;
3025#endif
3026}
3027
3028
3029/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3030static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3031{
3032#ifdef VMSVGA3D_DX
3033ASMBreakpoint();
3034 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3035 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3036 return vmsvga3dDXSetVSConstantBufferOffset(pThisCC, idDXContext);
3037#else
3038 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3039 return VERR_NOT_SUPPORTED;
3040#endif
3041}
3042
3043
3044/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3045static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3046{
3047#ifdef VMSVGA3D_DX
3048ASMBreakpoint();
3049 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3050 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3051 return vmsvga3dDXSetPSConstantBufferOffset(pThisCC, idDXContext);
3052#else
3053 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3054 return VERR_NOT_SUPPORTED;
3055#endif
3056}
3057
3058
3059/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3060static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3061{
3062#ifdef VMSVGA3D_DX
3063ASMBreakpoint();
3064 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3065 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3066 return vmsvga3dDXSetGSConstantBufferOffset(pThisCC, idDXContext);
3067#else
3068 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3069 return VERR_NOT_SUPPORTED;
3070#endif
3071}
3072
3073
3074/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3075static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3076{
3077#ifdef VMSVGA3D_DX
3078ASMBreakpoint();
3079 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3080 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3081 return vmsvga3dDXSetHSConstantBufferOffset(pThisCC, idDXContext);
3082#else
3083 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3084 return VERR_NOT_SUPPORTED;
3085#endif
3086}
3087
3088
3089/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3090static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3091{
3092#ifdef VMSVGA3D_DX
3093ASMBreakpoint();
3094 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3095 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3096 return vmsvga3dDXSetDSConstantBufferOffset(pThisCC, idDXContext);
3097#else
3098 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3099 return VERR_NOT_SUPPORTED;
3100#endif
3101}
3102
3103
3104/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3105static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3106{
3107#ifdef VMSVGA3D_DX
3108ASMBreakpoint();
3109 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3110 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3111 return vmsvga3dDXSetCSConstantBufferOffset(pThisCC, idDXContext);
3112#else
3113 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3114 return VERR_NOT_SUPPORTED;
3115#endif
3116}
3117
3118
3119/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3120static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3121{
3122#ifdef VMSVGA3D_DX
3123ASMBreakpoint();
3124 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3125 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3126 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3127#else
3128 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3129 return VERR_NOT_SUPPORTED;
3130#endif
3131}
3132
3133
3134/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3135static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3136{
3137#ifdef VMSVGA3D_DX
3138ASMBreakpoint();
3139 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3140 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3141 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3142#else
3143 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3144 return VERR_NOT_SUPPORTED;
3145#endif
3146}
3147
3148
3149/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3150static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3151{
3152#ifdef VMSVGA3D_DX
3153ASMBreakpoint();
3154 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3155 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3156 return vmsvga3dGrowOTable(pThisCC, idDXContext);
3157#else
3158 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3159 return VERR_NOT_SUPPORTED;
3160#endif
3161}
3162
3163
3164/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3165static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3166{
3167#ifdef VMSVGA3D_DX
3168ASMBreakpoint();
3169 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3170 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3171 return vmsvga3dDXGrowCOTable(pThisCC, idDXContext);
3172#else
3173 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3174 return VERR_NOT_SUPPORTED;
3175#endif
3176}
3177
3178
3179/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3180static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3181{
3182#ifdef VMSVGA3D_DX
3183ASMBreakpoint();
3184 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3185 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3186 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext);
3187#else
3188 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3189 return VERR_NOT_SUPPORTED;
3190#endif
3191}
3192
3193
3194/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3195static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v3 const *pCmd, uint32_t cbCmd)
3196{
3197#ifdef VMSVGA3D_DX
3198ASMBreakpoint();
3199 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3200 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3201 return vmsvga3dDefineGBSurface_v3(pThisCC, idDXContext);
3202#else
3203 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3204 return VERR_NOT_SUPPORTED;
3205#endif
3206}
3207
3208
3209/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3210static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3211{
3212#ifdef VMSVGA3D_DX
3213ASMBreakpoint();
3214 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3215 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3216 return vmsvga3dDXResolveCopy(pThisCC, idDXContext);
3217#else
3218 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3219 return VERR_NOT_SUPPORTED;
3220#endif
3221}
3222
3223
3224/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3225static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3226{
3227#ifdef VMSVGA3D_DX
3228ASMBreakpoint();
3229 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3230 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3231 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3232#else
3233 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3234 return VERR_NOT_SUPPORTED;
3235#endif
3236}
3237
3238
3239/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3240static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3241{
3242#ifdef VMSVGA3D_DX
3243ASMBreakpoint();
3244 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3245 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3246 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3247#else
3248 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3249 return VERR_NOT_SUPPORTED;
3250#endif
3251}
3252
3253
3254/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3255static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3256{
3257#ifdef VMSVGA3D_DX
3258ASMBreakpoint();
3259 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3260 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3261 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3262#else
3263 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3264 return VERR_NOT_SUPPORTED;
3265#endif
3266}
3267
3268
3269/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3270static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3271{
3272#ifdef VMSVGA3D_DX
3273ASMBreakpoint();
3274 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3275 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3276 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3277#else
3278 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3279 return VERR_NOT_SUPPORTED;
3280#endif
3281}
3282
3283
3284/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3285static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3286{
3287#ifdef VMSVGA3D_DX
3288ASMBreakpoint();
3289 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3290 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3291 return vmsvga3dDXDefineUAView(pThisCC, idDXContext);
3292#else
3293 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3294 return VERR_NOT_SUPPORTED;
3295#endif
3296}
3297
3298
3299/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3300static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3301{
3302#ifdef VMSVGA3D_DX
3303ASMBreakpoint();
3304 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3305 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3306 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext);
3307#else
3308 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3309 return VERR_NOT_SUPPORTED;
3310#endif
3311}
3312
3313
3314/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3315static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3316{
3317#ifdef VMSVGA3D_DX
3318ASMBreakpoint();
3319 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3320 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3321 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext);
3322#else
3323 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3324 return VERR_NOT_SUPPORTED;
3325#endif
3326}
3327
3328
3329/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3330static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3331{
3332#ifdef VMSVGA3D_DX
3333ASMBreakpoint();
3334 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3335 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3336 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext);
3337#else
3338 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3339 return VERR_NOT_SUPPORTED;
3340#endif
3341}
3342
3343
3344/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3345static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3346{
3347#ifdef VMSVGA3D_DX
3348ASMBreakpoint();
3349 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3350 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3351 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext);
3352#else
3353 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3354 return VERR_NOT_SUPPORTED;
3355#endif
3356}
3357
3358
3359/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3360static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3361{
3362#ifdef VMSVGA3D_DX
3363ASMBreakpoint();
3364 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3365 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3366 return vmsvga3dDXSetUAViews(pThisCC, idDXContext);
3367#else
3368 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3369 return VERR_NOT_SUPPORTED;
3370#endif
3371}
3372
3373
3374/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3375static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3376{
3377#ifdef VMSVGA3D_DX
3378ASMBreakpoint();
3379 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3380 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3381 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext);
3382#else
3383 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3384 return VERR_NOT_SUPPORTED;
3385#endif
3386}
3387
3388
3389/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3390static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3391{
3392#ifdef VMSVGA3D_DX
3393ASMBreakpoint();
3394 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3395 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3396 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext);
3397#else
3398 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3399 return VERR_NOT_SUPPORTED;
3400#endif
3401}
3402
3403
3404/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3405static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3406{
3407#ifdef VMSVGA3D_DX
3408ASMBreakpoint();
3409 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3410 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3411 return vmsvga3dDXDispatch(pThisCC, idDXContext);
3412#else
3413 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3414 return VERR_NOT_SUPPORTED;
3415#endif
3416}
3417
3418
3419/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3420static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3421{
3422#ifdef VMSVGA3D_DX
3423ASMBreakpoint();
3424 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3425 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3426 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
3427#else
3428 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3429 return VERR_NOT_SUPPORTED;
3430#endif
3431}
3432
3433
3434/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
3435static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
3436{
3437#ifdef VMSVGA3D_DX
3438ASMBreakpoint();
3439 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3440 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3441 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
3442#else
3443 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3444 return VERR_NOT_SUPPORTED;
3445#endif
3446}
3447
3448
3449/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
3450static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
3451{
3452#ifdef VMSVGA3D_DX
3453ASMBreakpoint();
3454 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3455 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3456 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
3457#else
3458 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3459 return VERR_NOT_SUPPORTED;
3460#endif
3461}
3462
3463
3464/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
3465static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
3466{
3467#ifdef VMSVGA3D_DX
3468ASMBreakpoint();
3469 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3470 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3471 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
3472#else
3473 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3474 return VERR_NOT_SUPPORTED;
3475#endif
3476}
3477
3478
3479/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
3480static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
3481{
3482#ifdef VMSVGA3D_DX
3483ASMBreakpoint();
3484 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3485 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3486 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext);
3487#else
3488 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3489 return VERR_NOT_SUPPORTED;
3490#endif
3491}
3492
3493
3494/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
3495static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
3496{
3497#ifdef VMSVGA3D_DX
3498ASMBreakpoint();
3499 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3500 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3501 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
3502#else
3503 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3504 return VERR_NOT_SUPPORTED;
3505#endif
3506}
3507
3508
3509/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
3510static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
3511{
3512#ifdef VMSVGA3D_DX
3513ASMBreakpoint();
3514 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3515 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3516 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
3517#else
3518 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3519 return VERR_NOT_SUPPORTED;
3520#endif
3521}
3522
3523
3524/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
3525static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
3526{
3527#ifdef VMSVGA3D_DX
3528ASMBreakpoint();
3529 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3530 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3531 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
3532#else
3533 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3534 return VERR_NOT_SUPPORTED;
3535#endif
3536}
3537
3538
3539/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
3540static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
3541{
3542#ifdef VMSVGA3D_DX
3543ASMBreakpoint();
3544 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3545 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3546 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
3547#else
3548 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3549 return VERR_NOT_SUPPORTED;
3550#endif
3551}
3552
3553
3554/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
3555static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
3556{
3557#ifdef VMSVGA3D_DX
3558ASMBreakpoint();
3559 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3560 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3561 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
3562#else
3563 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3564 return VERR_NOT_SUPPORTED;
3565#endif
3566}
3567
3568
3569/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
3570static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
3571{
3572#ifdef VMSVGA3D_DX
3573ASMBreakpoint();
3574 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3575 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3576 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
3577#else
3578 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3579 return VERR_NOT_SUPPORTED;
3580#endif
3581}
3582
3583
3584/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
3585static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDefineGBSurface_v4 const *pCmd, uint32_t cbCmd)
3586{
3587#ifdef VMSVGA3D_DX
3588ASMBreakpoint();
3589 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3590 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3591 return vmsvga3dDefineGBSurface_v4(pThisCC, idDXContext);
3592#else
3593 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3594 return VERR_NOT_SUPPORTED;
3595#endif
3596}
3597
3598
3599/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
3600static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
3601{
3602#ifdef VMSVGA3D_DX
3603ASMBreakpoint();
3604 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3605 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3606 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext);
3607#else
3608 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3609 return VERR_NOT_SUPPORTED;
3610#endif
3611}
3612
3613
3614/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
3615static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
3616{
3617#ifdef VMSVGA3D_DX
3618ASMBreakpoint();
3619 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3620 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3621 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
3622#else
3623 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3624 return VERR_NOT_SUPPORTED;
3625#endif
3626}
3627
3628
3629/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
3630static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
3631{
3632#ifdef VMSVGA3D_DX
3633ASMBreakpoint();
3634 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3635 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3636 return vmsvga3dDXDefineDepthStencilView_v2(pThisCC, idDXContext);
3637#else
3638 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3639 return VERR_NOT_SUPPORTED;
3640#endif
3641}
3642
3643
3644/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
3645static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
3646{
3647#ifdef VMSVGA3D_DX
3648ASMBreakpoint();
3649 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3650 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3651 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext);
3652#else
3653 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3654 return VERR_NOT_SUPPORTED;
3655#endif
3656}
3657
3658
3659/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
3660static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
3661{
3662#ifdef VMSVGA3D_DX
3663ASMBreakpoint();
3664 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3665 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3666 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
3667#else
3668 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3669 return VERR_NOT_SUPPORTED;
3670#endif
3671}
3672
3673
3674/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
3675static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
3676{
3677#ifdef VMSVGA3D_DX
3678ASMBreakpoint();
3679 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3680 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3681 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext);
3682#else
3683 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3684 return VERR_NOT_SUPPORTED;
3685#endif
3686}
3687
3688
3689/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
3690static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
3691{
3692#ifdef VMSVGA3D_DX
3693ASMBreakpoint();
3694 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3695 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3696 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
3697#else
3698 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3699 return VERR_NOT_SUPPORTED;
3700#endif
3701}
3702
3703
3704/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
3705static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
3706{
3707#ifdef VMSVGA3D_DX
3708ASMBreakpoint();
3709 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3710 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3711 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
3712#else
3713 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3714 return VERR_NOT_SUPPORTED;
3715#endif
3716}
3717
3718
3719/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
3720 * Check that the 3D command has at least a_cbMin of payload bytes after the
3721 * header. Will break out of the switch if it doesn't.
3722 */
3723# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3724 if (1) { \
3725 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
3726 RT_UNTRUSTED_VALIDATED_FENCE(); \
3727 } else do {} while (0)
3728
3729# define VMSVGA_3D_CMD_NOTIMPL() \
3730 if (1) { \
3731 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
3732 } else do {} while (0)
3733
3734/** SVGA_3D_CMD_* handler.
3735 * This function parses the command and calls the corresponding command handler.
3736 *
3737 * @param pThis The shared VGA/VMSVGA state.
3738 * @param pThisCC The VGA/VMSVGA state for the current context.
3739 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3740 * @param enmCmdId SVGA_3D_CMD_* command identifier.
3741 * @param cbCmd Size of the command in bytes.
3742 * @param pvCmd Pointer to the command.
3743 * @returns VBox status code if an error was detected parsing a command.
3744 */
3745int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
3746{
3747 if (enmCmdId > SVGA_3D_CMD_MAX)
3748 {
3749 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
3750 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_IMPLEMENTED);
3751 }
3752
3753 int rcParse = VINF_SUCCESS;
3754 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
3755
3756 switch (enmCmdId)
3757 {
3758 case SVGA_3D_CMD_SURFACE_DEFINE:
3759 {
3760 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
3761 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3762 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
3763
3764 SVGA3dCmdDefineSurface_v2 cmd;
3765 cmd.sid = pCmd->sid;
3766 cmd.surfaceFlags = pCmd->surfaceFlags;
3767 cmd.format = pCmd->format;
3768 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
3769 cmd.multisampleCount = 0;
3770 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
3771
3772 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3773 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3774# ifdef DEBUG_GMR_ACCESS
3775 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3776# endif
3777 break;
3778 }
3779
3780 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3781 {
3782 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
3783 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3784 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
3785
3786 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3787 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
3788# ifdef DEBUG_GMR_ACCESS
3789 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
3790# endif
3791 break;
3792 }
3793
3794 case SVGA_3D_CMD_SURFACE_DESTROY:
3795 {
3796 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
3797 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3798 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
3799
3800 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
3801 break;
3802 }
3803
3804 case SVGA_3D_CMD_SURFACE_COPY:
3805 {
3806 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
3807 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3808 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
3809
3810 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3811 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3812 break;
3813 }
3814
3815 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3816 {
3817 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
3818 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3819 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
3820
3821 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
3822 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3823 break;
3824 }
3825
3826 case SVGA_3D_CMD_SURFACE_DMA:
3827 {
3828 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
3829 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3830 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
3831
3832 uint64_t u64NanoTS = 0;
3833 if (LogRelIs3Enabled())
3834 u64NanoTS = RTTimeNanoTS();
3835 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3836 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3837 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
3838 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3839 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
3840 if (LogRelIs3Enabled())
3841 {
3842 if (cCopyBoxes)
3843 {
3844 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
3845 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
3846 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
3847 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
3848 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
3849 }
3850 }
3851 break;
3852 }
3853
3854 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3855 {
3856 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
3857 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3858 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
3859
3860 static uint64_t u64FrameStartNanoTS = 0;
3861 static uint64_t u64ElapsedPerSecNano = 0;
3862 static int cFrames = 0;
3863 uint64_t u64NanoTS = 0;
3864 if (LogRelIs3Enabled())
3865 u64NanoTS = RTTimeNanoTS();
3866 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3867 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3868 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
3869 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3870 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
3871 if (LogRelIs3Enabled())
3872 {
3873 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
3874 u64ElapsedPerSecNano += u64ElapsedNano;
3875
3876 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
3877 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
3878 (u64ElapsedNano) / 1000ULL, cRects,
3879 pFirstRect->left, pFirstRect->top,
3880 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
3881
3882 ++cFrames;
3883 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
3884 {
3885 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
3886 cFrames, u64ElapsedPerSecNano / 1000ULL));
3887 u64FrameStartNanoTS = u64NanoTS;
3888 cFrames = 0;
3889 u64ElapsedPerSecNano = 0;
3890 }
3891 }
3892 break;
3893 }
3894
3895 case SVGA_3D_CMD_CONTEXT_DEFINE:
3896 {
3897 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
3898 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3899 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
3900
3901 vmsvga3dContextDefine(pThisCC, pCmd->cid);
3902 break;
3903 }
3904
3905 case SVGA_3D_CMD_CONTEXT_DESTROY:
3906 {
3907 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
3908 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3909 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
3910
3911 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
3912 break;
3913 }
3914
3915 case SVGA_3D_CMD_SETTRANSFORM:
3916 {
3917 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
3918 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3919 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
3920
3921 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
3922 break;
3923 }
3924
3925 case SVGA_3D_CMD_SETZRANGE:
3926 {
3927 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
3928 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3929 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
3930
3931 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
3932 break;
3933 }
3934
3935 case SVGA_3D_CMD_SETRENDERSTATE:
3936 {
3937 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
3938 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3939 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
3940
3941 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3942 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3943 break;
3944 }
3945
3946 case SVGA_3D_CMD_SETRENDERTARGET:
3947 {
3948 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
3949 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3950 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
3951
3952 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
3953 break;
3954 }
3955
3956 case SVGA_3D_CMD_SETTEXTURESTATE:
3957 {
3958 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
3959 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3960 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
3961
3962 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3963 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3964 break;
3965 }
3966
3967 case SVGA_3D_CMD_SETMATERIAL:
3968 {
3969 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
3970 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3971 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
3972
3973 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
3974 break;
3975 }
3976
3977 case SVGA_3D_CMD_SETLIGHTDATA:
3978 {
3979 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
3980 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3981 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
3982
3983 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
3984 break;
3985 }
3986
3987 case SVGA_3D_CMD_SETLIGHTENABLED:
3988 {
3989 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
3990 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3991 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
3992
3993 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
3994 break;
3995 }
3996
3997 case SVGA_3D_CMD_SETVIEWPORT:
3998 {
3999 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
4000 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4001 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
4002
4003 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4004 break;
4005 }
4006
4007 case SVGA_3D_CMD_SETCLIPPLANE:
4008 {
4009 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
4010 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4011 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
4012
4013 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4014 break;
4015 }
4016
4017 case SVGA_3D_CMD_CLEAR:
4018 {
4019 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
4020 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4021 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
4022
4023 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4024 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4025 break;
4026 }
4027
4028 case SVGA_3D_CMD_PRESENT:
4029 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4030 {
4031 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
4032 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4033 if (enmCmdId == SVGA_3D_CMD_PRESENT)
4034 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
4035 else
4036 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
4037
4038 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4039 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4040 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4041 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
4042 break;
4043 }
4044
4045 case SVGA_3D_CMD_SHADER_DEFINE:
4046 {
4047 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
4048 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4049 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
4050
4051 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
4052 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4053 break;
4054 }
4055
4056 case SVGA_3D_CMD_SHADER_DESTROY:
4057 {
4058 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
4059 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4060 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
4061
4062 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4063 break;
4064 }
4065
4066 case SVGA_3D_CMD_SET_SHADER:
4067 {
4068 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
4069 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4070 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
4071
4072 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4073 break;
4074 }
4075
4076 case SVGA_3D_CMD_SET_SHADER_CONST:
4077 {
4078 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
4079 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4080 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
4081
4082 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4083 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4084 break;
4085 }
4086
4087 case SVGA_3D_CMD_DRAW_PRIMITIVES:
4088 {
4089 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
4090 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4091 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
4092
4093 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
4094 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
4095 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4096 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4097 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
4098
4099 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4100 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
4101 RT_UNTRUSTED_VALIDATED_FENCE();
4102
4103 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
4104 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
4105 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
4106
4107 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4108 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4109 pNumRange, cVertexDivisor, pVertexDivisor);
4110 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
4111 break;
4112 }
4113
4114 case SVGA_3D_CMD_SETSCISSORRECT:
4115 {
4116 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
4117 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4118 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
4119
4120 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4121 break;
4122 }
4123
4124 case SVGA_3D_CMD_BEGIN_QUERY:
4125 {
4126 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
4127 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4128 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
4129
4130 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4131 break;
4132 }
4133
4134 case SVGA_3D_CMD_END_QUERY:
4135 {
4136 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
4137 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4138 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
4139
4140 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4141 break;
4142 }
4143
4144 case SVGA_3D_CMD_WAIT_FOR_QUERY:
4145 {
4146 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
4147 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4148 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
4149
4150 vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4151 break;
4152 }
4153
4154 case SVGA_3D_CMD_GENERATE_MIPMAPS:
4155 {
4156 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
4157 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4158 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
4159
4160 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4161 break;
4162 }
4163
4164 case SVGA_3D_CMD_ACTIVATE_SURFACE:
4165 /* context id + surface id? */
4166 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
4167 break;
4168
4169 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4170 /* context id + surface id? */
4171 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
4172 break;
4173
4174 /*
4175 *
4176 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
4177 *
4178 */
4179 case SVGA_3D_CMD_SCREEN_DMA:
4180 {
4181 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
4182 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4183 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4184 break;
4185 }
4186
4187 case SVGA_3D_CMD_DEAD1:
4188 case SVGA_3D_CMD_DEAD2:
4189 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
4190 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
4191 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
4192 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
4193 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
4194 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
4195 {
4196 VMSVGA_3D_CMD_NOTIMPL();
4197 break;
4198 }
4199
4200 case SVGA_3D_CMD_SET_OTABLE_BASE:
4201 {
4202 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
4203 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4204 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4205 break;
4206 }
4207
4208 case SVGA_3D_CMD_READBACK_OTABLE:
4209 {
4210 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
4211 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4212 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4213 break;
4214 }
4215
4216 case SVGA_3D_CMD_DEFINE_GB_MOB:
4217 {
4218 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
4219 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4220 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
4221 break;
4222 }
4223
4224 case SVGA_3D_CMD_DESTROY_GB_MOB:
4225 {
4226 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
4227 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4228 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
4229 break;
4230 }
4231
4232 case SVGA_3D_CMD_DEAD3:
4233 {
4234 VMSVGA_3D_CMD_NOTIMPL();
4235 break;
4236 }
4237
4238 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
4239 {
4240 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
4241 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4242 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4243 break;
4244 }
4245
4246 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
4247 {
4248 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
4249 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4250 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
4251 break;
4252 }
4253
4254 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
4255 {
4256 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
4257 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4258 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
4259 break;
4260 }
4261
4262 case SVGA_3D_CMD_BIND_GB_SURFACE:
4263 {
4264 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
4265 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4266 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
4267 break;
4268 }
4269
4270 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
4271 {
4272 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
4273 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4274 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4275 break;
4276 }
4277
4278 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
4279 {
4280 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
4281 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4282 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
4283 break;
4284 }
4285
4286 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
4287 {
4288 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
4289 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4290 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4291 break;
4292 }
4293
4294 case SVGA_3D_CMD_READBACK_GB_IMAGE:
4295 {
4296 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
4297 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4298 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4299 break;
4300 }
4301
4302 case SVGA_3D_CMD_READBACK_GB_SURFACE:
4303 {
4304 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
4305 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4306 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4307 break;
4308 }
4309
4310 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
4311 {
4312 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
4313 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4314 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
4315 break;
4316 }
4317
4318 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
4319 {
4320 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
4321 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4322 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
4323 break;
4324 }
4325
4326 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
4327 {
4328 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
4329 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4330 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4331 break;
4332 }
4333
4334 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
4335 {
4336 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
4337 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4338 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4339 break;
4340 }
4341
4342 case SVGA_3D_CMD_BIND_GB_CONTEXT:
4343 {
4344 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
4345 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4346 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4347 break;
4348 }
4349
4350 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
4351 {
4352 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
4353 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4354 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4355 break;
4356 }
4357
4358 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
4359 {
4360 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
4361 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4362 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4363 break;
4364 }
4365
4366 case SVGA_3D_CMD_DEFINE_GB_SHADER:
4367 {
4368 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
4369 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4370 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4371 break;
4372 }
4373
4374 case SVGA_3D_CMD_DESTROY_GB_SHADER:
4375 {
4376 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
4377 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4378 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4379 break;
4380 }
4381
4382 case SVGA_3D_CMD_BIND_GB_SHADER:
4383 {
4384 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
4385 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4386 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4387 break;
4388 }
4389
4390 case SVGA_3D_CMD_SET_OTABLE_BASE64:
4391 {
4392 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
4393 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4394 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
4395 break;
4396 }
4397
4398 case SVGA_3D_CMD_BEGIN_GB_QUERY:
4399 {
4400 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
4401 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4402 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4403 break;
4404 }
4405
4406 case SVGA_3D_CMD_END_GB_QUERY:
4407 {
4408 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
4409 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4410 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4411 break;
4412 }
4413
4414 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
4415 {
4416 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
4417 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4418 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4419 break;
4420 }
4421
4422 case SVGA_3D_CMD_NOP:
4423 {
4424 /* Apparently there is nothing to do. */
4425 break;
4426 }
4427
4428 case SVGA_3D_CMD_ENABLE_GART:
4429 {
4430 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
4431 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4432 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4433 break;
4434 }
4435
4436 case SVGA_3D_CMD_DISABLE_GART:
4437 {
4438 /* No corresponding SVGA3dCmd structure. */
4439 VMSVGA_3D_CMD_NOTIMPL();
4440 break;
4441 }
4442
4443 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
4444 {
4445 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
4446 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4447 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4448 break;
4449 }
4450
4451 case SVGA_3D_CMD_UNMAP_GART_RANGE:
4452 {
4453 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
4454 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4455 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4456 break;
4457 }
4458
4459 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
4460 {
4461 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
4462 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4463 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
4464 break;
4465 }
4466
4467 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
4468 {
4469 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
4470 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4471 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
4472 break;
4473 }
4474
4475 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
4476 {
4477 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
4478 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4479 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
4480 break;
4481 }
4482
4483 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
4484 {
4485 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
4486 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4487 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
4488 break;
4489 }
4490
4491 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
4492 {
4493 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
4494 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4495 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4496 break;
4497 }
4498
4499 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
4500 {
4501 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
4502 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4503 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4504 break;
4505 }
4506
4507 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
4508 {
4509 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
4510 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4511 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4512 break;
4513 }
4514
4515 case SVGA_3D_CMD_GB_SCREEN_DMA:
4516 {
4517 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
4518 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4519 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4520 break;
4521 }
4522
4523 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
4524 {
4525 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
4526 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4527 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4528 break;
4529 }
4530
4531 case SVGA_3D_CMD_GB_MOB_FENCE:
4532 {
4533 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
4534 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4535 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4536 break;
4537 }
4538
4539 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
4540 {
4541 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
4542 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4543 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
4544 break;
4545 }
4546
4547 case SVGA_3D_CMD_DEFINE_GB_MOB64:
4548 {
4549 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
4550 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4551 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
4552 break;
4553 }
4554
4555 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
4556 {
4557 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
4558 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4559 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4560 break;
4561 }
4562
4563 case SVGA_3D_CMD_NOP_ERROR:
4564 {
4565 /* Apparently there is nothing to do. */
4566 break;
4567 }
4568
4569 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
4570 {
4571 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
4572 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4573 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4574 break;
4575 }
4576
4577 case SVGA_3D_CMD_SET_VERTEX_DECLS:
4578 {
4579 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
4580 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4581 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4582 break;
4583 }
4584
4585 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
4586 {
4587 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
4588 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4589 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
4590 break;
4591 }
4592
4593 case SVGA_3D_CMD_DRAW:
4594 {
4595 /* No corresponding SVGA3dCmd structure. */
4596 VMSVGA_3D_CMD_NOTIMPL();
4597 break;
4598 }
4599
4600 case SVGA_3D_CMD_DRAW_INDEXED:
4601 {
4602 /* No corresponding SVGA3dCmd structure. */
4603 VMSVGA_3D_CMD_NOTIMPL();
4604 break;
4605 }
4606
4607 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
4608 {
4609 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
4610 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4611 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
4612 break;
4613 }
4614
4615 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
4616 {
4617 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
4618 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4619 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
4620 break;
4621 }
4622
4623 case SVGA_3D_CMD_DX_BIND_CONTEXT:
4624 {
4625 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
4626 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4627 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
4628 break;
4629 }
4630
4631 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
4632 {
4633 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
4634 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4635 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, idDXContext, pCmd, cbCmd);
4636 break;
4637 }
4638
4639 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
4640 {
4641 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
4642 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4643 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
4644 break;
4645 }
4646
4647 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
4648 {
4649 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
4650 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4651 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
4652 break;
4653 }
4654
4655 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
4656 {
4657 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
4658 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4659 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
4660 break;
4661 }
4662
4663 case SVGA_3D_CMD_DX_SET_SHADER:
4664 {
4665 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
4666 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4667 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
4668 break;
4669 }
4670
4671 case SVGA_3D_CMD_DX_SET_SAMPLERS:
4672 {
4673 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
4674 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4675 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
4676 break;
4677 }
4678
4679 case SVGA_3D_CMD_DX_DRAW:
4680 {
4681 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
4682 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4683 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
4684 break;
4685 }
4686
4687 case SVGA_3D_CMD_DX_DRAW_INDEXED:
4688 {
4689 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
4690 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4691 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
4692 break;
4693 }
4694
4695 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
4696 {
4697 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
4698 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4699 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
4700 break;
4701 }
4702
4703 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
4704 {
4705 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
4706 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4707 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
4708 break;
4709 }
4710
4711 case SVGA_3D_CMD_DX_DRAW_AUTO:
4712 {
4713 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
4714 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4715 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
4716 break;
4717 }
4718
4719 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
4720 {
4721 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
4722 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4723 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
4724 break;
4725 }
4726
4727 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
4728 {
4729 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
4730 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4731 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
4732 break;
4733 }
4734
4735 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
4736 {
4737 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
4738 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4739 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
4740 break;
4741 }
4742
4743 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
4744 {
4745 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
4746 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4747 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
4748 break;
4749 }
4750
4751 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
4752 {
4753 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
4754 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4755 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
4756 break;
4757 }
4758
4759 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
4760 {
4761 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
4762 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4763 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
4764 break;
4765 }
4766
4767 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
4768 {
4769 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
4770 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4771 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
4772 break;
4773 }
4774
4775 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
4776 {
4777 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
4778 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4779 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
4780 break;
4781 }
4782
4783 case SVGA_3D_CMD_DX_DEFINE_QUERY:
4784 {
4785 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
4786 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4787 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
4788 break;
4789 }
4790
4791 case SVGA_3D_CMD_DX_DESTROY_QUERY:
4792 {
4793 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
4794 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4795 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
4796 break;
4797 }
4798
4799 case SVGA_3D_CMD_DX_BIND_QUERY:
4800 {
4801 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
4802 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4803 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
4804 break;
4805 }
4806
4807 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
4808 {
4809 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
4810 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4811 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
4812 break;
4813 }
4814
4815 case SVGA_3D_CMD_DX_BEGIN_QUERY:
4816 {
4817 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
4818 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4819 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
4820 break;
4821 }
4822
4823 case SVGA_3D_CMD_DX_END_QUERY:
4824 {
4825 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
4826 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4827 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
4828 break;
4829 }
4830
4831 case SVGA_3D_CMD_DX_READBACK_QUERY:
4832 {
4833 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
4834 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4835 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
4836 break;
4837 }
4838
4839 case SVGA_3D_CMD_DX_SET_PREDICATION:
4840 {
4841 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
4842 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4843 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
4844 break;
4845 }
4846
4847 case SVGA_3D_CMD_DX_SET_SOTARGETS:
4848 {
4849 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
4850 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4851 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
4852 break;
4853 }
4854
4855 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
4856 {
4857 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
4858 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4859 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
4860 break;
4861 }
4862
4863 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
4864 {
4865 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
4866 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4867 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
4868 break;
4869 }
4870
4871 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
4872 {
4873 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
4874 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4875 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
4876 break;
4877 }
4878
4879 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
4880 {
4881 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
4882 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4883 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
4884 break;
4885 }
4886
4887 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
4888 {
4889 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
4890 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4891 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
4892 break;
4893 }
4894
4895 case SVGA_3D_CMD_DX_PRED_COPY:
4896 {
4897 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
4898 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4899 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
4900 break;
4901 }
4902
4903 case SVGA_3D_CMD_DX_PRESENTBLT:
4904 {
4905 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
4906 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4907 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
4908 break;
4909 }
4910
4911 case SVGA_3D_CMD_DX_GENMIPS:
4912 {
4913 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
4914 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4915 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
4916 break;
4917 }
4918
4919 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
4920 {
4921 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
4922 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4923 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4924 break;
4925 }
4926
4927 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
4928 {
4929 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
4930 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4931 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4932 break;
4933 }
4934
4935 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
4936 {
4937 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
4938 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4939 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, idDXContext, pCmd, cbCmd);
4940 break;
4941 }
4942
4943 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
4944 {
4945 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
4946 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4947 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
4948 break;
4949 }
4950
4951 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
4952 {
4953 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
4954 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4955 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
4956 break;
4957 }
4958
4959 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
4960 {
4961 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
4962 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4963 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
4964 break;
4965 }
4966
4967 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
4968 {
4969 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
4970 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4971 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
4972 break;
4973 }
4974
4975 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
4976 {
4977 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
4978 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4979 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
4980 break;
4981 }
4982
4983 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
4984 {
4985 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
4986 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4987 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
4988 break;
4989 }
4990
4991 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
4992 {
4993 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
4994 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4995 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
4996 break;
4997 }
4998
4999 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
5000 {
5001 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
5002 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5003 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
5004 break;
5005 }
5006
5007 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
5008 {
5009 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
5010 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5011 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5012 break;
5013 }
5014
5015 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
5016 {
5017 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
5018 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5019 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5020 break;
5021 }
5022
5023 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
5024 {
5025 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
5026 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5027 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5028 break;
5029 }
5030
5031 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
5032 {
5033 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
5034 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5035 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5036 break;
5037 }
5038
5039 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
5040 {
5041 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
5042 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5043 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5044 break;
5045 }
5046
5047 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
5048 {
5049 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
5050 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5051 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5052 break;
5053 }
5054
5055 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
5056 {
5057 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
5058 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5059 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5060 break;
5061 }
5062
5063 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
5064 {
5065 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
5066 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5067 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
5068 break;
5069 }
5070
5071 case SVGA_3D_CMD_DX_DEFINE_SHADER:
5072 {
5073 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
5074 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5075 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
5076 break;
5077 }
5078
5079 case SVGA_3D_CMD_DX_DESTROY_SHADER:
5080 {
5081 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
5082 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5083 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
5084 break;
5085 }
5086
5087 case SVGA_3D_CMD_DX_BIND_SHADER:
5088 {
5089 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
5090 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5091 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
5092 break;
5093 }
5094
5095 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
5096 {
5097 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
5098 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5099 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5100 break;
5101 }
5102
5103 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
5104 {
5105 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
5106 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5107 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5108 break;
5109 }
5110
5111 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
5112 {
5113 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
5114 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5115 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5116 break;
5117 }
5118
5119 case SVGA_3D_CMD_DX_SET_COTABLE:
5120 {
5121 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
5122 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5123 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
5124 break;
5125 }
5126
5127 case SVGA_3D_CMD_DX_READBACK_COTABLE:
5128 {
5129 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
5130 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5131 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5132 break;
5133 }
5134
5135 case SVGA_3D_CMD_DX_BUFFER_COPY:
5136 {
5137 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
5138 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5139 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
5140 break;
5141 }
5142
5143 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
5144 {
5145 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
5146 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5147 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5148 break;
5149 }
5150
5151 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
5152 {
5153 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
5154 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5155 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
5156 break;
5157 }
5158
5159 case SVGA_3D_CMD_DX_MOVE_QUERY:
5160 {
5161 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
5162 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5163 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
5164 break;
5165 }
5166
5167 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
5168 {
5169 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
5170 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5171 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5172 break;
5173 }
5174
5175 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
5176 {
5177 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
5178 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5179 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
5180 break;
5181 }
5182
5183 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
5184 {
5185 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
5186 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5187 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5188 break;
5189 }
5190
5191 case SVGA_3D_CMD_DX_MOB_FENCE_64:
5192 {
5193 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
5194 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5195 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, idDXContext, pCmd, cbCmd);
5196 break;
5197 }
5198
5199 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
5200 {
5201 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
5202 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5203 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5204 break;
5205 }
5206
5207 case SVGA_3D_CMD_DX_HINT:
5208 {
5209 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
5210 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5211 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
5212 break;
5213 }
5214
5215 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
5216 {
5217 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
5218 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5219 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
5220 break;
5221 }
5222
5223 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
5224 {
5225 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
5226 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5227 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5228 break;
5229 }
5230
5231 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
5232 {
5233 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
5234 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5235 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5236 break;
5237 }
5238
5239 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
5240 {
5241 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
5242 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5243 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5244 break;
5245 }
5246
5247 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
5248 {
5249 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
5250 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5251 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5252 break;
5253 }
5254
5255 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
5256 {
5257 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
5258 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5259 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5260 break;
5261 }
5262
5263 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
5264 {
5265 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
5266 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5267 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
5268 break;
5269 }
5270
5271 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
5272 {
5273 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
5274 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5275 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
5276 break;
5277 }
5278
5279 case SVGA_3D_CMD_SCREEN_COPY:
5280 {
5281 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
5282 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5283 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
5284 break;
5285 }
5286
5287 case SVGA_3D_CMD_RESERVED1:
5288 {
5289 VMSVGA_3D_CMD_NOTIMPL();
5290 break;
5291 }
5292
5293 case SVGA_3D_CMD_RESERVED2:
5294 {
5295 VMSVGA_3D_CMD_NOTIMPL();
5296 break;
5297 }
5298
5299 case SVGA_3D_CMD_RESERVED3:
5300 {
5301 VMSVGA_3D_CMD_NOTIMPL();
5302 break;
5303 }
5304
5305 case SVGA_3D_CMD_RESERVED4:
5306 {
5307 VMSVGA_3D_CMD_NOTIMPL();
5308 break;
5309 }
5310
5311 case SVGA_3D_CMD_RESERVED5:
5312 {
5313 VMSVGA_3D_CMD_NOTIMPL();
5314 break;
5315 }
5316
5317 case SVGA_3D_CMD_RESERVED6:
5318 {
5319 VMSVGA_3D_CMD_NOTIMPL();
5320 break;
5321 }
5322
5323 case SVGA_3D_CMD_RESERVED7:
5324 {
5325 VMSVGA_3D_CMD_NOTIMPL();
5326 break;
5327 }
5328
5329 case SVGA_3D_CMD_RESERVED8:
5330 {
5331 VMSVGA_3D_CMD_NOTIMPL();
5332 break;
5333 }
5334
5335 case SVGA_3D_CMD_GROW_OTABLE:
5336 {
5337 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
5338 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5339 rcParse = vmsvga3dCmdGrowOTable(pThisCC, idDXContext, pCmd, cbCmd);
5340 break;
5341 }
5342
5343 case SVGA_3D_CMD_DX_GROW_COTABLE:
5344 {
5345 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
5346 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5347 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, idDXContext, pCmd, cbCmd);
5348 break;
5349 }
5350
5351 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
5352 {
5353 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
5354 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5355 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5356 break;
5357 }
5358
5359 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
5360 {
5361 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
5362 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5363 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, idDXContext, pCmd, cbCmd);
5364 break;
5365 }
5366
5367 case SVGA_3D_CMD_DX_RESOLVE_COPY:
5368 {
5369 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
5370 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5371 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5372 break;
5373 }
5374
5375 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
5376 {
5377 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
5378 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5379 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
5380 break;
5381 }
5382
5383 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
5384 {
5385 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
5386 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5387 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
5388 break;
5389 }
5390
5391 case SVGA_3D_CMD_DX_PRED_CONVERT:
5392 {
5393 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
5394 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5395 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
5396 break;
5397 }
5398
5399 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
5400 {
5401 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
5402 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5403 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
5404 break;
5405 }
5406
5407 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
5408 {
5409 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
5410 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5411 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
5412 break;
5413 }
5414
5415 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
5416 {
5417 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
5418 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5419 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
5420 break;
5421 }
5422
5423 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
5424 {
5425 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
5426 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5427 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
5428 break;
5429 }
5430
5431 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
5432 {
5433 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
5434 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5435 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
5436 break;
5437 }
5438
5439 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
5440 {
5441 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
5442 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5443 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5444 break;
5445 }
5446
5447 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
5448 {
5449 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
5450 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5451 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5452 break;
5453 }
5454
5455 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
5456 {
5457 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
5458 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5459 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5460 break;
5461 }
5462
5463 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
5464 {
5465 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
5466 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5467 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5468 break;
5469 }
5470
5471 case SVGA_3D_CMD_DX_DISPATCH:
5472 {
5473 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
5474 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5475 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
5476 break;
5477 }
5478
5479 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
5480 {
5481 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
5482 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5483 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
5484 break;
5485 }
5486
5487 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
5488 {
5489 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
5490 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5491 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5492 break;
5493 }
5494
5495 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
5496 {
5497 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
5498 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5499 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
5500 break;
5501 }
5502
5503 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
5504 {
5505 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
5506 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5507 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5508 break;
5509 }
5510
5511 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
5512 {
5513 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
5514 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5515 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
5516 break;
5517 }
5518
5519 case SVGA_3D_CMD_LOGICOPS_BITBLT:
5520 {
5521 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
5522 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5523 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
5524 break;
5525 }
5526
5527 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
5528 {
5529 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
5530 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5531 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
5532 break;
5533 }
5534
5535 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
5536 {
5537 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
5538 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5539 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
5540 break;
5541 }
5542
5543 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
5544 {
5545 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
5546 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5547 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
5548 break;
5549 }
5550
5551 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
5552 {
5553 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
5554 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5555 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
5556 break;
5557 }
5558
5559 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
5560 {
5561 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
5562 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5563 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
5564 break;
5565 }
5566
5567 case SVGA_3D_CMD_RESERVED2_1:
5568 {
5569 VMSVGA_3D_CMD_NOTIMPL();
5570 break;
5571 }
5572
5573 case SVGA_3D_CMD_RESERVED2_2:
5574 {
5575 VMSVGA_3D_CMD_NOTIMPL();
5576 break;
5577 }
5578
5579 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
5580 {
5581 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
5582 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5583 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, idDXContext, pCmd, cbCmd);
5584 break;
5585 }
5586
5587 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
5588 {
5589 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
5590 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5591 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
5592 break;
5593 }
5594
5595 case SVGA_3D_CMD_DX_SET_MIN_LOD:
5596 {
5597 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
5598 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5599 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
5600 break;
5601 }
5602
5603 case SVGA_3D_CMD_RESERVED2_3:
5604 {
5605 VMSVGA_3D_CMD_NOTIMPL();
5606 break;
5607 }
5608
5609 case SVGA_3D_CMD_RESERVED2_4:
5610 {
5611 VMSVGA_3D_CMD_NOTIMPL();
5612 break;
5613 }
5614
5615 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
5616 {
5617 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
5618 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5619 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
5620 break;
5621 }
5622
5623 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
5624 {
5625 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
5626 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5627 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
5628 break;
5629 }
5630
5631 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
5632 {
5633 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
5634 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5635 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
5636 break;
5637 }
5638
5639 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
5640 {
5641 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
5642 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5643 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
5644 break;
5645 }
5646
5647 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
5648 {
5649 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
5650 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5651 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
5652 break;
5653 }
5654
5655 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
5656 {
5657 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
5658 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5659 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
5660 break;
5661 }
5662
5663 /* Unsupported commands. */
5664 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
5665 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
5666 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
5667 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
5668 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
5669 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
5670 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
5671 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
5672 /* Prevent the compiler warning. */
5673 case SVGA_3D_CMD_LEGACY_BASE:
5674 case SVGA_3D_CMD_MAX:
5675 case SVGA_3D_CMD_FUTURE_MAX:
5676 /* No 'default' case */
5677 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
5678 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
5679 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
5680 rcParse = VERR_NOT_IMPLEMENTED;
5681 break;
5682 }
5683
5684 return VINF_SUCCESS;
5685// return rcParse;
5686}
5687# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
5688#endif /* VBOX_WITH_VMSVGA3D */
5689
5690
5691/*
5692 *
5693 * Handlers for FIFO commands.
5694 *
5695 * Every handler takes the following parameters:
5696 *
5697 * pThis The shared VGA/VMSVGA state.
5698 * pThisCC The VGA/VMSVGA state for ring-3.
5699 * pCmd The command data.
5700 */
5701
5702
5703/* SVGA_CMD_UPDATE */
5704void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
5705{
5706 RT_NOREF(pThis);
5707 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5708
5709 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
5710 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
5711
5712 /** @todo Multiple screens? */
5713 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5714 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5715 return;
5716
5717 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5718}
5719
5720
5721/* SVGA_CMD_UPDATE_VERBOSE */
5722void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
5723{
5724 RT_NOREF(pThis);
5725 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5726
5727 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
5728 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
5729
5730 /** @todo Multiple screens? */
5731 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5732 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
5733 return;
5734
5735 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
5736}
5737
5738
5739/* SVGA_CMD_RECT_FILL */
5740void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
5741{
5742 RT_NOREF(pThis, pCmd);
5743 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5744
5745 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
5746 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5747 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
5748}
5749
5750
5751/* SVGA_CMD_RECT_COPY */
5752void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
5753{
5754 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5755
5756 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
5757 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
5758
5759 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5760 AssertPtrReturnVoid(pScreen);
5761
5762 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5763 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5764 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5765 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5766 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5767 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5768 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5769
5770 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5771 pCmd->width, pCmd->height, pThis->vram_size);
5772 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5773}
5774
5775
5776/* SVGA_CMD_RECT_ROP_COPY */
5777void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
5778{
5779 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5780
5781 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
5782 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5783
5784 if (pCmd->rop != SVGA_ROP_COPY)
5785 {
5786 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
5787 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
5788 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
5789 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
5790 */
5791 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
5792 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
5793 return;
5794 }
5795
5796 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
5797 AssertPtrReturnVoid(pScreen);
5798
5799 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
5800 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
5801 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
5802 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
5803 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
5804 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
5805 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
5806
5807 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
5808 pCmd->width, pCmd->height, pThis->vram_size);
5809 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
5810}
5811
5812
5813/* SVGA_CMD_DISPLAY_CURSOR */
5814void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
5815{
5816 RT_NOREF(pThis, pCmd);
5817 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5818
5819 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
5820 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
5821 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
5822}
5823
5824
5825/* SVGA_CMD_MOVE_CURSOR */
5826void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
5827{
5828 RT_NOREF(pThis, pCmd);
5829 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5830
5831 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
5832 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
5833 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
5834}
5835
5836
5837/* SVGA_CMD_DEFINE_CURSOR */
5838void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
5839{
5840 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
5841
5842 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
5843 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
5844 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
5845
5846 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
5847 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
5848 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
5849 RT_UNTRUSTED_VALIDATED_FENCE();
5850
5851 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
5852 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
5853 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
5854
5855 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
5856 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
5857
5858 uint32_t const cx = pCmd->width;
5859 uint32_t const cy = pCmd->height;
5860
5861 /*
5862 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
5863 * The AND data uses 8-bit aligned scanlines.
5864 * The XOR data must be starting on a 32-bit boundrary.
5865 */
5866 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
5867 uint32_t cbDstAndMask = cbDstAndLine * cy;
5868 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
5869 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
5870
5871 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
5872 AssertReturnVoid(pbCopy);
5873
5874 /* Convert the AND mask. */
5875 uint8_t *pbDst = pbCopy;
5876 uint8_t const *pbSrc = pbSrcAndMask;
5877 switch (pCmd->andMaskDepth)
5878 {
5879 case 1:
5880 if (cbSrcAndLine == cbDstAndLine)
5881 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
5882 else
5883 {
5884 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
5885 for (uint32_t y = 0; y < cy; y++)
5886 {
5887 memcpy(pbDst, pbSrc, cbDstAndLine);
5888 pbDst += cbDstAndLine;
5889 pbSrc += cbSrcAndLine;
5890 }
5891 }
5892 break;
5893 /* Should take the XOR mask into account for the multi-bit AND mask. */
5894 case 8:
5895 for (uint32_t y = 0; y < cy; y++)
5896 {
5897 for (uint32_t x = 0; x < cx; )
5898 {
5899 uint8_t bDst = 0;
5900 uint8_t fBit = 0x80;
5901 do
5902 {
5903 uintptr_t const idxPal = pbSrc[x] * 3;
5904 if ((( pThis->last_palette[idxPal]
5905 | (pThis->last_palette[idxPal] >> 8)
5906 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
5907 bDst |= fBit;
5908 fBit >>= 1;
5909 x++;
5910 } while (x < cx && (x & 7));
5911 pbDst[(x - 1) / 8] = bDst;
5912 }
5913 pbDst += cbDstAndLine;
5914 pbSrc += cbSrcAndLine;
5915 }
5916 break;
5917 case 15:
5918 for (uint32_t y = 0; y < cy; y++)
5919 {
5920 for (uint32_t x = 0; x < cx; )
5921 {
5922 uint8_t bDst = 0;
5923 uint8_t fBit = 0x80;
5924 do
5925 {
5926 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
5927 bDst |= fBit;
5928 fBit >>= 1;
5929 x++;
5930 } while (x < cx && (x & 7));
5931 pbDst[(x - 1) / 8] = bDst;
5932 }
5933 pbDst += cbDstAndLine;
5934 pbSrc += cbSrcAndLine;
5935 }
5936 break;
5937 case 16:
5938 for (uint32_t y = 0; y < cy; y++)
5939 {
5940 for (uint32_t x = 0; x < cx; )
5941 {
5942 uint8_t bDst = 0;
5943 uint8_t fBit = 0x80;
5944 do
5945 {
5946 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
5947 bDst |= fBit;
5948 fBit >>= 1;
5949 x++;
5950 } while (x < cx && (x & 7));
5951 pbDst[(x - 1) / 8] = bDst;
5952 }
5953 pbDst += cbDstAndLine;
5954 pbSrc += cbSrcAndLine;
5955 }
5956 break;
5957 case 24:
5958 for (uint32_t y = 0; y < cy; y++)
5959 {
5960 for (uint32_t x = 0; x < cx; )
5961 {
5962 uint8_t bDst = 0;
5963 uint8_t fBit = 0x80;
5964 do
5965 {
5966 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
5967 bDst |= fBit;
5968 fBit >>= 1;
5969 x++;
5970 } while (x < cx && (x & 7));
5971 pbDst[(x - 1) / 8] = bDst;
5972 }
5973 pbDst += cbDstAndLine;
5974 pbSrc += cbSrcAndLine;
5975 }
5976 break;
5977 case 32:
5978 for (uint32_t y = 0; y < cy; y++)
5979 {
5980 for (uint32_t x = 0; x < cx; )
5981 {
5982 uint8_t bDst = 0;
5983 uint8_t fBit = 0x80;
5984 do
5985 {
5986 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
5987 bDst |= fBit;
5988 fBit >>= 1;
5989 x++;
5990 } while (x < cx && (x & 7));
5991 pbDst[(x - 1) / 8] = bDst;
5992 }
5993 pbDst += cbDstAndLine;
5994 pbSrc += cbSrcAndLine;
5995 }
5996 break;
5997 default:
5998 RTMemFreeZ(pbCopy, cbCopy);
5999 AssertFailedReturnVoid();
6000 }
6001
6002 /* Convert the XOR mask. */
6003 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
6004 pbSrc = pbSrcXorMask;
6005 switch (pCmd->xorMaskDepth)
6006 {
6007 case 1:
6008 for (uint32_t y = 0; y < cy; y++)
6009 {
6010 for (uint32_t x = 0; x < cx; )
6011 {
6012 /* most significant bit is the left most one. */
6013 uint8_t bSrc = pbSrc[x / 8];
6014 do
6015 {
6016 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
6017 bSrc <<= 1;
6018 x++;
6019 } while ((x & 7) && x < cx);
6020 }
6021 pbSrc += cbSrcXorLine;
6022 }
6023 break;
6024 case 8:
6025 for (uint32_t y = 0; y < cy; y++)
6026 {
6027 for (uint32_t x = 0; x < cx; x++)
6028 {
6029 uint32_t u = pThis->last_palette[pbSrc[x]];
6030 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
6031 }
6032 pbSrc += cbSrcXorLine;
6033 }
6034 break;
6035 case 15: /* Src: RGB-5-5-5 */
6036 for (uint32_t y = 0; y < cy; y++)
6037 {
6038 for (uint32_t x = 0; x < cx; x++)
6039 {
6040 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6041 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6042 ((uValue >> 5) & 0x1f) << 3,
6043 ((uValue >> 10) & 0x1f) << 3, 0);
6044 }
6045 pbSrc += cbSrcXorLine;
6046 }
6047 break;
6048 case 16: /* Src: RGB-5-6-5 */
6049 for (uint32_t y = 0; y < cy; y++)
6050 {
6051 for (uint32_t x = 0; x < cx; x++)
6052 {
6053 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
6054 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
6055 ((uValue >> 5) & 0x3f) << 2,
6056 ((uValue >> 11) & 0x1f) << 3, 0);
6057 }
6058 pbSrc += cbSrcXorLine;
6059 }
6060 break;
6061 case 24:
6062 for (uint32_t y = 0; y < cy; y++)
6063 {
6064 for (uint32_t x = 0; x < cx; x++)
6065 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
6066 pbSrc += cbSrcXorLine;
6067 }
6068 break;
6069 case 32:
6070 for (uint32_t y = 0; y < cy; y++)
6071 {
6072 for (uint32_t x = 0; x < cx; x++)
6073 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
6074 pbSrc += cbSrcXorLine;
6075 }
6076 break;
6077 default:
6078 RTMemFreeZ(pbCopy, cbCopy);
6079 AssertFailedReturnVoid();
6080 }
6081
6082 /*
6083 * Pass it to the frontend/whatever.
6084 */
6085 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6086 cx, cy, pbCopy, cbCopy);
6087}
6088
6089
6090/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
6091void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
6092{
6093 RT_NOREF(pThis);
6094 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6095
6096 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
6097 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
6098
6099 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
6100 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
6101 RT_UNTRUSTED_VALIDATED_FENCE();
6102
6103 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
6104 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
6105 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
6106 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
6107 uint32_t cbCursorShape = cbAndMask + cbXorMask;
6108
6109 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
6110 AssertPtrReturnVoid(pCursorCopy);
6111
6112 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
6113 memset(pCursorCopy, 0xff, cbAndMask);
6114 /* Colour data */
6115 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
6116
6117 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
6118 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
6119}
6120
6121
6122/* SVGA_CMD_ESCAPE */
6123void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
6124{
6125 RT_NOREF(pThis);
6126 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6127
6128 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
6129
6130 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
6131 {
6132 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
6133 RT_UNTRUSTED_VALIDATED_FENCE();
6134
6135 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
6136 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
6137
6138 switch (cmd)
6139 {
6140 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
6141 {
6142 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
6143 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
6144 RT_UNTRUSTED_VALIDATED_FENCE();
6145
6146 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
6147
6148 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
6149 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
6150 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
6151 RT_NOREF_PV(pVideoCmd);
6152 break;
6153 }
6154
6155 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
6156 {
6157 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
6158 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
6159 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
6160 RT_NOREF_PV(pVideoCmd);
6161 break;
6162 }
6163
6164 default:
6165 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
6166 break;
6167 }
6168 }
6169 else
6170 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
6171}
6172
6173
6174/* SVGA_CMD_DEFINE_SCREEN */
6175void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
6176{
6177 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6178
6179 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
6180 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
6181 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
6182 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
6183
6184 uint32_t const idScreen = pCmd->screen.id;
6185 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6186
6187 uint32_t const uWidth = pCmd->screen.size.width;
6188 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
6189
6190 uint32_t const uHeight = pCmd->screen.size.height;
6191 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
6192
6193 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
6194 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
6195 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
6196
6197 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
6198 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
6199
6200 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
6201 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
6202 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
6203 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
6204 RT_UNTRUSTED_VALIDATED_FENCE();
6205
6206 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6207 pScreen->fDefined = true;
6208 pScreen->fModified = true;
6209 pScreen->fuScreen = pCmd->screen.flags;
6210 pScreen->idScreen = idScreen;
6211 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
6212 {
6213 /* Not blanked. */
6214 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
6215 RT_UNTRUSTED_VALIDATED_FENCE();
6216
6217 pScreen->xOrigin = pCmd->screen.root.x;
6218 pScreen->yOrigin = pCmd->screen.root.y;
6219 pScreen->cWidth = uWidth;
6220 pScreen->cHeight = uHeight;
6221 pScreen->offVRAM = uScreenOffset;
6222 pScreen->cbPitch = cbPitch;
6223 pScreen->cBpp = 32;
6224 }
6225 else
6226 {
6227 /* Screen blanked. Keep old values. */
6228 }
6229
6230 pThis->svga.fGFBRegisters = false;
6231 vmsvgaR3ChangeMode(pThis, pThisCC);
6232
6233#ifdef VBOX_WITH_VMSVGA3D
6234 if (RT_LIKELY(pThis->svga.f3DEnabled))
6235 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
6236#endif
6237}
6238
6239
6240/* SVGA_CMD_DESTROY_SCREEN */
6241void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
6242{
6243 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6244
6245 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
6246 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
6247
6248 uint32_t const idScreen = pCmd->screenId;
6249 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
6250 RT_UNTRUSTED_VALIDATED_FENCE();
6251
6252 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
6253 pScreen->fModified = true;
6254 pScreen->fDefined = false;
6255 pScreen->idScreen = idScreen;
6256
6257#ifdef VBOX_WITH_VMSVGA3D
6258 if (RT_LIKELY(pThis->svga.f3DEnabled))
6259 vmsvga3dDestroyScreen(pThisCC, pScreen);
6260#endif
6261 vmsvgaR3ChangeMode(pThis, pThisCC);
6262}
6263
6264
6265/* SVGA_CMD_DEFINE_GMRFB */
6266void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
6267{
6268 RT_NOREF(pThis);
6269 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6270
6271 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
6272 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
6273 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
6274
6275 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
6276 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
6277 pSvgaR3State->GMRFB.format = pCmd->format;
6278}
6279
6280
6281/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
6282void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
6283{
6284 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6285
6286 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
6287 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
6288 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
6289
6290 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6291 RT_UNTRUSTED_VALIDATED_FENCE();
6292
6293 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
6294 AssertPtrReturnVoid(pScreen);
6295
6296 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
6297 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6298
6299 /* Clip destRect to the screen dimensions. */
6300 SVGASignedRect screenRect;
6301 screenRect.left = 0;
6302 screenRect.top = 0;
6303 screenRect.right = pScreen->cWidth;
6304 screenRect.bottom = pScreen->cHeight;
6305 SVGASignedRect clipRect = pCmd->destRect;
6306 vmsvgaR3ClipRect(&screenRect, &clipRect);
6307 RT_UNTRUSTED_VALIDATED_FENCE();
6308
6309 uint32_t const width = clipRect.right - clipRect.left;
6310 uint32_t const height = clipRect.bottom - clipRect.top;
6311
6312 if ( width == 0
6313 || height == 0)
6314 return; /* Nothing to do. */
6315
6316 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
6317 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
6318
6319 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6320 * Prepare parameters for vmsvgaR3GmrTransfer.
6321 */
6322 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6323
6324 /* Destination: host buffer which describes the screen 0 VRAM.
6325 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6326 */
6327 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6328 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6329 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6330 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6331 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6332 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6333 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6334 + cbScanline * clipRect.top;
6335 int32_t const cbHstPitch = cbScanline;
6336
6337 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6338 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6339 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6340 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
6341 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6342
6343 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
6344 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6345 gstPtr, offGst, cbGstPitch,
6346 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6347 AssertRC(rc);
6348 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
6349}
6350
6351
6352/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
6353void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
6354{
6355 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6356
6357 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
6358 /* Note! This can fetch 3d render results as well!! */
6359 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
6360 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
6361
6362 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
6363 RT_UNTRUSTED_VALIDATED_FENCE();
6364
6365 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
6366 AssertPtrReturnVoid(pScreen);
6367
6368 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
6369 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
6370
6371 /* Clip destRect to the screen dimensions. */
6372 SVGASignedRect screenRect;
6373 screenRect.left = 0;
6374 screenRect.top = 0;
6375 screenRect.right = pScreen->cWidth;
6376 screenRect.bottom = pScreen->cHeight;
6377 SVGASignedRect clipRect = pCmd->srcRect;
6378 vmsvgaR3ClipRect(&screenRect, &clipRect);
6379 RT_UNTRUSTED_VALIDATED_FENCE();
6380
6381 uint32_t const width = clipRect.right - clipRect.left;
6382 uint32_t const height = clipRect.bottom - clipRect.top;
6383
6384 if ( width == 0
6385 || height == 0)
6386 return; /* Nothing to do. */
6387
6388 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
6389 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
6390
6391 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
6392 * Prepare parameters for vmsvgaR3GmrTransfer.
6393 */
6394 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
6395
6396 /* Source: host buffer which describes the screen 0 VRAM.
6397 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
6398 */
6399 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
6400 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
6401 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
6402 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
6403 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
6404 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
6405 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
6406 + cbScanline * clipRect.top;
6407 int32_t const cbHstPitch = cbScanline;
6408
6409 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
6410 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
6411 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
6412 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
6413 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
6414
6415 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
6416 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6417 gstPtr, offGst, cbGstPitch,
6418 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
6419 AssertRC(rc);
6420}
6421
6422
6423/* SVGA_CMD_ANNOTATION_FILL */
6424void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
6425{
6426 RT_NOREF(pThis);
6427 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6428
6429 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
6430 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
6431
6432 pSvgaR3State->colorAnnotation = pCmd->color;
6433}
6434
6435
6436/* SVGA_CMD_ANNOTATION_COPY */
6437void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
6438{
6439 RT_NOREF(pThis, pCmd);
6440 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6441
6442 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
6443 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
6444
6445 AssertFailed();
6446}
6447
6448
6449#ifdef VBOX_WITH_VMSVGA3D
6450/* SVGA_CMD_DEFINE_GMR2 */
6451void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
6452{
6453 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6454
6455 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
6456 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
6457
6458 /* Validate current GMR id. */
6459 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6460 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
6461 RT_UNTRUSTED_VALIDATED_FENCE();
6462
6463 if (!pCmd->numPages)
6464 {
6465 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
6466 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6467 }
6468 else
6469 {
6470 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6471 if (pGMR->cMaxPages)
6472 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
6473
6474 /* Not sure if we should always free the descriptor, but for simplicity
6475 we do so if the new size is smaller than the current. */
6476 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
6477 if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
6478 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
6479
6480 pGMR->cMaxPages = pCmd->numPages;
6481 /* The rest is done by the REMAP_GMR2 command. */
6482 }
6483}
6484
6485
6486/* SVGA_CMD_REMAP_GMR2 */
6487void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
6488{
6489 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
6490
6491 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
6492 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
6493
6494 /* Validate current GMR id and size. */
6495 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
6496 RT_UNTRUSTED_VALIDATED_FENCE();
6497 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
6498 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
6499 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
6500 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
6501
6502 if (pCmd->numPages == 0)
6503 return;
6504 RT_UNTRUSTED_VALIDATED_FENCE();
6505
6506 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
6507 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
6508
6509 /*
6510 * We flatten the existing descriptors into a page array, overwrite the
6511 * pages specified in this command and then recompress the descriptor.
6512 */
6513 /** @todo Optimize the GMR remap algorithm! */
6514
6515 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
6516 uint64_t *paNewPage64 = NULL;
6517 if (pGMR->paDesc)
6518 {
6519 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
6520
6521 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
6522 AssertPtrReturnVoid(paNewPage64);
6523
6524 uint32_t idxPage = 0;
6525 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
6526 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
6527 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
6528 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
6529 RT_UNTRUSTED_VALIDATED_FENCE();
6530 }
6531
6532 /* Free the old GMR if present. */
6533 if (pGMR->paDesc)
6534 RTMemFree(pGMR->paDesc);
6535
6536 /* Allocate the maximum amount possible (everything non-continuous) */
6537 PVMSVGAGMRDESCRIPTOR paDescs;
6538 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
6539 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
6540
6541 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
6542 {
6543 /** @todo */
6544 AssertFailed();
6545 pGMR->numDescriptors = 0;
6546 }
6547 else
6548 {
6549 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
6550 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
6551 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
6552
6553 uint32_t cPages;
6554 if (paNewPage64)
6555 {
6556 /* Overwrite the old page array with the new page values. */
6557 if (fGCPhys64)
6558 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6559 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
6560 else
6561 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
6562 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
6563
6564 /* Use the updated page array instead of the command data. */
6565 fGCPhys64 = true;
6566 paPages64 = paNewPage64;
6567 cPages = cNewTotalPages;
6568 }
6569 else
6570 cPages = pCmd->numPages;
6571
6572 /* The first page. */
6573 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
6574 * applied to paNewPage64. */
6575 RTGCPHYS GCPhys;
6576 if (fGCPhys64)
6577 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6578 else
6579 GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
6580 paDescs[0].GCPhys = GCPhys;
6581 paDescs[0].numPages = 1;
6582
6583 /* Subsequent pages. */
6584 uint32_t iDescriptor = 0;
6585 for (uint32_t i = 1; i < cPages; i++)
6586 {
6587 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
6588 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
6589 else
6590 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
6591
6592 /* Continuous physical memory? */
6593 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
6594 {
6595 Assert(paDescs[iDescriptor].numPages);
6596 paDescs[iDescriptor].numPages++;
6597 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
6598 }
6599 else
6600 {
6601 iDescriptor++;
6602 paDescs[iDescriptor].GCPhys = GCPhys;
6603 paDescs[iDescriptor].numPages = 1;
6604 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
6605 }
6606 }
6607
6608 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
6609 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
6610 pGMR->numDescriptors = iDescriptor + 1;
6611 }
6612
6613 if (paNewPage64)
6614 RTMemFree(paNewPage64);
6615}
6616
6617
6618/**
6619 * Free the specified GMR
6620 *
6621 * @param pThisCC The VGA/VMSVGA state for ring-3.
6622 * @param idGMR GMR id
6623 */
6624void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
6625{
6626 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6627
6628 /* Free the old descriptor if present. */
6629 PGMR pGMR = &pSVGAState->paGMR[idGMR];
6630 if ( pGMR->numDescriptors
6631 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
6632 {
6633# ifdef DEBUG_GMR_ACCESS
6634 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
6635# endif
6636
6637 Assert(pGMR->paDesc);
6638 RTMemFree(pGMR->paDesc);
6639 pGMR->paDesc = NULL;
6640 pGMR->numDescriptors = 0;
6641 pGMR->cbTotal = 0;
6642 pGMR->cMaxPages = 0;
6643 }
6644 Assert(!pGMR->cMaxPages);
6645 Assert(!pGMR->cbTotal);
6646}
6647#endif /* VBOX_WITH_VMSVGA3D */
6648
6649
6650/**
6651 * Copy between a GMR and a host memory buffer.
6652 *
6653 * @returns VBox status code.
6654 * @param pThis The shared VGA/VMSVGA instance data.
6655 * @param pThisCC The VGA/VMSVGA state for ring-3.
6656 * @param enmTransferType Transfer type (read/write)
6657 * @param pbHstBuf Host buffer pointer (valid)
6658 * @param cbHstBuf Size of host buffer (valid)
6659 * @param offHst Host buffer offset of the first scanline
6660 * @param cbHstPitch Destination buffer pitch
6661 * @param gstPtr GMR description
6662 * @param offGst Guest buffer offset of the first scanline
6663 * @param cbGstPitch Guest buffer pitch
6664 * @param cbWidth Width in bytes to copy
6665 * @param cHeight Number of scanllines to copy
6666 */
6667int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
6668 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
6669 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
6670 uint32_t cbWidth, uint32_t cHeight)
6671{
6672 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6673 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
6674 int rc;
6675
6676 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
6677 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
6678 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
6679 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
6680 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
6681
6682 PGMR pGMR;
6683 uint32_t cbGmr; /* The GMR size in bytes. */
6684 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6685 {
6686 pGMR = NULL;
6687 cbGmr = pThis->vram_size;
6688 }
6689 else
6690 {
6691 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
6692 RT_UNTRUSTED_VALIDATED_FENCE();
6693 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
6694 cbGmr = pGMR->cbTotal;
6695 }
6696
6697 /*
6698 * GMR
6699 */
6700 /* Calculate GMR offset of the data to be copied. */
6701 AssertMsgReturn(gstPtr.offset < cbGmr,
6702 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6703 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6704 VERR_INVALID_PARAMETER);
6705 RT_UNTRUSTED_VALIDATED_FENCE();
6706 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
6707 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6708 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6709 VERR_INVALID_PARAMETER);
6710 RT_UNTRUSTED_VALIDATED_FENCE();
6711 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
6712
6713 /* Verify that cbWidth is less than scanline and fits into the GMR. */
6714 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
6715 AssertMsgReturn(cbGmrScanline != 0,
6716 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6717 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6718 VERR_INVALID_PARAMETER);
6719 RT_UNTRUSTED_VALIDATED_FENCE();
6720 AssertMsgReturn(cbWidth <= cbGmrScanline,
6721 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6722 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6723 VERR_INVALID_PARAMETER);
6724 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
6725 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6726 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6727 VERR_INVALID_PARAMETER);
6728 RT_UNTRUSTED_VALIDATED_FENCE();
6729
6730 /* How many bytes are available for the data in the GMR. */
6731 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
6732
6733 /* How many scanlines would fit into the available data. */
6734 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
6735 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
6736 if (cbWidth <= cbGmrLastScanline)
6737 ++cGmrScanlines;
6738
6739 if (cHeight > cGmrScanlines)
6740 cHeight = cGmrScanlines;
6741
6742 AssertMsgReturn(cHeight > 0,
6743 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
6744 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
6745 VERR_INVALID_PARAMETER);
6746 RT_UNTRUSTED_VALIDATED_FENCE();
6747
6748 /*
6749 * Host buffer.
6750 */
6751 AssertMsgReturn(offHst < cbHstBuf,
6752 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6753 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6754 VERR_INVALID_PARAMETER);
6755
6756 /* Verify that cbWidth is less than scanline and fits into the buffer. */
6757 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
6758 AssertMsgReturn(cbHstScanline != 0,
6759 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6760 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6761 VERR_INVALID_PARAMETER);
6762 AssertMsgReturn(cbWidth <= cbHstScanline,
6763 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6764 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6765 VERR_INVALID_PARAMETER);
6766 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
6767 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6768 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6769 VERR_INVALID_PARAMETER);
6770
6771 /* How many bytes are available for the data in the buffer. */
6772 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
6773
6774 /* How many scanlines would fit into the available data. */
6775 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
6776 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
6777 if (cbWidth <= cbHstLastScanline)
6778 ++cHstScanlines;
6779
6780 if (cHeight > cHstScanlines)
6781 cHeight = cHstScanlines;
6782
6783 AssertMsgReturn(cHeight > 0,
6784 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
6785 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
6786 VERR_INVALID_PARAMETER);
6787
6788 uint8_t *pbHst = pbHstBuf + offHst;
6789
6790 /* Shortcut for the framebuffer. */
6791 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
6792 {
6793 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
6794
6795 uint8_t const *pbSrc;
6796 int32_t cbSrcPitch;
6797 uint8_t *pbDst;
6798 int32_t cbDstPitch;
6799
6800 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
6801 {
6802 pbSrc = pbHst;
6803 cbSrcPitch = cbHstPitch;
6804 pbDst = pbGst;
6805 cbDstPitch = cbGstPitch;
6806 }
6807 else
6808 {
6809 pbSrc = pbGst;
6810 cbSrcPitch = cbGstPitch;
6811 pbDst = pbHst;
6812 cbDstPitch = cbHstPitch;
6813 }
6814
6815 if ( cbWidth == (uint32_t)cbGstPitch
6816 && cbGstPitch == cbHstPitch)
6817 {
6818 /* Entire scanlines, positive pitch. */
6819 memcpy(pbDst, pbSrc, cbWidth * cHeight);
6820 }
6821 else
6822 {
6823 for (uint32_t i = 0; i < cHeight; ++i)
6824 {
6825 memcpy(pbDst, pbSrc, cbWidth);
6826
6827 pbDst += cbDstPitch;
6828 pbSrc += cbSrcPitch;
6829 }
6830 }
6831 return VINF_SUCCESS;
6832 }
6833
6834 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
6835 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
6836
6837 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
6838 uint32_t iDesc = 0; /* Index in the descriptor array. */
6839 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
6840 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
6841 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
6842 for (uint32_t i = 0; i < cHeight; ++i)
6843 {
6844 uint32_t cbCurrentWidth = cbWidth;
6845 uint32_t offGmrCurrent = offGmrScanline;
6846 uint8_t *pbCurrentHost = pbHstScanline;
6847
6848 /* Find the right descriptor */
6849 while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
6850 {
6851 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6852 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
6853 ++iDesc;
6854 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6855 }
6856
6857 while (cbCurrentWidth)
6858 {
6859 uint32_t cbToCopy;
6860
6861 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
6862 {
6863 cbToCopy = cbCurrentWidth;
6864 }
6865 else
6866 {
6867 cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
6868 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
6869 }
6870
6871 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
6872
6873 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
6874
6875 /*
6876 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
6877 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
6878 * see @bugref{9654#c75}.
6879 */
6880 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
6881 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6882 else
6883 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
6884 AssertRCBreak(rc);
6885
6886 cbCurrentWidth -= cbToCopy;
6887 offGmrCurrent += cbToCopy;
6888 pbCurrentHost += cbToCopy;
6889
6890 /* Go to the next descriptor if there's anything left. */
6891 if (cbCurrentWidth)
6892 {
6893 offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
6894 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
6895 ++iDesc;
6896 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
6897 }
6898 }
6899
6900 offGmrScanline += cbGstPitch;
6901 pbHstScanline += cbHstPitch;
6902 }
6903
6904 return VINF_SUCCESS;
6905}
6906
6907
6908/**
6909 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
6910 *
6911 * @param pSizeSrc Source surface dimensions.
6912 * @param pSizeDest Destination surface dimensions.
6913 * @param pBox Coordinates to be clipped.
6914 */
6915void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
6916{
6917 /* Src x, w */
6918 if (pBox->srcx > pSizeSrc->width)
6919 pBox->srcx = pSizeSrc->width;
6920 if (pBox->w > pSizeSrc->width - pBox->srcx)
6921 pBox->w = pSizeSrc->width - pBox->srcx;
6922
6923 /* Src y, h */
6924 if (pBox->srcy > pSizeSrc->height)
6925 pBox->srcy = pSizeSrc->height;
6926 if (pBox->h > pSizeSrc->height - pBox->srcy)
6927 pBox->h = pSizeSrc->height - pBox->srcy;
6928
6929 /* Src z, d */
6930 if (pBox->srcz > pSizeSrc->depth)
6931 pBox->srcz = pSizeSrc->depth;
6932 if (pBox->d > pSizeSrc->depth - pBox->srcz)
6933 pBox->d = pSizeSrc->depth - pBox->srcz;
6934
6935 /* Dest x, w */
6936 if (pBox->x > pSizeDest->width)
6937 pBox->x = pSizeDest->width;
6938 if (pBox->w > pSizeDest->width - pBox->x)
6939 pBox->w = pSizeDest->width - pBox->x;
6940
6941 /* Dest y, h */
6942 if (pBox->y > pSizeDest->height)
6943 pBox->y = pSizeDest->height;
6944 if (pBox->h > pSizeDest->height - pBox->y)
6945 pBox->h = pSizeDest->height - pBox->y;
6946
6947 /* Dest z, d */
6948 if (pBox->z > pSizeDest->depth)
6949 pBox->z = pSizeDest->depth;
6950 if (pBox->d > pSizeDest->depth - pBox->z)
6951 pBox->d = pSizeDest->depth - pBox->z;
6952}
6953
6954
6955/**
6956 * Unsigned coordinates in pBox. Clip to [0; pSize).
6957 *
6958 * @param pSize Source surface dimensions.
6959 * @param pBox Coordinates to be clipped.
6960 */
6961void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
6962{
6963 /* x, w */
6964 if (pBox->x > pSize->width)
6965 pBox->x = pSize->width;
6966 if (pBox->w > pSize->width - pBox->x)
6967 pBox->w = pSize->width - pBox->x;
6968
6969 /* y, h */
6970 if (pBox->y > pSize->height)
6971 pBox->y = pSize->height;
6972 if (pBox->h > pSize->height - pBox->y)
6973 pBox->h = pSize->height - pBox->y;
6974
6975 /* z, d */
6976 if (pBox->z > pSize->depth)
6977 pBox->z = pSize->depth;
6978 if (pBox->d > pSize->depth - pBox->z)
6979 pBox->d = pSize->depth - pBox->z;
6980}
6981
6982
6983/**
6984 * Clip.
6985 *
6986 * @param pBound Bounding rectangle.
6987 * @param pRect Rectangle to be clipped.
6988 */
6989void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
6990{
6991 int32_t left;
6992 int32_t top;
6993 int32_t right;
6994 int32_t bottom;
6995
6996 /* Right order. */
6997 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
6998 if (pRect->left < pRect->right)
6999 {
7000 left = pRect->left;
7001 right = pRect->right;
7002 }
7003 else
7004 {
7005 left = pRect->right;
7006 right = pRect->left;
7007 }
7008 if (pRect->top < pRect->bottom)
7009 {
7010 top = pRect->top;
7011 bottom = pRect->bottom;
7012 }
7013 else
7014 {
7015 top = pRect->bottom;
7016 bottom = pRect->top;
7017 }
7018
7019 if (left < pBound->left)
7020 left = pBound->left;
7021 if (right < pBound->left)
7022 right = pBound->left;
7023
7024 if (left > pBound->right)
7025 left = pBound->right;
7026 if (right > pBound->right)
7027 right = pBound->right;
7028
7029 if (top < pBound->top)
7030 top = pBound->top;
7031 if (bottom < pBound->top)
7032 bottom = pBound->top;
7033
7034 if (top > pBound->bottom)
7035 top = pBound->bottom;
7036 if (bottom > pBound->bottom)
7037 bottom = pBound->bottom;
7038
7039 pRect->left = left;
7040 pRect->right = right;
7041 pRect->top = top;
7042 pRect->bottom = bottom;
7043}
7044
7045
7046/**
7047 * Clip.
7048 *
7049 * @param pBound Bounding rectangle.
7050 * @param pRect Rectangle to be clipped.
7051 */
7052void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
7053{
7054 uint32_t const leftBound = pBound->x;
7055 uint32_t const rightBound = pBound->x + pBound->w;
7056 uint32_t const topBound = pBound->y;
7057 uint32_t const bottomBound = pBound->y + pBound->h;
7058
7059 uint32_t x = pRect->x;
7060 uint32_t y = pRect->y;
7061 uint32_t w = pRect->w;
7062 uint32_t h = pRect->h;
7063
7064 /* Make sure that right and bottom coordinates can be safely computed. */
7065 if (x > rightBound)
7066 x = rightBound;
7067 if (w > rightBound - x)
7068 w = rightBound - x;
7069 if (y > bottomBound)
7070 y = bottomBound;
7071 if (h > bottomBound - y)
7072 h = bottomBound - y;
7073
7074 /* Switch from x, y, w, h to left, top, right, bottom. */
7075 uint32_t left = x;
7076 uint32_t right = x + w;
7077 uint32_t top = y;
7078 uint32_t bottom = y + h;
7079
7080 /* A standard left, right, bottom, top clipping. */
7081 if (left < leftBound)
7082 left = leftBound;
7083 if (right < leftBound)
7084 right = leftBound;
7085
7086 if (left > rightBound)
7087 left = rightBound;
7088 if (right > rightBound)
7089 right = rightBound;
7090
7091 if (top < topBound)
7092 top = topBound;
7093 if (bottom < topBound)
7094 bottom = topBound;
7095
7096 if (top > bottomBound)
7097 top = bottomBound;
7098 if (bottom > bottomBound)
7099 bottom = bottomBound;
7100
7101 /* Back to x, y, w, h representation. */
7102 pRect->x = left;
7103 pRect->y = top;
7104 pRect->w = right - left;
7105 pRect->h = bottom - top;
7106}
7107
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