DevVGA-SVGA.cpp@ 77958

Last change on this file since 77958 was 77958, checked in by vboxsync, 6 years ago
VMSVGA: Refined pitch lock handling, also reset FIFO on VM reset. See bugref:9424
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 292.9 KB

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1	/* $Id: DevVGA-SVGA.cpp 77958 2019-03-29 20:57:32Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	*/
12
13	/*
14	* Copyright (C) 2013-2019 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25
26	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
27	*
28	* This device emulation was contributed by trivirt AG. It offers an
29	* alternative to our Bochs based VGA graphics and 3d emulations. This is
30	* valuable for Xorg based guests, as there is driver support shipping with Xorg
31	* since it forked from XFree86.
32	*
33	*
34	* @section sec_dev_vmsvga_sdk The VMware SDK
35	*
36	* This is officially deprecated now, however it's still quite useful,
37	* especially for getting the old features working:
38	* http://vmware-svga.sourceforge.net/
39	*
40	* They currently point developers at the following resources.
41	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
42	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
43	* - http://cgit.freedesktop.org/mesa/vmwgfx/
44	*
45	* @subsection subsec_dev_vmsvga_sdk_results Test results
46	*
47	* Test results:
48	* - 2dmark.img:
49	* + todo
50	* - backdoor-tclo.img:
51	* + todo
52	* - blit-cube.img:
53	* + todo
54	* - bunnies.img:
55	* + todo
56	* - cube.img:
57	* + todo
58	* - cubemark.img:
59	* + todo
60	* - dynamic-vertex-stress.img:
61	* + todo
62	* - dynamic-vertex.img:
63	* + todo
64	* - fence-stress.img:
65	* + todo
66	* - gmr-test.img:
67	* + todo
68	* - half-float-test.img:
69	* + todo
70	* - noscreen-cursor.img:
71	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
72	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
73	* visible though.)
74	* - Cursor animation via the palette doesn't work.
75	* - During debugging, it turns out that the framebuffer content seems to
76	* be halfways ignore or something (memset(fb, 0xcc, lots)).
77	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
78	* grow it 0x10 fold (128KB -> 2MB like in WS10).
79	* - null.img:
80	* + todo
81	* - pong.img:
82	* + todo
83	* - presentReadback.img:
84	* + todo
85	* - resolution-set.img:
86	* + todo
87	* - rt-gamma-test.img:
88	* + todo
89	* - screen-annotation.img:
90	* + todo
91	* - screen-cursor.img:
92	* + todo
93	* - screen-dma-coalesce.img:
94	* + todo
95	* - screen-gmr-discontig.img:
96	* + todo
97	* - screen-gmr-remap.img:
98	* + todo
99	* - screen-multimon.img:
100	* + todo
101	* - screen-present-clip.img:
102	* + todo
103	* - screen-render-test.img:
104	* + todo
105	* - screen-simple.img:
106	* + todo
107	* - screen-text.img:
108	* + todo
109	* - simple-shaders.img:
110	* + todo
111	* - simple_blit.img:
112	* + todo
113	* - tiny-2d-updates.img:
114	* + todo
115	* - video-formats.img:
116	* + todo
117	* - video-sync.img:
118	* + todo
119	*
120	*/
121
122
123	/*********************************************************************************************************************************
124	* Header Files *
125	*********************************************************************************************************************************/
126	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
127	#define VMSVGA_USE_EMT_HALT_CODE
128	#include <VBox/vmm/pdmdev.h>
129	#include <VBox/version.h>
130	#include <VBox/err.h>
131	#include <VBox/log.h>
132	#include <VBox/vmm/pgm.h>
133	#ifdef VMSVGA_USE_EMT_HALT_CODE
134	# include <VBox/vmm/vmapi.h>
135	# include <VBox/vmm/vmcpuset.h>
136	#endif
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	# ifdef VBOX_STRICT
146	# include <iprt/time.h>
147	# endif
148	#endif
149
150	#include <VBox/AssertGuest.h>
151	#include <VBox/VMMDev.h>
152	#include <VBoxVideo.h>
153	#include <VBox/bioslogo.h>
154
155	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
156	#include "DevVGA.h"
157
158	#include "DevVGA-SVGA.h"
159	#include "vmsvga/svga_escape.h"
160	#include "vmsvga/svga_overlay.h"
161	#include "vmsvga/svga3d_caps.h"
162	#ifdef VBOX_WITH_VMSVGA3D
163	# include "DevVGA-SVGA3d.h"
164	# ifdef RT_OS_DARWIN
165	# include "DevVGA-SVGA3d-cocoa.h"
166	# endif
167	#endif
168
169
170	/*********************************************************************************************************************************
171	* Defined Constants And Macros *
172	*********************************************************************************************************************************/
173	/**
174	* Macro for checking if a fixed FIFO register is valid according to the
175	* current FIFO configuration.
176	*
177	* @returns true / false.
178	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
179	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
180	*/
181	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
182
183
184	/*********************************************************************************************************************************
185	* Structures and Typedefs *
186	*********************************************************************************************************************************/
187	/**
188	* 64-bit GMR descriptor.
189	*/
190	typedef struct
191	{
192	RTGCPHYS GCPhys;
193	uint64_t numPages;
194	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
195
196	/**
197	* GMR slot
198	*/
199	typedef struct
200	{
201	uint32_t cMaxPages;
202	uint32_t cbTotal;
203	uint32_t numDescriptors;
204	PVMSVGAGMRDESCRIPTOR paDesc;
205	} GMR, *PGMR;
206
207	#ifdef IN_RING3
208	/**
209	* Internal SVGA ring-3 only state.
210	*/
211	typedef struct VMSVGAR3STATE
212	{
213	GMR *paGMR; // [VMSVGAState::cGMR]
214	struct
215	{
216	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
217	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
218	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
219	} GMRFB;
220	struct
221	{
222	bool fActive;
223	uint32_t xHotspot;
224	uint32_t yHotspot;
225	uint32_t width;
226	uint32_t height;
227	uint32_t cbData;
228	void *pData;
229	} Cursor;
230	SVGAColorBGRX colorAnnotation;
231
232	# ifdef VMSVGA_USE_EMT_HALT_CODE
233	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
234	uint32_t volatile cBusyDelayedEmts;
235	/** Set of EMTs that are */
236	VMCPUSET BusyDelayedEmts;
237	# else
238	/** Number of EMTs waiting on hBusyDelayedEmts. */
239	uint32_t volatile cBusyDelayedEmts;
240	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
241	* busy (ugly). */
242	RTSEMEVENTMULTI hBusyDelayedEmts;
243	# endif
244
245	/** Information obout screens. */
246	VMSVGASCREENOBJECT aScreens[64];
247
248	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
249	STAMPROFILE StatBusyDelayEmts;
250
251	STAMPROFILE StatR3Cmd3dPresentProf;
252	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
253	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
254	STAMCOUNTER StatR3CmdDefineGmr2;
255	STAMCOUNTER StatR3CmdDefineGmr2Free;
256	STAMCOUNTER StatR3CmdDefineGmr2Modify;
257	STAMCOUNTER StatR3CmdRemapGmr2;
258	STAMCOUNTER StatR3CmdRemapGmr2Modify;
259	STAMCOUNTER StatR3CmdInvalidCmd;
260	STAMCOUNTER StatR3CmdFence;
261	STAMCOUNTER StatR3CmdUpdate;
262	STAMCOUNTER StatR3CmdUpdateVerbose;
263	STAMCOUNTER StatR3CmdDefineCursor;
264	STAMCOUNTER StatR3CmdDefineAlphaCursor;
265	STAMCOUNTER StatR3CmdEscape;
266	STAMCOUNTER StatR3CmdDefineScreen;
267	STAMCOUNTER StatR3CmdDestroyScreen;
268	STAMCOUNTER StatR3CmdDefineGmrFb;
269	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
270	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
271	STAMCOUNTER StatR3CmdAnnotationFill;
272	STAMCOUNTER StatR3CmdAnnotationCopy;
273	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
275	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
276	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
277	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
278	STAMCOUNTER StatR3Cmd3dSurfaceDma;
279	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
280	STAMCOUNTER StatR3Cmd3dContextDefine;
281	STAMCOUNTER StatR3Cmd3dContextDestroy;
282	STAMCOUNTER StatR3Cmd3dSetTransform;
283	STAMCOUNTER StatR3Cmd3dSetZRange;
284	STAMCOUNTER StatR3Cmd3dSetRenderState;
285	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
286	STAMCOUNTER StatR3Cmd3dSetTextureState;
287	STAMCOUNTER StatR3Cmd3dSetMaterial;
288	STAMCOUNTER StatR3Cmd3dSetLightData;
289	STAMCOUNTER StatR3Cmd3dSetLightEnable;
290	STAMCOUNTER StatR3Cmd3dSetViewPort;
291	STAMCOUNTER StatR3Cmd3dSetClipPlane;
292	STAMCOUNTER StatR3Cmd3dClear;
293	STAMCOUNTER StatR3Cmd3dPresent;
294	STAMCOUNTER StatR3Cmd3dPresentReadBack;
295	STAMCOUNTER StatR3Cmd3dShaderDefine;
296	STAMCOUNTER StatR3Cmd3dShaderDestroy;
297	STAMCOUNTER StatR3Cmd3dSetShader;
298	STAMCOUNTER StatR3Cmd3dSetShaderConst;
299	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
300	STAMCOUNTER StatR3Cmd3dSetScissorRect;
301	STAMCOUNTER StatR3Cmd3dBeginQuery;
302	STAMCOUNTER StatR3Cmd3dEndQuery;
303	STAMCOUNTER StatR3Cmd3dWaitForQuery;
304	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
305	STAMCOUNTER StatR3Cmd3dActivateSurface;
306	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
307
308	STAMCOUNTER StatR3RegConfigDoneWr;
309	STAMCOUNTER StatR3RegGmrDescriptorWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
311	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
312
313	STAMCOUNTER StatFifoCommands;
314	STAMCOUNTER StatFifoErrors;
315	STAMCOUNTER StatFifoUnkCmds;
316	STAMCOUNTER StatFifoTodoTimeout;
317	STAMCOUNTER StatFifoTodoWoken;
318	STAMPROFILE StatFifoStalls;
319	STAMPROFILE StatFifoExtendedSleep;
320	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
321	STAMCOUNTER StatFifoAccessHandler;
322	# endif
323	STAMCOUNTER StatFifoCursorFetchAgain;
324	STAMCOUNTER StatFifoCursorNoChange;
325	STAMCOUNTER StatFifoCursorPosition;
326	STAMCOUNTER StatFifoCursorVisiblity;
327	STAMCOUNTER StatFifoWatchdogWakeUps;
328	} VMSVGAR3STATE, *PVMSVGAR3STATE;
329	#endif /* IN_RING3 */
330
331
332	/*********************************************************************************************************************************
333	* Internal Functions *
334	*********************************************************************************************************************************/
335	#ifdef IN_RING3
336	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
337	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
338	# endif
339	# ifdef DEBUG_GMR_ACCESS
340	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
341	# endif
342	#endif
343
344
345	/*********************************************************************************************************************************
346	* Global Variables *
347	*********************************************************************************************************************************/
348	#ifdef IN_RING3
349
350	/**
351	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
352	*/
353	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
354	{
355	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
356	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
357	SSMFIELD_ENTRY_TERM()
358	};
359
360	/**
361	* SSM descriptor table for the GMR structure.
362	*/
363	static SSMFIELD const g_aGMRFields[] =
364	{
365	SSMFIELD_ENTRY( GMR, cMaxPages),
366	SSMFIELD_ENTRY( GMR, cbTotal),
367	SSMFIELD_ENTRY( GMR, numDescriptors),
368	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
369	SSMFIELD_ENTRY_TERM()
370	};
371
372	/**
373	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
374	*/
375	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
376	{
377	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
388	SSMFIELD_ENTRY_TERM()
389	};
390
391	/**
392	* SSM descriptor table for the VMSVGAR3STATE structure.
393	*/
394	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
395	{
396	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
397	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
404	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
407	#ifdef VMSVGA_USE_EMT_HALT_CODE
408	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
409	#else
410	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
411	#endif
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
469
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
474
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
482	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
484	# endif
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
489
490	SSMFIELD_ENTRY_TERM()
491	};
492
493	/**
494	* SSM descriptor table for the VGAState.svga structure.
495	*/
496	static SSMFIELD const g_aVGAStateSVGAFields[] =
497	{
498	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
504	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
507	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
508	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
509	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
510	SSMFIELD_ENTRY( VMSVGAState, fBusy),
511	SSMFIELD_ENTRY( VMSVGAState, fTraces),
512	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
513	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
514	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
517	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
518	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
519	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
520	SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
521	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
524	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
525	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
528	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
529	SSMFIELD_ENTRY( VMSVGAState, uWidth),
530	SSMFIELD_ENTRY( VMSVGAState, uHeight),
531	SSMFIELD_ENTRY( VMSVGAState, uBpp),
532	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
533	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
534	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
535	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
536	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
537	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
538	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
542	SSMFIELD_ENTRY_TERM()
543	};
544
545	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
546	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
547	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM);
548
549	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
550	{
551	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
552	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
553	&& pSVGAState
554	&& pSVGAState->aScreens[idScreen].fDefined)
555	{
556	return &pSVGAState->aScreens[idScreen];
557	}
558	return NULL;
559	}
560
561	#endif /* IN_RING3 */
562
563	#ifdef LOG_ENABLED
564
565	/**
566	* Index register string name lookup
567	*
568	* @returns Index register string or "UNKNOWN"
569	* @param pThis VMSVGA State
570	* @param idxReg The index register.
571	*/
572	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
573	{
574	switch (idxReg)
575	{
576	case SVGA_REG_ID: return "SVGA_REG_ID";
577	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
578	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
579	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
580	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
581	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
582	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
583	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
584	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
585	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
586	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
587	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
588	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
589	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
590	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
591	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
592	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
593	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
594	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
595	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
596	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
597	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
598	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
599	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
600	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
601	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
602	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
603	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
604	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
605	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
606	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
607	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
608	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
609	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
610	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
611	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
612	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
613	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
614	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
615	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
616	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
617	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
618	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
619	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
620	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
621	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
622	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
623	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
624	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
625	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
626
627	default:
628	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
629	return "SVGA_SCRATCH_BASE reg";
630	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
631	return "SVGA_PALETTE_BASE reg";
632	return "UNKNOWN";
633	}
634	}
635
636	#ifdef IN_RING3
637	/**
638	* FIFO command name lookup
639	*
640	* @returns FIFO command string or "UNKNOWN"
641	* @param u32Cmd FIFO command
642	*/
643	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
644	{
645	switch (u32Cmd)
646	{
647	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
648	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
649	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
650	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
651	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
652	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
653	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
654	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
655	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
656	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
657	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
658	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
659	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
660	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
661	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
662	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
663	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
664	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
665	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
666	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
667	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
668	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
669	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
670	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
671	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
672	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
673	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
674	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
675	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
676	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
677	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
678	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
679	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
680	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
681	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
682	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
683	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
684	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
685	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
686	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
687	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
688	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
689	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
690	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
691	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
692	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
693	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
694	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
695	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
696	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
697	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
698	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
699	default: return "UNKNOWN";
700	}
701	}
702	# endif /* IN_RING3 */
703
704	#endif /* LOG_ENABLED */
705
706	#ifdef IN_RING3
707	/**
708	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
709	*/
710	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
711	{
712	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
713
714	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
715	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
716
717	/** @todo Test how it interacts with multiple screen objects. */
718	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
719	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
720	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
721
722	if (x < uWidth)
723	{
724	pThis->svga.viewport.x = x;
725	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
726	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
727	}
728	else
729	{
730	pThis->svga.viewport.x = uWidth;
731	pThis->svga.viewport.cx = 0;
732	pThis->svga.viewport.xRight = uWidth;
733	}
734	if (y < uHeight)
735	{
736	pThis->svga.viewport.y = y;
737	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
738	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
739	pThis->svga.viewport.yHighWC = uHeight - y;
740	}
741	else
742	{
743	pThis->svga.viewport.y = uHeight;
744	pThis->svga.viewport.cy = 0;
745	pThis->svga.viewport.yLowWC = 0;
746	pThis->svga.viewport.yHighWC = 0;
747	}
748
749	# ifdef VBOX_WITH_VMSVGA3D
750	/*
751	* Now inform the 3D backend.
752	*/
753	if (pThis->svga.f3DEnabled)
754	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
755	# else
756	RT_NOREF(OldViewport);
757	# endif
758	}
759	#endif /* IN_RING3 */
760
761	/**
762	* Read port register
763	*
764	* @returns VBox status code.
765	* @param pThis VMSVGA State
766	* @param pu32 Where to store the read value
767	*/
768	PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
769	{
770	int rc = VINF_SUCCESS;
771	*pu32 = 0;
772
773	/* Rough index register validation. */
774	uint32_t idxReg = pThis->svga.u32IndexReg;
775	#if !defined(IN_RING3) && defined(VBOX_STRICT)
776	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
777	VINF_IOM_R3_IOPORT_READ);
778	#else
779	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
781	VINF_SUCCESS);
782	#endif
783	RT_UNTRUSTED_VALIDATED_FENCE();
784
785	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
786	if ( idxReg >= SVGA_REG_CAPABILITIES
787	&& pThis->svga.u32SVGAId == SVGA_ID_0)
788	{
789	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
790	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
791	}
792
793	switch (idxReg)
794	{
795	case SVGA_REG_ID:
796	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
797	*pu32 = pThis->svga.u32SVGAId;
798	break;
799
800	case SVGA_REG_ENABLE:
801	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
802	*pu32 = pThis->svga.fEnabled;
803	break;
804
805	case SVGA_REG_WIDTH:
806	{
807	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
808	if ( pThis->svga.fEnabled
809	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
810	{
811	*pu32 = pThis->svga.uWidth;
812	}
813	else
814	{
815	#ifndef IN_RING3
816	rc = VINF_IOM_R3_IOPORT_READ;
817	#else
818	*pu32 = pThis->pDrv->cx;
819	#endif
820	}
821	break;
822	}
823
824	case SVGA_REG_HEIGHT:
825	{
826	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
827	if ( pThis->svga.fEnabled
828	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
829	{
830	*pu32 = pThis->svga.uHeight;
831	}
832	else
833	{
834	#ifndef IN_RING3
835	rc = VINF_IOM_R3_IOPORT_READ;
836	#else
837	*pu32 = pThis->pDrv->cy;
838	#endif
839	}
840	break;
841	}
842
843	case SVGA_REG_MAX_WIDTH:
844	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
845	*pu32 = pThis->svga.u32MaxWidth;
846	break;
847
848	case SVGA_REG_MAX_HEIGHT:
849	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
850	*pu32 = pThis->svga.u32MaxHeight;
851	break;
852
853	case SVGA_REG_DEPTH:
854	/* This returns the color depth of the current mode. */
855	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
856	switch (pThis->svga.uBpp)
857	{
858	case 15:
859	case 16:
860	case 24:
861	*pu32 = pThis->svga.uBpp;
862	break;
863
864	default:
865	case 32:
866	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
867	break;
868	}
869	break;
870
871	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
872	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
873	if ( pThis->svga.fEnabled
874	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
875	{
876	*pu32 = pThis->svga.uBpp;
877	}
878	else
879	{
880	#ifndef IN_RING3
881	rc = VINF_IOM_R3_IOPORT_READ;
882	#else
883	*pu32 = pThis->pDrv->cBits;
884	#endif
885	}
886	break;
887
888	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
889	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
890	if ( pThis->svga.fEnabled
891	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
892	{
893	*pu32 = (pThis->svga.uBpp + 7) & ~7;
894	}
895	else
896	{
897	#ifndef IN_RING3
898	rc = VINF_IOM_R3_IOPORT_READ;
899	#else
900	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
901	#endif
902	}
903	break;
904
905	case SVGA_REG_PSEUDOCOLOR:
906	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
907	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
908	break;
909
910	case SVGA_REG_RED_MASK:
911	case SVGA_REG_GREEN_MASK:
912	case SVGA_REG_BLUE_MASK:
913	{
914	uint32_t uBpp;
915
916	if ( pThis->svga.fEnabled
917	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
918	{
919	uBpp = pThis->svga.uBpp;
920	}
921	else
922	{
923	#ifndef IN_RING3
924	rc = VINF_IOM_R3_IOPORT_READ;
925	break;
926	#else
927	uBpp = pThis->pDrv->cBits;
928	#endif
929	}
930	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
931	switch (uBpp)
932	{
933	case 8:
934	u32RedMask = 0x07;
935	u32GreenMask = 0x38;
936	u32BlueMask = 0xc0;
937	break;
938
939	case 15:
940	u32RedMask = 0x0000001f;
941	u32GreenMask = 0x000003e0;
942	u32BlueMask = 0x00007c00;
943	break;
944
945	case 16:
946	u32RedMask = 0x0000001f;
947	u32GreenMask = 0x000007e0;
948	u32BlueMask = 0x0000f800;
949	break;
950
951	case 24:
952	case 32:
953	default:
954	u32RedMask = 0x00ff0000;
955	u32GreenMask = 0x0000ff00;
956	u32BlueMask = 0x000000ff;
957	break;
958	}
959	switch (idxReg)
960	{
961	case SVGA_REG_RED_MASK:
962	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
963	*pu32 = u32RedMask;
964	break;
965
966	case SVGA_REG_GREEN_MASK:
967	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
968	*pu32 = u32GreenMask;
969	break;
970
971	case SVGA_REG_BLUE_MASK:
972	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
973	*pu32 = u32BlueMask;
974	break;
975	}
976	break;
977	}
978
979	case SVGA_REG_BYTES_PER_LINE:
980	{
981	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
982	if ( pThis->svga.fEnabled
983	&& pThis->svga.cbScanline)
984	{
985	*pu32 = pThis->svga.cbScanline;
986	}
987	else
988	{
989	#ifndef IN_RING3
990	rc = VINF_IOM_R3_IOPORT_READ;
991	#else
992	*pu32 = pThis->pDrv->cbScanline;
993	#endif
994	}
995	break;
996	}
997
998	case SVGA_REG_VRAM_SIZE: /* VRAM size */
999	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1000	*pu32 = pThis->vram_size;
1001	break;
1002
1003	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1004	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1005	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1006	*pu32 = pThis->GCPhysVRAM;
1007	break;
1008
1009	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1010	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1011	/* Always zero in our case. */
1012	*pu32 = 0;
1013	break;
1014
1015	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1016	{
1017	#ifndef IN_RING3
1018	rc = VINF_IOM_R3_IOPORT_READ;
1019	#else
1020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1021
1022	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1023	if ( pThis->svga.fEnabled
1024	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1025	{
1026	/* Hardware enabled; return real framebuffer size .*/
1027	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1028	}
1029	else
1030	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1031
1032	pu32 = RT_MIN(pThis->vram_size, pu32);
1033	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1034	#endif
1035	break;
1036	}
1037
1038	case SVGA_REG_CAPABILITIES:
1039	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1040	*pu32 = pThis->svga.u32RegCaps;
1041	break;
1042
1043	case SVGA_REG_MEM_START: /* FIFO start */
1044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1045	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1046	*pu32 = pThis->svga.GCPhysFIFO;
1047	break;
1048
1049	case SVGA_REG_MEM_SIZE: /* FIFO size */
1050	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1051	*pu32 = pThis->svga.cbFIFO;
1052	break;
1053
1054	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1055	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1056	*pu32 = pThis->svga.fConfigured;
1057	break;
1058
1059	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1060	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1061	*pu32 = 0;
1062	break;
1063
1064	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1065	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1066	if (pThis->svga.fBusy)
1067	{
1068	#ifndef IN_RING3
1069	/* Go to ring-3 and halt the CPU. */
1070	rc = VINF_IOM_R3_IOPORT_READ;
1071	break;
1072	#else
1073	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1074	/* The guest is basically doing a HLT via the device here, but with
1075	a special wake up condition on FIFO completion. */
1076	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1077	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1078	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1079	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1080	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1081	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1082	if (pThis->svga.fBusy)
1083	{
1084	PDMCritSectLeave(&pThis->CritSect); /* hack around lock order issue. */
1085	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1086	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1087	}
1088	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1089	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1090	# else
1091
1092	/* Delay the EMT a bit so the FIFO and others can get some work done.
1093	This used to be a crude 50 ms sleep. The current code tries to be
1094	more efficient, but the consept is still very crude. */
1095	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1096	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1097	RTThreadYield();
1098	if (pThis->svga.fBusy)
1099	{
1100	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1101
1102	if (pThis->svga.fBusy && cRefs == 1)
1103	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1104	if (pThis->svga.fBusy)
1105	{
1106	/** @todo If this code is going to stay, we need to call into the halt/wait
1107	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1108	* suffer when the guest is polling on a busy FIFO. */
1109	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1110	if (cNsMaxWait >= RT_NS_100US)
1111	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1112	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1113	RT_MIN(cNsMaxWait, RT_NS_10MS));
1114	}
1115
1116	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1117	}
1118	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1119	# endif
1120	*pu32 = pThis->svga.fBusy != 0;
1121	#endif
1122	}
1123	else
1124	*pu32 = false;
1125	break;
1126
1127	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1128	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1129	*pu32 = pThis->svga.u32GuestId;
1130	break;
1131
1132	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1134	*pu32 = pThis->svga.cScratchRegion;
1135	break;
1136
1137	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1139	*pu32 = SVGA_FIFO_NUM_REGS;
1140	break;
1141
1142	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1144	*pu32 = pThis->svga.u32PitchLock;
1145	break;
1146
1147	case SVGA_REG_IRQMASK: /* Interrupt mask */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1149	*pu32 = pThis->svga.u32IrqMask;
1150	break;
1151
1152	/* See "Guest memory regions" below. */
1153	case SVGA_REG_GMR_ID:
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1155	*pu32 = pThis->svga.u32CurrentGMRId;
1156	break;
1157
1158	case SVGA_REG_GMR_DESCRIPTOR:
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1160	/* Write only */
1161	*pu32 = 0;
1162	break;
1163
1164	case SVGA_REG_GMR_MAX_IDS:
1165	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1166	*pu32 = pThis->svga.cGMR;
1167	break;
1168
1169	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1171	*pu32 = VMSVGA_MAX_GMR_PAGES;
1172	break;
1173
1174	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1175	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1176	*pu32 = pThis->svga.fTraces;
1177	break;
1178
1179	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1180	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1181	*pu32 = VMSVGA_MAX_GMR_PAGES;
1182	break;
1183
1184	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1186	*pu32 = VMSVGA_SURFACE_SIZE;
1187	break;
1188
1189	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1191	break;
1192
1193	/* Mouse cursor support. */
1194	case SVGA_REG_CURSOR_ID:
1195	case SVGA_REG_CURSOR_X:
1196	case SVGA_REG_CURSOR_Y:
1197	case SVGA_REG_CURSOR_ON:
1198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1199	break;
1200
1201	/* Legacy multi-monitor support */
1202	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1204	*pu32 = 1;
1205	break;
1206
1207	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1208	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1209	*pu32 = 0;
1210	break;
1211
1212	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1214	*pu32 = 0;
1215	break;
1216
1217	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1219	*pu32 = 0;
1220	break;
1221
1222	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1223	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1224	*pu32 = 0;
1225	break;
1226
1227	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1228	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1229	*pu32 = pThis->svga.uWidth;
1230	break;
1231
1232	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1234	*pu32 = pThis->svga.uHeight;
1235	break;
1236
1237	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1239	/* We must return something sensible here otherwise the Linux driver
1240	will take a legacy code path without 3d support. This number also
1241	limits how many screens Linux guests will allow. */
1242	*pu32 = pThis->cMonitors;
1243	break;
1244
1245	default:
1246	{
1247	uint32_t offReg;
1248	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1249	{
1250	RT_UNTRUSTED_VALIDATED_FENCE();
1251	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1252	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1253	}
1254	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1255	{
1256	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1257	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1258	RT_UNTRUSTED_VALIDATED_FENCE();
1259	uint32_t u32 = pThis->last_palette[offReg / 3];
1260	switch (offReg % 3)
1261	{
1262	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1263	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1264	case 2: pu32 = u32 & 0xff; break; / blue */
1265	}
1266	}
1267	else
1268	{
1269	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1270	rc = VINF_IOM_R3_IOPORT_READ;
1271	#else
1272	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1273
1274	/* Do not assert. The guest might be reading all registers. */
1275	LogFunc(("Unknown reg=%#x\n", idxReg));
1276	#endif
1277	}
1278	break;
1279	}
1280	}
1281	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1282	return rc;
1283	}
1284
1285	#ifdef IN_RING3
1286	/**
1287	* Apply the current resolution settings to change the video mode.
1288	*
1289	* @returns VBox status code.
1290	* @param pThis VMSVGA State
1291	*/
1292	static int vmsvgaChangeMode(PVGASTATE pThis)
1293	{
1294	int rc;
1295
1296	/* Always do changemode on FIFO thread. */
1297	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1298
1299	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1300
1301	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1302
1303	if (pThis->svga.fGFBRegisters)
1304	{
1305	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1306	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1307	* deletes all screens other than screen #0, and redefines screen
1308	* #0 according to the specified mode. Drivers that use
1309	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1310	*/
1311
1312	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1313	pScreen->fDefined = true;
1314	pScreen->fModified = true;
1315	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1316	pScreen->idScreen = 0;
1317	pScreen->xOrigin = 0;
1318	pScreen->yOrigin = 0;
1319	pScreen->offVRAM = 0;
1320	pScreen->cbPitch = pThis->svga.cbScanline;
1321	pScreen->cWidth = pThis->svga.uWidth;
1322	pScreen->cHeight = pThis->svga.uHeight;
1323	pScreen->cBpp = pThis->svga.uBpp;
1324
1325	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1326	{
1327	/* Delete screen. */
1328	pScreen = &pSVGAState->aScreens[iScreen];
1329	if (pScreen->fDefined)
1330	{
1331	pScreen->fModified = true;
1332	pScreen->fDefined = false;
1333	}
1334	}
1335	}
1336	else
1337	{
1338	/* "If Screen Objects are supported, they can be used to fully
1339	* replace the functionality provided by the framebuffer registers
1340	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1341	*/
1342	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1343	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1344	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1345	}
1346
1347	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1348	{
1349	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1350	if (!pScreen->fModified)
1351	continue;
1352
1353	pScreen->fModified = false;
1354
1355	VBVAINFOVIEW view;
1356	RT_ZERO(view);
1357	view.u32ViewIndex = pScreen->idScreen;
1358	// view.u32ViewOffset = 0;
1359	view.u32ViewSize = pThis->vram_size;
1360	view.u32MaxScreenSize = pThis->vram_size;
1361
1362	VBVAINFOSCREEN screen;
1363	RT_ZERO(screen);
1364	screen.u32ViewIndex = pScreen->idScreen;
1365
1366	if (pScreen->fDefined)
1367	{
1368	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1369	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1370	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1371	{
1372	Assert(pThis->svga.fGFBRegisters);
1373	continue;
1374	}
1375
1376	screen.i32OriginX = pScreen->xOrigin;
1377	screen.i32OriginY = pScreen->yOrigin;
1378	screen.u32StartOffset = pScreen->offVRAM;
1379	screen.u32LineSize = pScreen->cbPitch;
1380	screen.u32Width = pScreen->cWidth;
1381	screen.u32Height = pScreen->cHeight;
1382	screen.u16BitsPerPixel = pScreen->cBpp;
1383	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1384	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1385	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1386	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1387	}
1388	else
1389	{
1390	/* Screen is destroyed. */
1391	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1392	}
1393
1394	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1395	AssertRC(rc);
1396	}
1397
1398	/* Last stuff. For the VGA device screenshot. */
1399	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1400	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1401	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1402	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1403	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1404
1405	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1406	if ( pThis->svga.viewport.cx == 0
1407	&& pThis->svga.viewport.cy == 0)
1408	{
1409	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1410	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1411	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1412	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1413	pThis->svga.viewport.yLowWC = 0;
1414	}
1415
1416	return VINF_SUCCESS;
1417	}
1418
1419	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1420	{
1421	if (pThis->svga.fGFBRegisters)
1422	{
1423	vgaR3UpdateDisplay(pThis, x, y, w, h);
1424	}
1425	else
1426	{
1427	VBVACMDHDR cmd;
1428	cmd.x = (int16_t)(pScreen->xOrigin + x);
1429	cmd.y = (int16_t)(pScreen->yOrigin + y);
1430	cmd.w = (uint16_t)w;
1431	cmd.h = (uint16_t)h;
1432
1433	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1434	pThis->pDrv->pfnVBVAUpdateProcess(pThis->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1435	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1436	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1437	}
1438
1439	return VINF_SUCCESS;
1440	}
1441
1442	#endif /* IN_RING3 */
1443
1444	#if defined(IN_RING0) \|\| defined(IN_RING3)
1445	/**
1446	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1447	*
1448	* @param pThis The VMSVGA state.
1449	* @param fState The busy state.
1450	*/
1451	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1452	{
1453	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1454
1455	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1456	{
1457	/* Race / unfortunately scheduling. Highly unlikly. */
1458	uint32_t cLoops = 64;
1459	do
1460	{
1461	ASMNopPause();
1462	fState = (pThis->svga.fBusy != 0);
1463	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1464	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1465	}
1466	}
1467
1468
1469	/**
1470	* Update the scanline pitch in response to the guest changing mode
1471	* width/bpp.
1472	*
1473	* @param pThis VMSVGA State
1474	*/
1475	DECLINLINE(void) vmsvgaUpdatePitch(PVGASTATE pThis)
1476	{
1477	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.CTX_SUFF(pFIFO);
1478	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1479	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1480	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1481
1482	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1483	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1484	* location but it has a different meaning.
1485	*/
1486	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1487	uFifoPitchLock = 0;
1488
1489	/* Sanitize values. */
1490	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1491	uFifoPitchLock = 0;
1492	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1493	uRegPitchLock = 0;
1494
1495	/* Prefer the register value to the FIFO value.*/
1496	if (uRegPitchLock)
1497	pThis->svga.cbScanline = uRegPitchLock;
1498	else if (uFifoPitchLock)
1499	pThis->svga.cbScanline = uFifoPitchLock;
1500	else
1501	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1502
1503	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1504	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1505	}
1506	#endif
1507
1508
1509	/**
1510	* Write port register
1511	*
1512	* @returns VBox status code.
1513	* @param pThis VMSVGA State
1514	* @param u32 Value to write
1515	*/
1516	PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1517	{
1518	#ifdef IN_RING3
1519	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1520	#endif
1521	int rc = VINF_SUCCESS;
1522
1523	/* Rough index register validation. */
1524	uint32_t idxReg = pThis->svga.u32IndexReg;
1525	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1526	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1527	VINF_IOM_R3_IOPORT_WRITE);
1528	#else
1529	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1530	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1531	VINF_SUCCESS);
1532	#endif
1533	RT_UNTRUSTED_VALIDATED_FENCE();
1534
1535	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1536	if ( idxReg >= SVGA_REG_CAPABILITIES
1537	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1538	{
1539	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1540	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1541	}
1542	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1543	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1544	switch (idxReg)
1545	{
1546	case SVGA_REG_WIDTH:
1547	case SVGA_REG_HEIGHT:
1548	case SVGA_REG_PITCHLOCK:
1549	case SVGA_REG_BITS_PER_PIXEL:
1550	pThis->svga.fGFBRegisters = true;
1551	break;
1552	default:
1553	break;
1554	}
1555
1556	switch (idxReg)
1557	{
1558	case SVGA_REG_ID:
1559	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1560	if ( u32 == SVGA_ID_0
1561	\|\| u32 == SVGA_ID_1
1562	\|\| u32 == SVGA_ID_2)
1563	pThis->svga.u32SVGAId = u32;
1564	else
1565	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1566	break;
1567
1568	case SVGA_REG_ENABLE:
1569	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1570	#ifdef IN_RING3
1571	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1572	&& pThis->svga.fEnabled == false)
1573	{
1574	/* Make a backup copy of the first 512kb in order to save font data etc. */
1575	/** @todo should probably swap here, rather than copy + zero */
1576	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1577	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1578	}
1579
1580	pThis->svga.fEnabled = u32;
1581	if (pThis->svga.fEnabled)
1582	{
1583	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1584	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1585	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1586	{
1587	/* Keep the current mode. */
1588	pThis->svga.uWidth = pThis->pDrv->cx;
1589	pThis->svga.uHeight = pThis->pDrv->cy;
1590	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1591	}
1592
1593	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1594	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1595	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1596	{
1597	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1598	}
1599	# ifdef LOG_ENABLED
1600	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1601	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1602	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1603	# endif
1604
1605	/* Disable or enable dirty page tracking according to the current fTraces value. */
1606	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1607
1608	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1609	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1610	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/, false /fRenderThreadMode/);
1611	}
1612	else
1613	{
1614	/* Restore the text mode backup. */
1615	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1616
1617	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1618
1619	/* Enable dirty page tracking again when going into legacy mode. */
1620	vmsvgaSetTraces(pThis, true);
1621
1622	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1623	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1624	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1625
1626	/* Clear the pitch lock. */
1627	pThis->svga.u32PitchLock = 0;
1628	}
1629	#else /* !IN_RING3 */
1630	rc = VINF_IOM_R3_IOPORT_WRITE;
1631	#endif /* !IN_RING3 */
1632	break;
1633
1634	case SVGA_REG_WIDTH:
1635	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1636	if (pThis->svga.uWidth != u32)
1637	{
1638	#if defined(IN_RING3) \|\| defined(IN_RING0)
1639	pThis->svga.uWidth = u32;
1640	vmsvgaUpdatePitch(pThis);
1641	if (pThis->svga.fEnabled)
1642	{
1643	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1644	}
1645	#else
1646	rc = VINF_IOM_R3_IOPORT_WRITE;
1647	#endif
1648	}
1649	/* else: nop */
1650	break;
1651
1652	case SVGA_REG_HEIGHT:
1653	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1654	if (pThis->svga.uHeight != u32)
1655	{
1656	pThis->svga.uHeight = u32;
1657	if (pThis->svga.fEnabled)
1658	{
1659	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1660	}
1661	}
1662	/* else: nop */
1663	break;
1664
1665	case SVGA_REG_DEPTH:
1666	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1667	/** @todo read-only?? */
1668	break;
1669
1670	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1671	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1672	if (pThis->svga.uBpp != u32)
1673	{
1674	#if defined(IN_RING3) \|\| defined(IN_RING0)
1675	pThis->svga.uBpp = u32;
1676	vmsvgaUpdatePitch(pThis);
1677	if (pThis->svga.fEnabled)
1678	{
1679	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1680	}
1681	#else
1682	rc = VINF_IOM_R3_IOPORT_WRITE;
1683	#endif
1684	}
1685	/* else: nop */
1686	break;
1687
1688	case SVGA_REG_PSEUDOCOLOR:
1689	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1690	break;
1691
1692	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1693	#ifdef IN_RING3
1694	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1695	pThis->svga.fConfigured = u32;
1696	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1697	if (!pThis->svga.fConfigured)
1698	{
1699	pThis->svga.fTraces = true;
1700	}
1701	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1702	#else
1703	rc = VINF_IOM_R3_IOPORT_WRITE;
1704	#endif
1705	break;
1706
1707	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1708	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1709	if ( pThis->svga.fEnabled
1710	&& pThis->svga.fConfigured)
1711	{
1712	#if defined(IN_RING3) \|\| defined(IN_RING0)
1713	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1714	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1715	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1716	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1717
1718	/* Kick the FIFO thread to start processing commands again. */
1719	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1720	#else
1721	rc = VINF_IOM_R3_IOPORT_WRITE;
1722	#endif
1723	}
1724	/* else nothing to do. */
1725	else
1726	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1727
1728	break;
1729
1730	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1731	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1732	break;
1733
1734	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1735	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1736	pThis->svga.u32GuestId = u32;
1737	break;
1738
1739	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1740	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1741	pThis->svga.u32PitchLock = u32;
1742	/* Should this also update the FIFO pitch lock? Unclear. */
1743	break;
1744
1745	case SVGA_REG_IRQMASK: /* Interrupt mask */
1746	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1747	pThis->svga.u32IrqMask = u32;
1748
1749	/* Irq pending after the above change? */
1750	if (pThis->svga.u32IrqStatus & u32)
1751	{
1752	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1753	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1754	}
1755	else
1756	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1757	break;
1758
1759	/* Mouse cursor support */
1760	case SVGA_REG_CURSOR_ID:
1761	case SVGA_REG_CURSOR_X:
1762	case SVGA_REG_CURSOR_Y:
1763	case SVGA_REG_CURSOR_ON:
1764	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1765	break;
1766
1767	/* Legacy multi-monitor support */
1768	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1769	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1770	break;
1771	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1772	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1773	break;
1774	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1775	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1776	break;
1777	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1778	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1779	break;
1780	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1781	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1782	break;
1783	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1784	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1785	break;
1786	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1787	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1788	break;
1789	#ifdef VBOX_WITH_VMSVGA3D
1790	/* See "Guest memory regions" below. */
1791	case SVGA_REG_GMR_ID:
1792	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1793	pThis->svga.u32CurrentGMRId = u32;
1794	break;
1795
1796	case SVGA_REG_GMR_DESCRIPTOR:
1797	# ifndef IN_RING3
1798	rc = VINF_IOM_R3_IOPORT_WRITE;
1799	break;
1800	# else /* IN_RING3 */
1801	{
1802	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1803
1804	/* Validate current GMR id. */
1805	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1806	AssertBreak(idGMR < pThis->svga.cGMR);
1807	RT_UNTRUSTED_VALIDATED_FENCE();
1808
1809	/* Free the old GMR if present. */
1810	vmsvgaGMRFree(pThis, idGMR);
1811
1812	/* Just undefine the GMR? */
1813	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1814	if (GCPhys == 0)
1815	{
1816	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1817	break;
1818	}
1819
1820
1821	/* Never cross a page boundary automatically. */
1822	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1823	uint32_t cPagesTotal = 0;
1824	uint32_t iDesc = 0;
1825	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1826	uint32_t cLoops = 0;
1827	RTGCPHYS GCPhysBase = GCPhys;
1828	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1829	{
1830	/* Read descriptor. */
1831	SVGAGuestMemDescriptor desc;
1832	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1833	AssertRCBreak(rc);
1834
1835	if (desc.numPages != 0)
1836	{
1837	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1838	cPagesTotal += desc.numPages;
1839	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1840
1841	if ((iDesc & 15) == 0)
1842	{
1843	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1844	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1845	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1846	}
1847
1848	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1849	paDescs[iDesc++].numPages = desc.numPages;
1850
1851	/* Continue with the next descriptor. */
1852	GCPhys += sizeof(desc);
1853	}
1854	else if (desc.ppn == 0)
1855	break; /* terminator */
1856	else /* Pointer to the next physical page of descriptors. */
1857	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1858
1859	cLoops++;
1860	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1861	}
1862
1863	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1864	if (RT_SUCCESS(rc))
1865	{
1866	/* Commit the GMR. */
1867	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1868	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1869	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1870	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1871	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1872	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1873	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1874	}
1875	else
1876	{
1877	RTMemFree(paDescs);
1878	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1879	}
1880	break;
1881	}
1882	# endif /* IN_RING3 */
1883	#endif // VBOX_WITH_VMSVGA3D
1884
1885	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1886	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1887	if (pThis->svga.fTraces == u32)
1888	break; /* nothing to do */
1889
1890	#ifdef IN_RING3
1891	vmsvgaSetTraces(pThis, !!u32);
1892	#else
1893	rc = VINF_IOM_R3_IOPORT_WRITE;
1894	#endif
1895	break;
1896
1897	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1898	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1899	break;
1900
1901	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1902	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1903	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1904	break;
1905
1906	case SVGA_REG_FB_START:
1907	case SVGA_REG_MEM_START:
1908	case SVGA_REG_HOST_BITS_PER_PIXEL:
1909	case SVGA_REG_MAX_WIDTH:
1910	case SVGA_REG_MAX_HEIGHT:
1911	case SVGA_REG_VRAM_SIZE:
1912	case SVGA_REG_FB_SIZE:
1913	case SVGA_REG_CAPABILITIES:
1914	case SVGA_REG_MEM_SIZE:
1915	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1916	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1917	case SVGA_REG_BYTES_PER_LINE:
1918	case SVGA_REG_FB_OFFSET:
1919	case SVGA_REG_RED_MASK:
1920	case SVGA_REG_GREEN_MASK:
1921	case SVGA_REG_BLUE_MASK:
1922	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1923	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1924	case SVGA_REG_GMR_MAX_IDS:
1925	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1926	/* Read only - ignore. */
1927	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1928	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1929	break;
1930
1931	default:
1932	{
1933	uint32_t offReg;
1934	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1935	{
1936	RT_UNTRUSTED_VALIDATED_FENCE();
1937	pThis->svga.au32ScratchRegion[offReg] = u32;
1938	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1939	}
1940	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1941	{
1942	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1943	Btw, see rgb_to_pixel32. */
1944	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1945	u32 &= 0xff;
1946	RT_UNTRUSTED_VALIDATED_FENCE();
1947	uint32_t uRgb = pThis->last_palette[offReg / 3];
1948	switch (offReg % 3)
1949	{
1950	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1951	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1952	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1953	}
1954	pThis->last_palette[offReg / 3] = uRgb;
1955	}
1956	else
1957	{
1958	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1959	rc = VINF_IOM_R3_IOPORT_WRITE;
1960	#else
1961	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1962	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1963	#endif
1964	}
1965	break;
1966	}
1967	}
1968	return rc;
1969	}
1970
1971	/**
1972	* Port I/O Handler for IN operations.
1973	*
1974	* @returns VINF_SUCCESS or VINF_EM_*.
1975	* @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1976	*
1977	* @param pDevIns The device instance.
1978	* @param pvUser User argument.
1979	* @param uPort Port number used for the IN operation.
1980	* @param pu32 Where to store the result. This is always a 32-bit
1981	* variable regardless of what @a cb might say.
1982	* @param cb Number of bytes read.
1983	*/
1984	PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
1985	{
1986	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1987	RT_NOREF_PV(pvUser);
1988
1989	/* Ignore non-dword accesses. */
1990	if (cb != 4)
1991	{
1992	Log(("Ignoring non-dword read at %x cb=%d\n", uPort, cb));
1993	*pu32 = UINT32_MAX;
1994	return VINF_SUCCESS;
1995	}
1996
1997	switch (uPort - pThis->svga.BasePort)
1998	{
1999	case SVGA_INDEX_PORT:
2000	*pu32 = pThis->svga.u32IndexReg;
2001	break;
2002
2003	case SVGA_VALUE_PORT:
2004	return vmsvgaReadPort(pThis, pu32);
2005
2006	case SVGA_BIOS_PORT:
2007	Log(("Ignoring BIOS port read\n"));
2008	*pu32 = 0;
2009	break;
2010
2011	case SVGA_IRQSTATUS_PORT:
2012	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2013	*pu32 = pThis->svga.u32IrqStatus;
2014	break;
2015
2016	default:
2017	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u (%#x) was read from.\n", uPort - pThis->svga.BasePort, uPort));
2018	*pu32 = UINT32_MAX;
2019	break;
2020	}
2021
2022	return VINF_SUCCESS;
2023	}
2024
2025	/**
2026	* Port I/O Handler for OUT operations.
2027	*
2028	* @returns VINF_SUCCESS or VINF_EM_*.
2029	*
2030	* @param pDevIns The device instance.
2031	* @param pvUser User argument.
2032	* @param uPort Port number used for the OUT operation.
2033	* @param u32 The value to output.
2034	* @param cb The value size in bytes.
2035	*/
2036	PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
2037	{
2038	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2039	RT_NOREF_PV(pvUser);
2040
2041	/* Ignore non-dword accesses. */
2042	if (cb != 4)
2043	{
2044	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", uPort, u32, cb));
2045	return VINF_SUCCESS;
2046	}
2047
2048	switch (uPort - pThis->svga.BasePort)
2049	{
2050	case SVGA_INDEX_PORT:
2051	pThis->svga.u32IndexReg = u32;
2052	break;
2053
2054	case SVGA_VALUE_PORT:
2055	return vmsvgaWritePort(pThis, u32);
2056
2057	case SVGA_BIOS_PORT:
2058	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2059	break;
2060
2061	case SVGA_IRQSTATUS_PORT:
2062	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2063	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2064	/* Clear the irq in case all events have been cleared. */
2065	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2066	{
2067	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2068	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2069	}
2070	break;
2071
2072	default:
2073	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u (%#x) was written to, value %#x LB %u.\n",
2074	uPort - pThis->svga.BasePort, uPort, u32, cb));
2075	break;
2076	}
2077	return VINF_SUCCESS;
2078	}
2079
2080	#ifdef IN_RING3
2081
2082	# ifdef DEBUG_FIFO_ACCESS
2083	/**
2084	* Handle FIFO memory access.
2085	* @returns VBox status code.
2086	* @param pVM VM handle.
2087	* @param pThis VGA device instance data.
2088	* @param GCPhys The access physical address.
2089	* @param fWriteAccess Read or write access
2090	*/
2091	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2092	{
2093	RT_NOREF(pVM);
2094	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2095	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2096
2097	switch (GCPhysOffset >> 2)
2098	{
2099	case SVGA_FIFO_MIN:
2100	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2101	break;
2102	case SVGA_FIFO_MAX:
2103	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2104	break;
2105	case SVGA_FIFO_NEXT_CMD:
2106	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2107	break;
2108	case SVGA_FIFO_STOP:
2109	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2110	break;
2111	case SVGA_FIFO_CAPABILITIES:
2112	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2113	break;
2114	case SVGA_FIFO_FLAGS:
2115	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2116	break;
2117	case SVGA_FIFO_FENCE:
2118	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2119	break;
2120	case SVGA_FIFO_3D_HWVERSION:
2121	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2122	break;
2123	case SVGA_FIFO_PITCHLOCK:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_CURSOR_ON:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_CURSOR_X:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_CURSOR_Y:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_CURSOR_COUNT:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_RESERVED:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_CURSOR_SCREEN_ID:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_DEAD:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_3D_HWVERSION_REVISED:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2181	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2182	break;
2183	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2184	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2185	break;
2186	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2187	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2188	break;
2189	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2190	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2191	break;
2192	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2193	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2194	break;
2195	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2196	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2197	break;
2198	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2199	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2200	break;
2201	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2202	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2203	break;
2204	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2205	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2206	break;
2207	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2208	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2209	break;
2210	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2211	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2212	break;
2213	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2214	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2215	break;
2216	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2217	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2218	break;
2219	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2220	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2221	break;
2222	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2223	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2224	break;
2225	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2226	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2227	break;
2228	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2229	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2230	break;
2231	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2232	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2233	break;
2234	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2235	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2236	break;
2237	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2238	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2239	break;
2240	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2241	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2242	break;
2243	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2244	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2245	break;
2246	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2247	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2248	break;
2249	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2250	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2251	break;
2252	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2253	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2254	break;
2255	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2256	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2257	break;
2258	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2259	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2260	break;
2261	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2262	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2263	break;
2264	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2265	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2266	break;
2267	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2268	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2269	break;
2270	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2271	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2272	break;
2273	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2364	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2365	break;
2366	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2367	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2368	break;
2369	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2370	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2371	break;
2372	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2373	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2374	break;
2375	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2376	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2377	break;
2378	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2379	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2380	break;
2381	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2382	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2383	break;
2384	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2385	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2386	break;
2387	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2388	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2389	break;
2390	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2391	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2392	break;
2393	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2394	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2395	break;
2396	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2397	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2398	break;
2399	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2400	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2401	break;
2402	case SVGA_FIFO_3D_CAPS_LAST:
2403	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2404	break;
2405	case SVGA_FIFO_GUEST_3D_HWVERSION:
2406	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2407	break;
2408	case SVGA_FIFO_FENCE_GOAL:
2409	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2410	break;
2411	case SVGA_FIFO_BUSY:
2412	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2413	break;
2414	default:
2415	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2416	break;
2417	}
2418
2419	return VINF_EM_RAW_EMULATE_INSTR;
2420	}
2421	# endif /* DEBUG_FIFO_ACCESS */
2422
2423	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2424	/**
2425	* HC access handler for the FIFO.
2426	*
2427	* @returns VINF_SUCCESS if the handler have carried out the operation.
2428	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2429	* @param pVM VM Handle.
2430	* @param pVCpu The cross context CPU structure for the calling EMT.
2431	* @param GCPhys The physical address the guest is writing to.
2432	* @param pvPhys The HC mapping of that address.
2433	* @param pvBuf What the guest is reading/writing.
2434	* @param cbBuf How much it's reading/writing.
2435	* @param enmAccessType The access type.
2436	* @param enmOrigin Who is making the access.
2437	* @param pvUser User argument.
2438	*/
2439	static DECLCALLBACK(VBOXSTRICTRC)
2440	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2441	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2442	{
2443	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2444	PVGASTATE pThis = (PVGASTATE)pvUser;
2445	AssertPtr(pThis);
2446
2447	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2448	/*
2449	* Wake up the FIFO thread as it might have work to do now.
2450	*/
2451	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2452	AssertLogRelRC(rc);
2453	# endif
2454
2455	# ifdef DEBUG_FIFO_ACCESS
2456	/*
2457	* When in debug-fifo-access mode, we do not disable the access handler,
2458	* but leave it on as we wish to catch all access.
2459	*/
2460	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2461	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2462	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2463	/*
2464	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2465	*/
2466	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2467	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2468	# endif
2469	if (RT_SUCCESS(rc))
2470	return VINF_PGM_HANDLER_DO_DEFAULT;
2471	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2472	return rc;
2473	}
2474	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2475
2476	#endif /* IN_RING3 */
2477
2478	#ifdef DEBUG_GMR_ACCESS
2479	# ifdef IN_RING3
2480
2481	/**
2482	* HC access handler for the FIFO.
2483	*
2484	* @returns VINF_SUCCESS if the handler have carried out the operation.
2485	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2486	* @param pVM VM Handle.
2487	* @param pVCpu The cross context CPU structure for the calling EMT.
2488	* @param GCPhys The physical address the guest is writing to.
2489	* @param pvPhys The HC mapping of that address.
2490	* @param pvBuf What the guest is reading/writing.
2491	* @param cbBuf How much it's reading/writing.
2492	* @param enmAccessType The access type.
2493	* @param enmOrigin Who is making the access.
2494	* @param pvUser User argument.
2495	*/
2496	static DECLCALLBACK(VBOXSTRICTRC)
2497	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2498	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2499	{
2500	PVGASTATE pThis = (PVGASTATE)pvUser;
2501	Assert(pThis);
2502	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2503	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2504
2505	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2506
2507	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2508	{
2509	PGMR pGMR = &pSVGAState->paGMR[i];
2510
2511	if (pGMR->numDescriptors)
2512	{
2513	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2514	{
2515	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2516	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2517	{
2518	/*
2519	* Turn off the write handler for this particular page and make it R/W.
2520	* Then return telling the caller to restart the guest instruction.
2521	*/
2522	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2523	AssertRC(rc);
2524	goto end;
2525	}
2526	}
2527	}
2528	}
2529	end:
2530	return VINF_PGM_HANDLER_DO_DEFAULT;
2531	}
2532
2533	/* Callback handler for VMR3ReqCallWaitU */
2534	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2535	{
2536	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2537	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2538	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2539	int rc;
2540
2541	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2542	{
2543	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2544	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2545	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2546	AssertRC(rc);
2547	}
2548	return VINF_SUCCESS;
2549	}
2550
2551	/* Callback handler for VMR3ReqCallWaitU */
2552	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2553	{
2554	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2555	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2556	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2557
2558	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2559	{
2560	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2561	AssertRC(rc);
2562	}
2563	return VINF_SUCCESS;
2564	}
2565
2566	/* Callback handler for VMR3ReqCallWaitU */
2567	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2568	{
2569	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2570
2571	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2572	{
2573	PGMR pGMR = &pSVGAState->paGMR[i];
2574
2575	if (pGMR->numDescriptors)
2576	{
2577	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2578	{
2579	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2580	AssertRC(rc);
2581	}
2582	}
2583	}
2584	return VINF_SUCCESS;
2585	}
2586
2587	# endif /* IN_RING3 */
2588	#endif /* DEBUG_GMR_ACCESS */
2589
2590	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2591
2592	#ifdef IN_RING3
2593
2594
2595	/**
2596	* Common worker for changing the pointer shape.
2597	*
2598	* @param pThis The VGA instance data.
2599	* @param pSVGAState The VMSVGA ring-3 instance data.
2600	* @param fAlpha Whether there is alpha or not.
2601	* @param xHot Hotspot x coordinate.
2602	* @param yHot Hotspot y coordinate.
2603	* @param cx Width.
2604	* @param cy Height.
2605	* @param pbData Heap copy of the cursor data. Consumed.
2606	* @param cbData The size of the data.
2607	*/
2608	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2609	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2610	{
2611	Log(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2612	#ifdef LOG_ENABLED
2613	if (LogIs2Enabled())
2614	{
2615	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2616	if (!fAlpha)
2617	{
2618	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2619	for (uint32_t y = 0; y < cy; y++)
2620	{
2621	Log2(("%3u:", y));
2622	uint8_t const pbLine = &pbData[y cbAndLine];
2623	for (uint32_t x = 0; x < cx; x += 8)
2624	{
2625	uint8_t b = pbLine[x / 8];
2626	char szByte[12];
2627	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2628	szByte[1] = b & 0x40 ? '*' : ' ';
2629	szByte[2] = b & 0x20 ? '*' : ' ';
2630	szByte[3] = b & 0x10 ? '*' : ' ';
2631	szByte[4] = b & 0x08 ? '*' : ' ';
2632	szByte[5] = b & 0x04 ? '*' : ' ';
2633	szByte[6] = b & 0x02 ? '*' : ' ';
2634	szByte[7] = b & 0x01 ? '*' : ' ';
2635	szByte[8] = '\0';
2636	Log2(("%s", szByte));
2637	}
2638	Log2(("\n"));
2639	}
2640	}
2641
2642	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2643	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2644	for (uint32_t y = 0; y < cy; y++)
2645	{
2646	Log2(("%3u:", y));
2647	uint32_t const pu32Line = &pu32Xor[y cx];
2648	for (uint32_t x = 0; x < cx; x++)
2649	Log2((" %08x", pu32Line[x]));
2650	Log2(("\n"));
2651	}
2652	}
2653	#endif
2654
2655	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2656	AssertRC(rc);
2657
2658	if (pSVGAState->Cursor.fActive)
2659	RTMemFree(pSVGAState->Cursor.pData);
2660
2661	pSVGAState->Cursor.fActive = true;
2662	pSVGAState->Cursor.xHotspot = xHot;
2663	pSVGAState->Cursor.yHotspot = yHot;
2664	pSVGAState->Cursor.width = cx;
2665	pSVGAState->Cursor.height = cy;
2666	pSVGAState->Cursor.cbData = cbData;
2667	pSVGAState->Cursor.pData = pbData;
2668	}
2669
2670
2671	/**
2672	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2673	*
2674	* @param pThis The VGA instance data.
2675	* @param pSVGAState The VMSVGA ring-3 instance data.
2676	* @param pCursor The cursor.
2677	* @param pbSrcAndMask The AND mask.
2678	* @param cbSrcAndLine The scanline length of the AND mask.
2679	* @param pbSrcXorMask The XOR mask.
2680	* @param cbSrcXorLine The scanline length of the XOR mask.
2681	*/
2682	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2683	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2684	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2685	{
2686	uint32_t const cx = pCursor->width;
2687	uint32_t const cy = pCursor->height;
2688
2689	/*
2690	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2691	* The AND data uses 8-bit aligned scanlines.
2692	* The XOR data must be starting on a 32-bit boundrary.
2693	*/
2694	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2695	uint32_t cbDstAndMask = cbDstAndLine * cy;
2696	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2697	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2698
2699	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2700	AssertReturnVoid(pbCopy);
2701
2702	/* Convert the AND mask. */
2703	uint8_t *pbDst = pbCopy;
2704	uint8_t const *pbSrc = pbSrcAndMask;
2705	switch (pCursor->andMaskDepth)
2706	{
2707	case 1:
2708	if (cbSrcAndLine == cbDstAndLine)
2709	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2710	else
2711	{
2712	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2713	for (uint32_t y = 0; y < cy; y++)
2714	{
2715	memcpy(pbDst, pbSrc, cbDstAndLine);
2716	pbDst += cbDstAndLine;
2717	pbSrc += cbSrcAndLine;
2718	}
2719	}
2720	break;
2721	/* Should take the XOR mask into account for the multi-bit AND mask. */
2722	case 8:
2723	for (uint32_t y = 0; y < cy; y++)
2724	{
2725	for (uint32_t x = 0; x < cx; )
2726	{
2727	uint8_t bDst = 0;
2728	uint8_t fBit = 1;
2729	do
2730	{
2731	uintptr_t const idxPal = pbSrc[x] * 3;
2732	if ((( pThis->last_palette[idxPal]
2733	\| (pThis->last_palette[idxPal] >> 8)
2734	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2735	bDst \|= fBit;
2736	fBit <<= 1;
2737	x++;
2738	} while (x < cx && (x & 7));
2739	pbDst[(x - 1) / 8] = bDst;
2740	}
2741	pbDst += cbDstAndLine;
2742	pbSrc += cbSrcAndLine;
2743	}
2744	break;
2745	case 15:
2746	for (uint32_t y = 0; y < cy; y++)
2747	{
2748	for (uint32_t x = 0; x < cx; )
2749	{
2750	uint8_t bDst = 0;
2751	uint8_t fBit = 1;
2752	do
2753	{
2754	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2755	bDst \|= fBit;
2756	fBit <<= 1;
2757	x++;
2758	} while (x < cx && (x & 7));
2759	pbDst[(x - 1) / 8] = bDst;
2760	}
2761	pbDst += cbDstAndLine;
2762	pbSrc += cbSrcAndLine;
2763	}
2764	break;
2765	case 16:
2766	for (uint32_t y = 0; y < cy; y++)
2767	{
2768	for (uint32_t x = 0; x < cx; )
2769	{
2770	uint8_t bDst = 0;
2771	uint8_t fBit = 1;
2772	do
2773	{
2774	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2775	bDst \|= fBit;
2776	fBit <<= 1;
2777	x++;
2778	} while (x < cx && (x & 7));
2779	pbDst[(x - 1) / 8] = bDst;
2780	}
2781	pbDst += cbDstAndLine;
2782	pbSrc += cbSrcAndLine;
2783	}
2784	break;
2785	case 24:
2786	for (uint32_t y = 0; y < cy; y++)
2787	{
2788	for (uint32_t x = 0; x < cx; )
2789	{
2790	uint8_t bDst = 0;
2791	uint8_t fBit = 1;
2792	do
2793	{
2794	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2795	bDst \|= fBit;
2796	fBit <<= 1;
2797	x++;
2798	} while (x < cx && (x & 7));
2799	pbDst[(x - 1) / 8] = bDst;
2800	}
2801	pbDst += cbDstAndLine;
2802	pbSrc += cbSrcAndLine;
2803	}
2804	break;
2805	case 32:
2806	for (uint32_t y = 0; y < cy; y++)
2807	{
2808	for (uint32_t x = 0; x < cx; )
2809	{
2810	uint8_t bDst = 0;
2811	uint8_t fBit = 1;
2812	do
2813	{
2814	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2815	bDst \|= fBit;
2816	fBit <<= 1;
2817	x++;
2818	} while (x < cx && (x & 7));
2819	pbDst[(x - 1) / 8] = bDst;
2820	}
2821	pbDst += cbDstAndLine;
2822	pbSrc += cbSrcAndLine;
2823	}
2824	break;
2825	default:
2826	RTMemFree(pbCopy);
2827	AssertFailedReturnVoid();
2828	}
2829
2830	/* Convert the XOR mask. */
2831	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2832	pbSrc = pbSrcXorMask;
2833	switch (pCursor->xorMaskDepth)
2834	{
2835	case 1:
2836	for (uint32_t y = 0; y < cy; y++)
2837	{
2838	for (uint32_t x = 0; x < cx; )
2839	{
2840	/* most significant bit is the left most one. */
2841	uint8_t bSrc = pbSrc[x / 8];
2842	do
2843	{
2844	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2845	bSrc <<= 1;
2846	x++;
2847	} while ((x & 7) && x < cx);
2848	}
2849	pbSrc += cbSrcXorLine;
2850	}
2851	break;
2852	case 8:
2853	for (uint32_t y = 0; y < cy; y++)
2854	{
2855	for (uint32_t x = 0; x < cx; x++)
2856	{
2857	uint32_t u = pThis->last_palette[pbSrc[x]];
2858	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2859	}
2860	pbSrc += cbSrcXorLine;
2861	}
2862	break;
2863	case 15: /* Src: RGB-5-5-5 */
2864	for (uint32_t y = 0; y < cy; y++)
2865	{
2866	for (uint32_t x = 0; x < cx; x++)
2867	{
2868	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2869	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2870	((uValue >> 5) & 0x1f) << 3,
2871	((uValue >> 10) & 0x1f) << 3, 0);
2872	}
2873	pbSrc += cbSrcXorLine;
2874	}
2875	break;
2876	case 16: /* Src: RGB-5-6-5 */
2877	for (uint32_t y = 0; y < cy; y++)
2878	{
2879	for (uint32_t x = 0; x < cx; x++)
2880	{
2881	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2882	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2883	((uValue >> 5) & 0x3f) << 2,
2884	((uValue >> 11) & 0x1f) << 3, 0);
2885	}
2886	pbSrc += cbSrcXorLine;
2887	}
2888	break;
2889	case 24:
2890	for (uint32_t y = 0; y < cy; y++)
2891	{
2892	for (uint32_t x = 0; x < cx; x++)
2893	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2894	pbSrc += cbSrcXorLine;
2895	}
2896	break;
2897	case 32:
2898	for (uint32_t y = 0; y < cy; y++)
2899	{
2900	for (uint32_t x = 0; x < cx; x++)
2901	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2902	pbSrc += cbSrcXorLine;
2903	}
2904	break;
2905	default:
2906	RTMemFree(pbCopy);
2907	AssertFailedReturnVoid();
2908	}
2909
2910	/*
2911	* Pass it to the frontend/whatever.
2912	*/
2913	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2914	}
2915
2916
2917	/**
2918	* Worker for vmsvgaR3FifoThread that handles an external command.
2919	*
2920	* @param pThis VGA device instance data.
2921	*/
2922	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2923	{
2924	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2925	switch (pThis->svga.u8FIFOExtCommand)
2926	{
2927	case VMSVGA_FIFO_EXTCMD_RESET:
2928	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2929	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2930	# ifdef VBOX_WITH_VMSVGA3D
2931	if (pThis->svga.f3DEnabled)
2932	{
2933	/* The 3d subsystem must be reset from the fifo thread. */
2934	vmsvga3dReset(pThis);
2935	}
2936	# endif
2937	break;
2938
2939	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2940	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2941	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2942	# ifdef VBOX_WITH_VMSVGA3D
2943	if (pThis->svga.f3DEnabled)
2944	{
2945	/* The 3d subsystem must be shut down from the fifo thread. */
2946	vmsvga3dTerminate(pThis);
2947	}
2948	# endif
2949	break;
2950
2951	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2952	{
2953	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2954	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2955	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2956	vmsvgaSaveExecFifo(pThis, pSSM);
2957	# ifdef VBOX_WITH_VMSVGA3D
2958	if (pThis->svga.f3DEnabled)
2959	vmsvga3dSaveExec(pThis, pSSM);
2960	# endif
2961	break;
2962	}
2963
2964	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2965	{
2966	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2967	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2968	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2969	vmsvgaLoadExecFifo(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2970	# ifdef VBOX_WITH_VMSVGA3D
2971	if (pThis->svga.f3DEnabled)
2972	vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2973	# endif
2974	break;
2975	}
2976
2977	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2978	{
2979	# ifdef VBOX_WITH_VMSVGA3D
2980	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2981	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2982	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2983	# endif
2984	break;
2985	}
2986
2987
2988	default:
2989	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2990	break;
2991	}
2992
2993	/*
2994	* Signal the end of the external command.
2995	*/
2996	pThis->svga.pvFIFOExtCmdParam = NULL;
2997	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2998	ASMMemoryFence(); /* paranoia^2 */
2999	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
3000	AssertLogRelRC(rc);
3001	}
3002
3003	/**
3004	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3005	* doing a job on the FIFO thread (even when it's officially suspended).
3006	*
3007	* @returns VBox status code (fully asserted).
3008	* @param pThis VGA device instance data.
3009	* @param uExtCmd The command to execute on the FIFO thread.
3010	* @param pvParam Pointer to command parameters.
3011	* @param cMsWait The time to wait for the command, given in
3012	* milliseconds.
3013	*/
3014	static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3015	{
3016	Assert(cMsWait >= RT_MS_1SEC * 5);
3017	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3018	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3019
3020	int rc;
3021	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
3022	PDMTHREADSTATE enmState = pThread->enmState;
3023	if (enmState == PDMTHREADSTATE_SUSPENDED)
3024	{
3025	/*
3026	* The thread is suspended, we have to temporarily wake it up so it can
3027	* perform the task.
3028	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3029	*/
3030	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3031	/* Post the request. */
3032	pThis->svga.fFifoExtCommandWakeup = true;
3033	pThis->svga.pvFIFOExtCmdParam = pvParam;
3034	pThis->svga.u8FIFOExtCommand = uExtCmd;
3035	ASMMemoryFence(); /* paranoia^3 */
3036
3037	/* Resume the thread. */
3038	rc = PDMR3ThreadResume(pThread);
3039	AssertLogRelRC(rc);
3040	if (RT_SUCCESS(rc))
3041	{
3042	/* Wait. Take care in case the semaphore was already posted (same as below). */
3043	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3044	if ( rc == VINF_SUCCESS
3045	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3046	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3047	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3048	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3049
3050	/* suspend the thread */
3051	pThis->svga.fFifoExtCommandWakeup = false;
3052	int rc2 = PDMR3ThreadSuspend(pThread);
3053	AssertLogRelRC(rc2);
3054	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3055	rc = rc2;
3056	}
3057	pThis->svga.fFifoExtCommandWakeup = false;
3058	pThis->svga.pvFIFOExtCmdParam = NULL;
3059	}
3060	else if (enmState == PDMTHREADSTATE_RUNNING)
3061	{
3062	/*
3063	* The thread is running, should only happen during reset and vmsvga3dsfc.
3064	* We ASSUME not racing code here, both wrt thread state and ext commands.
3065	*/
3066	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3067	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3068
3069	/* Post the request. */
3070	pThis->svga.pvFIFOExtCmdParam = pvParam;
3071	pThis->svga.u8FIFOExtCommand = uExtCmd;
3072	ASMMemoryFence(); /* paranoia^2 */
3073	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3074	AssertLogRelRC(rc);
3075
3076	/* Wait. Take care in case the semaphore was already posted (same as above). */
3077	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3078	if ( rc == VINF_SUCCESS
3079	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3080	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3081	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3082	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3083
3084	pThis->svga.pvFIFOExtCmdParam = NULL;
3085	}
3086	else
3087	{
3088	/*
3089	* Something is wrong with the thread!
3090	*/
3091	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3092	rc = VERR_INVALID_STATE;
3093	}
3094	return rc;
3095	}
3096
3097
3098	/**
3099	* Marks the FIFO non-busy, notifying any waiting EMTs.
3100	*
3101	* @param pThis The VGA state.
3102	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3103	* @param offFifoMin The start byte offset of the command FIFO.
3104	*/
3105	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3106	{
3107	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3108	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3109	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3110
3111	/* Wake up any waiting EMTs. */
3112	if (pSVGAState->cBusyDelayedEmts > 0)
3113	{
3114	#ifdef VMSVGA_USE_EMT_HALT_CODE
3115	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3116	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3117	if (idCpu != NIL_VMCPUID)
3118	{
3119	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3120	while (idCpu-- > 0)
3121	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3122	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3123	}
3124	#else
3125	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3126	AssertRC(rc2);
3127	#endif
3128	}
3129	}
3130
3131	/**
3132	* Reads (more) payload into the command buffer.
3133	*
3134	* @returns pbBounceBuf on success
3135	* @retval (void *)1 if the thread was requested to stop.
3136	* @retval NULL on FIFO error.
3137	*
3138	* @param cbPayloadReq The number of bytes of payload requested.
3139	* @param pFIFO The FIFO.
3140	* @param offCurrentCmd The FIFO byte offset of the current command.
3141	* @param offFifoMin The start byte offset of the command FIFO.
3142	* @param offFifoMax The end byte offset of the command FIFO.
3143	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3144	* always sufficient size.
3145	* @param pcbAlreadyRead How much payload we've already read into the bounce
3146	* buffer. (We will NEVER re-read anything.)
3147	* @param pThread The calling PDM thread handle.
3148	* @param pThis The VGA state.
3149	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3150	* statistics collection.
3151	*/
3152	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3153	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3154	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3155	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3156	{
3157	Assert(pbBounceBuf);
3158	Assert(pcbAlreadyRead);
3159	Assert(offFifoMin < offFifoMax);
3160	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3161	Assert(offFifoMax <= pThis->svga.cbFIFO);
3162
3163	/*
3164	* Check if the requested payload size has already been satisfied .
3165	* .
3166	* When called to read more, the caller is responsible for making sure the .
3167	* new command size (cbRequsted) never is smaller than what has already .
3168	* been read.
3169	*/
3170	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3171	if (cbPayloadReq <= cbAlreadyRead)
3172	{
3173	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3174	return pbBounceBuf;
3175	}
3176
3177	/*
3178	* Commands bigger than the fifo buffer are invalid.
3179	*/
3180	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3181	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3182	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3183	NULL);
3184
3185	/*
3186	* Move offCurrentCmd past the command dword.
3187	*/
3188	offCurrentCmd += sizeof(uint32_t);
3189	if (offCurrentCmd >= offFifoMax)
3190	offCurrentCmd = offFifoMin;
3191
3192	/*
3193	* Do we have sufficient payload data available already?
3194	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3195	*/
3196	uint32_t cbAfter, cbBefore;
3197	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3198	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3199	if (offNextCmd >= offCurrentCmd)
3200	{
3201	if (RT_LIKELY(offNextCmd < offFifoMax))
3202	cbAfter = offNextCmd - offCurrentCmd;
3203	else
3204	{
3205	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3206	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3207	offNextCmd, offFifoMin, offFifoMax));
3208	cbAfter = offFifoMax - offCurrentCmd;
3209	}
3210	cbBefore = 0;
3211	}
3212	else
3213	{
3214	cbAfter = offFifoMax - offCurrentCmd;
3215	if (offNextCmd >= offFifoMin)
3216	cbBefore = offNextCmd - offFifoMin;
3217	else
3218	{
3219	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3220	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3221	offNextCmd, offFifoMin, offFifoMax));
3222	cbBefore = 0;
3223	}
3224	}
3225	if (cbAfter + cbBefore < cbPayloadReq)
3226	{
3227	/*
3228	* Insufficient, must wait for it to arrive.
3229	*/
3230	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3231	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3232	for (uint32_t i = 0;; i++)
3233	{
3234	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3235	{
3236	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3237	return (void *)(uintptr_t)1;
3238	}
3239	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3240	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3241
3242	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3243
3244	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3245	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3246	if (offNextCmd >= offCurrentCmd)
3247	{
3248	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3249	cbBefore = 0;
3250	}
3251	else
3252	{
3253	cbAfter = offFifoMax - offCurrentCmd;
3254	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3255	}
3256
3257	if (cbAfter + cbBefore >= cbPayloadReq)
3258	break;
3259	}
3260	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3261	}
3262
3263	/*
3264	* Copy out the memory and update what pcbAlreadyRead points to.
3265	*/
3266	if (cbAfter >= cbPayloadReq)
3267	memcpy(pbBounceBuf + cbAlreadyRead,
3268	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3269	cbPayloadReq - cbAlreadyRead);
3270	else
3271	{
3272	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3273	if (cbAlreadyRead < cbAfter)
3274	{
3275	memcpy(pbBounceBuf + cbAlreadyRead,
3276	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3277	cbAfter - cbAlreadyRead);
3278	cbAlreadyRead = cbAfter;
3279	}
3280	memcpy(pbBounceBuf + cbAlreadyRead,
3281	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3282	cbPayloadReq - cbAlreadyRead);
3283	}
3284	*pcbAlreadyRead = cbPayloadReq;
3285	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3286	return pbBounceBuf;
3287	}
3288
3289
3290	/**
3291	* Sends cursor position and visibility information from the FIFO to the front-end.
3292	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3293	*/
3294	static uint32_t
3295	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3296	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3297	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3298	{
3299	/*
3300	* Check if the cursor update counter has changed and try get a stable
3301	* set of values if it has. This is race-prone, especially consindering
3302	* the screen ID, but little we can do about that.
3303	*/
3304	uint32_t x, y, fVisible, idScreen;
3305	for (uint32_t i = 0; ; i++)
3306	{
3307	x = pFIFO[SVGA_FIFO_CURSOR_X];
3308	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3309	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3310	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3311	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3312	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3313	\|\| i > 3)
3314	break;
3315	if (i == 0)
3316	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3317	ASMNopPause();
3318	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3319	}
3320
3321	/*
3322	* Check if anything has changed, as calling into pDrv is not light-weight.
3323	*/
3324	if ( *pxLast == x
3325	&& *pyLast == y
3326	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3327	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3328	else
3329	{
3330	/*
3331	* Detected changes.
3332	*
3333	* We handle global, not per-screen visibility information by sending
3334	* pfnVBVAMousePointerShape without shape data.
3335	*/
3336	*pxLast = x;
3337	*pyLast = y;
3338	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3339	if (idScreen != SVGA_ID_INVALID)
3340	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3341	else if (*pfLastVisible != fVisible)
3342	{
3343	*pfLastVisible = fVisible;
3344	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3345	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3346	}
3347	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3348	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3349	}
3350
3351	/*
3352	* Update done. Signal this to the guest.
3353	*/
3354	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3355
3356	return uCursorUpdateCount;
3357	}
3358
3359
3360	/**
3361	* Checks if there is work to be done, either cursor updating or FIFO commands.
3362	*
3363	* @returns true if pending work, false if not.
3364	* @param pFIFO The FIFO to examine.
3365	* @param uLastCursorCount The last cursor update counter value.
3366	*/
3367	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3368	{
3369	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3370	return true;
3371
3372	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3373	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3374	return true;
3375
3376	return false;
3377	}
3378
3379
3380	/**
3381	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3382	*
3383	* @param pThis The VGA state.
3384	*/
3385	void vmsvgaFIFOWatchdogTimer(PVGASTATE pThis)
3386	{
3387	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3388	to recheck it before doing the signalling. */
3389	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3390	AssertReturnVoid(pThis->svga.pFIFOR3);
3391	if ( vmsvgaFIFOHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3392	&& pThis->svga.fFIFOThreadSleeping)
3393	{
3394	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3395	AssertRC(rc);
3396	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3397	}
3398	}
3399
3400
3401	/* The async FIFO handling thread. */
3402	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3403	{
3404	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3405	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3406	int rc;
3407
3408	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3409	return VINF_SUCCESS;
3410
3411	/*
3412	* Special mode where we only execute an external command and the go back
3413	* to being suspended. Currently, all ext cmds ends up here, with the reset
3414	* one also being eligble for runtime execution further down as well.
3415	*/
3416	if (pThis->svga.fFifoExtCommandWakeup)
3417	{
3418	vmsvgaR3FifoHandleExtCmd(pThis);
3419	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3420	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3421	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3422	else
3423	vmsvgaR3FifoHandleExtCmd(pThis);
3424	return VINF_SUCCESS;
3425	}
3426
3427
3428	/*
3429	* Signal the semaphore to make sure we don't wait for 250ms after a
3430	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3431	*/
3432	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3433
3434	/*
3435	* Allocate a bounce buffer for command we get from the FIFO.
3436	* (All code must return via the end of the function to free this buffer.)
3437	*/
3438	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3439	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3440
3441	/*
3442	* Polling/sleep interval config.
3443	*
3444	* We wait for an a short interval if the guest has recently given us work
3445	* to do, but the interval increases the longer we're kept idle. Once we've
3446	* reached the refresh timer interval, we'll switch to extended waits,
3447	* depending on it or the guest to kick us into action when needed.
3448	*
3449	* Should the refresh time go fishing, we'll just continue increasing the
3450	* sleep length till we reaches the 250 ms max after about 16 seconds.
3451	*/
3452	RTMSINTERVAL const cMsMinSleep = 16;
3453	RTMSINTERVAL const cMsIncSleep = 2;
3454	RTMSINTERVAL const cMsMaxSleep = 250;
3455	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3456	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3457
3458	/*
3459	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3460	*
3461	* Initialize with values that will detect an update from the guest.
3462	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3463	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3464	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3465	*/
3466	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3467	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3468	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3469	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3470	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3471
3472	/*
3473	* The FIFO loop.
3474	*/
3475	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3476	bool fBadOrDisabledFifo = false;
3477	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3478	{
3479	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3480	/*
3481	* Should service the run loop every so often.
3482	*/
3483	if (pThis->svga.f3DEnabled)
3484	vmsvga3dCocoaServiceRunLoop();
3485	# endif
3486
3487	/*
3488	* Unless there's already work pending, go to sleep for a short while.
3489	* (See polling/sleep interval config above.)
3490	*/
3491	if ( fBadOrDisabledFifo
3492	\|\| !vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3493	{
3494	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3495	Assert(pThis->cMilliesRefreshInterval > 0);
3496	if (cMsSleep < pThis->cMilliesRefreshInterval)
3497	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3498	else
3499	{
3500	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3501	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3502	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3503	# endif
3504	if ( !fBadOrDisabledFifo
3505	&& vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3506	rc = VINF_SUCCESS;
3507	else
3508	{
3509	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3510	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsExtendedSleep);
3511	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3512	}
3513	}
3514	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3515	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3516	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3517	{
3518	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3519	break;
3520	}
3521	}
3522	else
3523	rc = VINF_SUCCESS;
3524	fBadOrDisabledFifo = false;
3525	if (rc == VERR_TIMEOUT)
3526	{
3527	if (!vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3528	{
3529	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3530	continue;
3531	}
3532	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3533
3534	Log(("vmsvgaFIFOLoop: timeout\n"));
3535	}
3536	else if (vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3537	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3538	cMsSleep = cMsMinSleep;
3539
3540	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
3541	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3542	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3543
3544	/*
3545	* Handle external commands (currently only reset).
3546	*/
3547	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3548	{
3549	vmsvgaR3FifoHandleExtCmd(pThis);
3550	continue;
3551	}
3552
3553	/*
3554	* The device must be enabled and configured.
3555	*/
3556	if ( !pThis->svga.fEnabled
3557	\|\| !pThis->svga.fConfigured)
3558	{
3559	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3560	fBadOrDisabledFifo = true;
3561	cMsSleep = cMsMaxSleep; /* cheat */
3562	continue;
3563	}
3564
3565	/*
3566	* Get and check the min/max values. We ASSUME that they will remain
3567	* unchanged while we process requests. A further ASSUMPTION is that
3568	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3569	* we don't read it back while in the loop.
3570	*/
3571	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3572	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3573	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3574	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3575	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3576	\|\| offFifoMax <= offFifoMin
3577	\|\| offFifoMax > pThis->svga.cbFIFO
3578	\|\| (offFifoMax & 3) != 0
3579	\|\| (offFifoMin & 3) != 0
3580	\|\| offCurrentCmd < offFifoMin
3581	\|\| offCurrentCmd > offFifoMax))
3582	{
3583	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3584	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3585	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3586	fBadOrDisabledFifo = true;
3587	continue;
3588	}
3589	RT_UNTRUSTED_VALIDATED_FENCE();
3590	if (RT_UNLIKELY(offCurrentCmd & 3))
3591	{
3592	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3593	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3594	offCurrentCmd = ~UINT32_C(3);
3595	}
3596
3597	/*
3598	* Update the cursor position before we start on the FIFO commands.
3599	*/
3600	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3601	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3602	{
3603	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3604	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3605	{ /* halfways likely */ }
3606	else
3607	{
3608	uint32_t const uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3609	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3610	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3611	}
3612	}
3613
3614	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3615	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3616	*
3617	* Will break out of the switch on failure.
3618	* Will restart and quit the loop if the thread was requested to stop.
3619	*
3620	* @param a_PtrVar Request variable pointer.
3621	* @param a_Type Request typedef (not pointer) for casting.
3622	* @param a_cbPayloadReq How much payload to fetch.
3623	* @remarks Accesses a bunch of variables in the current scope!
3624	*/
3625	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3626	if (1) { \
3627	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3628	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3629	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3630	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3631	} else do {} while (0)
3632	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3633	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3634	* buffer after figuring out the actual command size.
3635	*
3636	* Will break out of the switch on failure.
3637	*
3638	* @param a_PtrVar Request variable pointer.
3639	* @param a_Type Request typedef (not pointer) for casting.
3640	* @param a_cbPayloadReq How much payload to fetch.
3641	* @remarks Accesses a bunch of variables in the current scope!
3642	*/
3643	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3644	if (1) { \
3645	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3646	} else do {} while (0)
3647
3648	/*
3649	* Mark the FIFO as busy.
3650	*/
3651	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3652	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3653	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3654
3655	/*
3656	* Execute all queued FIFO commands.
3657	* Quit if pending external command or changes in the thread state.
3658	*/
3659	bool fDone = false;
3660	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3661	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3662	{
3663	uint32_t cbPayload = 0;
3664	uint32_t u32IrqStatus = 0;
3665
3666	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3667
3668	/* First check any pending actions. */
3669	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3670	{
3671	vmsvgaChangeMode(pThis);
3672	# ifdef VBOX_WITH_VMSVGA3D
3673	if (pThis->svga.p3dState != NULL)
3674	vmsvga3dChangeMode(pThis);
3675	# endif
3676	}
3677
3678	/* Check for pending external commands (reset). */
3679	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3680	break;
3681
3682	/*
3683	* Process the command.
3684	*/
3685	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3686	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3687	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3688	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3689	switch (enmCmdId)
3690	{
3691	case SVGA_CMD_INVALID_CMD:
3692	/* Nothing to do. */
3693	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3694	break;
3695
3696	case SVGA_CMD_FENCE:
3697	{
3698	SVGAFifoCmdFence *pCmdFence;
3699	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3700	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3701	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3702	{
3703	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3704	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3705
3706	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3707	{
3708	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3709	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3710	}
3711	else
3712	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3713	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3714	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3715	{
3716	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3717	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3718	}
3719	}
3720	else
3721	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3722	break;
3723	}
3724	case SVGA_CMD_UPDATE:
3725	case SVGA_CMD_UPDATE_VERBOSE:
3726	{
3727	SVGAFifoCmdUpdate *pUpdate;
3728	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3729	if (enmCmdId == SVGA_CMD_UPDATE)
3730	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3731	else
3732	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3733	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3734	/** @todo Multiple screens? */
3735	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3736	AssertBreak(pScreen);
3737	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3738	break;
3739	}
3740
3741	case SVGA_CMD_DEFINE_CURSOR:
3742	{
3743	/* Followed by bitmap data. */
3744	SVGAFifoCmdDefineCursor *pCursor;
3745	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3746	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3747
3748	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3749	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3750	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3751	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3752	AssertBreak(pCursor->andMaskDepth <= 32);
3753	AssertBreak(pCursor->xorMaskDepth <= 32);
3754	RT_UNTRUSTED_VALIDATED_FENCE();
3755
3756	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3757	uint32_t cbAndMask = cbAndLine * pCursor->height;
3758	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3759	uint32_t cbXorMask = cbXorLine * pCursor->height;
3760	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3761
3762	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3763	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3764	break;
3765	}
3766
3767	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3768	{
3769	/* Followed by bitmap data. */
3770	uint32_t cbCursorShape, cbAndMask;
3771	uint8_t *pCursorCopy;
3772	uint32_t cbCmd;
3773
3774	SVGAFifoCmdDefineAlphaCursor *pCursor;
3775	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3776	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3777
3778	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3779
3780	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3781	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3782	RT_UNTRUSTED_VALIDATED_FENCE();
3783
3784	/* Refetch the bitmap data as well. */
3785	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3786	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3787	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3788
3789	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3790	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3791	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3792	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3793
3794	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3795	AssertBreak(pCursorCopy);
3796
3797	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3798	memset(pCursorCopy, 0xff, cbAndMask);
3799	/* Colour data */
3800	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3801
3802	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3803	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3804	break;
3805	}
3806
3807	case SVGA_CMD_ESCAPE:
3808	{
3809	/* Followed by nsize bytes of data. */
3810	SVGAFifoCmdEscape *pEscape;
3811	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3812	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3813
3814	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3815	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3816	RT_UNTRUSTED_VALIDATED_FENCE();
3817	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3818	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3819
3820	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3821	{
3822	AssertBreak(pEscape->size >= sizeof(uint32_t));
3823	RT_UNTRUSTED_VALIDATED_FENCE();
3824	uint32_t cmd = (uint32_t )(pEscape + 1);
3825	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3826
3827	switch (cmd)
3828	{
3829	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3830	{
3831	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3832	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3833	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3834
3835	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3836	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3837	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3838
3839	RT_NOREF_PV(pVideoCmd);
3840	break;
3841
3842	}
3843
3844	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3845	{
3846	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3847	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3848	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3849	RT_NOREF_PV(pVideoCmd);
3850	break;
3851	}
3852
3853	default:
3854	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3855	break;
3856	}
3857	}
3858	else
3859	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3860
3861	break;
3862	}
3863	# ifdef VBOX_WITH_VMSVGA3D
3864	case SVGA_CMD_DEFINE_GMR2:
3865	{
3866	SVGAFifoCmdDefineGMR2 *pCmd;
3867	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3868	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3869	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3870
3871	/* Validate current GMR id. */
3872	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3873	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3874	RT_UNTRUSTED_VALIDATED_FENCE();
3875
3876	if (!pCmd->numPages)
3877	{
3878	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3879	vmsvgaGMRFree(pThis, pCmd->gmrId);
3880	}
3881	else
3882	{
3883	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3884	if (pGMR->cMaxPages)
3885	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3886
3887	/* Not sure if we should always free the descriptor, but for simplicity
3888	we do so if the new size is smaller than the current. */
3889	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3890	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3891	vmsvgaGMRFree(pThis, pCmd->gmrId);
3892
3893	pGMR->cMaxPages = pCmd->numPages;
3894	/* The rest is done by the REMAP_GMR2 command. */
3895	}
3896	break;
3897	}
3898
3899	case SVGA_CMD_REMAP_GMR2:
3900	{
3901	/* Followed by page descriptors or guest ptr. */
3902	SVGAFifoCmdRemapGMR2 *pCmd;
3903	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3904	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3905
3906	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3907	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3908	RT_UNTRUSTED_VALIDATED_FENCE();
3909
3910	/* Calculate the size of what comes after next and fetch it. */
3911	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3912	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3913	cbCmd += sizeof(SVGAGuestPtr);
3914	else
3915	{
3916	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3917	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3918	{
3919	cbCmd += cbPageDesc;
3920	pCmd->numPages = 1;
3921	}
3922	else
3923	{
3924	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3925	cbCmd += cbPageDesc * pCmd->numPages;
3926	}
3927	}
3928	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3929
3930	/* Validate current GMR id and size. */
3931	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3932	RT_UNTRUSTED_VALIDATED_FENCE();
3933	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3934	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3935	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3936	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3937
3938	if (pCmd->numPages == 0)
3939	break;
3940
3941	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3942	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3943
3944	/*
3945	* We flatten the existing descriptors into a page array, overwrite the
3946	* pages specified in this command and then recompress the descriptor.
3947	*/
3948	/** @todo Optimize the GMR remap algorithm! */
3949
3950	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3951	uint64_t *paNewPage64 = NULL;
3952	if (pGMR->paDesc)
3953	{
3954	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3955
3956	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3957	AssertBreak(paNewPage64);
3958
3959	uint32_t idxPage = 0;
3960	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3961	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3962	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3963	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3964	RT_UNTRUSTED_VALIDATED_FENCE();
3965	}
3966
3967	/* Free the old GMR if present. */
3968	if (pGMR->paDesc)
3969	RTMemFree(pGMR->paDesc);
3970
3971	/* Allocate the maximum amount possible (everything non-continuous) */
3972	PVMSVGAGMRDESCRIPTOR paDescs;
3973	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3974	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3975
3976	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3977	{
3978	/** @todo */
3979	AssertFailed();
3980	pGMR->numDescriptors = 0;
3981	}
3982	else
3983	{
3984	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3985	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3986	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3987
3988	if (paNewPage64)
3989	{
3990	/* Overwrite the old page array with the new page values. */
3991	if (fGCPhys64)
3992	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3993	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3994	else
3995	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3996	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3997
3998	/* Use the updated page array instead of the command data. */
3999	fGCPhys64 = true;
4000	paPages64 = paNewPage64;
4001	pCmd->numPages = cNewTotalPages;
4002	}
4003
4004	/* The first page. */
4005	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4006	* applied to paNewPage64. */
4007	RTGCPHYS GCPhys;
4008	if (fGCPhys64)
4009	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4010	else
4011	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4012	paDescs[0].GCPhys = GCPhys;
4013	paDescs[0].numPages = 1;
4014
4015	/* Subsequent pages. */
4016	uint32_t iDescriptor = 0;
4017	for (uint32_t i = 1; i < pCmd->numPages; i++)
4018	{
4019	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4020	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4021	else
4022	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4023
4024	/* Continuous physical memory? */
4025	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4026	{
4027	Assert(paDescs[iDescriptor].numPages);
4028	paDescs[iDescriptor].numPages++;
4029	LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4030	}
4031	else
4032	{
4033	iDescriptor++;
4034	paDescs[iDescriptor].GCPhys = GCPhys;
4035	paDescs[iDescriptor].numPages = 1;
4036	LogFlow(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4037	}
4038	}
4039
4040	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4041	LogFlow(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4042	pGMR->numDescriptors = iDescriptor + 1;
4043	}
4044
4045	if (paNewPage64)
4046	RTMemFree(paNewPage64);
4047
4048	# ifdef DEBUG_GMR_ACCESS
4049	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
4050	# endif
4051	break;
4052	}
4053	# endif // VBOX_WITH_VMSVGA3D
4054	case SVGA_CMD_DEFINE_SCREEN:
4055	{
4056	/* The size of this command is specified by the guest and depends on capabilities. */
4057	Assert(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4058
4059	SVGAFifoCmdDefineScreen *pCmd;
4060	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4061	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4062	RT_UNTRUSTED_VALIDATED_FENCE();
4063
4064	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4065	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4066	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4067
4068	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4069	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4070	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4071
4072	uint32_t const idScreen = pCmd->screen.id;
4073	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4074
4075	uint32_t const uWidth = pCmd->screen.size.width;
4076	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4077
4078	uint32_t const uHeight = pCmd->screen.size.height;
4079	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4080
4081	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4082	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4083	AssertBreak(cbWidth <= cbPitch);
4084
4085	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4086	AssertBreak(uScreenOffset < pThis->vram_size);
4087
4088	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4089	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4090	AssertBreak( (uHeight == 0 && cbPitch == 0)
4091	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4092	RT_UNTRUSTED_VALIDATED_FENCE();
4093
4094	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4095
4096	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4097
4098	pScreen->fDefined = true;
4099	pScreen->fModified = true;
4100	pScreen->fuScreen = pCmd->screen.flags;
4101	pScreen->idScreen = idScreen;
4102	if (!fBlank)
4103	{
4104	AssertBreak(uWidth > 0 && uHeight > 0);
4105
4106	pScreen->xOrigin = pCmd->screen.root.x;
4107	pScreen->yOrigin = pCmd->screen.root.y;
4108	pScreen->cWidth = uWidth;
4109	pScreen->cHeight = uHeight;
4110	pScreen->offVRAM = uScreenOffset;
4111	pScreen->cbPitch = cbPitch;
4112	pScreen->cBpp = 32;
4113	}
4114	else
4115	{
4116	/* Keep old values. */
4117	}
4118
4119	pThis->svga.fGFBRegisters = false;
4120	vmsvgaChangeMode(pThis);
4121	break;
4122	}
4123
4124	case SVGA_CMD_DESTROY_SCREEN:
4125	{
4126	SVGAFifoCmdDestroyScreen *pCmd;
4127	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4128	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4129
4130	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4131
4132	uint32_t const idScreen = pCmd->screenId;
4133	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4134	RT_UNTRUSTED_VALIDATED_FENCE();
4135
4136	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4137	pScreen->fModified = true;
4138	pScreen->fDefined = false;
4139	pScreen->idScreen = idScreen;
4140
4141	vmsvgaChangeMode(pThis);
4142	break;
4143	}
4144
4145	case SVGA_CMD_DEFINE_GMRFB:
4146	{
4147	SVGAFifoCmdDefineGMRFB *pCmd;
4148	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4149	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4150
4151	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4152	pSVGAState->GMRFB.ptr = pCmd->ptr;
4153	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4154	pSVGAState->GMRFB.format = pCmd->format;
4155	break;
4156	}
4157
4158	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4159	{
4160	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4161	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4162	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4163
4164	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4165	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4166
4167	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4168	RT_UNTRUSTED_VALIDATED_FENCE();
4169
4170	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4171	AssertBreak(pScreen);
4172
4173	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4174	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4175
4176	/* Clip destRect to the screen dimensions. */
4177	SVGASignedRect screenRect;
4178	screenRect.left = 0;
4179	screenRect.top = 0;
4180	screenRect.right = pScreen->cWidth;
4181	screenRect.bottom = pScreen->cHeight;
4182	SVGASignedRect clipRect = pCmd->destRect;
4183	vmsvgaClipRect(&screenRect, &clipRect);
4184	RT_UNTRUSTED_VALIDATED_FENCE();
4185
4186	uint32_t const width = clipRect.right - clipRect.left;
4187	uint32_t const height = clipRect.bottom - clipRect.top;
4188
4189	if ( width == 0
4190	\|\| height == 0)
4191	break; /* Nothing to do. */
4192
4193	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4194	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4195
4196	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4197	* Prepare parameters for vmsvgaGMRTransfer.
4198	*/
4199	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4200
4201	/* Destination: host buffer which describes the screen 0 VRAM.
4202	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4203	*/
4204	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4205	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4206	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4207	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4208	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4209	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4210	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4211	+ cbScanline * clipRect.top;
4212	int32_t const cbHstPitch = cbScanline;
4213
4214	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4215	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4216	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4217	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4218	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4219
4220	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4221	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4222	gstPtr, offGst, cbGstPitch,
4223	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4224	AssertRC(rc);
4225	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4226	break;
4227	}
4228
4229	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4230	{
4231	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4232	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4233	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4234
4235	/* Note! This can fetch 3d render results as well!! */
4236	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4237	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4238
4239	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4240	RT_UNTRUSTED_VALIDATED_FENCE();
4241
4242	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4243	AssertBreak(pScreen);
4244
4245	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4246	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4247
4248	/* Clip destRect to the screen dimensions. */
4249	SVGASignedRect screenRect;
4250	screenRect.left = 0;
4251	screenRect.top = 0;
4252	screenRect.right = pScreen->cWidth;
4253	screenRect.bottom = pScreen->cHeight;
4254	SVGASignedRect clipRect = pCmd->srcRect;
4255	vmsvgaClipRect(&screenRect, &clipRect);
4256	RT_UNTRUSTED_VALIDATED_FENCE();
4257
4258	uint32_t const width = clipRect.right - clipRect.left;
4259	uint32_t const height = clipRect.bottom - clipRect.top;
4260
4261	if ( width == 0
4262	\|\| height == 0)
4263	break; /* Nothing to do. */
4264
4265	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4266	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4267
4268	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4269	* Prepare parameters for vmsvgaGMRTransfer.
4270	*/
4271	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4272
4273	/* Source: host buffer which describes the screen 0 VRAM.
4274	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4275	*/
4276	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4277	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4278	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4279	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4280	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4281	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4282	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4283	+ cbScanline * clipRect.top;
4284	int32_t const cbHstPitch = cbScanline;
4285
4286	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4287	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4288	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4289	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4290	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4291
4292	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4293	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4294	gstPtr, offGst, cbGstPitch,
4295	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4296	AssertRC(rc);
4297	break;
4298	}
4299
4300	case SVGA_CMD_ANNOTATION_FILL:
4301	{
4302	SVGAFifoCmdAnnotationFill *pCmd;
4303	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4304	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4305
4306	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4307	pSVGAState->colorAnnotation = pCmd->color;
4308	break;
4309	}
4310
4311	case SVGA_CMD_ANNOTATION_COPY:
4312	{
4313	SVGAFifoCmdAnnotationCopy *pCmd;
4314	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4315	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4316
4317	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4318	AssertFailed();
4319	break;
4320	}
4321
4322	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4323
4324	default:
4325	# ifdef VBOX_WITH_VMSVGA3D
4326	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4327	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4328	{
4329	RT_UNTRUSTED_VALIDATED_FENCE();
4330
4331	/* All 3d commands start with a common header, which defines the size of the command. */
4332	SVGA3dCmdHeader *pHdr;
4333	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4334	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4335	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4336	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4337
4338	if (RT_LIKELY(pThis->svga.f3DEnabled))
4339	{ /* likely */ }
4340	else
4341	{
4342	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4343	break;
4344	}
4345
4346	/**
4347	* Check that the 3D command has at least a_cbMin of payload bytes after the
4348	* header. Will break out of the switch if it doesn't.
4349	*/
4350	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4351	do { AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4352	RT_UNTRUSTED_VALIDATED_FENCE(); \
4353	} while (0)
4354	switch ((int)enmCmdId)
4355	{
4356	case SVGA_3D_CMD_SURFACE_DEFINE:
4357	{
4358	uint32_t cMipLevels;
4359	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4360	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4361	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4362
4363	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4364	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4365	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4366	# ifdef DEBUG_GMR_ACCESS
4367	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4368	# endif
4369	break;
4370	}
4371
4372	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4373	{
4374	uint32_t cMipLevels;
4375	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4376	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4377	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4378
4379	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4380	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4381	pCmd->multisampleCount, pCmd->autogenFilter,
4382	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4383	break;
4384	}
4385
4386	case SVGA_3D_CMD_SURFACE_DESTROY:
4387	{
4388	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4389	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4390	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4391	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4392	break;
4393	}
4394
4395	case SVGA_3D_CMD_SURFACE_COPY:
4396	{
4397	uint32_t cCopyBoxes;
4398	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4399	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4400	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4401
4402	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4403	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4404	break;
4405	}
4406
4407	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4408	{
4409	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4410	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4411	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4412
4413	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4414	break;
4415	}
4416
4417	case SVGA_3D_CMD_SURFACE_DMA:
4418	{
4419	uint32_t cCopyBoxes;
4420	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4421	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4422	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4423
4424	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4425	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4426	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4427	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4428	break;
4429	}
4430
4431	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4432	{
4433	uint32_t cRects;
4434	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4435	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4436	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4437
4438	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4439	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4440	break;
4441	}
4442
4443	case SVGA_3D_CMD_CONTEXT_DEFINE:
4444	{
4445	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4446	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4447	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4448
4449	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4450	break;
4451	}
4452
4453	case SVGA_3D_CMD_CONTEXT_DESTROY:
4454	{
4455	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4456	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4457	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4458
4459	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4460	break;
4461	}
4462
4463	case SVGA_3D_CMD_SETTRANSFORM:
4464	{
4465	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4466	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4467	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4468
4469	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4470	break;
4471	}
4472
4473	case SVGA_3D_CMD_SETZRANGE:
4474	{
4475	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4476	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4477	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4478
4479	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4480	break;
4481	}
4482
4483	case SVGA_3D_CMD_SETRENDERSTATE:
4484	{
4485	uint32_t cRenderStates;
4486	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4487	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4488	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4489
4490	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4491	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4492	break;
4493	}
4494
4495	case SVGA_3D_CMD_SETRENDERTARGET:
4496	{
4497	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4498	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4499	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4500
4501	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4502	break;
4503	}
4504
4505	case SVGA_3D_CMD_SETTEXTURESTATE:
4506	{
4507	uint32_t cTextureStates;
4508	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4509	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4510	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4511
4512	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4513	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4514	break;
4515	}
4516
4517	case SVGA_3D_CMD_SETMATERIAL:
4518	{
4519	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4520	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4521	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4522
4523	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4524	break;
4525	}
4526
4527	case SVGA_3D_CMD_SETLIGHTDATA:
4528	{
4529	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4530	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4531	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4532
4533	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4534	break;
4535	}
4536
4537	case SVGA_3D_CMD_SETLIGHTENABLED:
4538	{
4539	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4540	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4541	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4542
4543	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4544	break;
4545	}
4546
4547	case SVGA_3D_CMD_SETVIEWPORT:
4548	{
4549	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4550	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4551	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4552
4553	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4554	break;
4555	}
4556
4557	case SVGA_3D_CMD_SETCLIPPLANE:
4558	{
4559	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4560	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4561	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4562
4563	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4564	break;
4565	}
4566
4567	case SVGA_3D_CMD_CLEAR:
4568	{
4569	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4570	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4571	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4572
4573	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4574	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4575	break;
4576	}
4577
4578	case SVGA_3D_CMD_PRESENT:
4579	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4580	{
4581	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4582	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4583	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4584	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4585	else
4586	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4587
4588	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4589
4590	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4591	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4592	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4593	break;
4594	}
4595
4596	case SVGA_3D_CMD_SHADER_DEFINE:
4597	{
4598	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4599	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4600	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4601
4602	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4603	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4604	break;
4605	}
4606
4607	case SVGA_3D_CMD_SHADER_DESTROY:
4608	{
4609	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4610	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4611	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4612
4613	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4614	break;
4615	}
4616
4617	case SVGA_3D_CMD_SET_SHADER:
4618	{
4619	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4620	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4621	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4622
4623	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4624	break;
4625	}
4626
4627	case SVGA_3D_CMD_SET_SHADER_CONST:
4628	{
4629	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4630	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4631	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4632
4633	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4634	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4635	break;
4636	}
4637
4638	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4639	{
4640	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4641	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4642	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4643
4644	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4645	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4646	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4647	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4648	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4649
4650	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4651	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4652
4653	RT_UNTRUSTED_VALIDATED_FENCE();
4654
4655	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4656	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4657	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4658
4659	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4660	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4661	pNumRange, cVertexDivisor, pVertexDivisor);
4662	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4663	break;
4664	}
4665
4666	case SVGA_3D_CMD_SETSCISSORRECT:
4667	{
4668	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4669	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4670	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4671
4672	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4673	break;
4674	}
4675
4676	case SVGA_3D_CMD_BEGIN_QUERY:
4677	{
4678	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4679	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4680	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4681
4682	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4683	break;
4684	}
4685
4686	case SVGA_3D_CMD_END_QUERY:
4687	{
4688	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4689	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4690	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4691
4692	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4693	break;
4694	}
4695
4696	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4697	{
4698	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4699	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4700	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4701
4702	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4703	break;
4704	}
4705
4706	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4707	{
4708	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4709	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4710	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4711
4712	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4713	break;
4714	}
4715
4716	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4717	/* context id + surface id? */
4718	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4719	break;
4720	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4721	/* context id + surface id? */
4722	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4723	break;
4724
4725	default:
4726	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4727	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4728	break;
4729	}
4730	}
4731	else
4732	# endif // VBOX_WITH_VMSVGA3D
4733	{
4734	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4735	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4736	}
4737	}
4738
4739	/* Go to the next slot */
4740	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4741	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4742	if (offCurrentCmd >= offFifoMax)
4743	{
4744	offCurrentCmd -= offFifoMax - offFifoMin;
4745	Assert(offCurrentCmd >= offFifoMin);
4746	Assert(offCurrentCmd < offFifoMax);
4747	}
4748	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4749	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4750
4751	/*
4752	* Raise IRQ if required. Must enter the critical section here
4753	* before making final decisions here, otherwise cubebench and
4754	* others may end up waiting forever.
4755	*/
4756	if ( u32IrqStatus
4757	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4758	{
4759	int rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
4760	AssertRC(rc2);
4761
4762	/* FIFO progress might trigger an interrupt. */
4763	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4764	{
4765	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4766	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4767	}
4768
4769	/* Unmasked IRQ pending? */
4770	if (pThis->svga.u32IrqMask & u32IrqStatus)
4771	{
4772	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4773	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4774	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4775	}
4776
4777	PDMCritSectLeave(&pThis->CritSect);
4778	}
4779	}
4780
4781	/* If really done, clear the busy flag. */
4782	if (fDone)
4783	{
4784	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4785	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4786	}
4787	}
4788
4789	/*
4790	* Free the bounce buffer. (There are no returns above!)
4791	*/
4792	RTMemFree(pbBounceBuf);
4793
4794	return VINF_SUCCESS;
4795	}
4796
4797	/**
4798	* Free the specified GMR
4799	*
4800	* @param pThis VGA device instance data.
4801	* @param idGMR GMR id
4802	*/
4803	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4804	{
4805	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4806
4807	/* Free the old descriptor if present. */
4808	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4809	if ( pGMR->numDescriptors
4810	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4811	{
4812	# ifdef DEBUG_GMR_ACCESS
4813	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4814	# endif
4815
4816	Assert(pGMR->paDesc);
4817	RTMemFree(pGMR->paDesc);
4818	pGMR->paDesc = NULL;
4819	pGMR->numDescriptors = 0;
4820	pGMR->cbTotal = 0;
4821	pGMR->cMaxPages = 0;
4822	}
4823	Assert(!pGMR->cMaxPages);
4824	Assert(!pGMR->cbTotal);
4825	}
4826
4827	/**
4828	* Copy between a GMR and a host memory buffer.
4829	*
4830	* @returns VBox status code.
4831	* @param pThis VGA device instance data.
4832	* @param enmTransferType Transfer type (read/write)
4833	* @param pbHstBuf Host buffer pointer (valid)
4834	* @param cbHstBuf Size of host buffer (valid)
4835	* @param offHst Host buffer offset of the first scanline
4836	* @param cbHstPitch Destination buffer pitch
4837	* @param gstPtr GMR description
4838	* @param offGst Guest buffer offset of the first scanline
4839	* @param cbGstPitch Guest buffer pitch
4840	* @param cbWidth Width in bytes to copy
4841	* @param cHeight Number of scanllines to copy
4842	*/
4843	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4844	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4845	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4846	uint32_t cbWidth, uint32_t cHeight)
4847	{
4848	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4849	int rc;
4850
4851	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4852	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4853	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4854	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4855	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4856
4857	PGMR pGMR;
4858	uint32_t cbGmr; /* The GMR size in bytes. */
4859	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4860	{
4861	pGMR = NULL;
4862	cbGmr = pThis->vram_size;
4863	}
4864	else
4865	{
4866	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4867	RT_UNTRUSTED_VALIDATED_FENCE();
4868	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4869	cbGmr = pGMR->cbTotal;
4870	}
4871
4872	/*
4873	* GMR
4874	*/
4875	/* Calculate GMR offset of the data to be copied. */
4876	AssertMsgReturn(gstPtr.offset < cbGmr,
4877	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4878	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4879	VERR_INVALID_PARAMETER);
4880	RT_UNTRUSTED_VALIDATED_FENCE();
4881	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4882	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4883	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4884	VERR_INVALID_PARAMETER);
4885	RT_UNTRUSTED_VALIDATED_FENCE();
4886	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4887
4888	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4889	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4890	AssertMsgReturn(cbGmrScanline != 0,
4891	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4892	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4893	VERR_INVALID_PARAMETER);
4894	RT_UNTRUSTED_VALIDATED_FENCE();
4895	AssertMsgReturn(cbWidth <= cbGmrScanline,
4896	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4897	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4898	VERR_INVALID_PARAMETER);
4899	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4900	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4901	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4902	VERR_INVALID_PARAMETER);
4903	RT_UNTRUSTED_VALIDATED_FENCE();
4904
4905	/* How many bytes are available for the data in the GMR. */
4906	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4907
4908	/* How many scanlines would fit into the available data. */
4909	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4910	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4911	if (cbWidth <= cbGmrLastScanline)
4912	++cGmrScanlines;
4913
4914	if (cHeight > cGmrScanlines)
4915	cHeight = cGmrScanlines;
4916
4917	AssertMsgReturn(cHeight > 0,
4918	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4919	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4920	VERR_INVALID_PARAMETER);
4921	RT_UNTRUSTED_VALIDATED_FENCE();
4922
4923	/*
4924	* Host buffer.
4925	*/
4926	AssertMsgReturn(offHst < cbHstBuf,
4927	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4928	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4929	VERR_INVALID_PARAMETER);
4930
4931	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4932	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4933	AssertMsgReturn(cbHstScanline != 0,
4934	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4935	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4936	VERR_INVALID_PARAMETER);
4937	AssertMsgReturn(cbWidth <= cbHstScanline,
4938	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4939	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4940	VERR_INVALID_PARAMETER);
4941	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4942	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4943	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4944	VERR_INVALID_PARAMETER);
4945
4946	/* How many bytes are available for the data in the buffer. */
4947	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4948
4949	/* How many scanlines would fit into the available data. */
4950	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4951	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4952	if (cbWidth <= cbHstLastScanline)
4953	++cHstScanlines;
4954
4955	if (cHeight > cHstScanlines)
4956	cHeight = cHstScanlines;
4957
4958	AssertMsgReturn(cHeight > 0,
4959	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4960	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4961	VERR_INVALID_PARAMETER);
4962
4963	uint8_t *pbHst = pbHstBuf + offHst;
4964
4965	/* Shortcut for the framebuffer. */
4966	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4967	{
4968	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4969
4970	uint8_t const *pbSrc;
4971	int32_t cbSrcPitch;
4972	uint8_t *pbDst;
4973	int32_t cbDstPitch;
4974
4975	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4976	{
4977	pbSrc = pbHst;
4978	cbSrcPitch = cbHstPitch;
4979	pbDst = pbGst;
4980	cbDstPitch = cbGstPitch;
4981	}
4982	else
4983	{
4984	pbSrc = pbGst;
4985	cbSrcPitch = cbGstPitch;
4986	pbDst = pbHst;
4987	cbDstPitch = cbHstPitch;
4988	}
4989
4990	if ( cbWidth == (uint32_t)cbGstPitch
4991	&& cbGstPitch == cbHstPitch)
4992	{
4993	/* Entire scanlines, positive pitch. */
4994	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4995	}
4996	else
4997	{
4998	for (uint32_t i = 0; i < cHeight; ++i)
4999	{
5000	memcpy(pbDst, pbSrc, cbWidth);
5001
5002	pbDst += cbDstPitch;
5003	pbSrc += cbSrcPitch;
5004	}
5005	}
5006	return VINF_SUCCESS;
5007	}
5008
5009	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5010	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5011
5012	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5013	uint32_t iDesc = 0; /* Index in the descriptor array. */
5014	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5015	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5016	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5017	for (uint32_t i = 0; i < cHeight; ++i)
5018	{
5019	uint32_t cbCurrentWidth = cbWidth;
5020	uint32_t offGmrCurrent = offGmrScanline;
5021	uint8_t *pbCurrentHost = pbHstScanline;
5022
5023	/* Find the right descriptor */
5024	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5025	{
5026	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5027	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5028	++iDesc;
5029	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5030	}
5031
5032	while (cbCurrentWidth)
5033	{
5034	uint32_t cbToCopy;
5035
5036	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5037	{
5038	cbToCopy = cbCurrentWidth;
5039	}
5040	else
5041	{
5042	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5043	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5044	}
5045
5046	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5047
5048	LogFlowFunc(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5049
5050	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5051	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5052	else
5053	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5054	AssertRCBreak(rc);
5055
5056	cbCurrentWidth -= cbToCopy;
5057	offGmrCurrent += cbToCopy;
5058	pbCurrentHost += cbToCopy;
5059
5060	/* Go to the next descriptor if there's anything left. */
5061	if (cbCurrentWidth)
5062	{
5063	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5064	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5065	++iDesc;
5066	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5067	}
5068	}
5069
5070	offGmrScanline += cbGstPitch;
5071	pbHstScanline += cbHstPitch;
5072	}
5073
5074	return VINF_SUCCESS;
5075	}
5076
5077
5078	/**
5079	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5080	*
5081	* @param pSizeSrc Source surface dimensions.
5082	* @param pSizeDest Destination surface dimensions.
5083	* @param pBox Coordinates to be clipped.
5084	*/
5085	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5086	const SVGA3dSize *pSizeDest,
5087	SVGA3dCopyBox *pBox)
5088	{
5089	/* Src x, w */
5090	if (pBox->srcx > pSizeSrc->width)
5091	pBox->srcx = pSizeSrc->width;
5092	if (pBox->w > pSizeSrc->width - pBox->srcx)
5093	pBox->w = pSizeSrc->width - pBox->srcx;
5094
5095	/* Src y, h */
5096	if (pBox->srcy > pSizeSrc->height)
5097	pBox->srcy = pSizeSrc->height;
5098	if (pBox->h > pSizeSrc->height - pBox->srcy)
5099	pBox->h = pSizeSrc->height - pBox->srcy;
5100
5101	/* Src z, d */
5102	if (pBox->srcz > pSizeSrc->depth)
5103	pBox->srcz = pSizeSrc->depth;
5104	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5105	pBox->d = pSizeSrc->depth - pBox->srcz;
5106
5107	/* Dest x, w */
5108	if (pBox->x > pSizeDest->width)
5109	pBox->x = pSizeDest->width;
5110	if (pBox->w > pSizeDest->width - pBox->x)
5111	pBox->w = pSizeDest->width - pBox->x;
5112
5113	/* Dest y, h */
5114	if (pBox->y > pSizeDest->height)
5115	pBox->y = pSizeDest->height;
5116	if (pBox->h > pSizeDest->height - pBox->y)
5117	pBox->h = pSizeDest->height - pBox->y;
5118
5119	/* Dest z, d */
5120	if (pBox->z > pSizeDest->depth)
5121	pBox->z = pSizeDest->depth;
5122	if (pBox->d > pSizeDest->depth - pBox->z)
5123	pBox->d = pSizeDest->depth - pBox->z;
5124	}
5125
5126	/**
5127	* Unsigned coordinates in pBox. Clip to [0; pSize).
5128	*
5129	* @param pSize Source surface dimensions.
5130	* @param pBox Coordinates to be clipped.
5131	*/
5132	void vmsvgaClipBox(const SVGA3dSize *pSize,
5133	SVGA3dBox *pBox)
5134	{
5135	/* x, w */
5136	if (pBox->x > pSize->width)
5137	pBox->x = pSize->width;
5138	if (pBox->w > pSize->width - pBox->x)
5139	pBox->w = pSize->width - pBox->x;
5140
5141	/* y, h */
5142	if (pBox->y > pSize->height)
5143	pBox->y = pSize->height;
5144	if (pBox->h > pSize->height - pBox->y)
5145	pBox->h = pSize->height - pBox->y;
5146
5147	/* z, d */
5148	if (pBox->z > pSize->depth)
5149	pBox->z = pSize->depth;
5150	if (pBox->d > pSize->depth - pBox->z)
5151	pBox->d = pSize->depth - pBox->z;
5152	}
5153
5154	/**
5155	* Clip.
5156	*
5157	* @param pBound Bounding rectangle.
5158	* @param pRect Rectangle to be clipped.
5159	*/
5160	void vmsvgaClipRect(SVGASignedRect const *pBound,
5161	SVGASignedRect *pRect)
5162	{
5163	int32_t left;
5164	int32_t top;
5165	int32_t right;
5166	int32_t bottom;
5167
5168	/* Right order. */
5169	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5170	if (pRect->left < pRect->right)
5171	{
5172	left = pRect->left;
5173	right = pRect->right;
5174	}
5175	else
5176	{
5177	left = pRect->right;
5178	right = pRect->left;
5179	}
5180	if (pRect->top < pRect->bottom)
5181	{
5182	top = pRect->top;
5183	bottom = pRect->bottom;
5184	}
5185	else
5186	{
5187	top = pRect->bottom;
5188	bottom = pRect->top;
5189	}
5190
5191	if (left < pBound->left)
5192	left = pBound->left;
5193	if (right < pBound->left)
5194	right = pBound->left;
5195
5196	if (left > pBound->right)
5197	left = pBound->right;
5198	if (right > pBound->right)
5199	right = pBound->right;
5200
5201	if (top < pBound->top)
5202	top = pBound->top;
5203	if (bottom < pBound->top)
5204	bottom = pBound->top;
5205
5206	if (top > pBound->bottom)
5207	top = pBound->bottom;
5208	if (bottom > pBound->bottom)
5209	bottom = pBound->bottom;
5210
5211	pRect->left = left;
5212	pRect->right = right;
5213	pRect->top = top;
5214	pRect->bottom = bottom;
5215	}
5216
5217	/**
5218	* Unblock the FIFO I/O thread so it can respond to a state change.
5219	*
5220	* @returns VBox status code.
5221	* @param pDevIns The VGA device instance.
5222	* @param pThread The send thread.
5223	*/
5224	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5225	{
5226	RT_NOREF(pDevIns);
5227	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5228	Log(("vmsvgaFIFOLoopWakeUp\n"));
5229	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5230	}
5231
5232	/**
5233	* Enables or disables dirty page tracking for the framebuffer
5234	*
5235	* @param pThis VGA device instance data.
5236	* @param fTraces Enable/disable traces
5237	*/
5238	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5239	{
5240	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5241	&& !fTraces)
5242	{
5243	//Assert(pThis->svga.fTraces);
5244	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5245	return;
5246	}
5247
5248	pThis->svga.fTraces = fTraces;
5249	if (pThis->svga.fTraces)
5250	{
5251	unsigned cbFrameBuffer = pThis->vram_size;
5252
5253	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5254	/** @todo How does this work with screens? */
5255	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5256	{
5257	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5258	Assert(pThis->svga.cbScanline);
5259	#endif
5260	/* Hardware enabled; return real framebuffer size .*/
5261	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5262	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5263	}
5264
5265	if (!pThis->svga.fVRAMTracking)
5266	{
5267	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5268	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5269	pThis->svga.fVRAMTracking = true;
5270	}
5271	}
5272	else
5273	{
5274	if (pThis->svga.fVRAMTracking)
5275	{
5276	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5277	vgaR3UnregisterVRAMHandler(pThis);
5278	pThis->svga.fVRAMTracking = false;
5279	}
5280	}
5281	}
5282
5283	/**
5284	* @callback_method_impl{FNPCIIOREGIONMAP}
5285	*/
5286	DECLCALLBACK(int) vmsvgaR3IORegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5287	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5288	{
5289	int rc;
5290	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5291
5292	Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5293	if (enmType == PCI_ADDRESS_SPACE_IO)
5294	{
5295	AssertReturn(iRegion == pThis->pciRegions.iIO, VERR_INTERNAL_ERROR);
5296	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5297	vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr /, NULL / InStr */, "VMSVGA");
5298	if (RT_FAILURE(rc))
5299	return rc;
5300	if (pThis->fR0Enabled)
5301	{
5302	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5303	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5304	if (RT_FAILURE(rc))
5305	return rc;
5306	}
5307	if (pThis->fGCEnabled)
5308	{
5309	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5310	"vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
5311	if (RT_FAILURE(rc))
5312	return rc;
5313	}
5314
5315	pThis->svga.BasePort = GCPhysAddress;
5316	Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
5317	}
5318	else
5319	{
5320	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
5321	if (GCPhysAddress != NIL_RTGCPHYS)
5322	{
5323	/*
5324	* Mapping the FIFO RAM.
5325	*/
5326	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5327	rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
5328	AssertRC(rc);
5329
5330	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5331	if (RT_SUCCESS(rc))
5332	{
5333	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5334	# ifdef DEBUG_FIFO_ACCESS
5335	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5336	# else
5337	GCPhysAddress + PAGE_SIZE - 1,
5338	# endif
5339	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5340	"VMSVGA FIFO");
5341	AssertRC(rc);
5342	}
5343	# endif
5344	if (RT_SUCCESS(rc))
5345	{
5346	pThis->svga.GCPhysFIFO = GCPhysAddress;
5347	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5348	}
5349	}
5350	else
5351	{
5352	Assert(pThis->svga.GCPhysFIFO);
5353	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5354	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5355	AssertRC(rc);
5356	# endif
5357	pThis->svga.GCPhysFIFO = 0;
5358	}
5359	}
5360	return VINF_SUCCESS;
5361	}
5362
5363	# ifdef VBOX_WITH_VMSVGA3D
5364
5365	/**
5366	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5367	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5368	*
5369	* @param pThis The VGA device instance data.
5370	* @param sid Either UINT32_MAX or the ID of a specific
5371	* surface. If UINT32_MAX is used, all surfaces
5372	* are processed.
5373	*/
5374	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
5375	{
5376	vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5377	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5378	}
5379
5380
5381	/**
5382	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5383	*/
5384	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5385	{
5386	/* There might be a specific surface ID at the start of the
5387	arguments, if not show all surfaces. */
5388	uint32_t sid = UINT32_MAX;
5389	if (pszArgs)
5390	pszArgs = RTStrStripL(pszArgs);
5391	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5392	sid = RTStrToUInt32(pszArgs);
5393
5394	/* Verbose or terse display, we default to verbose. */
5395	bool fVerbose = true;
5396	if (RTStrIStr(pszArgs, "terse"))
5397	fVerbose = false;
5398
5399	/* The size of the ascii art (x direction, y is 3/4 of x). */
5400	uint32_t cxAscii = 80;
5401	if (RTStrIStr(pszArgs, "gigantic"))
5402	cxAscii = 300;
5403	else if (RTStrIStr(pszArgs, "huge"))
5404	cxAscii = 180;
5405	else if (RTStrIStr(pszArgs, "big"))
5406	cxAscii = 132;
5407	else if (RTStrIStr(pszArgs, "normal"))
5408	cxAscii = 80;
5409	else if (RTStrIStr(pszArgs, "medium"))
5410	cxAscii = 64;
5411	else if (RTStrIStr(pszArgs, "small"))
5412	cxAscii = 48;
5413	else if (RTStrIStr(pszArgs, "tiny"))
5414	cxAscii = 24;
5415
5416	/* Y invert the image when producing the ASCII art. */
5417	bool fInvY = false;
5418	if (RTStrIStr(pszArgs, "invy"))
5419	fInvY = true;
5420
5421	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5422	}
5423
5424
5425	/**
5426	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5427	*/
5428	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5429	{
5430	/* pszArg = "sid[>dir]"
5431	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5432	*/
5433	char *pszBitmapPath = NULL;
5434	uint32_t sid = UINT32_MAX;
5435	if (pszArgs)
5436	pszArgs = RTStrStripL(pszArgs);
5437	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5438	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5439	if ( pszBitmapPath
5440	&& *pszBitmapPath == '>')
5441	++pszBitmapPath;
5442
5443	const bool fVerbose = true;
5444	const uint32_t cxAscii = 0; /* No ASCII */
5445	const bool fInvY = false; /* Do not invert. */
5446	vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5447	}
5448
5449
5450	/**
5451	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5452	*/
5453	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5454	{
5455	/* There might be a specific surface ID at the start of the
5456	arguments, if not show all contexts. */
5457	uint32_t sid = UINT32_MAX;
5458	if (pszArgs)
5459	pszArgs = RTStrStripL(pszArgs);
5460	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5461	sid = RTStrToUInt32(pszArgs);
5462
5463	/* Verbose or terse display, we default to verbose. */
5464	bool fVerbose = true;
5465	if (RTStrIStr(pszArgs, "terse"))
5466	fVerbose = false;
5467
5468	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5469	}
5470
5471	# endif /* VBOX_WITH_VMSVGA3D */
5472
5473	/**
5474	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5475	*/
5476	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5477	{
5478	RT_NOREF(pszArgs);
5479	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5480	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5481	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.pFIFOR3;
5482
5483	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5484	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5485	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
5486	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5487	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5488	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5489	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5490	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5491	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5492	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5493	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5494	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5495	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5496	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5497	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5498	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5499	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5500	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5501	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5502	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5503	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5504	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5505	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5506
5507	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5508	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5509	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5510	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5511
5512	# ifdef VBOX_WITH_VMSVGA3D
5513	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5514	# endif
5515	if (pThis->pDrv)
5516	{
5517	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThis->pDrv->cx, pThis->pDrv->cy, pThis->pDrv->cBits);
5518	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThis->pDrv->cbScanline, pThis->pDrv->cbScanline);
5519	}
5520	}
5521
5522	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5523	*/
5524	static int vmsvgaLoadExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5525	{
5526	RT_NOREF(uPass);
5527
5528	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5529	int rc;
5530
5531	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5532	{
5533	uint32_t cScreens = 0;
5534	rc = SSMR3GetU32(pSSM, &cScreens);
5535	AssertRCReturn(rc, rc);
5536	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5537	("cScreens=%#x\n", cScreens),
5538	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5539
5540	for (uint32_t i = 0; i < cScreens; ++i)
5541	{
5542	VMSVGASCREENOBJECT screen;
5543	RT_ZERO(screen);
5544
5545	rc = SSMR3GetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5546	AssertLogRelRCReturn(rc, rc);
5547
5548	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5549	{
5550	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5551	*pScreen = screen;
5552	pScreen->fModified = true;
5553	}
5554	else
5555	{
5556	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5557	}
5558	}
5559	}
5560	else
5561	{
5562	/* Try to setup at least the first screen. */
5563	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5564	pScreen->fDefined = true;
5565	pScreen->fModified = true;
5566	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5567	pScreen->idScreen = 0;
5568	pScreen->xOrigin = 0;
5569	pScreen->yOrigin = 0;
5570	pScreen->offVRAM = pThis->svga.uScreenOffset;
5571	pScreen->cbPitch = pThis->svga.cbScanline;
5572	pScreen->cWidth = pThis->svga.uWidth;
5573	pScreen->cHeight = pThis->svga.uHeight;
5574	pScreen->cBpp = pThis->svga.uBpp;
5575	}
5576
5577	return VINF_SUCCESS;
5578	}
5579
5580	/**
5581	* @copydoc FNSSMDEVLOADEXEC
5582	*/
5583	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5584	{
5585	RT_NOREF(uPass);
5586	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5587	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5588	int rc;
5589
5590	/* Load our part of the VGAState */
5591	rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5592	AssertRCReturn(rc, rc);
5593
5594	/* Load the VGA framebuffer. */
5595	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5596	uint32_t cbVgaFramebuffer = _32K;
5597	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5598	{
5599	rc = SSMR3GetU32(pSSM, &cbVgaFramebuffer);
5600	AssertRCReturn(rc, rc);
5601	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5602	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5603	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5604	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5605	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5606	}
5607	rc = SSMR3GetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5608	AssertRCReturn(rc, rc);
5609	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5610	SSMR3Skip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5611	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5612	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5613
5614	/* Load the VMSVGA state. */
5615	rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5616	AssertRCReturn(rc, rc);
5617
5618	/* Load the active cursor bitmaps. */
5619	if (pSVGAState->Cursor.fActive)
5620	{
5621	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5622	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5623
5624	rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5625	AssertRCReturn(rc, rc);
5626	}
5627
5628	/* Load the GMR state. */
5629	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5630	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5631	{
5632	rc = SSMR3GetU32(pSSM, &cGMR);
5633	AssertRCReturn(rc, rc);
5634	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5635	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5636	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5637	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5638	}
5639
5640	if (pThis->svga.cGMR != cGMR)
5641	{
5642	/* Reallocate GMR array. */
5643	Assert(pSVGAState->paGMR != NULL);
5644	RTMemFree(pSVGAState->paGMR);
5645	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5646	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5647	pThis->svga.cGMR = cGMR;
5648	}
5649
5650	for (uint32_t i = 0; i < cGMR; ++i)
5651	{
5652	PGMR pGMR = &pSVGAState->paGMR[i];
5653
5654	rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5655	AssertRCReturn(rc, rc);
5656
5657	if (pGMR->numDescriptors)
5658	{
5659	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5660	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5661	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5662
5663	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5664	{
5665	rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5666	AssertRCReturn(rc, rc);
5667	}
5668	}
5669	}
5670
5671	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5672	vmsvga3dPowerOn(pThis);
5673	# endif
5674
5675	VMSVGA_STATE_LOAD LoadState;
5676	LoadState.pSSM = pSSM;
5677	LoadState.uVersion = uVersion;
5678	LoadState.uPass = uPass;
5679	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5680	AssertLogRelRCReturn(rc, rc);
5681
5682	return VINF_SUCCESS;
5683	}
5684
5685	/**
5686	* Reinit the video mode after the state has been loaded.
5687	*/
5688	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5689	{
5690	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5691	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5692
5693	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5694
5695	/* Set the active cursor. */
5696	if (pSVGAState->Cursor.fActive)
5697	{
5698	int rc;
5699
5700	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5701	true,
5702	true,
5703	pSVGAState->Cursor.xHotspot,
5704	pSVGAState->Cursor.yHotspot,
5705	pSVGAState->Cursor.width,
5706	pSVGAState->Cursor.height,
5707	pSVGAState->Cursor.pData);
5708	AssertRC(rc);
5709	}
5710	return VINF_SUCCESS;
5711	}
5712
5713	/**
5714	* Portion of SVGA state which must be saved in the FIFO thread.
5715	*/
5716	static int vmsvgaSaveExecFifo(PVGASTATE pThis, PSSMHANDLE pSSM)
5717	{
5718	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5719	int rc;
5720
5721	/* Save the screen objects. */
5722	/* Count defined screen object. */
5723	uint32_t cScreens = 0;
5724	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5725	{
5726	if (pSVGAState->aScreens[i].fDefined)
5727	++cScreens;
5728	}
5729
5730	rc = SSMR3PutU32(pSSM, cScreens);
5731	AssertLogRelRCReturn(rc, rc);
5732
5733	for (uint32_t i = 0; i < cScreens; ++i)
5734	{
5735	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5736
5737	rc = SSMR3PutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5738	AssertLogRelRCReturn(rc, rc);
5739	}
5740	return VINF_SUCCESS;
5741	}
5742
5743	/**
5744	* @copydoc FNSSMDEVSAVEEXEC
5745	*/
5746	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5747	{
5748	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5749	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5750	int rc;
5751
5752	/* Save our part of the VGAState */
5753	rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5754	AssertLogRelRCReturn(rc, rc);
5755
5756	/* Save the framebuffer backup. */
5757	rc = SSMR3PutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5758	rc = SSMR3PutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5759	AssertLogRelRCReturn(rc, rc);
5760
5761	/* Save the VMSVGA state. */
5762	rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5763	AssertLogRelRCReturn(rc, rc);
5764
5765	/* Save the active cursor bitmaps. */
5766	if (pSVGAState->Cursor.fActive)
5767	{
5768	rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5769	AssertLogRelRCReturn(rc, rc);
5770	}
5771
5772	/* Save the GMR state */
5773	rc = SSMR3PutU32(pSSM, pThis->svga.cGMR);
5774	AssertLogRelRCReturn(rc, rc);
5775	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5776	{
5777	PGMR pGMR = &pSVGAState->paGMR[i];
5778
5779	rc = SSMR3PutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5780	AssertLogRelRCReturn(rc, rc);
5781
5782	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5783	{
5784	rc = SSMR3PutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5785	AssertLogRelRCReturn(rc, rc);
5786	}
5787	}
5788
5789	/*
5790	* Must save some state (3D in particular) in the FIFO thread.
5791	*/
5792	rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5793	AssertLogRelRCReturn(rc, rc);
5794
5795	return VINF_SUCCESS;
5796	}
5797
5798	/**
5799	* Destructor for PVMSVGAR3STATE structure.
5800	*
5801	* @param pThis The VGA instance.
5802	* @param pSVGAState Pointer to the structure. It is not deallocated.
5803	*/
5804	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5805	{
5806	#ifndef VMSVGA_USE_EMT_HALT_CODE
5807	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5808	{
5809	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5810	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5811	}
5812	#endif
5813
5814	if (pSVGAState->Cursor.fActive)
5815	{
5816	RTMemFree(pSVGAState->Cursor.pData);
5817	pSVGAState->Cursor.pData = NULL;
5818	pSVGAState->Cursor.fActive = false;
5819	}
5820
5821	if (pSVGAState->paGMR)
5822	{
5823	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5824	if (pSVGAState->paGMR[i].paDesc)
5825	RTMemFree(pSVGAState->paGMR[i].paDesc);
5826
5827	RTMemFree(pSVGAState->paGMR);
5828	pSVGAState->paGMR = NULL;
5829	}
5830	}
5831
5832	/**
5833	* Constructor for PVMSVGAR3STATE structure.
5834	*
5835	* @returns VBox status code.
5836	* @param pThis The VGA instance.
5837	* @param pSVGAState Pointer to the structure. It is already allocated.
5838	*/
5839	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5840	{
5841	int rc = VINF_SUCCESS;
5842	RT_ZERO(*pSVGAState);
5843
5844	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5845	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5846
5847	#ifndef VMSVGA_USE_EMT_HALT_CODE
5848	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5849	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5850	AssertRCReturn(rc, rc);
5851	#endif
5852
5853	return rc;
5854	}
5855
5856	/**
5857	* Resets the SVGA hardware state
5858	*
5859	* @returns VBox status code.
5860	* @param pDevIns The device instance.
5861	*/
5862	int vmsvgaReset(PPDMDEVINS pDevIns)
5863	{
5864	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5865	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5866
5867	/* Reset before init? */
5868	if (!pSVGAState)
5869	return VINF_SUCCESS;
5870
5871	Log(("vmsvgaReset\n"));
5872
5873	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5874	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5875	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5876
5877	/* Reset other stuff. */
5878	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5879	RT_ZERO(pThis->svga.au32ScratchRegion);
5880
5881	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5882	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
5883
5884	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5885
5886	/* Register caps. */
5887	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
5888	# ifdef VBOX_WITH_VMSVGA3D
5889	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5890	# endif
5891
5892	/* Clear the FIFO so that there's no leftover junk. */
5893	RT_BZERO(pThis->svga.pFIFOR3, pThis->svga.cbFIFO);
5894
5895	/* Setup FIFO capabilities. */
5896	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2 \| SVGA_FIFO_CAP_RESERVE \| SVGA_FIFO_CAP_PITCHLOCK;
5897
5898	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5899	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5900
5901	/* VRAM tracking is enabled by default during bootup. */
5902	pThis->svga.fVRAMTracking = true;
5903	pThis->svga.fEnabled = false;
5904
5905	/* Invalidate current settings. */
5906	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5907	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5908	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
5909	pThis->svga.cbScanline = 0;
5910	pThis->svga.u32PitchLock = 0;
5911
5912	return rc;
5913	}
5914
5915	/**
5916	* Cleans up the SVGA hardware state
5917	*
5918	* @returns VBox status code.
5919	* @param pDevIns The device instance.
5920	*/
5921	int vmsvgaDestruct(PPDMDEVINS pDevIns)
5922	{
5923	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5924
5925	/*
5926	* Ask the FIFO thread to terminate the 3d state and then terminate it.
5927	*/
5928	if (pThis->svga.pFIFOIOThread)
5929	{
5930	int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
5931	AssertLogRelRC(rc);
5932
5933	rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
5934	AssertLogRelRC(rc);
5935	pThis->svga.pFIFOIOThread = NULL;
5936	}
5937
5938	/*
5939	* Destroy the special SVGA state.
5940	*/
5941	if (pThis->svga.pSvgaR3State)
5942	{
5943	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
5944
5945	RTMemFree(pThis->svga.pSvgaR3State);
5946	pThis->svga.pSvgaR3State = NULL;
5947	}
5948
5949	/*
5950	* Free our resources residing in the VGA state.
5951	*/
5952	if (pThis->svga.pbVgaFrameBufferR3)
5953	{
5954	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
5955	pThis->svga.pbVgaFrameBufferR3 = NULL;
5956	}
5957	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
5958	{
5959	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
5960	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
5961	}
5962	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
5963	{
5964	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5965	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
5966	}
5967
5968	return VINF_SUCCESS;
5969	}
5970
5971	/**
5972	* Initialize the SVGA hardware state
5973	*
5974	* @returns VBox status code.
5975	* @param pDevIns The device instance.
5976	*/
5977	int vmsvgaInit(PPDMDEVINS pDevIns)
5978	{
5979	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5980	PVMSVGAR3STATE pSVGAState;
5981	PVM pVM = PDMDevHlpGetVM(pDevIns);
5982	int rc;
5983
5984	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5985	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
5986
5987	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
5988
5989	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
5990	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
5991	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
5992
5993	/* Create event semaphore. */
5994	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5995
5996	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
5997	if (RT_FAILURE(rc))
5998	{
5999	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
6000	return rc;
6001	}
6002
6003	/* Create event semaphore. */
6004	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
6005	if (RT_FAILURE(rc))
6006	{
6007	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
6008	return rc;
6009	}
6010
6011	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6012	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
6013
6014	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6015	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6016
6017	pSVGAState = pThis->svga.pSvgaR3State;
6018
6019	/* Register caps. */
6020	pThis->svga.u32RegCaps = SVGA_CAP_GMR \| SVGA_CAP_GMR2 \| SVGA_CAP_CURSOR \| SVGA_CAP_CURSOR_BYPASS_2 \| SVGA_CAP_EXTENDED_FIFO \| SVGA_CAP_IRQMASK \| SVGA_CAP_PITCHLOCK \| SVGA_CAP_TRACES \| SVGA_CAP_SCREEN_OBJECT_2 \| SVGA_CAP_ALPHA_CURSOR;
6021	# ifdef VBOX_WITH_VMSVGA3D
6022	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
6023	# endif
6024
6025	/* Setup FIFO capabilities. */
6026	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE \| SVGA_FIFO_CAP_CURSOR_BYPASS_3 \| SVGA_FIFO_CAP_GMR2 \| SVGA_FIFO_CAP_3D_HWVERSION_REVISED \| SVGA_FIFO_CAP_SCREEN_OBJECT_2 \| SVGA_FIFO_CAP_RESERVE \| SVGA_FIFO_CAP_PITCHLOCK;
6027
6028	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6029	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6030
6031	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
6032	# ifdef VBOX_WITH_VMSVGA3D
6033	if (pThis->svga.f3DEnabled)
6034	{
6035	rc = vmsvga3dInit(pThis);
6036	if (RT_FAILURE(rc))
6037	{
6038	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6039	pThis->svga.f3DEnabled = false;
6040	}
6041	}
6042	# endif
6043	/* VRAM tracking is enabled by default during bootup. */
6044	pThis->svga.fVRAMTracking = true;
6045
6046	/* Invalidate current settings. */
6047	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6048	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6049	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6050	pThis->svga.cbScanline = 0;
6051
6052	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6053	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6054	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6055	{
6056	pThis->svga.u32MaxWidth -= 256;
6057	pThis->svga.u32MaxHeight -= 256;
6058	}
6059	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6060
6061	# ifdef DEBUG_GMR_ACCESS
6062	/* Register the GMR access handler type. */
6063	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
6064	vmsvgaR3GMRAccessHandler,
6065	NULL, NULL, NULL,
6066	NULL, NULL, NULL,
6067	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6068	AssertRCReturn(rc, rc);
6069	# endif
6070
6071	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6072	/* Register the FIFO access handler type. In addition to
6073	debugging FIFO access, this is also used to facilitate
6074	extended fifo thread sleeps. */
6075	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6076	# ifdef DEBUG_FIFO_ACCESS
6077	PGMPHYSHANDLERKIND_ALL,
6078	# else
6079	PGMPHYSHANDLERKIND_WRITE,
6080	# endif
6081	vmsvgaR3FIFOAccessHandler,
6082	NULL, NULL, NULL,
6083	NULL, NULL, NULL,
6084	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6085	AssertRCReturn(rc, rc);
6086	# endif
6087
6088	/* Create the async IO thread. */
6089	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
6090	RTTHREADTYPE_IO, "VMSVGA FIFO");
6091	if (RT_FAILURE(rc))
6092	{
6093	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6094	return rc;
6095	}
6096
6097	/*
6098	* Statistics.
6099	*/
6100	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dActivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dActivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_ACTIVATE_SURFACE");
6101	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dBeginQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dBeginQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_BEGIN_QUERY");
6102	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dClear, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dClear", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CLEAR");
6103	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DEFINE");
6104	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dContextDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dContextDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_CONTEXT_DESTROY");
6105	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDeactivateSurface, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDeactivateSurface", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6106	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitives, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dDrawPrimitives", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_DRAW_PRIMITIVES");
6107	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dDrawPrimitivesProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dDrawPrimitivesProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6108	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dEndQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dEndQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_END_QUERY");
6109	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dGenerateMipmaps, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dGenerateMipmaps", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_GENERATE_MIPMAPS");
6110	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresent, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresent", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT");
6111	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dPresentReadBack, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dPresentReadBack", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_PRESENT_READBACK");
6112	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dPresentProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dPresentProfBoth", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6113	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetClipPlane, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetClipPlane", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETCLIPPLANE");
6114	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightData, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightData", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTDATA");
6115	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetLightEnable, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetLightEnable", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETLIGHTENABLE");
6116	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetMaterial, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetMaterial", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETMATERIAL");
6117	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERSTATE");
6118	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetRenderTarget, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetRenderTarget", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETRENDERTARGET");
6119	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetScissorRect, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetScissorRect", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETSCISSORRECT");
6120	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShader, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShader", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER");
6121	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetShaderConst, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetShaderConst", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SET_SHADER_CONST");
6122	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTextureState, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTextureState", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTEXTURESTATE");
6123	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetTransform, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetTransform", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETTRANSFORM");
6124	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetViewPort, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetViewPort", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETVIEWPORT");
6125	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSetZRange, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSetZRange", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SETZRANGE");
6126	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DEFINE");
6127	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dShaderDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dShaderDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SHADER_DESTROY");
6128	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceCopy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_COPY");
6129	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefine, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefine", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE");
6130	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDefineV2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDefineV2", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6131	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDestroy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDestroy", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DESTROY");
6132	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDma, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceDma", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_DMA");
6133	STAM_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceDmaProf, STAMTYPE_PROFILE, "/Devices/VMSVGA/Cmd/3dSurfaceDmaProf", STAMUNIT_TICKS_PER_CALL, "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6134	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceScreen", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_SCREEN");
6135	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dSurfaceStretchBlt, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dSurfaceStretchBlt", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6136	STAM_REL_REG(pVM, &pSVGAState->StatR3Cmd3dWaitForQuery, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/3dWaitForQuery", STAMUNIT_OCCURENCES, "SVGA_3D_CMD_WAIT_FOR_QUERY");
6137	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationCopy, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationCopy", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_COPY");
6138	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdAnnotationFill, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/AnnotationFill", STAMUNIT_OCCURENCES, "SVGA_CMD_ANNOTATION_FILL");
6139	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitGmrFbToScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitGmrFbToScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6140	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdBlitScreentoGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/BlitScreentoGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6141	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineAlphaCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineAlphaCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6142	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineCursor, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineCursor", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_CURSOR");
6143	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMR2");
6144	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Free, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Free", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6145	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6146	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineGmrFb, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineGmrFb", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_GMRFB");
6147	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDefineScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DefineScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DEFINE_SCREEN");
6148	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdDestroyScreen, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/DestroyScreen", STAMUNIT_OCCURENCES, "SVGA_CMD_DESTROY_SCREEN");
6149	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdEscape, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Escape", STAMUNIT_OCCURENCES, "SVGA_CMD_ESCAPE");
6150	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdFence, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Fence", STAMUNIT_OCCURENCES, "SVGA_CMD_FENCE");
6151	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdInvalidCmd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/InvalidCmd", STAMUNIT_OCCURENCES, "SVGA_CMD_INVALID_CMD");
6152	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2", STAMUNIT_OCCURENCES, "SVGA_CMD_REMAP_GMR2");
6153	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdRemapGmr2Modify, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/RemapGmr2/Modify", STAMUNIT_OCCURENCES, "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6154	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdate, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/Update", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE");
6155	STAM_REL_REG(pVM, &pSVGAState->StatR3CmdUpdateVerbose, STAMTYPE_COUNTER, "/Devices/VMSVGA/Cmd/UpdateVerbose", STAMUNIT_OCCURENCES, "SVGA_CMD_UPDATE_VERBOSE");
6156
6157	STAM_REL_REG(pVM, &pSVGAState->StatR3RegConfigDoneWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE writes");
6158	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_DESCRIPTOR writes");
6159	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Errors", STAMUNIT_OCCURENCES, "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6160	STAM_REL_REG(pVM, &pSVGAState->StatR3RegGmrDescriptorWrFree, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrDescriptorWrite/Free", STAMUNIT_OCCURENCES, "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6161	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL writes.");
6162	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyWrite", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY writes.");
6163	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxWrite", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX writes.");
6164	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH writes.");
6165	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT writes.");
6166	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID writes.");
6167	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6168	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X writes.");
6169	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y writes.");
6170	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH writes.");
6171	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE writes.");
6172	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID writes.");
6173	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID writes.");
6174	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightWrite", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT writes.");
6175	STAM_REL_REG(pVM, &pThis->svga.StatRegIdWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdWrite", STAMUNIT_OCCURENCES, "SVGA_REG_ID writes.");
6176	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskWrite", STAMUNIT_OCCURENCES, "SVGA_REG_IRQMASK writes.");
6177	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS writes.");
6178	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysWrite", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6179	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteWrite", STAMUNIT_OCCURENCES, "SVGA_PALETTE_XXXX writes.");
6180	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK writes.");
6181	STAM_REL_REG(pVM, &pThis->svga.StatRegPseudoColorWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PseudoColorWrite", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR writes.");
6182	STAM_REL_REG(pVM, &pThis->svga.StatRegReadOnlyWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ReadOnlyWrite", STAMUNIT_OCCURENCES, "Read-only SVGA_REG_XXXX writes.");
6183	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_XXXX writes.");
6184	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncWrite", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC writes.");
6185	STAM_REL_REG(pVM, &pThis->svga.StatRegTopWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TOP writes.");
6186	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesWrite", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES writes.");
6187	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownWrite", STAMUNIT_OCCURENCES, "Writes to unknown register.");
6188	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthWr, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthWrite", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH writes.");
6189
6190	STAM_REL_REG(pVM, &pThis->svga.StatRegBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_BITS_PER_PIXEL reads.");
6191	STAM_REL_REG(pVM, &pThis->svga.StatRegBlueMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BlueMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_BLUE_MASK reads.");
6192	STAM_REL_REG(pVM, &pThis->svga.StatRegBusyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BusyRead", STAMUNIT_OCCURENCES, "SVGA_REG_BUSY reads.");
6193	STAM_REL_REG(pVM, &pThis->svga.StatRegBytesPerLineRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/BytesPerLineRead", STAMUNIT_OCCURENCES, "SVGA_REG_BYTES_PER_LINE reads.");
6194	STAM_REL_REG(pVM, &pThis->svga.StatRegCapabilitesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CapabilitesRead", STAMUNIT_OCCURENCES, "SVGA_REG_CAPABILITIES reads.");
6195	STAM_REL_REG(pVM, &pThis->svga.StatRegConfigDoneRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ConfigDoneRead", STAMUNIT_OCCURENCES, "SVGA_REG_CONFIG_DONE reads.");
6196	STAM_REL_REG(pVM, &pThis->svga.StatRegCursorXxxxRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/CursorXxxxRead", STAMUNIT_OCCURENCES, "SVGA_REG_CURSOR_XXXX reads.");
6197	STAM_REL_REG(pVM, &pThis->svga.StatRegDepthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DepthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DEPTH reads.");
6198	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_HEIGHT reads.");
6199	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_ID reads.");
6200	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayIsPrimaryRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayIsPrimaryRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6201	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionXRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionXRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_X reads.");
6202	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayPositionYRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayPositionYRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_POSITION_Y reads.");
6203	STAM_REL_REG(pVM, &pThis->svga.StatRegDisplayWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/DisplayWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_DISPLAY_WIDTH reads.");
6204	STAM_REL_REG(pVM, &pThis->svga.StatRegEnableRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/EnableRead", STAMUNIT_OCCURENCES, "SVGA_REG_ENABLE reads.");
6205	STAM_REL_REG(pVM, &pThis->svga.StatRegFbOffsetRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbOffsetRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_OFFSET reads.");
6206	STAM_REL_REG(pVM, &pThis->svga.StatRegFbSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_SIZE reads.");
6207	STAM_REL_REG(pVM, &pThis->svga.StatRegFbStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/FbStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_FB_START reads.");
6208	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_ID reads.");
6209	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxDescriptorLengthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxDescriptorLengthRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6210	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrMaxIdsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrMaxIdsRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMR_MAX_IDS reads.");
6211	STAM_REL_REG(pVM, &pThis->svga.StatRegGmrsMaxPagesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GmrsMaxPagesRead", STAMUNIT_OCCURENCES, "SVGA_REG_GMRS_MAX_PAGES reads.");
6212	STAM_REL_REG(pVM, &pThis->svga.StatRegGreenMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GreenMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_GREEN_MASK reads.");
6213	STAM_REL_REG(pVM, &pThis->svga.StatRegGuestIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/GuestIdRead", STAMUNIT_OCCURENCES, "SVGA_REG_GUEST_ID reads.");
6214	STAM_REL_REG(pVM, &pThis->svga.StatRegHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_HEIGHT reads.");
6215	STAM_REL_REG(pVM, &pThis->svga.StatRegHostBitsPerPixelRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/HostBitsPerPixelRead", STAMUNIT_OCCURENCES, "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6216	STAM_REL_REG(pVM, &pThis->svga.StatRegIdRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IdRead", STAMUNIT_OCCURENCES, "SVGA_REG_ID reads.");
6217	STAM_REL_REG(pVM, &pThis->svga.StatRegIrqMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/IrqMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_IRQ_MASK reads.");
6218	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxHeightRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxHeightRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_HEIGHT reads.");
6219	STAM_REL_REG(pVM, &pThis->svga.StatRegMaxWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MaxWidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_MAX_WIDTH reads.");
6220	STAM_REL_REG(pVM, &pThis->svga.StatRegMemorySizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemorySizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEMORY_SIZE reads.");
6221	STAM_REL_REG(pVM, &pThis->svga.StatRegMemRegsRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemRegsRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_REGS reads.");
6222	STAM_REL_REG(pVM, &pThis->svga.StatRegMemSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_SIZE reads.");
6223	STAM_REL_REG(pVM, &pThis->svga.StatRegMemStartRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/MemStartRead", STAMUNIT_OCCURENCES, "SVGA_REG_MEM_START reads.");
6224	STAM_REL_REG(pVM, &pThis->svga.StatRegNumDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_DISPLAYS reads.");
6225	STAM_REL_REG(pVM, &pThis->svga.StatRegNumGuestDisplaysRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/NumGuestDisplaysRead", STAMUNIT_OCCURENCES, "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6226	STAM_REL_REG(pVM, &pThis->svga.StatRegPaletteRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PaletteRead", STAMUNIT_OCCURENCES, "SVGA_REG_PLAETTE_XXXX reads.");
6227	STAM_REL_REG(pVM, &pThis->svga.StatRegPitchLockRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PitchLockRead", STAMUNIT_OCCURENCES, "SVGA_REG_PITCHLOCK reads.");
6228	STAM_REL_REG(pVM, &pThis->svga.StatRegPsuedoColorRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/PsuedoColorRead", STAMUNIT_OCCURENCES, "SVGA_REG_PSEUDOCOLOR reads.");
6229	STAM_REL_REG(pVM, &pThis->svga.StatRegRedMaskRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/RedMaskRead", STAMUNIT_OCCURENCES, "SVGA_REG_RED_MASK reads.");
6230	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH reads.");
6231	STAM_REL_REG(pVM, &pThis->svga.StatRegScratchSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/ScratchSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_SCRATCH_SIZE reads.");
6232	STAM_REL_REG(pVM, &pThis->svga.StatRegSyncRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/SyncRead", STAMUNIT_OCCURENCES, "SVGA_REG_SYNC reads.");
6233	STAM_REL_REG(pVM, &pThis->svga.StatRegTopRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TopRead", STAMUNIT_OCCURENCES, "SVGA_REG_TOP reads.");
6234	STAM_REL_REG(pVM, &pThis->svga.StatRegTracesRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/TracesRead", STAMUNIT_OCCURENCES, "SVGA_REG_TRACES reads.");
6235	STAM_REL_REG(pVM, &pThis->svga.StatRegUnknownRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/UnknownRead", STAMUNIT_OCCURENCES, "SVGA_REG_UNKNOWN reads.");
6236	STAM_REL_REG(pVM, &pThis->svga.StatRegVramSizeRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/VramSizeRead", STAMUNIT_OCCURENCES, "SVGA_REG_VRAM_SIZE reads.");
6237	STAM_REL_REG(pVM, &pThis->svga.StatRegWidthRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WidthRead", STAMUNIT_OCCURENCES, "SVGA_REG_WIDTH reads.");
6238	STAM_REL_REG(pVM, &pThis->svga.StatRegWriteOnlyRd, STAMTYPE_COUNTER, "/Devices/VMSVGA/Reg/WriteOnlyRead", STAMUNIT_OCCURENCES, "Write-only SVGA_REG_XXXX reads.");
6239
6240	STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
6241	STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
6242	STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
6243	STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
6244	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
6245	STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
6246	STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6247	STAM_REL_REG(pVM, &pSVGAState->StatFifoExtendedSleep, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoExtendedSleep", STAMUNIT_TICKS_PER_CALL, "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6248	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6249	STAM_REL_REG(pVM, &pSVGAState->StatFifoAccessHandler, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoAccessHandler", STAMUNIT_OCCURENCES, "Number of times the FIFO access handler triggered.");
6250	# endif
6251	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorFetchAgain, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorFetchAgain", STAMUNIT_OCCURENCES, "Times the cursor update counter changed while reading.");
6252	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorNoChange, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorNoChange", STAMUNIT_OCCURENCES, "No cursor position change event though the update counter was modified.");
6253	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorPosition, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorPosition", STAMUNIT_OCCURENCES, "Cursor position and visibility changes.");
6254	STAM_REL_REG(pVM, &pSVGAState->StatFifoCursorVisiblity, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCursorVisiblity", STAMUNIT_OCCURENCES, "Cursor visibility changes.");
6255	STAM_REL_REG(pVM, &pSVGAState->StatFifoWatchdogWakeUps, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoWatchdogWakeUps", STAMUNIT_OCCURENCES, "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6256
6257	/*
6258	* Info handlers.
6259	*/
6260	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6261	# ifdef VBOX_WITH_VMSVGA3D
6262	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6263	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6264	"VMSVGA 3d surface details. "
6265	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6266	vmsvgaR3Info3dSurface);
6267	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6268	"VMSVGA 3d surface details and bitmap: "
6269	"sid[>dir]",
6270	vmsvgaR3Info3dSurfaceBmp);
6271	# endif
6272
6273	return VINF_SUCCESS;
6274	}
6275
6276	# ifdef VBOX_WITH_VMSVGA3D
6277	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6278	static const char * const g_apszVmSvgaDevCapNames[] =
6279	{
6280	"x3D", /* = 0 */
6281	"xMAX_LIGHTS",
6282	"xMAX_TEXTURES",
6283	"xMAX_CLIP_PLANES",
6284	"xVERTEX_SHADER_VERSION",
6285	"xVERTEX_SHADER",
6286	"xFRAGMENT_SHADER_VERSION",
6287	"xFRAGMENT_SHADER",
6288	"xMAX_RENDER_TARGETS",
6289	"xS23E8_TEXTURES",
6290	"xS10E5_TEXTURES",
6291	"xMAX_FIXED_VERTEXBLEND",
6292	"xD16_BUFFER_FORMAT",
6293	"xD24S8_BUFFER_FORMAT",
6294	"xD24X8_BUFFER_FORMAT",
6295	"xQUERY_TYPES",
6296	"xTEXTURE_GRADIENT_SAMPLING",
6297	"rMAX_POINT_SIZE",
6298	"xMAX_SHADER_TEXTURES",
6299	"xMAX_TEXTURE_WIDTH",
6300	"xMAX_TEXTURE_HEIGHT",
6301	"xMAX_VOLUME_EXTENT",
6302	"xMAX_TEXTURE_REPEAT",
6303	"xMAX_TEXTURE_ASPECT_RATIO",
6304	"xMAX_TEXTURE_ANISOTROPY",
6305	"xMAX_PRIMITIVE_COUNT",
6306	"xMAX_VERTEX_INDEX",
6307	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6308	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6309	"xMAX_VERTEX_SHADER_TEMPS",
6310	"xMAX_FRAGMENT_SHADER_TEMPS",
6311	"xTEXTURE_OPS",
6312	"xSURFACEFMT_X8R8G8B8",
6313	"xSURFACEFMT_A8R8G8B8",
6314	"xSURFACEFMT_A2R10G10B10",
6315	"xSURFACEFMT_X1R5G5B5",
6316	"xSURFACEFMT_A1R5G5B5",
6317	"xSURFACEFMT_A4R4G4B4",
6318	"xSURFACEFMT_R5G6B5",
6319	"xSURFACEFMT_LUMINANCE16",
6320	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6321	"xSURFACEFMT_ALPHA8",
6322	"xSURFACEFMT_LUMINANCE8",
6323	"xSURFACEFMT_Z_D16",
6324	"xSURFACEFMT_Z_D24S8",
6325	"xSURFACEFMT_Z_D24X8",
6326	"xSURFACEFMT_DXT1",
6327	"xSURFACEFMT_DXT2",
6328	"xSURFACEFMT_DXT3",
6329	"xSURFACEFMT_DXT4",
6330	"xSURFACEFMT_DXT5",
6331	"xSURFACEFMT_BUMPX8L8V8U8",
6332	"xSURFACEFMT_A2W10V10U10",
6333	"xSURFACEFMT_BUMPU8V8",
6334	"xSURFACEFMT_Q8W8V8U8",
6335	"xSURFACEFMT_CxV8U8",
6336	"xSURFACEFMT_R_S10E5",
6337	"xSURFACEFMT_R_S23E8",
6338	"xSURFACEFMT_RG_S10E5",
6339	"xSURFACEFMT_RG_S23E8",
6340	"xSURFACEFMT_ARGB_S10E5",
6341	"xSURFACEFMT_ARGB_S23E8",
6342	"xMISSING62",
6343	"xMAX_VERTEX_SHADER_TEXTURES",
6344	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6345	"xSURFACEFMT_V16U16",
6346	"xSURFACEFMT_G16R16",
6347	"xSURFACEFMT_A16B16G16R16",
6348	"xSURFACEFMT_UYVY",
6349	"xSURFACEFMT_YUY2",
6350	"xMULTISAMPLE_NONMASKABLESAMPLES",
6351	"xMULTISAMPLE_MASKABLESAMPLES",
6352	"xALPHATOCOVERAGE",
6353	"xSUPERSAMPLE",
6354	"xAUTOGENMIPMAPS",
6355	"xSURFACEFMT_NV12",
6356	"xSURFACEFMT_AYUV",
6357	"xMAX_CONTEXT_IDS",
6358	"xMAX_SURFACE_IDS",
6359	"xSURFACEFMT_Z_DF16",
6360	"xSURFACEFMT_Z_DF24",
6361	"xSURFACEFMT_Z_D24S8_INT",
6362	"xSURFACEFMT_BC4_UNORM",
6363	"xSURFACEFMT_BC5_UNORM", /* 83 */
6364	};
6365	# endif
6366
6367
6368	/**
6369	* Power On notification.
6370	*
6371	* @returns VBox status code.
6372	* @param pDevIns The device instance data.
6373	*
6374	* @remarks Caller enters the device critical section.
6375	*/
6376	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6377	{
6378	# ifdef VBOX_WITH_VMSVGA3D
6379	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6380	if (pThis->svga.f3DEnabled)
6381	{
6382	int rc = vmsvga3dPowerOn(pThis);
6383
6384	if (RT_SUCCESS(rc))
6385	{
6386	bool fSavedBuffering = RTLogRelSetBuffering(true);
6387	SVGA3dCapsRecord *pCaps;
6388	SVGA3dCapPair *pData;
6389	uint32_t idxCap = 0;
6390
6391	/* 3d hardware version; latest and greatest */
6392	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6393	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6394
6395	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
6396	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6397	pData = (SVGA3dCapPair *)&pCaps->data;
6398
6399	/* Fill out all 3d capabilities. */
6400	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6401	{
6402	uint32_t val = 0;
6403
6404	rc = vmsvga3dQueryCaps(pThis, i, &val);
6405	if (RT_SUCCESS(rc))
6406	{
6407	pData[idxCap][0] = i;
6408	pData[idxCap][1] = val;
6409	idxCap++;
6410	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6411	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6412	else
6413	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6414	&g_apszVmSvgaDevCapNames[i][1]));
6415	}
6416	else
6417	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6418	}
6419	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6420	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6421
6422	/* Mark end of record array. */
6423	pCaps->header.length = 0;
6424
6425	RTLogRelSetBuffering(fSavedBuffering);
6426	}
6427	}
6428	# else /* !VBOX_WITH_VMSVGA3D */
6429	RT_NOREF(pDevIns);
6430	# endif /* !VBOX_WITH_VMSVGA3D */
6431	}
6432
6433	#endif /* IN_RING3 */
6434

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 77958

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