Changeset 77958 in vbox

Timestamp:

Mar 29, 2019 8:57:32 PM (6 years ago)

Author:

vboxsync

Message:

VMSVGA: Refined pitch lock handling, also reset FIFO on VM reset. See bugref:9424

File:

• trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp (modified) (6 diffs)

trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp

@@ -1478 +1478 @@
     uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
     uint32_t uRegPitchLock  = pThis->svga.u32PitchLock;
+    uint32_t uFifoMin       = pFIFO[SVGA_FIFO_MIN];
+
+    /* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
+     * it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
+     * location but it has a different meaning.
+     */
+    if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
+        uFifoPitchLock = 0;
 
     /* Sanitize values. */
@@ -1487 +1495 @@
     /* Prefer the register value to the FIFO value.*/
     if (uRegPitchLock)
-        pThis->svga.cbScanline = pThis->svga.u32PitchLock;
+        pThis->svga.cbScanline = uRegPitchLock;
     else if (uFifoPitchLock)
         pThis->svga.cbScanline = uFifoPitchLock;
     else
         pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
+
+    if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
+        pThis->svga.u32PitchLock = pThis->svga.cbScanline;
 }
 #endif
@@ -1612 +1623 @@
             for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
                 pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
+
+            /* Clear the pitch lock. */
+            pThis->svga.u32PitchLock = 0;
         }
 #else  /* !IN_RING3 */
@@ -5474 +5488 @@
     pHlp->pfnPrintf(pHlp, "FIFO external cmd:  %#x\n", pThis->svga.u8FIFOExtCommand);
     pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
+    pHlp->pfnPrintf(pHlp, "FIFO min/max:       %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
     pHlp->pfnPrintf(pHlp, "Busy:               %#x\n", pThis->svga.fBusy);
     pHlp->pfnPrintf(pHlp, "Traces:             %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
@@ -5875 +5890 @@
 # endif
 
+    /* Clear the FIFO so that there's no leftover junk. */
+    RT_BZERO(pThis->svga.pFIFOR3, pThis->svga.cbFIFO);
+
     /* Setup FIFO capabilities. */
     pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2 | SVGA_FIFO_CAP_RESERVE | SVGA_FIFO_CAP_PITCHLOCK;
@@ -5886 +5904 @@
 
     /* Invalidate current settings. */
-    pThis->svga.uWidth     = VMSVGA_VAL_UNINITIALIZED;
-    pThis->svga.uHeight    = VMSVGA_VAL_UNINITIALIZED;
-    pThis->svga.uBpp       = VMSVGA_VAL_UNINITIALIZED;
-    pThis->svga.cbScanline = 0;
+    pThis->svga.uWidth       = VMSVGA_VAL_UNINITIALIZED;
+    pThis->svga.uHeight      = VMSVGA_VAL_UNINITIALIZED;
+    pThis->svga.uBpp         = VMSVGA_VAL_UNINITIALIZED;
+    pThis->svga.cbScanline   = 0;
+    pThis->svga.u32PitchLock = 0;
 
     return rc;