DevVGA-SVGA.cpp@ 82079

Last change on this file since 82079 was 82079, checked in by vboxsync, 5 years ago
DevVGA: Map the first page of the FIFO into ring-0 so we can safely access the SVGA_FIFO_MIN, SVGA_FIFO_PITCHLOCK, and SVGA_FIFO_BUSY registers from there. bugref:9218
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 284.6 KB

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1	/* $Id: DevVGA-SVGA.cpp 82079 2019-11-21 12:46:06Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	*/
13
14	/*
15	* Copyright (C) 2013-2019 Oracle Corporation
16	*
17	* This file is part of VirtualBox Open Source Edition (OSE), as
18	* available from http://www.virtualbox.org. This file is free software;
19	* you can redistribute it and/or modify it under the terms of the GNU
20	* General Public License (GPL) as published by the Free Software
21	* Foundation, in version 2 as it comes in the "COPYING" file of the
22	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
23	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
24	*/
25
26
27	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
28	*
29	* This device emulation was contributed by trivirt AG. It offers an
30	* alternative to our Bochs based VGA graphics and 3d emulations. This is
31	* valuable for Xorg based guests, as there is driver support shipping with Xorg
32	* since it forked from XFree86.
33	*
34	*
35	* @section sec_dev_vmsvga_sdk The VMware SDK
36	*
37	* This is officially deprecated now, however it's still quite useful,
38	* especially for getting the old features working:
39	* http://vmware-svga.sourceforge.net/
40	*
41	* They currently point developers at the following resources.
42	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
43	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
44	* - http://cgit.freedesktop.org/mesa/vmwgfx/
45	*
46	* @subsection subsec_dev_vmsvga_sdk_results Test results
47	*
48	* Test results:
49	* - 2dmark.img:
50	* + todo
51	* - backdoor-tclo.img:
52	* + todo
53	* - blit-cube.img:
54	* + todo
55	* - bunnies.img:
56	* + todo
57	* - cube.img:
58	* + todo
59	* - cubemark.img:
60	* + todo
61	* - dynamic-vertex-stress.img:
62	* + todo
63	* - dynamic-vertex.img:
64	* + todo
65	* - fence-stress.img:
66	* + todo
67	* - gmr-test.img:
68	* + todo
69	* - half-float-test.img:
70	* + todo
71	* - noscreen-cursor.img:
72	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
73	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
74	* visible though.)
75	* - Cursor animation via the palette doesn't work.
76	* - During debugging, it turns out that the framebuffer content seems to
77	* be halfways ignore or something (memset(fb, 0xcc, lots)).
78	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
79	* grow it 0x10 fold (128KB -> 2MB like in WS10).
80	* - null.img:
81	* + todo
82	* - pong.img:
83	* + todo
84	* - presentReadback.img:
85	* + todo
86	* - resolution-set.img:
87	* + todo
88	* - rt-gamma-test.img:
89	* + todo
90	* - screen-annotation.img:
91	* + todo
92	* - screen-cursor.img:
93	* + todo
94	* - screen-dma-coalesce.img:
95	* + todo
96	* - screen-gmr-discontig.img:
97	* + todo
98	* - screen-gmr-remap.img:
99	* + todo
100	* - screen-multimon.img:
101	* + todo
102	* - screen-present-clip.img:
103	* + todo
104	* - screen-render-test.img:
105	* + todo
106	* - screen-simple.img:
107	* + todo
108	* - screen-text.img:
109	* + todo
110	* - simple-shaders.img:
111	* + todo
112	* - simple_blit.img:
113	* + todo
114	* - tiny-2d-updates.img:
115	* + todo
116	* - video-formats.img:
117	* + todo
118	* - video-sync.img:
119	* + todo
120	*
121	*/
122
123
124	/*********************************************************************************************************************************
125	* Header Files *
126	*********************************************************************************************************************************/
127	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
128	#define VMSVGA_USE_EMT_HALT_CODE
129	#include <VBox/vmm/pdmdev.h>
130	#include <VBox/version.h>
131	#include <VBox/err.h>
132	#include <VBox/log.h>
133	#include <VBox/vmm/pgm.h>
134	#ifdef VMSVGA_USE_EMT_HALT_CODE
135	# include <VBox/vmm/vmapi.h>
136	# include <VBox/vmm/vmcpuset.h>
137	#endif
138	#include <VBox/sup.h>
139
140	#include <iprt/assert.h>
141	#include <iprt/semaphore.h>
142	#include <iprt/uuid.h>
143	#ifdef IN_RING3
144	# include <iprt/ctype.h>
145	# include <iprt/mem.h>
146	# ifdef VBOX_STRICT
147	# include <iprt/time.h>
148	# endif
149	#endif
150
151	#include <VBox/AssertGuest.h>
152	#include <VBox/VMMDev.h>
153	#include <VBoxVideo.h>
154	#include <VBox/bioslogo.h>
155
156	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
157	#include "DevVGA.h"
158
159	#include "DevVGA-SVGA.h"
160	#include "vmsvga/svga_escape.h"
161	#include "vmsvga/svga_overlay.h"
162	#include "vmsvga/svga3d_caps.h"
163	#ifdef VBOX_WITH_VMSVGA3D
164	# include "DevVGA-SVGA3d.h"
165	# ifdef RT_OS_DARWIN
166	# include "DevVGA-SVGA3d-cocoa.h"
167	# endif
168	#endif
169
170
171	/*********************************************************************************************************************************
172	* Defined Constants And Macros *
173	*********************************************************************************************************************************/
174	/**
175	* Macro for checking if a fixed FIFO register is valid according to the
176	* current FIFO configuration.
177	*
178	* @returns true / false.
179	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
180	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
181	*/
182	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
183
184
185	/*********************************************************************************************************************************
186	* Structures and Typedefs *
187	*********************************************************************************************************************************/
188	/**
189	* 64-bit GMR descriptor.
190	*/
191	typedef struct
192	{
193	RTGCPHYS GCPhys;
194	uint64_t numPages;
195	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
196
197	/**
198	* GMR slot
199	*/
200	typedef struct
201	{
202	uint32_t cMaxPages;
203	uint32_t cbTotal;
204	uint32_t numDescriptors;
205	PVMSVGAGMRDESCRIPTOR paDesc;
206	} GMR, *PGMR;
207
208	#ifdef IN_RING3
209	/**
210	* Internal SVGA ring-3 only state.
211	*/
212	typedef struct VMSVGAR3STATE
213	{
214	GMR *paGMR; // [VMSVGAState::cGMR]
215	struct
216	{
217	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
218	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
219	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
220	} GMRFB;
221	struct
222	{
223	bool fActive;
224	uint32_t xHotspot;
225	uint32_t yHotspot;
226	uint32_t width;
227	uint32_t height;
228	uint32_t cbData;
229	void *pData;
230	} Cursor;
231	SVGAColorBGRX colorAnnotation;
232
233	# ifdef VMSVGA_USE_EMT_HALT_CODE
234	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
235	uint32_t volatile cBusyDelayedEmts;
236	/** Set of EMTs that are */
237	VMCPUSET BusyDelayedEmts;
238	# else
239	/** Number of EMTs waiting on hBusyDelayedEmts. */
240	uint32_t volatile cBusyDelayedEmts;
241	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
242	* busy (ugly). */
243	RTSEMEVENTMULTI hBusyDelayedEmts;
244	# endif
245
246	/** Information obout screens. */
247	VMSVGASCREENOBJECT aScreens[64];
248
249	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
250	STAMPROFILE StatBusyDelayEmts;
251
252	STAMPROFILE StatR3Cmd3dPresentProf;
253	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
254	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
255	STAMCOUNTER StatR3CmdDefineGmr2;
256	STAMCOUNTER StatR3CmdDefineGmr2Free;
257	STAMCOUNTER StatR3CmdDefineGmr2Modify;
258	STAMCOUNTER StatR3CmdRemapGmr2;
259	STAMCOUNTER StatR3CmdRemapGmr2Modify;
260	STAMCOUNTER StatR3CmdInvalidCmd;
261	STAMCOUNTER StatR3CmdFence;
262	STAMCOUNTER StatR3CmdUpdate;
263	STAMCOUNTER StatR3CmdUpdateVerbose;
264	STAMCOUNTER StatR3CmdDefineCursor;
265	STAMCOUNTER StatR3CmdDefineAlphaCursor;
266	STAMCOUNTER StatR3CmdEscape;
267	STAMCOUNTER StatR3CmdDefineScreen;
268	STAMCOUNTER StatR3CmdDestroyScreen;
269	STAMCOUNTER StatR3CmdDefineGmrFb;
270	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
271	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
272	STAMCOUNTER StatR3CmdAnnotationFill;
273	STAMCOUNTER StatR3CmdAnnotationCopy;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
275	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
276	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
277	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
279	STAMCOUNTER StatR3Cmd3dSurfaceDma;
280	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
281	STAMCOUNTER StatR3Cmd3dContextDefine;
282	STAMCOUNTER StatR3Cmd3dContextDestroy;
283	STAMCOUNTER StatR3Cmd3dSetTransform;
284	STAMCOUNTER StatR3Cmd3dSetZRange;
285	STAMCOUNTER StatR3Cmd3dSetRenderState;
286	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
287	STAMCOUNTER StatR3Cmd3dSetTextureState;
288	STAMCOUNTER StatR3Cmd3dSetMaterial;
289	STAMCOUNTER StatR3Cmd3dSetLightData;
290	STAMCOUNTER StatR3Cmd3dSetLightEnable;
291	STAMCOUNTER StatR3Cmd3dSetViewPort;
292	STAMCOUNTER StatR3Cmd3dSetClipPlane;
293	STAMCOUNTER StatR3Cmd3dClear;
294	STAMCOUNTER StatR3Cmd3dPresent;
295	STAMCOUNTER StatR3Cmd3dPresentReadBack;
296	STAMCOUNTER StatR3Cmd3dShaderDefine;
297	STAMCOUNTER StatR3Cmd3dShaderDestroy;
298	STAMCOUNTER StatR3Cmd3dSetShader;
299	STAMCOUNTER StatR3Cmd3dSetShaderConst;
300	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
301	STAMCOUNTER StatR3Cmd3dSetScissorRect;
302	STAMCOUNTER StatR3Cmd3dBeginQuery;
303	STAMCOUNTER StatR3Cmd3dEndQuery;
304	STAMCOUNTER StatR3Cmd3dWaitForQuery;
305	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
306	STAMCOUNTER StatR3Cmd3dActivateSurface;
307	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
308
309	STAMCOUNTER StatR3RegConfigDoneWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWr;
311	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
312	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
313
314	STAMCOUNTER StatFifoCommands;
315	STAMCOUNTER StatFifoErrors;
316	STAMCOUNTER StatFifoUnkCmds;
317	STAMCOUNTER StatFifoTodoTimeout;
318	STAMCOUNTER StatFifoTodoWoken;
319	STAMPROFILE StatFifoStalls;
320	STAMPROFILE StatFifoExtendedSleep;
321	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
322	STAMCOUNTER StatFifoAccessHandler;
323	# endif
324	STAMCOUNTER StatFifoCursorFetchAgain;
325	STAMCOUNTER StatFifoCursorNoChange;
326	STAMCOUNTER StatFifoCursorPosition;
327	STAMCOUNTER StatFifoCursorVisiblity;
328	STAMCOUNTER StatFifoWatchdogWakeUps;
329	} VMSVGAR3STATE, *PVMSVGAR3STATE;
330	#endif /* IN_RING3 */
331
332
333	/*********************************************************************************************************************************
334	* Internal Functions *
335	*********************************************************************************************************************************/
336	#ifdef IN_RING3
337	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
338	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
339	# endif
340	# ifdef DEBUG_GMR_ACCESS
341	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
342	# endif
343	#endif
344
345
346	/*********************************************************************************************************************************
347	* Global Variables *
348	*********************************************************************************************************************************/
349	#ifdef IN_RING3
350
351	/**
352	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
353	*/
354	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
355	{
356	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
357	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
358	SSMFIELD_ENTRY_TERM()
359	};
360
361	/**
362	* SSM descriptor table for the GMR structure.
363	*/
364	static SSMFIELD const g_aGMRFields[] =
365	{
366	SSMFIELD_ENTRY( GMR, cMaxPages),
367	SSMFIELD_ENTRY( GMR, cbTotal),
368	SSMFIELD_ENTRY( GMR, numDescriptors),
369	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
370	SSMFIELD_ENTRY_TERM()
371	};
372
373	/**
374	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
375	*/
376	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
377	{
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
389	SSMFIELD_ENTRY_TERM()
390	};
391
392	/**
393	* SSM descriptor table for the VMSVGAR3STATE structure.
394	*/
395	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
396	{
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
405	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
408	#ifdef VMSVGA_USE_EMT_HALT_CODE
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
410	#else
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
412	#endif
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
470
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
483	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
485	# endif
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
490
491	SSMFIELD_ENTRY_TERM()
492	};
493
494	/**
495	* SSM descriptor table for the VGAState.svga structure.
496	*/
497	static SSMFIELD const g_aVGAStateSVGAFields[] =
498	{
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
504	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
505	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
507	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
508	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
509	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
510	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
511	SSMFIELD_ENTRY( VMSVGAState, fBusy),
512	SSMFIELD_ENTRY( VMSVGAState, fTraces),
513	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
514	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
517	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
518	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
519	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
520	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
521	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
524	SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
525	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
528	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
529	SSMFIELD_ENTRY( VMSVGAState, uWidth),
530	SSMFIELD_ENTRY( VMSVGAState, uHeight),
531	SSMFIELD_ENTRY( VMSVGAState, uBpp),
532	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
533	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
534	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
535	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
536	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
537	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
538	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
541	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
542	SSMFIELD_ENTRY_TERM()
543	};
544
545	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
546	static int vmsvgaLoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
547	static int vmsvgaSaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM);
548
549	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
550	{
551	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
552	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
553	&& pSVGAState
554	&& pSVGAState->aScreens[idScreen].fDefined)
555	{
556	return &pSVGAState->aScreens[idScreen];
557	}
558	return NULL;
559	}
560
561	#endif /* IN_RING3 */
562
563	#ifdef LOG_ENABLED
564
565	/**
566	* Index register string name lookup
567	*
568	* @returns Index register string or "UNKNOWN"
569	* @param pThis VMSVGA State
570	* @param idxReg The index register.
571	*/
572	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
573	{
574	switch (idxReg)
575	{
576	case SVGA_REG_ID: return "SVGA_REG_ID";
577	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
578	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
579	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
580	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
581	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
582	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
583	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
584	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
585	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
586	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
587	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
588	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
589	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
590	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
591	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
592	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
593	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
594	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
595	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
596	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
597	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
598	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
599	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
600	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
601	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
602	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
603	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
604	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
605	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
606	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
607	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
608	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
609	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
610	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
611	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
612	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
613	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
614	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
615	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
616	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
617	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
618	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
619	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
620	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
621	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
622	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
623	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
624	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
625	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
626
627	default:
628	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
629	return "SVGA_SCRATCH_BASE reg";
630	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
631	return "SVGA_PALETTE_BASE reg";
632	return "UNKNOWN";
633	}
634	}
635
636	#ifdef IN_RING3
637	/**
638	* FIFO command name lookup
639	*
640	* @returns FIFO command string or "UNKNOWN"
641	* @param u32Cmd FIFO command
642	*/
643	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
644	{
645	switch (u32Cmd)
646	{
647	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
648	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
649	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
650	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
651	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
652	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
653	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
654	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
655	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
656	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
657	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
658	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
659	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
660	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
661	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
662	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
663	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
664	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
665	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
666	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
667	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
668	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
669	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
670	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
671	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
672	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
673	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
674	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
675	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
676	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
677	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
678	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
679	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
680	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
681	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
682	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
683	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
684	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
685	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
686	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
687	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
688	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
689	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
690	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
691	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
692	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
693	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
694	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
695	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
696	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
697	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
698	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
699	default: return "UNKNOWN";
700	}
701	}
702	# endif /* IN_RING3 */
703
704	#endif /* LOG_ENABLED */
705
706	#ifdef IN_RING3
707	/**
708	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
709	*/
710	DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
711	{
712	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
713
714	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
715	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
716
717	/** @todo Test how it interacts with multiple screen objects. */
718	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
719	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
720	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
721
722	if (x < uWidth)
723	{
724	pThis->svga.viewport.x = x;
725	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
726	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
727	}
728	else
729	{
730	pThis->svga.viewport.x = uWidth;
731	pThis->svga.viewport.cx = 0;
732	pThis->svga.viewport.xRight = uWidth;
733	}
734	if (y < uHeight)
735	{
736	pThis->svga.viewport.y = y;
737	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
738	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
739	pThis->svga.viewport.yHighWC = uHeight - y;
740	}
741	else
742	{
743	pThis->svga.viewport.y = uHeight;
744	pThis->svga.viewport.cy = 0;
745	pThis->svga.viewport.yLowWC = 0;
746	pThis->svga.viewport.yHighWC = 0;
747	}
748
749	# ifdef VBOX_WITH_VMSVGA3D
750	/*
751	* Now inform the 3D backend.
752	*/
753	if (pThis->svga.f3DEnabled)
754	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
755	# else
756	RT_NOREF(OldViewport);
757	# endif
758	}
759	#endif /* IN_RING3 */
760
761	/**
762	* Read port register
763	*
764	* @returns VBox status code.
765	* @param pDevIns The device instance.
766	* @param pThis VMSVGA State
767	* @param pu32 Where to store the read value
768	*/
769	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
770	{
771	int rc = VINF_SUCCESS;
772	*pu32 = 0;
773
774	/* Rough index register validation. */
775	uint32_t idxReg = pThis->svga.u32IndexReg;
776	#if !defined(IN_RING3) && defined(VBOX_STRICT)
777	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
778	VINF_IOM_R3_IOPORT_READ);
779	#else
780	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
781	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
782	VINF_SUCCESS);
783	#endif
784	RT_UNTRUSTED_VALIDATED_FENCE();
785
786	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
787	if ( idxReg >= SVGA_REG_CAPABILITIES
788	&& pThis->svga.u32SVGAId == SVGA_ID_0)
789	{
790	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
791	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
792	}
793
794	switch (idxReg)
795	{
796	case SVGA_REG_ID:
797	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
798	*pu32 = pThis->svga.u32SVGAId;
799	break;
800
801	case SVGA_REG_ENABLE:
802	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
803	*pu32 = pThis->svga.fEnabled;
804	break;
805
806	case SVGA_REG_WIDTH:
807	{
808	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
809	if ( pThis->svga.fEnabled
810	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
811	{
812	*pu32 = pThis->svga.uWidth;
813	}
814	else
815	{
816	#ifndef IN_RING3
817	rc = VINF_IOM_R3_IOPORT_READ;
818	#else
819	*pu32 = pThis->pDrv->cx;
820	#endif
821	}
822	break;
823	}
824
825	case SVGA_REG_HEIGHT:
826	{
827	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
828	if ( pThis->svga.fEnabled
829	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
830	{
831	*pu32 = pThis->svga.uHeight;
832	}
833	else
834	{
835	#ifndef IN_RING3
836	rc = VINF_IOM_R3_IOPORT_READ;
837	#else
838	*pu32 = pThis->pDrv->cy;
839	#endif
840	}
841	break;
842	}
843
844	case SVGA_REG_MAX_WIDTH:
845	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
846	*pu32 = pThis->svga.u32MaxWidth;
847	break;
848
849	case SVGA_REG_MAX_HEIGHT:
850	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
851	*pu32 = pThis->svga.u32MaxHeight;
852	break;
853
854	case SVGA_REG_DEPTH:
855	/* This returns the color depth of the current mode. */
856	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
857	switch (pThis->svga.uBpp)
858	{
859	case 15:
860	case 16:
861	case 24:
862	*pu32 = pThis->svga.uBpp;
863	break;
864
865	default:
866	case 32:
867	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
868	break;
869	}
870	break;
871
872	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
873	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
874	if ( pThis->svga.fEnabled
875	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
876	{
877	*pu32 = pThis->svga.uBpp;
878	}
879	else
880	{
881	#ifndef IN_RING3
882	rc = VINF_IOM_R3_IOPORT_READ;
883	#else
884	*pu32 = pThis->pDrv->cBits;
885	#endif
886	}
887	break;
888
889	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
890	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
891	if ( pThis->svga.fEnabled
892	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
893	{
894	*pu32 = (pThis->svga.uBpp + 7) & ~7;
895	}
896	else
897	{
898	#ifndef IN_RING3
899	rc = VINF_IOM_R3_IOPORT_READ;
900	#else
901	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
902	#endif
903	}
904	break;
905
906	case SVGA_REG_PSEUDOCOLOR:
907	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
908	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
909	break;
910
911	case SVGA_REG_RED_MASK:
912	case SVGA_REG_GREEN_MASK:
913	case SVGA_REG_BLUE_MASK:
914	{
915	uint32_t uBpp;
916
917	if ( pThis->svga.fEnabled
918	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
919	{
920	uBpp = pThis->svga.uBpp;
921	}
922	else
923	{
924	#ifndef IN_RING3
925	rc = VINF_IOM_R3_IOPORT_READ;
926	break;
927	#else
928	uBpp = pThis->pDrv->cBits;
929	#endif
930	}
931	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
932	switch (uBpp)
933	{
934	case 8:
935	u32RedMask = 0x07;
936	u32GreenMask = 0x38;
937	u32BlueMask = 0xc0;
938	break;
939
940	case 15:
941	u32RedMask = 0x0000001f;
942	u32GreenMask = 0x000003e0;
943	u32BlueMask = 0x00007c00;
944	break;
945
946	case 16:
947	u32RedMask = 0x0000001f;
948	u32GreenMask = 0x000007e0;
949	u32BlueMask = 0x0000f800;
950	break;
951
952	case 24:
953	case 32:
954	default:
955	u32RedMask = 0x00ff0000;
956	u32GreenMask = 0x0000ff00;
957	u32BlueMask = 0x000000ff;
958	break;
959	}
960	switch (idxReg)
961	{
962	case SVGA_REG_RED_MASK:
963	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
964	*pu32 = u32RedMask;
965	break;
966
967	case SVGA_REG_GREEN_MASK:
968	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
969	*pu32 = u32GreenMask;
970	break;
971
972	case SVGA_REG_BLUE_MASK:
973	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
974	*pu32 = u32BlueMask;
975	break;
976	}
977	break;
978	}
979
980	case SVGA_REG_BYTES_PER_LINE:
981	{
982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
983	if ( pThis->svga.fEnabled
984	&& pThis->svga.cbScanline)
985	{
986	*pu32 = pThis->svga.cbScanline;
987	}
988	else
989	{
990	#ifndef IN_RING3
991	rc = VINF_IOM_R3_IOPORT_READ;
992	#else
993	*pu32 = pThis->pDrv->cbScanline;
994	#endif
995	}
996	break;
997	}
998
999	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1000	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1001	*pu32 = pThis->vram_size;
1002	break;
1003
1004	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1005	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1006	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1007	*pu32 = pThis->GCPhysVRAM;
1008	break;
1009
1010	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1011	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1012	/* Always zero in our case. */
1013	*pu32 = 0;
1014	break;
1015
1016	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1017	{
1018	#ifndef IN_RING3
1019	rc = VINF_IOM_R3_IOPORT_READ;
1020	#else
1021	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1022
1023	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1024	if ( pThis->svga.fEnabled
1025	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1026	{
1027	/* Hardware enabled; return real framebuffer size .*/
1028	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1029	}
1030	else
1031	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1032
1033	pu32 = RT_MIN(pThis->vram_size, pu32);
1034	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1035	#endif
1036	break;
1037	}
1038
1039	case SVGA_REG_CAPABILITIES:
1040	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1041	*pu32 = pThis->svga.u32RegCaps;
1042	break;
1043
1044	case SVGA_REG_MEM_START: /* FIFO start */
1045	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1046	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1047	*pu32 = pThis->svga.GCPhysFIFO;
1048	break;
1049
1050	case SVGA_REG_MEM_SIZE: /* FIFO size */
1051	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1052	*pu32 = pThis->svga.cbFIFO;
1053	break;
1054
1055	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1056	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1057	*pu32 = pThis->svga.fConfigured;
1058	break;
1059
1060	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1061	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1062	*pu32 = 0;
1063	break;
1064
1065	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1066	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1067	if (pThis->svga.fBusy)
1068	{
1069	#ifndef IN_RING3
1070	/* Go to ring-3 and halt the CPU. */
1071	rc = VINF_IOM_R3_IOPORT_READ;
1072	RT_NOREF(pDevIns);
1073	break;
1074	#else
1075	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1076	/* The guest is basically doing a HLT via the device here, but with
1077	a special wake up condition on FIFO completion. */
1078	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1079	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1080	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1081	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1082	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1083	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1084	if (pThis->svga.fBusy)
1085	{
1086	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1087	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1088	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1089	}
1090	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1091	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1092	# else
1093
1094	/* Delay the EMT a bit so the FIFO and others can get some work done.
1095	This used to be a crude 50 ms sleep. The current code tries to be
1096	more efficient, but the consept is still very crude. */
1097	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1098	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1099	RTThreadYield();
1100	if (pThis->svga.fBusy)
1101	{
1102	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1103
1104	if (pThis->svga.fBusy && cRefs == 1)
1105	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1106	if (pThis->svga.fBusy)
1107	{
1108	/** @todo If this code is going to stay, we need to call into the halt/wait
1109	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1110	* suffer when the guest is polling on a busy FIFO. */
1111	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1112	if (cNsMaxWait >= RT_NS_100US)
1113	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1114	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1115	RT_MIN(cNsMaxWait, RT_NS_10MS));
1116	}
1117
1118	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1119	}
1120	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1121	# endif
1122	*pu32 = pThis->svga.fBusy != 0;
1123	#endif
1124	}
1125	else
1126	*pu32 = false;
1127	break;
1128
1129	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1130	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1131	*pu32 = pThis->svga.u32GuestId;
1132	break;
1133
1134	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1135	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1136	*pu32 = pThis->svga.cScratchRegion;
1137	break;
1138
1139	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1140	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1141	*pu32 = SVGA_FIFO_NUM_REGS;
1142	break;
1143
1144	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1145	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1146	*pu32 = pThis->svga.u32PitchLock;
1147	break;
1148
1149	case SVGA_REG_IRQMASK: /* Interrupt mask */
1150	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1151	*pu32 = pThis->svga.u32IrqMask;
1152	break;
1153
1154	/* See "Guest memory regions" below. */
1155	case SVGA_REG_GMR_ID:
1156	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1157	*pu32 = pThis->svga.u32CurrentGMRId;
1158	break;
1159
1160	case SVGA_REG_GMR_DESCRIPTOR:
1161	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1162	/* Write only */
1163	*pu32 = 0;
1164	break;
1165
1166	case SVGA_REG_GMR_MAX_IDS:
1167	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1168	*pu32 = pThis->svga.cGMR;
1169	break;
1170
1171	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1172	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1173	*pu32 = VMSVGA_MAX_GMR_PAGES;
1174	break;
1175
1176	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1177	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1178	*pu32 = pThis->svga.fTraces;
1179	break;
1180
1181	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1183	*pu32 = VMSVGA_MAX_GMR_PAGES;
1184	break;
1185
1186	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1187	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1188	*pu32 = VMSVGA_SURFACE_SIZE;
1189	break;
1190
1191	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1192	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1193	break;
1194
1195	/* Mouse cursor support. */
1196	case SVGA_REG_CURSOR_ID:
1197	case SVGA_REG_CURSOR_X:
1198	case SVGA_REG_CURSOR_Y:
1199	case SVGA_REG_CURSOR_ON:
1200	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1201	break;
1202
1203	/* Legacy multi-monitor support */
1204	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1205	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1206	*pu32 = 1;
1207	break;
1208
1209	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1210	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1211	*pu32 = 0;
1212	break;
1213
1214	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1215	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1216	*pu32 = 0;
1217	break;
1218
1219	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1220	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1221	*pu32 = 0;
1222	break;
1223
1224	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1225	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1226	*pu32 = 0;
1227	break;
1228
1229	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1230	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1231	*pu32 = pThis->svga.uWidth;
1232	break;
1233
1234	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1235	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1236	*pu32 = pThis->svga.uHeight;
1237	break;
1238
1239	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1240	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1241	/* We must return something sensible here otherwise the Linux driver
1242	will take a legacy code path without 3d support. This number also
1243	limits how many screens Linux guests will allow. */
1244	*pu32 = pThis->cMonitors;
1245	break;
1246
1247	default:
1248	{
1249	uint32_t offReg;
1250	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1251	{
1252	RT_UNTRUSTED_VALIDATED_FENCE();
1253	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1254	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1255	}
1256	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1257	{
1258	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1259	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1260	RT_UNTRUSTED_VALIDATED_FENCE();
1261	uint32_t u32 = pThis->last_palette[offReg / 3];
1262	switch (offReg % 3)
1263	{
1264	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1265	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1266	case 2: pu32 = u32 & 0xff; break; / blue */
1267	}
1268	}
1269	else
1270	{
1271	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1272	rc = VINF_IOM_R3_IOPORT_READ;
1273	#else
1274	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1275
1276	/* Do not assert. The guest might be reading all registers. */
1277	LogFunc(("Unknown reg=%#x\n", idxReg));
1278	#endif
1279	}
1280	break;
1281	}
1282	}
1283	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1284	return rc;
1285	}
1286
1287	#ifdef IN_RING3
1288	/**
1289	* Apply the current resolution settings to change the video mode.
1290	*
1291	* @returns VBox status code.
1292	* @param pThis VMSVGA State
1293	*/
1294	static int vmsvgaChangeMode(PVGASTATE pThis)
1295	{
1296	int rc;
1297
1298	/* Always do changemode on FIFO thread. */
1299	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1300
1301	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1302
1303	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1304
1305	if (pThis->svga.fGFBRegisters)
1306	{
1307	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1308	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1309	* deletes all screens other than screen #0, and redefines screen
1310	* #0 according to the specified mode. Drivers that use
1311	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1312	*/
1313
1314	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1315	pScreen->fDefined = true;
1316	pScreen->fModified = true;
1317	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1318	pScreen->idScreen = 0;
1319	pScreen->xOrigin = 0;
1320	pScreen->yOrigin = 0;
1321	pScreen->offVRAM = 0;
1322	pScreen->cbPitch = pThis->svga.cbScanline;
1323	pScreen->cWidth = pThis->svga.uWidth;
1324	pScreen->cHeight = pThis->svga.uHeight;
1325	pScreen->cBpp = pThis->svga.uBpp;
1326
1327	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1328	{
1329	/* Delete screen. */
1330	pScreen = &pSVGAState->aScreens[iScreen];
1331	if (pScreen->fDefined)
1332	{
1333	pScreen->fModified = true;
1334	pScreen->fDefined = false;
1335	}
1336	}
1337	}
1338	else
1339	{
1340	/* "If Screen Objects are supported, they can be used to fully
1341	* replace the functionality provided by the framebuffer registers
1342	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1343	*/
1344	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1345	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1346	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1347	}
1348
1349	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1350	{
1351	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1352	if (!pScreen->fModified)
1353	continue;
1354
1355	pScreen->fModified = false;
1356
1357	VBVAINFOVIEW view;
1358	RT_ZERO(view);
1359	view.u32ViewIndex = pScreen->idScreen;
1360	// view.u32ViewOffset = 0;
1361	view.u32ViewSize = pThis->vram_size;
1362	view.u32MaxScreenSize = pThis->vram_size;
1363
1364	VBVAINFOSCREEN screen;
1365	RT_ZERO(screen);
1366	screen.u32ViewIndex = pScreen->idScreen;
1367
1368	if (pScreen->fDefined)
1369	{
1370	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1371	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1372	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1373	{
1374	Assert(pThis->svga.fGFBRegisters);
1375	continue;
1376	}
1377
1378	screen.i32OriginX = pScreen->xOrigin;
1379	screen.i32OriginY = pScreen->yOrigin;
1380	screen.u32StartOffset = pScreen->offVRAM;
1381	screen.u32LineSize = pScreen->cbPitch;
1382	screen.u32Width = pScreen->cWidth;
1383	screen.u32Height = pScreen->cHeight;
1384	screen.u16BitsPerPixel = pScreen->cBpp;
1385	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1386	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1387	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1388	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1389	}
1390	else
1391	{
1392	/* Screen is destroyed. */
1393	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1394	}
1395
1396	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1397	AssertRC(rc);
1398	}
1399
1400	/* Last stuff. For the VGA device screenshot. */
1401	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1402	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1403	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1404	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1405	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1406
1407	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1408	if ( pThis->svga.viewport.cx == 0
1409	&& pThis->svga.viewport.cy == 0)
1410	{
1411	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1412	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1413	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1414	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1415	pThis->svga.viewport.yLowWC = 0;
1416	}
1417
1418	return VINF_SUCCESS;
1419	}
1420
1421	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1422	{
1423	VBVACMDHDR cmd;
1424	cmd.x = (int16_t)(pScreen->xOrigin + x);
1425	cmd.y = (int16_t)(pScreen->yOrigin + y);
1426	cmd.w = (uint16_t)w;
1427	cmd.h = (uint16_t)h;
1428
1429	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1430	pThis->pDrv->pfnVBVAUpdateProcess(pThis->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1431	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1432	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1433
1434	return VINF_SUCCESS;
1435	}
1436
1437	#endif /* IN_RING3 */
1438	#if defined(IN_RING0) \|\| defined(IN_RING3)
1439
1440	/**
1441	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1442	*
1443	* @param pThis The VMSVGA state.
1444	* @param fState The busy state.
1445	*/
1446	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1447	{
1448	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1449
1450	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1451	{
1452	/* Race / unfortunately scheduling. Highly unlikly. */
1453	uint32_t cLoops = 64;
1454	do
1455	{
1456	ASMNopPause();
1457	fState = (pThis->svga.fBusy != 0);
1458	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1459	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1460	}
1461	}
1462
1463
1464	/**
1465	* Update the scanline pitch in response to the guest changing mode
1466	* width/bpp.
1467	*
1468	* @param pThis VMSVGA State
1469	*/
1470	DECLINLINE(void) vmsvgaUpdatePitch(PVGASTATE pThis)
1471	{
1472	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.CTX_SUFF(pFIFO);
1473	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1474	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1475	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1476
1477	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1478	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1479	* location but it has a different meaning.
1480	*/
1481	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1482	uFifoPitchLock = 0;
1483
1484	/* Sanitize values. */
1485	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1486	uFifoPitchLock = 0;
1487	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1488	uRegPitchLock = 0;
1489
1490	/* Prefer the register value to the FIFO value.*/
1491	if (uRegPitchLock)
1492	pThis->svga.cbScanline = uRegPitchLock;
1493	else if (uFifoPitchLock)
1494	pThis->svga.cbScanline = uFifoPitchLock;
1495	else
1496	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1497
1498	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1499	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1500	}
1501
1502	#endif /* IN_RING0 \|\| IN_RING3 */
1503
1504
1505	/**
1506	* Write port register
1507	*
1508	* @returns VBox status code.
1509	* @param pThis VMSVGA State
1510	* @param u32 Value to write
1511	*/
1512	static int vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1513	{
1514	#ifdef IN_RING3
1515	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1516	#endif
1517	int rc = VINF_SUCCESS;
1518
1519	/* Rough index register validation. */
1520	uint32_t idxReg = pThis->svga.u32IndexReg;
1521	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1522	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1523	VINF_IOM_R3_IOPORT_WRITE);
1524	#else
1525	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1526	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1527	VINF_SUCCESS);
1528	#endif
1529	RT_UNTRUSTED_VALIDATED_FENCE();
1530
1531	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1532	if ( idxReg >= SVGA_REG_CAPABILITIES
1533	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1534	{
1535	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1536	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1537	}
1538	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1539	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1540	switch (idxReg)
1541	{
1542	case SVGA_REG_WIDTH:
1543	case SVGA_REG_HEIGHT:
1544	case SVGA_REG_PITCHLOCK:
1545	case SVGA_REG_BITS_PER_PIXEL:
1546	pThis->svga.fGFBRegisters = true;
1547	break;
1548	default:
1549	break;
1550	}
1551
1552	switch (idxReg)
1553	{
1554	case SVGA_REG_ID:
1555	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1556	if ( u32 == SVGA_ID_0
1557	\|\| u32 == SVGA_ID_1
1558	\|\| u32 == SVGA_ID_2)
1559	pThis->svga.u32SVGAId = u32;
1560	else
1561	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1562	break;
1563
1564	case SVGA_REG_ENABLE:
1565	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1566	#ifdef IN_RING3
1567	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1568	&& pThis->svga.fEnabled == false)
1569	{
1570	/* Make a backup copy of the first 512kb in order to save font data etc. */
1571	/** @todo should probably swap here, rather than copy + zero */
1572	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1573	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1574	}
1575
1576	pThis->svga.fEnabled = u32;
1577	if (pThis->svga.fEnabled)
1578	{
1579	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1580	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1581	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1582	{
1583	/* Keep the current mode. */
1584	pThis->svga.uWidth = pThis->pDrv->cx;
1585	pThis->svga.uHeight = pThis->pDrv->cy;
1586	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1587	}
1588
1589	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1590	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1591	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1592	{
1593	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1594	}
1595	# ifdef LOG_ENABLED
1596	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1597	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1598	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1599	# endif
1600
1601	/* Disable or enable dirty page tracking according to the current fTraces value. */
1602	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1603
1604	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1605	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1606	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/);
1607	}
1608	else
1609	{
1610	/* Restore the text mode backup. */
1611	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1612
1613	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1614
1615	/* Enable dirty page tracking again when going into legacy mode. */
1616	vmsvgaSetTraces(pThis, true);
1617
1618	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1619	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1620	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1621
1622	/* Clear the pitch lock. */
1623	pThis->svga.u32PitchLock = 0;
1624	}
1625	#else /* !IN_RING3 */
1626	rc = VINF_IOM_R3_IOPORT_WRITE;
1627	#endif /* !IN_RING3 */
1628	break;
1629
1630	case SVGA_REG_WIDTH:
1631	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1632	if (pThis->svga.uWidth != u32)
1633	{
1634	#if defined(IN_RING3) \|\| defined(IN_RING0)
1635	pThis->svga.uWidth = u32;
1636	vmsvgaUpdatePitch(pThis);
1637	if (pThis->svga.fEnabled)
1638	{
1639	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1640	}
1641	#else
1642	rc = VINF_IOM_R3_IOPORT_WRITE;
1643	#endif
1644	}
1645	/* else: nop */
1646	break;
1647
1648	case SVGA_REG_HEIGHT:
1649	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1650	if (pThis->svga.uHeight != u32)
1651	{
1652	pThis->svga.uHeight = u32;
1653	if (pThis->svga.fEnabled)
1654	{
1655	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1656	}
1657	}
1658	/* else: nop */
1659	break;
1660
1661	case SVGA_REG_DEPTH:
1662	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1663	/** @todo read-only?? */
1664	break;
1665
1666	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1667	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1668	if (pThis->svga.uBpp != u32)
1669	{
1670	#if defined(IN_RING3) \|\| defined(IN_RING0)
1671	pThis->svga.uBpp = u32;
1672	vmsvgaUpdatePitch(pThis);
1673	if (pThis->svga.fEnabled)
1674	{
1675	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1676	}
1677	#else
1678	rc = VINF_IOM_R3_IOPORT_WRITE;
1679	#endif
1680	}
1681	/* else: nop */
1682	break;
1683
1684	case SVGA_REG_PSEUDOCOLOR:
1685	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1686	break;
1687
1688	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1689	#ifdef IN_RING3
1690	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1691	pThis->svga.fConfigured = u32;
1692	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1693	if (!pThis->svga.fConfigured)
1694	{
1695	pThis->svga.fTraces = true;
1696	}
1697	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1698	#else
1699	rc = VINF_IOM_R3_IOPORT_WRITE;
1700	#endif
1701	break;
1702
1703	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1704	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1705	if ( pThis->svga.fEnabled
1706	&& pThis->svga.fConfigured)
1707	{
1708	#if defined(IN_RING3) \|\| defined(IN_RING0)
1709	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1710	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1711	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1712	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1713
1714	/* Kick the FIFO thread to start processing commands again. */
1715	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1716	#else
1717	rc = VINF_IOM_R3_IOPORT_WRITE;
1718	#endif
1719	}
1720	/* else nothing to do. */
1721	else
1722	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1723
1724	break;
1725
1726	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1727	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1728	break;
1729
1730	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1731	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1732	pThis->svga.u32GuestId = u32;
1733	break;
1734
1735	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1736	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1737	pThis->svga.u32PitchLock = u32;
1738	/* Should this also update the FIFO pitch lock? Unclear. */
1739	break;
1740
1741	case SVGA_REG_IRQMASK: /* Interrupt mask */
1742	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1743	pThis->svga.u32IrqMask = u32;
1744
1745	/* Irq pending after the above change? */
1746	if (pThis->svga.u32IrqStatus & u32)
1747	{
1748	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1749	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1750	}
1751	else
1752	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1753	break;
1754
1755	/* Mouse cursor support */
1756	case SVGA_REG_CURSOR_ID:
1757	case SVGA_REG_CURSOR_X:
1758	case SVGA_REG_CURSOR_Y:
1759	case SVGA_REG_CURSOR_ON:
1760	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1761	break;
1762
1763	/* Legacy multi-monitor support */
1764	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1765	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1766	break;
1767	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1768	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1769	break;
1770	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1771	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1772	break;
1773	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1774	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1775	break;
1776	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1777	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1778	break;
1779	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1781	break;
1782	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1783	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1784	break;
1785	#ifdef VBOX_WITH_VMSVGA3D
1786	/* See "Guest memory regions" below. */
1787	case SVGA_REG_GMR_ID:
1788	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1789	pThis->svga.u32CurrentGMRId = u32;
1790	break;
1791
1792	case SVGA_REG_GMR_DESCRIPTOR:
1793	# ifndef IN_RING3
1794	rc = VINF_IOM_R3_IOPORT_WRITE;
1795	break;
1796	# else /* IN_RING3 */
1797	{
1798	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1799
1800	/* Validate current GMR id. */
1801	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1802	AssertBreak(idGMR < pThis->svga.cGMR);
1803	RT_UNTRUSTED_VALIDATED_FENCE();
1804
1805	/* Free the old GMR if present. */
1806	vmsvgaGMRFree(pThis, idGMR);
1807
1808	/* Just undefine the GMR? */
1809	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1810	if (GCPhys == 0)
1811	{
1812	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1813	break;
1814	}
1815
1816
1817	/* Never cross a page boundary automatically. */
1818	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1819	uint32_t cPagesTotal = 0;
1820	uint32_t iDesc = 0;
1821	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1822	uint32_t cLoops = 0;
1823	RTGCPHYS GCPhysBase = GCPhys;
1824	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1825	{
1826	/* Read descriptor. */
1827	SVGAGuestMemDescriptor desc;
1828	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1829	AssertRCBreak(rc);
1830
1831	if (desc.numPages != 0)
1832	{
1833	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1834	cPagesTotal += desc.numPages;
1835	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1836
1837	if ((iDesc & 15) == 0)
1838	{
1839	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1840	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1841	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1842	}
1843
1844	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1845	paDescs[iDesc++].numPages = desc.numPages;
1846
1847	/* Continue with the next descriptor. */
1848	GCPhys += sizeof(desc);
1849	}
1850	else if (desc.ppn == 0)
1851	break; /* terminator */
1852	else /* Pointer to the next physical page of descriptors. */
1853	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1854
1855	cLoops++;
1856	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1857	}
1858
1859	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1860	if (RT_SUCCESS(rc))
1861	{
1862	/* Commit the GMR. */
1863	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1864	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1865	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1866	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1867	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1868	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1869	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1870	}
1871	else
1872	{
1873	RTMemFree(paDescs);
1874	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1875	}
1876	break;
1877	}
1878	# endif /* IN_RING3 */
1879	#endif // VBOX_WITH_VMSVGA3D
1880
1881	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1882	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1883	if (pThis->svga.fTraces == u32)
1884	break; /* nothing to do */
1885
1886	#ifdef IN_RING3
1887	vmsvgaSetTraces(pThis, !!u32);
1888	#else
1889	rc = VINF_IOM_R3_IOPORT_WRITE;
1890	#endif
1891	break;
1892
1893	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1894	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1895	break;
1896
1897	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1898	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1899	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1900	break;
1901
1902	case SVGA_REG_FB_START:
1903	case SVGA_REG_MEM_START:
1904	case SVGA_REG_HOST_BITS_PER_PIXEL:
1905	case SVGA_REG_MAX_WIDTH:
1906	case SVGA_REG_MAX_HEIGHT:
1907	case SVGA_REG_VRAM_SIZE:
1908	case SVGA_REG_FB_SIZE:
1909	case SVGA_REG_CAPABILITIES:
1910	case SVGA_REG_MEM_SIZE:
1911	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1912	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1913	case SVGA_REG_BYTES_PER_LINE:
1914	case SVGA_REG_FB_OFFSET:
1915	case SVGA_REG_RED_MASK:
1916	case SVGA_REG_GREEN_MASK:
1917	case SVGA_REG_BLUE_MASK:
1918	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1919	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1920	case SVGA_REG_GMR_MAX_IDS:
1921	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1922	/* Read only - ignore. */
1923	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1924	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1925	break;
1926
1927	default:
1928	{
1929	uint32_t offReg;
1930	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1931	{
1932	RT_UNTRUSTED_VALIDATED_FENCE();
1933	pThis->svga.au32ScratchRegion[offReg] = u32;
1934	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1935	}
1936	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1937	{
1938	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1939	Btw, see rgb_to_pixel32. */
1940	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1941	u32 &= 0xff;
1942	RT_UNTRUSTED_VALIDATED_FENCE();
1943	uint32_t uRgb = pThis->last_palette[offReg / 3];
1944	switch (offReg % 3)
1945	{
1946	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1947	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1948	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1949	}
1950	pThis->last_palette[offReg / 3] = uRgb;
1951	}
1952	else
1953	{
1954	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1955	rc = VINF_IOM_R3_IOPORT_WRITE;
1956	#else
1957	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1958	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1959	#endif
1960	}
1961	break;
1962	}
1963	}
1964	return rc;
1965	}
1966
1967	/**
1968	* @callback_method_impl{FNIOMIOPORTNEWIN}
1969	*/
1970	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1971	{
1972	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1973	RT_NOREF_PV(pvUser);
1974
1975	/* Only dword accesses. */
1976	if (cb == 4)
1977	{
1978	switch (offPort)
1979	{
1980	case SVGA_INDEX_PORT:
1981	*pu32 = pThis->svga.u32IndexReg;
1982	break;
1983
1984	case SVGA_VALUE_PORT:
1985	return vmsvgaReadPort(pDevIns, pThis, pu32);
1986
1987	case SVGA_BIOS_PORT:
1988	Log(("Ignoring BIOS port read\n"));
1989	*pu32 = 0;
1990	break;
1991
1992	case SVGA_IRQSTATUS_PORT:
1993	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1994	*pu32 = pThis->svga.u32IrqStatus;
1995	break;
1996
1997	default:
1998	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
1999	*pu32 = UINT32_MAX;
2000	break;
2001	}
2002	}
2003	else
2004	{
2005	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2006	*pu32 = UINT32_MAX;
2007	}
2008	return VINF_SUCCESS;
2009	}
2010
2011	/**
2012	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2013	*/
2014	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2015	{
2016	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2017	RT_NOREF_PV(pvUser);
2018
2019	/* Only dword accesses. */
2020	if (cb == 4)
2021	switch (offPort)
2022	{
2023	case SVGA_INDEX_PORT:
2024	pThis->svga.u32IndexReg = u32;
2025	break;
2026
2027	case SVGA_VALUE_PORT:
2028	return vmsvgaWritePort(pThis, u32);
2029
2030	case SVGA_BIOS_PORT:
2031	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2032	break;
2033
2034	case SVGA_IRQSTATUS_PORT:
2035	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2036	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2037	/* Clear the irq in case all events have been cleared. */
2038	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2039	{
2040	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2041	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2042	}
2043	break;
2044
2045	default:
2046	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2047	break;
2048	}
2049	else
2050	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2051
2052	return VINF_SUCCESS;
2053	}
2054
2055	#ifdef IN_RING3
2056
2057	# ifdef DEBUG_FIFO_ACCESS
2058	/**
2059	* Handle FIFO memory access.
2060	* @returns VBox status code.
2061	* @param pVM VM handle.
2062	* @param pThis VGA device instance data.
2063	* @param GCPhys The access physical address.
2064	* @param fWriteAccess Read or write access
2065	*/
2066	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2067	{
2068	RT_NOREF(pVM);
2069	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2070	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2071
2072	switch (GCPhysOffset >> 2)
2073	{
2074	case SVGA_FIFO_MIN:
2075	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2076	break;
2077	case SVGA_FIFO_MAX:
2078	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2079	break;
2080	case SVGA_FIFO_NEXT_CMD:
2081	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2082	break;
2083	case SVGA_FIFO_STOP:
2084	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2085	break;
2086	case SVGA_FIFO_CAPABILITIES:
2087	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2088	break;
2089	case SVGA_FIFO_FLAGS:
2090	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2091	break;
2092	case SVGA_FIFO_FENCE:
2093	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2094	break;
2095	case SVGA_FIFO_3D_HWVERSION:
2096	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2097	break;
2098	case SVGA_FIFO_PITCHLOCK:
2099	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2100	break;
2101	case SVGA_FIFO_CURSOR_ON:
2102	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2103	break;
2104	case SVGA_FIFO_CURSOR_X:
2105	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2106	break;
2107	case SVGA_FIFO_CURSOR_Y:
2108	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2109	break;
2110	case SVGA_FIFO_CURSOR_COUNT:
2111	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2112	break;
2113	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2114	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2115	break;
2116	case SVGA_FIFO_RESERVED:
2117	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2118	break;
2119	case SVGA_FIFO_CURSOR_SCREEN_ID:
2120	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2121	break;
2122	case SVGA_FIFO_DEAD:
2123	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2124	break;
2125	case SVGA_FIFO_3D_HWVERSION_REVISED:
2126	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2127	break;
2128	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2129	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2130	break;
2131	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2132	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2133	break;
2134	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2135	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2136	break;
2137	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2138	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2139	break;
2140	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2141	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2142	break;
2143	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2144	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2145	break;
2146	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2147	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2148	break;
2149	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2150	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2151	break;
2152	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2153	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2154	break;
2155	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2156	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2157	break;
2158	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2159	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2160	break;
2161	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2162	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2163	break;
2164	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2165	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2166	break;
2167	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2168	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2169	break;
2170	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2171	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2172	break;
2173	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2174	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2175	break;
2176	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2183	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2184	break;
2185	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2186	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2187	break;
2188	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2189	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2190	break;
2191	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2192	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2193	break;
2194	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2195	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2196	break;
2197	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2198	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2199	break;
2200	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2201	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2202	break;
2203	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2204	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2205	break;
2206	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2207	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2208	break;
2209	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2210	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2211	break;
2212	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2213	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2214	break;
2215	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2216	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2217	break;
2218	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2219	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2220	break;
2221	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2222	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2223	break;
2224	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2225	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2226	break;
2227	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2228	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2229	break;
2230	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2231	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2232	break;
2233	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2234	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2235	break;
2236	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2237	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2238	break;
2239	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2240	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2241	break;
2242	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2243	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2244	break;
2245	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2246	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2247	break;
2248	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2249	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2250	break;
2251	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2327	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2328	break;
2329	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2330	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2331	break;
2332	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2333	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2334	break;
2335	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2336	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2337	break;
2338	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2339	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2340	break;
2341	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2342	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2343	break;
2344	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2345	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2346	break;
2347	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2348	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2349	break;
2350	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2351	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2352	break;
2353	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2354	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2355	break;
2356	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2357	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2358	break;
2359	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2360	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2361	break;
2362	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2363	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2364	break;
2365	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2366	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2367	break;
2368	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2369	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2370	break;
2371	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2372	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2373	break;
2374	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2375	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2376	break;
2377	case SVGA_FIFO_3D_CAPS_LAST:
2378	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2379	break;
2380	case SVGA_FIFO_GUEST_3D_HWVERSION:
2381	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2382	break;
2383	case SVGA_FIFO_FENCE_GOAL:
2384	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2385	break;
2386	case SVGA_FIFO_BUSY:
2387	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2388	break;
2389	default:
2390	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2391	break;
2392	}
2393
2394	return VINF_EM_RAW_EMULATE_INSTR;
2395	}
2396	# endif /* DEBUG_FIFO_ACCESS */
2397
2398	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2399	/**
2400	* HC access handler for the FIFO.
2401	*
2402	* @returns VINF_SUCCESS if the handler have carried out the operation.
2403	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2404	* @param pVM VM Handle.
2405	* @param pVCpu The cross context CPU structure for the calling EMT.
2406	* @param GCPhys The physical address the guest is writing to.
2407	* @param pvPhys The HC mapping of that address.
2408	* @param pvBuf What the guest is reading/writing.
2409	* @param cbBuf How much it's reading/writing.
2410	* @param enmAccessType The access type.
2411	* @param enmOrigin Who is making the access.
2412	* @param pvUser User argument.
2413	*/
2414	static DECLCALLBACK(VBOXSTRICTRC)
2415	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2416	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2417	{
2418	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2419	PVGASTATE pThis = (PVGASTATE)pvUser;
2420	AssertPtr(pThis);
2421
2422	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2423	/*
2424	* Wake up the FIFO thread as it might have work to do now.
2425	*/
2426	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2427	AssertLogRelRC(rc);
2428	# endif
2429
2430	# ifdef DEBUG_FIFO_ACCESS
2431	/*
2432	* When in debug-fifo-access mode, we do not disable the access handler,
2433	* but leave it on as we wish to catch all access.
2434	*/
2435	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2436	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2437	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2438	/*
2439	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2440	*/
2441	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2442	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2443	# endif
2444	if (RT_SUCCESS(rc))
2445	return VINF_PGM_HANDLER_DO_DEFAULT;
2446	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2447	return rc;
2448	}
2449	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2450
2451	#endif /* IN_RING3 */
2452
2453	#ifdef DEBUG_GMR_ACCESS
2454	# ifdef IN_RING3
2455
2456	/**
2457	* HC access handler for the FIFO.
2458	*
2459	* @returns VINF_SUCCESS if the handler have carried out the operation.
2460	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2461	* @param pVM VM Handle.
2462	* @param pVCpu The cross context CPU structure for the calling EMT.
2463	* @param GCPhys The physical address the guest is writing to.
2464	* @param pvPhys The HC mapping of that address.
2465	* @param pvBuf What the guest is reading/writing.
2466	* @param cbBuf How much it's reading/writing.
2467	* @param enmAccessType The access type.
2468	* @param enmOrigin Who is making the access.
2469	* @param pvUser User argument.
2470	*/
2471	static DECLCALLBACK(VBOXSTRICTRC)
2472	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2473	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2474	{
2475	PVGASTATE pThis = (PVGASTATE)pvUser;
2476	Assert(pThis);
2477	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2478	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2479
2480	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2481
2482	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2483	{
2484	PGMR pGMR = &pSVGAState->paGMR[i];
2485
2486	if (pGMR->numDescriptors)
2487	{
2488	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2489	{
2490	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2491	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2492	{
2493	/*
2494	* Turn off the write handler for this particular page and make it R/W.
2495	* Then return telling the caller to restart the guest instruction.
2496	*/
2497	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2498	AssertRC(rc);
2499	goto end;
2500	}
2501	}
2502	}
2503	}
2504	end:
2505	return VINF_PGM_HANDLER_DO_DEFAULT;
2506	}
2507
2508	/* Callback handler for VMR3ReqCallWaitU */
2509	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2510	{
2511	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2512	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2513	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2514	int rc;
2515
2516	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2517	{
2518	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2519	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2520	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2521	AssertRC(rc);
2522	}
2523	return VINF_SUCCESS;
2524	}
2525
2526	/* Callback handler for VMR3ReqCallWaitU */
2527	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2528	{
2529	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2530	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2531	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2532
2533	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2534	{
2535	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2536	AssertRC(rc);
2537	}
2538	return VINF_SUCCESS;
2539	}
2540
2541	/* Callback handler for VMR3ReqCallWaitU */
2542	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2543	{
2544	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2545
2546	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2547	{
2548	PGMR pGMR = &pSVGAState->paGMR[i];
2549
2550	if (pGMR->numDescriptors)
2551	{
2552	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2553	{
2554	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2555	AssertRC(rc);
2556	}
2557	}
2558	}
2559	return VINF_SUCCESS;
2560	}
2561
2562	# endif /* IN_RING3 */
2563	#endif /* DEBUG_GMR_ACCESS */
2564
2565	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2566
2567	#ifdef IN_RING3
2568
2569
2570	/**
2571	* Common worker for changing the pointer shape.
2572	*
2573	* @param pThis The VGA instance data.
2574	* @param pSVGAState The VMSVGA ring-3 instance data.
2575	* @param fAlpha Whether there is alpha or not.
2576	* @param xHot Hotspot x coordinate.
2577	* @param yHot Hotspot y coordinate.
2578	* @param cx Width.
2579	* @param cy Height.
2580	* @param pbData Heap copy of the cursor data. Consumed.
2581	* @param cbData The size of the data.
2582	*/
2583	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2584	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2585	{
2586	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2587	#ifdef LOG_ENABLED
2588	if (LogIs2Enabled())
2589	{
2590	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2591	if (!fAlpha)
2592	{
2593	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2594	for (uint32_t y = 0; y < cy; y++)
2595	{
2596	Log2(("%3u:", y));
2597	uint8_t const pbLine = &pbData[y cbAndLine];
2598	for (uint32_t x = 0; x < cx; x += 8)
2599	{
2600	uint8_t b = pbLine[x / 8];
2601	char szByte[12];
2602	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2603	szByte[1] = b & 0x40 ? '*' : ' ';
2604	szByte[2] = b & 0x20 ? '*' : ' ';
2605	szByte[3] = b & 0x10 ? '*' : ' ';
2606	szByte[4] = b & 0x08 ? '*' : ' ';
2607	szByte[5] = b & 0x04 ? '*' : ' ';
2608	szByte[6] = b & 0x02 ? '*' : ' ';
2609	szByte[7] = b & 0x01 ? '*' : ' ';
2610	szByte[8] = '\0';
2611	Log2(("%s", szByte));
2612	}
2613	Log2(("\n"));
2614	}
2615	}
2616
2617	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2618	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2619	for (uint32_t y = 0; y < cy; y++)
2620	{
2621	Log2(("%3u:", y));
2622	uint32_t const pu32Line = &pu32Xor[y cx];
2623	for (uint32_t x = 0; x < cx; x++)
2624	Log2((" %08x", pu32Line[x]));
2625	Log2(("\n"));
2626	}
2627	}
2628	#endif
2629
2630	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2631	AssertRC(rc);
2632
2633	if (pSVGAState->Cursor.fActive)
2634	RTMemFree(pSVGAState->Cursor.pData);
2635
2636	pSVGAState->Cursor.fActive = true;
2637	pSVGAState->Cursor.xHotspot = xHot;
2638	pSVGAState->Cursor.yHotspot = yHot;
2639	pSVGAState->Cursor.width = cx;
2640	pSVGAState->Cursor.height = cy;
2641	pSVGAState->Cursor.cbData = cbData;
2642	pSVGAState->Cursor.pData = pbData;
2643	}
2644
2645
2646	/**
2647	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2648	*
2649	* @param pThis The VGA instance data.
2650	* @param pSVGAState The VMSVGA ring-3 instance data.
2651	* @param pCursor The cursor.
2652	* @param pbSrcAndMask The AND mask.
2653	* @param cbSrcAndLine The scanline length of the AND mask.
2654	* @param pbSrcXorMask The XOR mask.
2655	* @param cbSrcXorLine The scanline length of the XOR mask.
2656	*/
2657	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2658	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2659	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2660	{
2661	uint32_t const cx = pCursor->width;
2662	uint32_t const cy = pCursor->height;
2663
2664	/*
2665	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2666	* The AND data uses 8-bit aligned scanlines.
2667	* The XOR data must be starting on a 32-bit boundrary.
2668	*/
2669	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2670	uint32_t cbDstAndMask = cbDstAndLine * cy;
2671	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2672	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2673
2674	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2675	AssertReturnVoid(pbCopy);
2676
2677	/* Convert the AND mask. */
2678	uint8_t *pbDst = pbCopy;
2679	uint8_t const *pbSrc = pbSrcAndMask;
2680	switch (pCursor->andMaskDepth)
2681	{
2682	case 1:
2683	if (cbSrcAndLine == cbDstAndLine)
2684	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2685	else
2686	{
2687	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2688	for (uint32_t y = 0; y < cy; y++)
2689	{
2690	memcpy(pbDst, pbSrc, cbDstAndLine);
2691	pbDst += cbDstAndLine;
2692	pbSrc += cbSrcAndLine;
2693	}
2694	}
2695	break;
2696	/* Should take the XOR mask into account for the multi-bit AND mask. */
2697	case 8:
2698	for (uint32_t y = 0; y < cy; y++)
2699	{
2700	for (uint32_t x = 0; x < cx; )
2701	{
2702	uint8_t bDst = 0;
2703	uint8_t fBit = 1;
2704	do
2705	{
2706	uintptr_t const idxPal = pbSrc[x] * 3;
2707	if ((( pThis->last_palette[idxPal]
2708	\| (pThis->last_palette[idxPal] >> 8)
2709	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2710	bDst \|= fBit;
2711	fBit <<= 1;
2712	x++;
2713	} while (x < cx && (x & 7));
2714	pbDst[(x - 1) / 8] = bDst;
2715	}
2716	pbDst += cbDstAndLine;
2717	pbSrc += cbSrcAndLine;
2718	}
2719	break;
2720	case 15:
2721	for (uint32_t y = 0; y < cy; y++)
2722	{
2723	for (uint32_t x = 0; x < cx; )
2724	{
2725	uint8_t bDst = 0;
2726	uint8_t fBit = 1;
2727	do
2728	{
2729	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2730	bDst \|= fBit;
2731	fBit <<= 1;
2732	x++;
2733	} while (x < cx && (x & 7));
2734	pbDst[(x - 1) / 8] = bDst;
2735	}
2736	pbDst += cbDstAndLine;
2737	pbSrc += cbSrcAndLine;
2738	}
2739	break;
2740	case 16:
2741	for (uint32_t y = 0; y < cy; y++)
2742	{
2743	for (uint32_t x = 0; x < cx; )
2744	{
2745	uint8_t bDst = 0;
2746	uint8_t fBit = 1;
2747	do
2748	{
2749	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2750	bDst \|= fBit;
2751	fBit <<= 1;
2752	x++;
2753	} while (x < cx && (x & 7));
2754	pbDst[(x - 1) / 8] = bDst;
2755	}
2756	pbDst += cbDstAndLine;
2757	pbSrc += cbSrcAndLine;
2758	}
2759	break;
2760	case 24:
2761	for (uint32_t y = 0; y < cy; y++)
2762	{
2763	for (uint32_t x = 0; x < cx; )
2764	{
2765	uint8_t bDst = 0;
2766	uint8_t fBit = 1;
2767	do
2768	{
2769	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2770	bDst \|= fBit;
2771	fBit <<= 1;
2772	x++;
2773	} while (x < cx && (x & 7));
2774	pbDst[(x - 1) / 8] = bDst;
2775	}
2776	pbDst += cbDstAndLine;
2777	pbSrc += cbSrcAndLine;
2778	}
2779	break;
2780	case 32:
2781	for (uint32_t y = 0; y < cy; y++)
2782	{
2783	for (uint32_t x = 0; x < cx; )
2784	{
2785	uint8_t bDst = 0;
2786	uint8_t fBit = 1;
2787	do
2788	{
2789	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2790	bDst \|= fBit;
2791	fBit <<= 1;
2792	x++;
2793	} while (x < cx && (x & 7));
2794	pbDst[(x - 1) / 8] = bDst;
2795	}
2796	pbDst += cbDstAndLine;
2797	pbSrc += cbSrcAndLine;
2798	}
2799	break;
2800	default:
2801	RTMemFree(pbCopy);
2802	AssertFailedReturnVoid();
2803	}
2804
2805	/* Convert the XOR mask. */
2806	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2807	pbSrc = pbSrcXorMask;
2808	switch (pCursor->xorMaskDepth)
2809	{
2810	case 1:
2811	for (uint32_t y = 0; y < cy; y++)
2812	{
2813	for (uint32_t x = 0; x < cx; )
2814	{
2815	/* most significant bit is the left most one. */
2816	uint8_t bSrc = pbSrc[x / 8];
2817	do
2818	{
2819	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2820	bSrc <<= 1;
2821	x++;
2822	} while ((x & 7) && x < cx);
2823	}
2824	pbSrc += cbSrcXorLine;
2825	}
2826	break;
2827	case 8:
2828	for (uint32_t y = 0; y < cy; y++)
2829	{
2830	for (uint32_t x = 0; x < cx; x++)
2831	{
2832	uint32_t u = pThis->last_palette[pbSrc[x]];
2833	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2834	}
2835	pbSrc += cbSrcXorLine;
2836	}
2837	break;
2838	case 15: /* Src: RGB-5-5-5 */
2839	for (uint32_t y = 0; y < cy; y++)
2840	{
2841	for (uint32_t x = 0; x < cx; x++)
2842	{
2843	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2844	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2845	((uValue >> 5) & 0x1f) << 3,
2846	((uValue >> 10) & 0x1f) << 3, 0);
2847	}
2848	pbSrc += cbSrcXorLine;
2849	}
2850	break;
2851	case 16: /* Src: RGB-5-6-5 */
2852	for (uint32_t y = 0; y < cy; y++)
2853	{
2854	for (uint32_t x = 0; x < cx; x++)
2855	{
2856	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2857	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2858	((uValue >> 5) & 0x3f) << 2,
2859	((uValue >> 11) & 0x1f) << 3, 0);
2860	}
2861	pbSrc += cbSrcXorLine;
2862	}
2863	break;
2864	case 24:
2865	for (uint32_t y = 0; y < cy; y++)
2866	{
2867	for (uint32_t x = 0; x < cx; x++)
2868	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2869	pbSrc += cbSrcXorLine;
2870	}
2871	break;
2872	case 32:
2873	for (uint32_t y = 0; y < cy; y++)
2874	{
2875	for (uint32_t x = 0; x < cx; x++)
2876	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2877	pbSrc += cbSrcXorLine;
2878	}
2879	break;
2880	default:
2881	RTMemFree(pbCopy);
2882	AssertFailedReturnVoid();
2883	}
2884
2885	/*
2886	* Pass it to the frontend/whatever.
2887	*/
2888	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2889	}
2890
2891
2892	/**
2893	* Worker for vmsvgaR3FifoThread that handles an external command.
2894	*
2895	* @param pThis VGA device instance data.
2896	*/
2897	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2898	{
2899	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2900	switch (pThis->svga.u8FIFOExtCommand)
2901	{
2902	case VMSVGA_FIFO_EXTCMD_RESET:
2903	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2904	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2905	# ifdef VBOX_WITH_VMSVGA3D
2906	if (pThis->svga.f3DEnabled)
2907	{
2908	/* The 3d subsystem must be reset from the fifo thread. */
2909	vmsvga3dReset(pThis);
2910	}
2911	# endif
2912	break;
2913
2914	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2915	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2916	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2917	# ifdef VBOX_WITH_VMSVGA3D
2918	if (pThis->svga.f3DEnabled)
2919	{
2920	/* The 3d subsystem must be shut down from the fifo thread. */
2921	vmsvga3dTerminate(pThis);
2922	}
2923	# endif
2924	break;
2925
2926	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2927	{
2928	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2929	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2930	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2931	vmsvgaSaveExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pSSM);
2932	# ifdef VBOX_WITH_VMSVGA3D
2933	if (pThis->svga.f3DEnabled)
2934	vmsvga3dSaveExec(pThis->pDevInsR3, pThis, pSSM);
2935	# endif
2936	break;
2937	}
2938
2939	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2940	{
2941	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2942	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2943	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2944	vmsvgaLoadExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2945	# ifdef VBOX_WITH_VMSVGA3D
2946	if (pThis->svga.f3DEnabled)
2947	vmsvga3dLoadExec(pThis->pDevInsR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2948	# endif
2949	break;
2950	}
2951
2952	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2953	{
2954	# ifdef VBOX_WITH_VMSVGA3D
2955	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2956	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2957	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2958	# endif
2959	break;
2960	}
2961
2962
2963	default:
2964	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2965	break;
2966	}
2967
2968	/*
2969	* Signal the end of the external command.
2970	*/
2971	pThis->svga.pvFIFOExtCmdParam = NULL;
2972	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2973	ASMMemoryFence(); /* paranoia^2 */
2974	int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2975	AssertLogRelRC(rc);
2976	}
2977
2978	/**
2979	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2980	* doing a job on the FIFO thread (even when it's officially suspended).
2981	*
2982	* @returns VBox status code (fully asserted).
2983	* @param pDevIns The device instance.
2984	* @param pThis VGA device instance data.
2985	* @param uExtCmd The command to execute on the FIFO thread.
2986	* @param pvParam Pointer to command parameters.
2987	* @param cMsWait The time to wait for the command, given in
2988	* milliseconds.
2989	*/
2990	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2991	{
2992	Assert(cMsWait >= RT_MS_1SEC * 5);
2993	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2994	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2995
2996	int rc;
2997	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2998	PDMTHREADSTATE enmState = pThread->enmState;
2999	if (enmState == PDMTHREADSTATE_SUSPENDED)
3000	{
3001	/*
3002	* The thread is suspended, we have to temporarily wake it up so it can
3003	* perform the task.
3004	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3005	*/
3006	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3007	/* Post the request. */
3008	pThis->svga.fFifoExtCommandWakeup = true;
3009	pThis->svga.pvFIFOExtCmdParam = pvParam;
3010	pThis->svga.u8FIFOExtCommand = uExtCmd;
3011	ASMMemoryFence(); /* paranoia^3 */
3012
3013	/* Resume the thread. */
3014	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3015	AssertLogRelRC(rc);
3016	if (RT_SUCCESS(rc))
3017	{
3018	/* Wait. Take care in case the semaphore was already posted (same as below). */
3019	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3020	if ( rc == VINF_SUCCESS
3021	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3022	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3023	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3024	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3025
3026	/* suspend the thread */
3027	pThis->svga.fFifoExtCommandWakeup = false;
3028	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3029	AssertLogRelRC(rc2);
3030	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3031	rc = rc2;
3032	}
3033	pThis->svga.fFifoExtCommandWakeup = false;
3034	pThis->svga.pvFIFOExtCmdParam = NULL;
3035	}
3036	else if (enmState == PDMTHREADSTATE_RUNNING)
3037	{
3038	/*
3039	* The thread is running, should only happen during reset and vmsvga3dsfc.
3040	* We ASSUME not racing code here, both wrt thread state and ext commands.
3041	*/
3042	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3043	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3044
3045	/* Post the request. */
3046	pThis->svga.pvFIFOExtCmdParam = pvParam;
3047	pThis->svga.u8FIFOExtCommand = uExtCmd;
3048	ASMMemoryFence(); /* paranoia^2 */
3049	rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3050	AssertLogRelRC(rc);
3051
3052	/* Wait. Take care in case the semaphore was already posted (same as above). */
3053	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
3054	if ( rc == VINF_SUCCESS
3055	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3056	rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3057	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3058	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3059
3060	pThis->svga.pvFIFOExtCmdParam = NULL;
3061	}
3062	else
3063	{
3064	/*
3065	* Something is wrong with the thread!
3066	*/
3067	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3068	rc = VERR_INVALID_STATE;
3069	}
3070	return rc;
3071	}
3072
3073
3074	/**
3075	* Marks the FIFO non-busy, notifying any waiting EMTs.
3076	*
3077	* @param pThis The VGA state.
3078	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3079	* @param offFifoMin The start byte offset of the command FIFO.
3080	*/
3081	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3082	{
3083	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3084	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3085	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3086
3087	/* Wake up any waiting EMTs. */
3088	if (pSVGAState->cBusyDelayedEmts > 0)
3089	{
3090	#ifdef VMSVGA_USE_EMT_HALT_CODE
3091	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3092	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3093	if (idCpu != NIL_VMCPUID)
3094	{
3095	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3096	while (idCpu-- > 0)
3097	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3098	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3099	}
3100	#else
3101	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3102	AssertRC(rc2);
3103	#endif
3104	}
3105	}
3106
3107	/**
3108	* Reads (more) payload into the command buffer.
3109	*
3110	* @returns pbBounceBuf on success
3111	* @retval (void *)1 if the thread was requested to stop.
3112	* @retval NULL on FIFO error.
3113	*
3114	* @param cbPayloadReq The number of bytes of payload requested.
3115	* @param pFIFO The FIFO.
3116	* @param offCurrentCmd The FIFO byte offset of the current command.
3117	* @param offFifoMin The start byte offset of the command FIFO.
3118	* @param offFifoMax The end byte offset of the command FIFO.
3119	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3120	* always sufficient size.
3121	* @param pcbAlreadyRead How much payload we've already read into the bounce
3122	* buffer. (We will NEVER re-read anything.)
3123	* @param pThread The calling PDM thread handle.
3124	* @param pThis The VGA state.
3125	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3126	* statistics collection.
3127	*/
3128	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3129	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3130	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3131	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
3132	{
3133	Assert(pbBounceBuf);
3134	Assert(pcbAlreadyRead);
3135	Assert(offFifoMin < offFifoMax);
3136	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3137	Assert(offFifoMax <= pThis->svga.cbFIFO);
3138
3139	/*
3140	* Check if the requested payload size has already been satisfied .
3141	* .
3142	* When called to read more, the caller is responsible for making sure the .
3143	* new command size (cbRequsted) never is smaller than what has already .
3144	* been read.
3145	*/
3146	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3147	if (cbPayloadReq <= cbAlreadyRead)
3148	{
3149	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3150	return pbBounceBuf;
3151	}
3152
3153	/*
3154	* Commands bigger than the fifo buffer are invalid.
3155	*/
3156	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3157	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3158	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3159	NULL);
3160
3161	/*
3162	* Move offCurrentCmd past the command dword.
3163	*/
3164	offCurrentCmd += sizeof(uint32_t);
3165	if (offCurrentCmd >= offFifoMax)
3166	offCurrentCmd = offFifoMin;
3167
3168	/*
3169	* Do we have sufficient payload data available already?
3170	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3171	*/
3172	uint32_t cbAfter, cbBefore;
3173	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3174	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3175	if (offNextCmd >= offCurrentCmd)
3176	{
3177	if (RT_LIKELY(offNextCmd < offFifoMax))
3178	cbAfter = offNextCmd - offCurrentCmd;
3179	else
3180	{
3181	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3182	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3183	offNextCmd, offFifoMin, offFifoMax));
3184	cbAfter = offFifoMax - offCurrentCmd;
3185	}
3186	cbBefore = 0;
3187	}
3188	else
3189	{
3190	cbAfter = offFifoMax - offCurrentCmd;
3191	if (offNextCmd >= offFifoMin)
3192	cbBefore = offNextCmd - offFifoMin;
3193	else
3194	{
3195	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3196	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3197	offNextCmd, offFifoMin, offFifoMax));
3198	cbBefore = 0;
3199	}
3200	}
3201	if (cbAfter + cbBefore < cbPayloadReq)
3202	{
3203	/*
3204	* Insufficient, must wait for it to arrive.
3205	*/
3206	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3207	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3208	for (uint32_t i = 0;; i++)
3209	{
3210	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3211	{
3212	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3213	return (void *)(uintptr_t)1;
3214	}
3215	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3216	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3217
3218	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
3219
3220	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3221	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3222	if (offNextCmd >= offCurrentCmd)
3223	{
3224	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3225	cbBefore = 0;
3226	}
3227	else
3228	{
3229	cbAfter = offFifoMax - offCurrentCmd;
3230	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3231	}
3232
3233	if (cbAfter + cbBefore >= cbPayloadReq)
3234	break;
3235	}
3236	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3237	}
3238
3239	/*
3240	* Copy out the memory and update what pcbAlreadyRead points to.
3241	*/
3242	if (cbAfter >= cbPayloadReq)
3243	memcpy(pbBounceBuf + cbAlreadyRead,
3244	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3245	cbPayloadReq - cbAlreadyRead);
3246	else
3247	{
3248	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3249	if (cbAlreadyRead < cbAfter)
3250	{
3251	memcpy(pbBounceBuf + cbAlreadyRead,
3252	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3253	cbAfter - cbAlreadyRead);
3254	cbAlreadyRead = cbAfter;
3255	}
3256	memcpy(pbBounceBuf + cbAlreadyRead,
3257	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3258	cbPayloadReq - cbAlreadyRead);
3259	}
3260	*pcbAlreadyRead = cbPayloadReq;
3261	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3262	return pbBounceBuf;
3263	}
3264
3265
3266	/**
3267	* Sends cursor position and visibility information from the FIFO to the front-end.
3268	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3269	*/
3270	static uint32_t
3271	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3272	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3273	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3274	{
3275	/*
3276	* Check if the cursor update counter has changed and try get a stable
3277	* set of values if it has. This is race-prone, especially consindering
3278	* the screen ID, but little we can do about that.
3279	*/
3280	uint32_t x, y, fVisible, idScreen;
3281	for (uint32_t i = 0; ; i++)
3282	{
3283	x = pFIFO[SVGA_FIFO_CURSOR_X];
3284	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3285	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3286	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3287	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3288	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3289	\|\| i > 3)
3290	break;
3291	if (i == 0)
3292	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3293	ASMNopPause();
3294	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3295	}
3296
3297	/*
3298	* Check if anything has changed, as calling into pDrv is not light-weight.
3299	*/
3300	if ( *pxLast == x
3301	&& *pyLast == y
3302	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3303	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3304	else
3305	{
3306	/*
3307	* Detected changes.
3308	*
3309	* We handle global, not per-screen visibility information by sending
3310	* pfnVBVAMousePointerShape without shape data.
3311	*/
3312	*pxLast = x;
3313	*pyLast = y;
3314	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3315	if (idScreen != SVGA_ID_INVALID)
3316	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3317	else if (*pfLastVisible != fVisible)
3318	{
3319	LogRel2(("vmsvgaFIFOUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3320	*pfLastVisible = fVisible;
3321	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3322	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3323	}
3324	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3325	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3326	}
3327
3328	/*
3329	* Update done. Signal this to the guest.
3330	*/
3331	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3332
3333	return uCursorUpdateCount;
3334	}
3335
3336
3337	/**
3338	* Checks if there is work to be done, either cursor updating or FIFO commands.
3339	*
3340	* @returns true if pending work, false if not.
3341	* @param pFIFO The FIFO to examine.
3342	* @param uLastCursorCount The last cursor update counter value.
3343	*/
3344	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3345	{
3346	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3347	return true;
3348
3349	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3350	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3351	return true;
3352
3353	return false;
3354	}
3355
3356
3357	/**
3358	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3359	*
3360	* @param pThis The VGA state.
3361	*/
3362	void vmsvgaFIFOWatchdogTimer(PVGASTATE pThis)
3363	{
3364	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3365	to recheck it before doing the signalling. */
3366	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3367	AssertReturnVoid(pFIFO);
3368	if ( vmsvgaFIFOHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3369	&& pThis->svga.fFIFOThreadSleeping)
3370	{
3371	int rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3372	AssertRC(rc);
3373	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3374	}
3375	}
3376
3377
3378	/* The async FIFO handling thread. */
3379	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3380	{
3381	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3382	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3383	int rc;
3384
3385	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3386	return VINF_SUCCESS;
3387
3388	/*
3389	* Special mode where we only execute an external command and the go back
3390	* to being suspended. Currently, all ext cmds ends up here, with the reset
3391	* one also being eligble for runtime execution further down as well.
3392	*/
3393	if (pThis->svga.fFifoExtCommandWakeup)
3394	{
3395	vmsvgaR3FifoHandleExtCmd(pThis);
3396	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3397	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3398	SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
3399	else
3400	vmsvgaR3FifoHandleExtCmd(pThis);
3401	return VINF_SUCCESS;
3402	}
3403
3404
3405	/*
3406	* Signal the semaphore to make sure we don't wait for 250ms after a
3407	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3408	*/
3409	SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3410
3411	/*
3412	* Allocate a bounce buffer for command we get from the FIFO.
3413	* (All code must return via the end of the function to free this buffer.)
3414	*/
3415	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3416	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3417
3418	/*
3419	* Polling/sleep interval config.
3420	*
3421	* We wait for an a short interval if the guest has recently given us work
3422	* to do, but the interval increases the longer we're kept idle. Once we've
3423	* reached the refresh timer interval, we'll switch to extended waits,
3424	* depending on it or the guest to kick us into action when needed.
3425	*
3426	* Should the refresh time go fishing, we'll just continue increasing the
3427	* sleep length till we reaches the 250 ms max after about 16 seconds.
3428	*/
3429	RTMSINTERVAL const cMsMinSleep = 16;
3430	RTMSINTERVAL const cMsIncSleep = 2;
3431	RTMSINTERVAL const cMsMaxSleep = 250;
3432	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3433	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3434
3435	/*
3436	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3437	*
3438	* Initialize with values that will detect an update from the guest.
3439	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3440	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3441	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3442	*/
3443	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3444	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3445	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3446	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3447	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3448
3449	/*
3450	* The FIFO loop.
3451	*/
3452	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3453	bool fBadOrDisabledFifo = false;
3454	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3455	{
3456	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3457	/*
3458	* Should service the run loop every so often.
3459	*/
3460	if (pThis->svga.f3DEnabled)
3461	vmsvga3dCocoaServiceRunLoop();
3462	# endif
3463
3464	/*
3465	* Unless there's already work pending, go to sleep for a short while.
3466	* (See polling/sleep interval config above.)
3467	*/
3468	if ( fBadOrDisabledFifo
3469	\|\| !vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3470	{
3471	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3472	Assert(pThis->cMilliesRefreshInterval > 0);
3473	if (cMsSleep < pThis->cMilliesRefreshInterval)
3474	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsSleep);
3475	else
3476	{
3477	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3478	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3479	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3480	# endif
3481	if ( !fBadOrDisabledFifo
3482	&& vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3483	rc = VINF_SUCCESS;
3484	else
3485	{
3486	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3487	rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, cMsExtendedSleep);
3488	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3489	}
3490	}
3491	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3492	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3493	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3494	{
3495	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3496	break;
3497	}
3498	}
3499	else
3500	rc = VINF_SUCCESS;
3501	fBadOrDisabledFifo = false;
3502	if (rc == VERR_TIMEOUT)
3503	{
3504	if (!vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3505	{
3506	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3507	continue;
3508	}
3509	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3510
3511	Log(("vmsvgaFIFOLoop: timeout\n"));
3512	}
3513	else if (vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3514	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3515	cMsSleep = cMsMinSleep;
3516
3517	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3518	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3519	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3520
3521	/*
3522	* Handle external commands (currently only reset).
3523	*/
3524	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3525	{
3526	vmsvgaR3FifoHandleExtCmd(pThis);
3527	continue;
3528	}
3529
3530	/*
3531	* The device must be enabled and configured.
3532	*/
3533	if ( !pThis->svga.fEnabled
3534	\|\| !pThis->svga.fConfigured)
3535	{
3536	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3537	fBadOrDisabledFifo = true;
3538	cMsSleep = cMsMaxSleep; /* cheat */
3539	continue;
3540	}
3541
3542	/*
3543	* Get and check the min/max values. We ASSUME that they will remain
3544	* unchanged while we process requests. A further ASSUMPTION is that
3545	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3546	* we don't read it back while in the loop.
3547	*/
3548	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3549	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3550	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3551	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3552	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3553	\|\| offFifoMax <= offFifoMin
3554	\|\| offFifoMax > pThis->svga.cbFIFO
3555	\|\| (offFifoMax & 3) != 0
3556	\|\| (offFifoMin & 3) != 0
3557	\|\| offCurrentCmd < offFifoMin
3558	\|\| offCurrentCmd > offFifoMax))
3559	{
3560	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3561	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3562	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3563	fBadOrDisabledFifo = true;
3564	continue;
3565	}
3566	RT_UNTRUSTED_VALIDATED_FENCE();
3567	if (RT_UNLIKELY(offCurrentCmd & 3))
3568	{
3569	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3570	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3571	offCurrentCmd &= ~UINT32_C(3);
3572	}
3573
3574	/*
3575	* Update the cursor position before we start on the FIFO commands.
3576	*/
3577	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3578	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3579	{
3580	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3581	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3582	{ /* halfways likely */ }
3583	else
3584	{
3585	uint32_t const uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3586	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3587	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3588	}
3589	}
3590
3591	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3592	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3593	*
3594	* Will break out of the switch on failure.
3595	* Will restart and quit the loop if the thread was requested to stop.
3596	*
3597	* @param a_PtrVar Request variable pointer.
3598	* @param a_Type Request typedef (not pointer) for casting.
3599	* @param a_cbPayloadReq How much payload to fetch.
3600	* @remarks Accesses a bunch of variables in the current scope!
3601	*/
3602	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3603	if (1) { \
3604	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3605	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
3606	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3607	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3608	} else do {} while (0)
3609	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3610	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3611	* buffer after figuring out the actual command size.
3612	*
3613	* Will break out of the switch on failure.
3614	*
3615	* @param a_PtrVar Request variable pointer.
3616	* @param a_Type Request typedef (not pointer) for casting.
3617	* @param a_cbPayloadReq How much payload to fetch.
3618	* @remarks Accesses a bunch of variables in the current scope!
3619	*/
3620	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3621	if (1) { \
3622	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3623	} else do {} while (0)
3624
3625	/*
3626	* Mark the FIFO as busy.
3627	*/
3628	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3629	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3630	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3631
3632	/*
3633	* Execute all queued FIFO commands.
3634	* Quit if pending external command or changes in the thread state.
3635	*/
3636	bool fDone = false;
3637	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3638	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3639	{
3640	uint32_t cbPayload = 0;
3641	uint32_t u32IrqStatus = 0;
3642
3643	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3644
3645	/* First check any pending actions. */
3646	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3647	{
3648	vmsvgaChangeMode(pThis);
3649	# ifdef VBOX_WITH_VMSVGA3D
3650	if (pThis->svga.p3dState != NULL)
3651	vmsvga3dChangeMode(pThis);
3652	# endif
3653	}
3654
3655	/* Check for pending external commands (reset). */
3656	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3657	break;
3658
3659	/*
3660	* Process the command.
3661	*/
3662	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3663	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3664	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3665	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3666	switch (enmCmdId)
3667	{
3668	case SVGA_CMD_INVALID_CMD:
3669	/* Nothing to do. */
3670	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3671	break;
3672
3673	case SVGA_CMD_FENCE:
3674	{
3675	SVGAFifoCmdFence *pCmdFence;
3676	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3677	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3678	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3679	{
3680	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3681	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3682
3683	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3684	{
3685	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3686	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3687	}
3688	else
3689	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3690	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3691	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3692	{
3693	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3694	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3695	}
3696	}
3697	else
3698	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3699	break;
3700	}
3701	case SVGA_CMD_UPDATE:
3702	case SVGA_CMD_UPDATE_VERBOSE:
3703	{
3704	SVGAFifoCmdUpdate *pUpdate;
3705	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3706	if (enmCmdId == SVGA_CMD_UPDATE)
3707	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3708	else
3709	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3710	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3711	/** @todo Multiple screens? */
3712	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3713	AssertBreak(pScreen);
3714	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3715	break;
3716	}
3717
3718	case SVGA_CMD_DEFINE_CURSOR:
3719	{
3720	/* Followed by bitmap data. */
3721	SVGAFifoCmdDefineCursor *pCursor;
3722	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3723	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3724
3725	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3726	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3727	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3728	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3729	AssertBreak(pCursor->andMaskDepth <= 32);
3730	AssertBreak(pCursor->xorMaskDepth <= 32);
3731	RT_UNTRUSTED_VALIDATED_FENCE();
3732
3733	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3734	uint32_t cbAndMask = cbAndLine * pCursor->height;
3735	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3736	uint32_t cbXorMask = cbXorLine * pCursor->height;
3737	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3738
3739	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3740	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3741	break;
3742	}
3743
3744	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3745	{
3746	/* Followed by bitmap data. */
3747	uint32_t cbCursorShape, cbAndMask;
3748	uint8_t *pCursorCopy;
3749	uint32_t cbCmd;
3750
3751	SVGAFifoCmdDefineAlphaCursor *pCursor;
3752	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3753	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3754
3755	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3756
3757	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3758	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3759	RT_UNTRUSTED_VALIDATED_FENCE();
3760
3761	/* Refetch the bitmap data as well. */
3762	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3763	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3764	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3765
3766	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3767	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3768	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3769	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3770
3771	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3772	AssertBreak(pCursorCopy);
3773
3774	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3775	memset(pCursorCopy, 0xff, cbAndMask);
3776	/* Colour data */
3777	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3778
3779	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3780	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3781	break;
3782	}
3783
3784	case SVGA_CMD_ESCAPE:
3785	{
3786	/* Followed by nsize bytes of data. */
3787	SVGAFifoCmdEscape *pEscape;
3788	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3789	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3790
3791	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3792	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3793	RT_UNTRUSTED_VALIDATED_FENCE();
3794	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3795	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3796
3797	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3798	{
3799	AssertBreak(pEscape->size >= sizeof(uint32_t));
3800	RT_UNTRUSTED_VALIDATED_FENCE();
3801	uint32_t cmd = (uint32_t )(pEscape + 1);
3802	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3803
3804	switch (cmd)
3805	{
3806	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3807	{
3808	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3809	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3810	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3811
3812	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3813	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3814	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3815
3816	RT_NOREF_PV(pVideoCmd);
3817	break;
3818
3819	}
3820
3821	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3822	{
3823	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3824	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3825	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3826	RT_NOREF_PV(pVideoCmd);
3827	break;
3828	}
3829
3830	default:
3831	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3832	break;
3833	}
3834	}
3835	else
3836	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3837
3838	break;
3839	}
3840	# ifdef VBOX_WITH_VMSVGA3D
3841	case SVGA_CMD_DEFINE_GMR2:
3842	{
3843	SVGAFifoCmdDefineGMR2 *pCmd;
3844	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3845	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3846	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3847
3848	/* Validate current GMR id. */
3849	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3850	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3851	RT_UNTRUSTED_VALIDATED_FENCE();
3852
3853	if (!pCmd->numPages)
3854	{
3855	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3856	vmsvgaGMRFree(pThis, pCmd->gmrId);
3857	}
3858	else
3859	{
3860	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3861	if (pGMR->cMaxPages)
3862	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3863
3864	/* Not sure if we should always free the descriptor, but for simplicity
3865	we do so if the new size is smaller than the current. */
3866	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3867	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3868	vmsvgaGMRFree(pThis, pCmd->gmrId);
3869
3870	pGMR->cMaxPages = pCmd->numPages;
3871	/* The rest is done by the REMAP_GMR2 command. */
3872	}
3873	break;
3874	}
3875
3876	case SVGA_CMD_REMAP_GMR2:
3877	{
3878	/* Followed by page descriptors or guest ptr. */
3879	SVGAFifoCmdRemapGMR2 *pCmd;
3880	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3881	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3882
3883	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3884	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3885	RT_UNTRUSTED_VALIDATED_FENCE();
3886
3887	/* Calculate the size of what comes after next and fetch it. */
3888	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3889	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3890	cbCmd += sizeof(SVGAGuestPtr);
3891	else
3892	{
3893	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3894	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3895	{
3896	cbCmd += cbPageDesc;
3897	pCmd->numPages = 1;
3898	}
3899	else
3900	{
3901	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3902	cbCmd += cbPageDesc * pCmd->numPages;
3903	}
3904	}
3905	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3906
3907	/* Validate current GMR id and size. */
3908	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3909	RT_UNTRUSTED_VALIDATED_FENCE();
3910	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3911	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3912	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3913	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3914
3915	if (pCmd->numPages == 0)
3916	break;
3917
3918	/** @todo Move to a separate function vmsvgaGMRRemap() */
3919
3920	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3921	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3922
3923	/*
3924	* We flatten the existing descriptors into a page array, overwrite the
3925	* pages specified in this command and then recompress the descriptor.
3926	*/
3927	/** @todo Optimize the GMR remap algorithm! */
3928
3929	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3930	uint64_t *paNewPage64 = NULL;
3931	if (pGMR->paDesc)
3932	{
3933	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3934
3935	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3936	AssertBreak(paNewPage64);
3937
3938	uint32_t idxPage = 0;
3939	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3940	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3941	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3942	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3943	RT_UNTRUSTED_VALIDATED_FENCE();
3944	}
3945
3946	/* Free the old GMR if present. */
3947	if (pGMR->paDesc)
3948	RTMemFree(pGMR->paDesc);
3949
3950	/* Allocate the maximum amount possible (everything non-continuous) */
3951	PVMSVGAGMRDESCRIPTOR paDescs;
3952	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3953	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3954
3955	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3956	{
3957	/** @todo */
3958	AssertFailed();
3959	pGMR->numDescriptors = 0;
3960	}
3961	else
3962	{
3963	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3964	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3965	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3966
3967	if (paNewPage64)
3968	{
3969	/* Overwrite the old page array with the new page values. */
3970	if (fGCPhys64)
3971	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3972	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3973	else
3974	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3975	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3976
3977	/* Use the updated page array instead of the command data. */
3978	fGCPhys64 = true;
3979	paPages64 = paNewPage64;
3980	pCmd->numPages = cNewTotalPages;
3981	}
3982
3983	/* The first page. */
3984	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3985	* applied to paNewPage64. */
3986	RTGCPHYS GCPhys;
3987	if (fGCPhys64)
3988	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3989	else
3990	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3991	paDescs[0].GCPhys = GCPhys;
3992	paDescs[0].numPages = 1;
3993
3994	/* Subsequent pages. */
3995	uint32_t iDescriptor = 0;
3996	for (uint32_t i = 1; i < pCmd->numPages; i++)
3997	{
3998	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3999	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4000	else
4001	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4002
4003	/* Continuous physical memory? */
4004	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4005	{
4006	Assert(paDescs[iDescriptor].numPages);
4007	paDescs[iDescriptor].numPages++;
4008	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4009	}
4010	else
4011	{
4012	iDescriptor++;
4013	paDescs[iDescriptor].GCPhys = GCPhys;
4014	paDescs[iDescriptor].numPages = 1;
4015	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4016	}
4017	}
4018
4019	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4020	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4021	pGMR->numDescriptors = iDescriptor + 1;
4022	}
4023
4024	if (paNewPage64)
4025	RTMemFree(paNewPage64);
4026
4027	# ifdef DEBUG_GMR_ACCESS
4028	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
4029	# endif
4030	break;
4031	}
4032	# endif // VBOX_WITH_VMSVGA3D
4033	case SVGA_CMD_DEFINE_SCREEN:
4034	{
4035	/* The size of this command is specified by the guest and depends on capabilities. */
4036	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4037
4038	SVGAFifoCmdDefineScreen *pCmd;
4039	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4040	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4041	RT_UNTRUSTED_VALIDATED_FENCE();
4042
4043	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4044	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4045	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4046
4047	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4048	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4049	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4050
4051	uint32_t const idScreen = pCmd->screen.id;
4052	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4053
4054	uint32_t const uWidth = pCmd->screen.size.width;
4055	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4056
4057	uint32_t const uHeight = pCmd->screen.size.height;
4058	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4059
4060	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4061	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4062	AssertBreak(cbWidth <= cbPitch);
4063
4064	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4065	AssertBreak(uScreenOffset < pThis->vram_size);
4066
4067	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4068	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4069	AssertBreak( (uHeight == 0 && cbPitch == 0)
4070	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4071	RT_UNTRUSTED_VALIDATED_FENCE();
4072
4073	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4074
4075	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4076
4077	pScreen->fDefined = true;
4078	pScreen->fModified = true;
4079	pScreen->fuScreen = pCmd->screen.flags;
4080	pScreen->idScreen = idScreen;
4081	if (!fBlank)
4082	{
4083	AssertBreak(uWidth > 0 && uHeight > 0);
4084
4085	pScreen->xOrigin = pCmd->screen.root.x;
4086	pScreen->yOrigin = pCmd->screen.root.y;
4087	pScreen->cWidth = uWidth;
4088	pScreen->cHeight = uHeight;
4089	pScreen->offVRAM = uScreenOffset;
4090	pScreen->cbPitch = cbPitch;
4091	pScreen->cBpp = 32;
4092	}
4093	else
4094	{
4095	/* Keep old values. */
4096	}
4097
4098	pThis->svga.fGFBRegisters = false;
4099	vmsvgaChangeMode(pThis);
4100	break;
4101	}
4102
4103	case SVGA_CMD_DESTROY_SCREEN:
4104	{
4105	SVGAFifoCmdDestroyScreen *pCmd;
4106	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4107	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4108
4109	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4110
4111	uint32_t const idScreen = pCmd->screenId;
4112	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4113	RT_UNTRUSTED_VALIDATED_FENCE();
4114
4115	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4116	pScreen->fModified = true;
4117	pScreen->fDefined = false;
4118	pScreen->idScreen = idScreen;
4119
4120	vmsvgaChangeMode(pThis);
4121	break;
4122	}
4123
4124	case SVGA_CMD_DEFINE_GMRFB:
4125	{
4126	SVGAFifoCmdDefineGMRFB *pCmd;
4127	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4128	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4129
4130	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4131	pSVGAState->GMRFB.ptr = pCmd->ptr;
4132	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4133	pSVGAState->GMRFB.format = pCmd->format;
4134	break;
4135	}
4136
4137	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4138	{
4139	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4140	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4141	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4142
4143	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4144	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4145
4146	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4147	RT_UNTRUSTED_VALIDATED_FENCE();
4148
4149	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4150	AssertBreak(pScreen);
4151
4152	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4153	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4154
4155	/* Clip destRect to the screen dimensions. */
4156	SVGASignedRect screenRect;
4157	screenRect.left = 0;
4158	screenRect.top = 0;
4159	screenRect.right = pScreen->cWidth;
4160	screenRect.bottom = pScreen->cHeight;
4161	SVGASignedRect clipRect = pCmd->destRect;
4162	vmsvgaClipRect(&screenRect, &clipRect);
4163	RT_UNTRUSTED_VALIDATED_FENCE();
4164
4165	uint32_t const width = clipRect.right - clipRect.left;
4166	uint32_t const height = clipRect.bottom - clipRect.top;
4167
4168	if ( width == 0
4169	\|\| height == 0)
4170	break; /* Nothing to do. */
4171
4172	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4173	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4174
4175	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4176	* Prepare parameters for vmsvgaGMRTransfer.
4177	*/
4178	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4179
4180	/* Destination: host buffer which describes the screen 0 VRAM.
4181	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4182	*/
4183	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4184	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4185	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4186	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4187	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4188	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4189	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4190	+ cbScanline * clipRect.top;
4191	int32_t const cbHstPitch = cbScanline;
4192
4193	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4194	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4195	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4196	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4197	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4198
4199	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4200	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4201	gstPtr, offGst, cbGstPitch,
4202	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4203	AssertRC(rc);
4204	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4205	break;
4206	}
4207
4208	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4209	{
4210	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4211	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4212	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4213
4214	/* Note! This can fetch 3d render results as well!! */
4215	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4216	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4217
4218	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4219	RT_UNTRUSTED_VALIDATED_FENCE();
4220
4221	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4222	AssertBreak(pScreen);
4223
4224	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4225	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4226
4227	/* Clip destRect to the screen dimensions. */
4228	SVGASignedRect screenRect;
4229	screenRect.left = 0;
4230	screenRect.top = 0;
4231	screenRect.right = pScreen->cWidth;
4232	screenRect.bottom = pScreen->cHeight;
4233	SVGASignedRect clipRect = pCmd->srcRect;
4234	vmsvgaClipRect(&screenRect, &clipRect);
4235	RT_UNTRUSTED_VALIDATED_FENCE();
4236
4237	uint32_t const width = clipRect.right - clipRect.left;
4238	uint32_t const height = clipRect.bottom - clipRect.top;
4239
4240	if ( width == 0
4241	\|\| height == 0)
4242	break; /* Nothing to do. */
4243
4244	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4245	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4246
4247	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4248	* Prepare parameters for vmsvgaGMRTransfer.
4249	*/
4250	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4251
4252	/* Source: host buffer which describes the screen 0 VRAM.
4253	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4254	*/
4255	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4256	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4257	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4258	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4259	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4260	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4261	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4262	+ cbScanline * clipRect.top;
4263	int32_t const cbHstPitch = cbScanline;
4264
4265	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4266	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4267	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4268	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4269	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4270
4271	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4272	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4273	gstPtr, offGst, cbGstPitch,
4274	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4275	AssertRC(rc);
4276	break;
4277	}
4278
4279	case SVGA_CMD_ANNOTATION_FILL:
4280	{
4281	SVGAFifoCmdAnnotationFill *pCmd;
4282	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4283	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4284
4285	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4286	pSVGAState->colorAnnotation = pCmd->color;
4287	break;
4288	}
4289
4290	case SVGA_CMD_ANNOTATION_COPY:
4291	{
4292	SVGAFifoCmdAnnotationCopy *pCmd;
4293	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4294	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4295
4296	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4297	AssertFailed();
4298	break;
4299	}
4300
4301	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4302
4303	default:
4304	# ifdef VBOX_WITH_VMSVGA3D
4305	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4306	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4307	{
4308	RT_UNTRUSTED_VALIDATED_FENCE();
4309
4310	/* All 3d commands start with a common header, which defines the size of the command. */
4311	SVGA3dCmdHeader *pHdr;
4312	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4313	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4314	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4315	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4316
4317	if (RT_LIKELY(pThis->svga.f3DEnabled))
4318	{ /* likely */ }
4319	else
4320	{
4321	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4322	break;
4323	}
4324
4325	/**
4326	* Check that the 3D command has at least a_cbMin of payload bytes after the
4327	* header. Will break out of the switch if it doesn't.
4328	*/
4329	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4330	if (1) { \
4331	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4332	RT_UNTRUSTED_VALIDATED_FENCE(); \
4333	} else do {} while (0)
4334	switch ((int)enmCmdId)
4335	{
4336	case SVGA_3D_CMD_SURFACE_DEFINE:
4337	{
4338	uint32_t cMipLevels;
4339	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4340	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4341	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4342
4343	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4344	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4345	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4346	# ifdef DEBUG_GMR_ACCESS
4347	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4348	# endif
4349	break;
4350	}
4351
4352	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4353	{
4354	uint32_t cMipLevels;
4355	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4356	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4357	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4358
4359	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4360	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4361	pCmd->multisampleCount, pCmd->autogenFilter,
4362	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4363	break;
4364	}
4365
4366	case SVGA_3D_CMD_SURFACE_DESTROY:
4367	{
4368	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4369	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4370	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4371	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4372	break;
4373	}
4374
4375	case SVGA_3D_CMD_SURFACE_COPY:
4376	{
4377	uint32_t cCopyBoxes;
4378	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4379	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4380	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4381
4382	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4383	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4384	break;
4385	}
4386
4387	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4388	{
4389	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4390	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4391	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4392
4393	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4394	break;
4395	}
4396
4397	case SVGA_3D_CMD_SURFACE_DMA:
4398	{
4399	uint32_t cCopyBoxes;
4400	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4401	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4402	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4403
4404	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4405	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4406	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4407	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4408	break;
4409	}
4410
4411	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4412	{
4413	uint32_t cRects;
4414	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4415	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4416	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4417
4418	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4419	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4420	break;
4421	}
4422
4423	case SVGA_3D_CMD_CONTEXT_DEFINE:
4424	{
4425	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4426	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4427	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4428
4429	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4430	break;
4431	}
4432
4433	case SVGA_3D_CMD_CONTEXT_DESTROY:
4434	{
4435	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4436	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4437	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4438
4439	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4440	break;
4441	}
4442
4443	case SVGA_3D_CMD_SETTRANSFORM:
4444	{
4445	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4446	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4447	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4448
4449	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4450	break;
4451	}
4452
4453	case SVGA_3D_CMD_SETZRANGE:
4454	{
4455	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4456	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4457	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4458
4459	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4460	break;
4461	}
4462
4463	case SVGA_3D_CMD_SETRENDERSTATE:
4464	{
4465	uint32_t cRenderStates;
4466	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4467	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4468	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4469
4470	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4471	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4472	break;
4473	}
4474
4475	case SVGA_3D_CMD_SETRENDERTARGET:
4476	{
4477	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4478	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4479	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4480
4481	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4482	break;
4483	}
4484
4485	case SVGA_3D_CMD_SETTEXTURESTATE:
4486	{
4487	uint32_t cTextureStates;
4488	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4489	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4490	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4491
4492	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4493	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4494	break;
4495	}
4496
4497	case SVGA_3D_CMD_SETMATERIAL:
4498	{
4499	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4500	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4501	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4502
4503	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4504	break;
4505	}
4506
4507	case SVGA_3D_CMD_SETLIGHTDATA:
4508	{
4509	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4510	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4511	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4512
4513	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4514	break;
4515	}
4516
4517	case SVGA_3D_CMD_SETLIGHTENABLED:
4518	{
4519	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4520	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4521	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4522
4523	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4524	break;
4525	}
4526
4527	case SVGA_3D_CMD_SETVIEWPORT:
4528	{
4529	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4530	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4531	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4532
4533	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4534	break;
4535	}
4536
4537	case SVGA_3D_CMD_SETCLIPPLANE:
4538	{
4539	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4540	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4541	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4542
4543	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4544	break;
4545	}
4546
4547	case SVGA_3D_CMD_CLEAR:
4548	{
4549	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4550	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4551	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4552
4553	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4554	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4555	break;
4556	}
4557
4558	case SVGA_3D_CMD_PRESENT:
4559	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4560	{
4561	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4562	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4563	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4564	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4565	else
4566	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4567
4568	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4569
4570	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4571	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4572	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4573	break;
4574	}
4575
4576	case SVGA_3D_CMD_SHADER_DEFINE:
4577	{
4578	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4579	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4580	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4581
4582	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4583	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4584	break;
4585	}
4586
4587	case SVGA_3D_CMD_SHADER_DESTROY:
4588	{
4589	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4590	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4591	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4592
4593	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4594	break;
4595	}
4596
4597	case SVGA_3D_CMD_SET_SHADER:
4598	{
4599	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4600	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4601	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4602
4603	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4604	break;
4605	}
4606
4607	case SVGA_3D_CMD_SET_SHADER_CONST:
4608	{
4609	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4610	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4611	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4612
4613	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4614	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4615	break;
4616	}
4617
4618	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4619	{
4620	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4621	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4622	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4623
4624	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4625	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4626	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4627	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4628	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4629
4630	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4631	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4632
4633	RT_UNTRUSTED_VALIDATED_FENCE();
4634
4635	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4636	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4637	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4638
4639	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4640	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4641	pNumRange, cVertexDivisor, pVertexDivisor);
4642	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4643	break;
4644	}
4645
4646	case SVGA_3D_CMD_SETSCISSORRECT:
4647	{
4648	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4649	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4650	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4651
4652	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4653	break;
4654	}
4655
4656	case SVGA_3D_CMD_BEGIN_QUERY:
4657	{
4658	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4659	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4660	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4661
4662	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4663	break;
4664	}
4665
4666	case SVGA_3D_CMD_END_QUERY:
4667	{
4668	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4669	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4670	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4671
4672	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4673	break;
4674	}
4675
4676	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4677	{
4678	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4679	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4680	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4681
4682	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4683	break;
4684	}
4685
4686	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4687	{
4688	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4689	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4690	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4691
4692	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4693	break;
4694	}
4695
4696	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4697	/* context id + surface id? */
4698	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4699	break;
4700	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4701	/* context id + surface id? */
4702	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4703	break;
4704
4705	default:
4706	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4707	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4708	break;
4709	}
4710	}
4711	else
4712	# endif // VBOX_WITH_VMSVGA3D
4713	{
4714	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4715	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4716	}
4717	}
4718
4719	/* Go to the next slot */
4720	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4721	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4722	if (offCurrentCmd >= offFifoMax)
4723	{
4724	offCurrentCmd -= offFifoMax - offFifoMin;
4725	Assert(offCurrentCmd >= offFifoMin);
4726	Assert(offCurrentCmd < offFifoMax);
4727	}
4728	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4729	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4730
4731	/*
4732	* Raise IRQ if required. Must enter the critical section here
4733	* before making final decisions here, otherwise cubebench and
4734	* others may end up waiting forever.
4735	*/
4736	if ( u32IrqStatus
4737	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4738	{
4739	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4740	AssertRC(rc2);
4741
4742	/* FIFO progress might trigger an interrupt. */
4743	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4744	{
4745	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4746	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4747	}
4748
4749	/* Unmasked IRQ pending? */
4750	if (pThis->svga.u32IrqMask & u32IrqStatus)
4751	{
4752	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4753	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4754	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4755	}
4756
4757	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4758	}
4759	}
4760
4761	/* If really done, clear the busy flag. */
4762	if (fDone)
4763	{
4764	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4765	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4766	}
4767	}
4768
4769	/*
4770	* Free the bounce buffer. (There are no returns above!)
4771	*/
4772	RTMemFree(pbBounceBuf);
4773
4774	return VINF_SUCCESS;
4775	}
4776
4777	/**
4778	* Free the specified GMR
4779	*
4780	* @param pThis VGA device instance data.
4781	* @param idGMR GMR id
4782	*/
4783	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4784	{
4785	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4786
4787	/* Free the old descriptor if present. */
4788	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4789	if ( pGMR->numDescriptors
4790	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4791	{
4792	# ifdef DEBUG_GMR_ACCESS
4793	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4794	# endif
4795
4796	Assert(pGMR->paDesc);
4797	RTMemFree(pGMR->paDesc);
4798	pGMR->paDesc = NULL;
4799	pGMR->numDescriptors = 0;
4800	pGMR->cbTotal = 0;
4801	pGMR->cMaxPages = 0;
4802	}
4803	Assert(!pGMR->cMaxPages);
4804	Assert(!pGMR->cbTotal);
4805	}
4806
4807	/**
4808	* Copy between a GMR and a host memory buffer.
4809	*
4810	* @returns VBox status code.
4811	* @param pThis VGA device instance data.
4812	* @param enmTransferType Transfer type (read/write)
4813	* @param pbHstBuf Host buffer pointer (valid)
4814	* @param cbHstBuf Size of host buffer (valid)
4815	* @param offHst Host buffer offset of the first scanline
4816	* @param cbHstPitch Destination buffer pitch
4817	* @param gstPtr GMR description
4818	* @param offGst Guest buffer offset of the first scanline
4819	* @param cbGstPitch Guest buffer pitch
4820	* @param cbWidth Width in bytes to copy
4821	* @param cHeight Number of scanllines to copy
4822	*/
4823	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4824	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4825	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4826	uint32_t cbWidth, uint32_t cHeight)
4827	{
4828	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4829	int rc;
4830
4831	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4832	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4833	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4834	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4835	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4836
4837	PGMR pGMR;
4838	uint32_t cbGmr; /* The GMR size in bytes. */
4839	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4840	{
4841	pGMR = NULL;
4842	cbGmr = pThis->vram_size;
4843	}
4844	else
4845	{
4846	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4847	RT_UNTRUSTED_VALIDATED_FENCE();
4848	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4849	cbGmr = pGMR->cbTotal;
4850	}
4851
4852	/*
4853	* GMR
4854	*/
4855	/* Calculate GMR offset of the data to be copied. */
4856	AssertMsgReturn(gstPtr.offset < cbGmr,
4857	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4858	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4859	VERR_INVALID_PARAMETER);
4860	RT_UNTRUSTED_VALIDATED_FENCE();
4861	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4862	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4863	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4864	VERR_INVALID_PARAMETER);
4865	RT_UNTRUSTED_VALIDATED_FENCE();
4866	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4867
4868	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4869	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4870	AssertMsgReturn(cbGmrScanline != 0,
4871	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4872	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4873	VERR_INVALID_PARAMETER);
4874	RT_UNTRUSTED_VALIDATED_FENCE();
4875	AssertMsgReturn(cbWidth <= cbGmrScanline,
4876	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4877	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4878	VERR_INVALID_PARAMETER);
4879	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4880	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4881	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4882	VERR_INVALID_PARAMETER);
4883	RT_UNTRUSTED_VALIDATED_FENCE();
4884
4885	/* How many bytes are available for the data in the GMR. */
4886	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4887
4888	/* How many scanlines would fit into the available data. */
4889	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4890	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4891	if (cbWidth <= cbGmrLastScanline)
4892	++cGmrScanlines;
4893
4894	if (cHeight > cGmrScanlines)
4895	cHeight = cGmrScanlines;
4896
4897	AssertMsgReturn(cHeight > 0,
4898	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4899	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4900	VERR_INVALID_PARAMETER);
4901	RT_UNTRUSTED_VALIDATED_FENCE();
4902
4903	/*
4904	* Host buffer.
4905	*/
4906	AssertMsgReturn(offHst < cbHstBuf,
4907	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4908	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4909	VERR_INVALID_PARAMETER);
4910
4911	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4912	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4913	AssertMsgReturn(cbHstScanline != 0,
4914	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4915	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4916	VERR_INVALID_PARAMETER);
4917	AssertMsgReturn(cbWidth <= cbHstScanline,
4918	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4919	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4920	VERR_INVALID_PARAMETER);
4921	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4922	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4923	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4924	VERR_INVALID_PARAMETER);
4925
4926	/* How many bytes are available for the data in the buffer. */
4927	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4928
4929	/* How many scanlines would fit into the available data. */
4930	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4931	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4932	if (cbWidth <= cbHstLastScanline)
4933	++cHstScanlines;
4934
4935	if (cHeight > cHstScanlines)
4936	cHeight = cHstScanlines;
4937
4938	AssertMsgReturn(cHeight > 0,
4939	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4940	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4941	VERR_INVALID_PARAMETER);
4942
4943	uint8_t *pbHst = pbHstBuf + offHst;
4944
4945	/* Shortcut for the framebuffer. */
4946	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4947	{
4948	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4949
4950	uint8_t const *pbSrc;
4951	int32_t cbSrcPitch;
4952	uint8_t *pbDst;
4953	int32_t cbDstPitch;
4954
4955	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4956	{
4957	pbSrc = pbHst;
4958	cbSrcPitch = cbHstPitch;
4959	pbDst = pbGst;
4960	cbDstPitch = cbGstPitch;
4961	}
4962	else
4963	{
4964	pbSrc = pbGst;
4965	cbSrcPitch = cbGstPitch;
4966	pbDst = pbHst;
4967	cbDstPitch = cbHstPitch;
4968	}
4969
4970	if ( cbWidth == (uint32_t)cbGstPitch
4971	&& cbGstPitch == cbHstPitch)
4972	{
4973	/* Entire scanlines, positive pitch. */
4974	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4975	}
4976	else
4977	{
4978	for (uint32_t i = 0; i < cHeight; ++i)
4979	{
4980	memcpy(pbDst, pbSrc, cbWidth);
4981
4982	pbDst += cbDstPitch;
4983	pbSrc += cbSrcPitch;
4984	}
4985	}
4986	return VINF_SUCCESS;
4987	}
4988
4989	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4990	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4991
4992	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4993	uint32_t iDesc = 0; /* Index in the descriptor array. */
4994	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4995	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4996	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4997	for (uint32_t i = 0; i < cHeight; ++i)
4998	{
4999	uint32_t cbCurrentWidth = cbWidth;
5000	uint32_t offGmrCurrent = offGmrScanline;
5001	uint8_t *pbCurrentHost = pbHstScanline;
5002
5003	/* Find the right descriptor */
5004	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5005	{
5006	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5007	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5008	++iDesc;
5009	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5010	}
5011
5012	while (cbCurrentWidth)
5013	{
5014	uint32_t cbToCopy;
5015
5016	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5017	{
5018	cbToCopy = cbCurrentWidth;
5019	}
5020	else
5021	{
5022	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5023	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5024	}
5025
5026	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5027
5028	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5029
5030	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5031	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5032	else
5033	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5034	AssertRCBreak(rc);
5035
5036	cbCurrentWidth -= cbToCopy;
5037	offGmrCurrent += cbToCopy;
5038	pbCurrentHost += cbToCopy;
5039
5040	/* Go to the next descriptor if there's anything left. */
5041	if (cbCurrentWidth)
5042	{
5043	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5044	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5045	++iDesc;
5046	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5047	}
5048	}
5049
5050	offGmrScanline += cbGstPitch;
5051	pbHstScanline += cbHstPitch;
5052	}
5053
5054	return VINF_SUCCESS;
5055	}
5056
5057
5058	/**
5059	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5060	*
5061	* @param pSizeSrc Source surface dimensions.
5062	* @param pSizeDest Destination surface dimensions.
5063	* @param pBox Coordinates to be clipped.
5064	*/
5065	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5066	const SVGA3dSize *pSizeDest,
5067	SVGA3dCopyBox *pBox)
5068	{
5069	/* Src x, w */
5070	if (pBox->srcx > pSizeSrc->width)
5071	pBox->srcx = pSizeSrc->width;
5072	if (pBox->w > pSizeSrc->width - pBox->srcx)
5073	pBox->w = pSizeSrc->width - pBox->srcx;
5074
5075	/* Src y, h */
5076	if (pBox->srcy > pSizeSrc->height)
5077	pBox->srcy = pSizeSrc->height;
5078	if (pBox->h > pSizeSrc->height - pBox->srcy)
5079	pBox->h = pSizeSrc->height - pBox->srcy;
5080
5081	/* Src z, d */
5082	if (pBox->srcz > pSizeSrc->depth)
5083	pBox->srcz = pSizeSrc->depth;
5084	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5085	pBox->d = pSizeSrc->depth - pBox->srcz;
5086
5087	/* Dest x, w */
5088	if (pBox->x > pSizeDest->width)
5089	pBox->x = pSizeDest->width;
5090	if (pBox->w > pSizeDest->width - pBox->x)
5091	pBox->w = pSizeDest->width - pBox->x;
5092
5093	/* Dest y, h */
5094	if (pBox->y > pSizeDest->height)
5095	pBox->y = pSizeDest->height;
5096	if (pBox->h > pSizeDest->height - pBox->y)
5097	pBox->h = pSizeDest->height - pBox->y;
5098
5099	/* Dest z, d */
5100	if (pBox->z > pSizeDest->depth)
5101	pBox->z = pSizeDest->depth;
5102	if (pBox->d > pSizeDest->depth - pBox->z)
5103	pBox->d = pSizeDest->depth - pBox->z;
5104	}
5105
5106	/**
5107	* Unsigned coordinates in pBox. Clip to [0; pSize).
5108	*
5109	* @param pSize Source surface dimensions.
5110	* @param pBox Coordinates to be clipped.
5111	*/
5112	void vmsvgaClipBox(const SVGA3dSize *pSize,
5113	SVGA3dBox *pBox)
5114	{
5115	/* x, w */
5116	if (pBox->x > pSize->width)
5117	pBox->x = pSize->width;
5118	if (pBox->w > pSize->width - pBox->x)
5119	pBox->w = pSize->width - pBox->x;
5120
5121	/* y, h */
5122	if (pBox->y > pSize->height)
5123	pBox->y = pSize->height;
5124	if (pBox->h > pSize->height - pBox->y)
5125	pBox->h = pSize->height - pBox->y;
5126
5127	/* z, d */
5128	if (pBox->z > pSize->depth)
5129	pBox->z = pSize->depth;
5130	if (pBox->d > pSize->depth - pBox->z)
5131	pBox->d = pSize->depth - pBox->z;
5132	}
5133
5134	/**
5135	* Clip.
5136	*
5137	* @param pBound Bounding rectangle.
5138	* @param pRect Rectangle to be clipped.
5139	*/
5140	void vmsvgaClipRect(SVGASignedRect const *pBound,
5141	SVGASignedRect *pRect)
5142	{
5143	int32_t left;
5144	int32_t top;
5145	int32_t right;
5146	int32_t bottom;
5147
5148	/* Right order. */
5149	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5150	if (pRect->left < pRect->right)
5151	{
5152	left = pRect->left;
5153	right = pRect->right;
5154	}
5155	else
5156	{
5157	left = pRect->right;
5158	right = pRect->left;
5159	}
5160	if (pRect->top < pRect->bottom)
5161	{
5162	top = pRect->top;
5163	bottom = pRect->bottom;
5164	}
5165	else
5166	{
5167	top = pRect->bottom;
5168	bottom = pRect->top;
5169	}
5170
5171	if (left < pBound->left)
5172	left = pBound->left;
5173	if (right < pBound->left)
5174	right = pBound->left;
5175
5176	if (left > pBound->right)
5177	left = pBound->right;
5178	if (right > pBound->right)
5179	right = pBound->right;
5180
5181	if (top < pBound->top)
5182	top = pBound->top;
5183	if (bottom < pBound->top)
5184	bottom = pBound->top;
5185
5186	if (top > pBound->bottom)
5187	top = pBound->bottom;
5188	if (bottom > pBound->bottom)
5189	bottom = pBound->bottom;
5190
5191	pRect->left = left;
5192	pRect->right = right;
5193	pRect->top = top;
5194	pRect->bottom = bottom;
5195	}
5196
5197	/**
5198	* Unblock the FIFO I/O thread so it can respond to a state change.
5199	*
5200	* @returns VBox status code.
5201	* @param pDevIns The VGA device instance.
5202	* @param pThread The send thread.
5203	*/
5204	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5205	{
5206	RT_NOREF(pDevIns);
5207	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5208	Log(("vmsvgaFIFOLoopWakeUp\n"));
5209	return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
5210	}
5211
5212	/**
5213	* Enables or disables dirty page tracking for the framebuffer
5214	*
5215	* @param pThis VGA device instance data.
5216	* @param fTraces Enable/disable traces
5217	*/
5218	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5219	{
5220	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5221	&& !fTraces)
5222	{
5223	//Assert(pThis->svga.fTraces);
5224	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5225	return;
5226	}
5227
5228	pThis->svga.fTraces = fTraces;
5229	if (pThis->svga.fTraces)
5230	{
5231	unsigned cbFrameBuffer = pThis->vram_size;
5232
5233	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5234	/** @todo How does this work with screens? */
5235	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5236	{
5237	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5238	Assert(pThis->svga.cbScanline);
5239	#endif
5240	/* Hardware enabled; return real framebuffer size .*/
5241	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5242	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5243	}
5244
5245	if (!pThis->svga.fVRAMTracking)
5246	{
5247	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5248	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5249	pThis->svga.fVRAMTracking = true;
5250	}
5251	}
5252	else
5253	{
5254	if (pThis->svga.fVRAMTracking)
5255	{
5256	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5257	vgaR3UnregisterVRAMHandler(pThis);
5258	pThis->svga.fVRAMTracking = false;
5259	}
5260	}
5261	}
5262
5263	/**
5264	* @callback_method_impl{FNPCIIOREGIONMAP}
5265	*/
5266	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5267	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5268	{
5269	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5270	int rc;
5271	RT_NOREF(pPciDev);
5272	Assert(pPciDev == pDevIns->apPciDevs[0]);
5273
5274	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5275	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR);
5276	if (GCPhysAddress != NIL_RTGCPHYS)
5277	{
5278	/*
5279	* Mapping the FIFO RAM.
5280	*/
5281	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5282	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5283	AssertRC(rc);
5284
5285	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5286	if (RT_SUCCESS(rc))
5287	{
5288	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5289	# ifdef DEBUG_FIFO_ACCESS
5290	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5291	# else
5292	GCPhysAddress + PAGE_SIZE - 1,
5293	# endif
5294	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5295	"VMSVGA FIFO");
5296	AssertRC(rc);
5297	}
5298	# endif
5299	if (RT_SUCCESS(rc))
5300	{
5301	pThis->svga.GCPhysFIFO = GCPhysAddress;
5302	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5303	}
5304	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5305	}
5306	else
5307	{
5308	Assert(pThis->svga.GCPhysFIFO);
5309	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5310	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5311	AssertRC(rc);
5312	# else
5313	rc = VINF_SUCCESS;
5314	# endif
5315	pThis->svga.GCPhysFIFO = 0;
5316	}
5317	return rc;
5318	}
5319
5320	# ifdef VBOX_WITH_VMSVGA3D
5321
5322	/**
5323	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5324	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5325	*
5326	* @param pDevIns The device instance.
5327	* @param pThis The VGA device instance data.
5328	* @param sid Either UINT32_MAX or the ID of a specific
5329	* surface. If UINT32_MAX is used, all surfaces
5330	* are processed.
5331	*/
5332	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t sid)
5333	{
5334	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5335	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5336	}
5337
5338
5339	/**
5340	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5341	*/
5342	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5343	{
5344	/* There might be a specific surface ID at the start of the
5345	arguments, if not show all surfaces. */
5346	uint32_t sid = UINT32_MAX;
5347	if (pszArgs)
5348	pszArgs = RTStrStripL(pszArgs);
5349	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5350	sid = RTStrToUInt32(pszArgs);
5351
5352	/* Verbose or terse display, we default to verbose. */
5353	bool fVerbose = true;
5354	if (RTStrIStr(pszArgs, "terse"))
5355	fVerbose = false;
5356
5357	/* The size of the ascii art (x direction, y is 3/4 of x). */
5358	uint32_t cxAscii = 80;
5359	if (RTStrIStr(pszArgs, "gigantic"))
5360	cxAscii = 300;
5361	else if (RTStrIStr(pszArgs, "huge"))
5362	cxAscii = 180;
5363	else if (RTStrIStr(pszArgs, "big"))
5364	cxAscii = 132;
5365	else if (RTStrIStr(pszArgs, "normal"))
5366	cxAscii = 80;
5367	else if (RTStrIStr(pszArgs, "medium"))
5368	cxAscii = 64;
5369	else if (RTStrIStr(pszArgs, "small"))
5370	cxAscii = 48;
5371	else if (RTStrIStr(pszArgs, "tiny"))
5372	cxAscii = 24;
5373
5374	/* Y invert the image when producing the ASCII art. */
5375	bool fInvY = false;
5376	if (RTStrIStr(pszArgs, "invy"))
5377	fInvY = true;
5378
5379	vmsvga3dInfoSurfaceWorker(pDevIns, PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5380	}
5381
5382
5383	/**
5384	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5385	*/
5386	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5387	{
5388	/* pszArg = "sid[>dir]"
5389	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5390	*/
5391	char *pszBitmapPath = NULL;
5392	uint32_t sid = UINT32_MAX;
5393	if (pszArgs)
5394	pszArgs = RTStrStripL(pszArgs);
5395	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5396	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5397	if ( pszBitmapPath
5398	&& *pszBitmapPath == '>')
5399	++pszBitmapPath;
5400
5401	const bool fVerbose = true;
5402	const uint32_t cxAscii = 0; /* No ASCII */
5403	const bool fInvY = false; /* Do not invert. */
5404	vmsvga3dInfoSurfaceWorker(pDevIns, PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5405	}
5406
5407
5408	/**
5409	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5410	*/
5411	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5412	{
5413	/* There might be a specific surface ID at the start of the
5414	arguments, if not show all contexts. */
5415	uint32_t sid = UINT32_MAX;
5416	if (pszArgs)
5417	pszArgs = RTStrStripL(pszArgs);
5418	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5419	sid = RTStrToUInt32(pszArgs);
5420
5421	/* Verbose or terse display, we default to verbose. */
5422	bool fVerbose = true;
5423	if (RTStrIStr(pszArgs, "terse"))
5424	fVerbose = false;
5425
5426	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5427	}
5428
5429	# endif /* VBOX_WITH_VMSVGA3D */
5430
5431	/**
5432	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5433	*/
5434	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5435	{
5436	RT_NOREF(pszArgs);
5437	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5438	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5439	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.pFIFOR3;
5440
5441	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5442	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5443	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5444	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5445	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5446	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5447	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5448	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5449	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5450	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5451	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5452	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5453	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5454	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5455	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5456	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5457	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5458	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5459	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5460	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5461	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5462	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5463	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5464	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5465	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5466
5467	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5468	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5469	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5470	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5471
5472	# ifdef VBOX_WITH_VMSVGA3D
5473	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5474	# endif
5475	if (pThis->pDrv)
5476	{
5477	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThis->pDrv->cx, pThis->pDrv->cy, pThis->pDrv->cBits);
5478	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThis->pDrv->cbScanline, pThis->pDrv->cbScanline);
5479	}
5480	}
5481
5482	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5483	*/
5484	static int vmsvgaLoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5485	{
5486	RT_NOREF(uPass);
5487
5488	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5489	int rc;
5490
5491	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5492	{
5493	uint32_t cScreens = 0;
5494	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5495	AssertRCReturn(rc, rc);
5496	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5497	("cScreens=%#x\n", cScreens),
5498	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5499
5500	for (uint32_t i = 0; i < cScreens; ++i)
5501	{
5502	VMSVGASCREENOBJECT screen;
5503	RT_ZERO(screen);
5504
5505	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5506	AssertLogRelRCReturn(rc, rc);
5507
5508	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5509	{
5510	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5511	*pScreen = screen;
5512	pScreen->fModified = true;
5513	}
5514	else
5515	{
5516	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5517	}
5518	}
5519	}
5520	else
5521	{
5522	/* Try to setup at least the first screen. */
5523	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5524	pScreen->fDefined = true;
5525	pScreen->fModified = true;
5526	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5527	pScreen->idScreen = 0;
5528	pScreen->xOrigin = 0;
5529	pScreen->yOrigin = 0;
5530	pScreen->offVRAM = pThis->svga.uScreenOffset;
5531	pScreen->cbPitch = pThis->svga.cbScanline;
5532	pScreen->cWidth = pThis->svga.uWidth;
5533	pScreen->cHeight = pThis->svga.uHeight;
5534	pScreen->cBpp = pThis->svga.uBpp;
5535	}
5536
5537	return VINF_SUCCESS;
5538	}
5539
5540	/**
5541	* @copydoc FNSSMDEVLOADEXEC
5542	*/
5543	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5544	{
5545	RT_NOREF(uPass);
5546	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5547	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5548	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5549	int rc;
5550
5551	/* Load our part of the VGAState */
5552	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5553	AssertRCReturn(rc, rc);
5554
5555	/* Load the VGA framebuffer. */
5556	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5557	uint32_t cbVgaFramebuffer = _32K;
5558	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5559	{
5560	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5561	AssertRCReturn(rc, rc);
5562	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5563	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5564	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5565	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5566	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5567	}
5568	rc = pHlp->pfnSSMGetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5569	AssertRCReturn(rc, rc);
5570	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5571	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5572	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5573	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5574
5575	/* Load the VMSVGA state. */
5576	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5577	AssertRCReturn(rc, rc);
5578
5579	/* Load the active cursor bitmaps. */
5580	if (pSVGAState->Cursor.fActive)
5581	{
5582	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5583	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5584
5585	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5586	AssertRCReturn(rc, rc);
5587	}
5588
5589	/* Load the GMR state. */
5590	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5591	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5592	{
5593	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5594	AssertRCReturn(rc, rc);
5595	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5596	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5597	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5598	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5599	}
5600
5601	if (pThis->svga.cGMR != cGMR)
5602	{
5603	/* Reallocate GMR array. */
5604	Assert(pSVGAState->paGMR != NULL);
5605	RTMemFree(pSVGAState->paGMR);
5606	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5607	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5608	pThis->svga.cGMR = cGMR;
5609	}
5610
5611	for (uint32_t i = 0; i < cGMR; ++i)
5612	{
5613	PGMR pGMR = &pSVGAState->paGMR[i];
5614
5615	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5616	AssertRCReturn(rc, rc);
5617
5618	if (pGMR->numDescriptors)
5619	{
5620	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5621	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5622	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5623
5624	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5625	{
5626	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5627	AssertRCReturn(rc, rc);
5628	}
5629	}
5630	}
5631
5632	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5633	vmsvga3dPowerOn(pThis);
5634	# endif
5635
5636	VMSVGA_STATE_LOAD LoadState;
5637	LoadState.pSSM = pSSM;
5638	LoadState.uVersion = uVersion;
5639	LoadState.uPass = uPass;
5640	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5641	AssertLogRelRCReturn(rc, rc);
5642
5643	return VINF_SUCCESS;
5644	}
5645
5646	/**
5647	* Reinit the video mode after the state has been loaded.
5648	*/
5649	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5650	{
5651	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5652	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5653
5654	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5655
5656	/* Set the active cursor. */
5657	if (pSVGAState->Cursor.fActive)
5658	{
5659	int rc;
5660
5661	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5662	true,
5663	true,
5664	pSVGAState->Cursor.xHotspot,
5665	pSVGAState->Cursor.yHotspot,
5666	pSVGAState->Cursor.width,
5667	pSVGAState->Cursor.height,
5668	pSVGAState->Cursor.pData);
5669	AssertRC(rc);
5670	}
5671	return VINF_SUCCESS;
5672	}
5673
5674	/**
5675	* Portion of SVGA state which must be saved in the FIFO thread.
5676	*/
5677	static int vmsvgaSaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM)
5678	{
5679	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5680	int rc;
5681
5682	/* Save the screen objects. */
5683	/* Count defined screen object. */
5684	uint32_t cScreens = 0;
5685	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5686	{
5687	if (pSVGAState->aScreens[i].fDefined)
5688	++cScreens;
5689	}
5690
5691	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5692	AssertLogRelRCReturn(rc, rc);
5693
5694	for (uint32_t i = 0; i < cScreens; ++i)
5695	{
5696	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5697
5698	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5699	AssertLogRelRCReturn(rc, rc);
5700	}
5701	return VINF_SUCCESS;
5702	}
5703
5704	/**
5705	* @copydoc FNSSMDEVSAVEEXEC
5706	*/
5707	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5708	{
5709	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5710	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5711	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5712	int rc;
5713
5714	/* Save our part of the VGAState */
5715	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5716	AssertLogRelRCReturn(rc, rc);
5717
5718	/* Save the framebuffer backup. */
5719	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5720	rc = pHlp->pfnSSMPutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5721	AssertLogRelRCReturn(rc, rc);
5722
5723	/* Save the VMSVGA state. */
5724	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5725	AssertLogRelRCReturn(rc, rc);
5726
5727	/* Save the active cursor bitmaps. */
5728	if (pSVGAState->Cursor.fActive)
5729	{
5730	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5731	AssertLogRelRCReturn(rc, rc);
5732	}
5733
5734	/* Save the GMR state */
5735	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5736	AssertLogRelRCReturn(rc, rc);
5737	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5738	{
5739	PGMR pGMR = &pSVGAState->paGMR[i];
5740
5741	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5742	AssertLogRelRCReturn(rc, rc);
5743
5744	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5745	{
5746	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5747	AssertLogRelRCReturn(rc, rc);
5748	}
5749	}
5750
5751	/*
5752	* Must save some state (3D in particular) in the FIFO thread.
5753	*/
5754	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5755	AssertLogRelRCReturn(rc, rc);
5756
5757	return VINF_SUCCESS;
5758	}
5759
5760	/**
5761	* Destructor for PVMSVGAR3STATE structure.
5762	*
5763	* @param pThis The VGA instance.
5764	* @param pSVGAState Pointer to the structure. It is not deallocated.
5765	*/
5766	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5767	{
5768	#ifndef VMSVGA_USE_EMT_HALT_CODE
5769	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5770	{
5771	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5772	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5773	}
5774	#endif
5775
5776	if (pSVGAState->Cursor.fActive)
5777	{
5778	RTMemFree(pSVGAState->Cursor.pData);
5779	pSVGAState->Cursor.pData = NULL;
5780	pSVGAState->Cursor.fActive = false;
5781	}
5782
5783	if (pSVGAState->paGMR)
5784	{
5785	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5786	if (pSVGAState->paGMR[i].paDesc)
5787	RTMemFree(pSVGAState->paGMR[i].paDesc);
5788
5789	RTMemFree(pSVGAState->paGMR);
5790	pSVGAState->paGMR = NULL;
5791	}
5792	}
5793
5794	/**
5795	* Constructor for PVMSVGAR3STATE structure.
5796	*
5797	* @returns VBox status code.
5798	* @param pThis The VGA instance.
5799	* @param pSVGAState Pointer to the structure. It is already allocated.
5800	*/
5801	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5802	{
5803	int rc = VINF_SUCCESS;
5804	RT_ZERO(*pSVGAState);
5805
5806	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5807	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5808
5809	#ifndef VMSVGA_USE_EMT_HALT_CODE
5810	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5811	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5812	AssertRCReturn(rc, rc);
5813	#endif
5814
5815	return rc;
5816	}
5817
5818	/**
5819	* Initializes the host capabilities: registers and FIFO.
5820	*
5821	* @returns VBox status code.
5822	* @param pThis The VGA instance.
5823	*/
5824	static void vmsvgaInitCaps(PVGASTATE pThis)
5825	{
5826	/* Register caps. */
5827	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5828	\| SVGA_CAP_GMR2
5829	\| SVGA_CAP_CURSOR
5830	\| SVGA_CAP_CURSOR_BYPASS_2
5831	\| SVGA_CAP_EXTENDED_FIFO
5832	\| SVGA_CAP_IRQMASK
5833	\| SVGA_CAP_PITCHLOCK
5834	\| SVGA_CAP_TRACES
5835	\| SVGA_CAP_SCREEN_OBJECT_2
5836	\| SVGA_CAP_ALPHA_CURSOR;
5837	# ifdef VBOX_WITH_VMSVGA3D
5838	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5839	# endif
5840
5841	/* Clear the FIFO. */
5842	RT_BZERO(pThis->svga.pFIFOR3, pThis->svga.cbFIFO);
5843
5844	/* Setup FIFO capabilities. */
5845	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5846	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5847	\| SVGA_FIFO_CAP_GMR2
5848	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5849	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5850	\| SVGA_FIFO_CAP_RESERVE
5851	\| SVGA_FIFO_CAP_PITCHLOCK;
5852
5853	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5854	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5855	}
5856
5857	# ifdef VBOX_WITH_VMSVGA3D
5858	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5859	static const char * const g_apszVmSvgaDevCapNames[] =
5860	{
5861	"x3D", /* = 0 */
5862	"xMAX_LIGHTS",
5863	"xMAX_TEXTURES",
5864	"xMAX_CLIP_PLANES",
5865	"xVERTEX_SHADER_VERSION",
5866	"xVERTEX_SHADER",
5867	"xFRAGMENT_SHADER_VERSION",
5868	"xFRAGMENT_SHADER",
5869	"xMAX_RENDER_TARGETS",
5870	"xS23E8_TEXTURES",
5871	"xS10E5_TEXTURES",
5872	"xMAX_FIXED_VERTEXBLEND",
5873	"xD16_BUFFER_FORMAT",
5874	"xD24S8_BUFFER_FORMAT",
5875	"xD24X8_BUFFER_FORMAT",
5876	"xQUERY_TYPES",
5877	"xTEXTURE_GRADIENT_SAMPLING",
5878	"rMAX_POINT_SIZE",
5879	"xMAX_SHADER_TEXTURES",
5880	"xMAX_TEXTURE_WIDTH",
5881	"xMAX_TEXTURE_HEIGHT",
5882	"xMAX_VOLUME_EXTENT",
5883	"xMAX_TEXTURE_REPEAT",
5884	"xMAX_TEXTURE_ASPECT_RATIO",
5885	"xMAX_TEXTURE_ANISOTROPY",
5886	"xMAX_PRIMITIVE_COUNT",
5887	"xMAX_VERTEX_INDEX",
5888	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5889	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5890	"xMAX_VERTEX_SHADER_TEMPS",
5891	"xMAX_FRAGMENT_SHADER_TEMPS",
5892	"xTEXTURE_OPS",
5893	"xSURFACEFMT_X8R8G8B8",
5894	"xSURFACEFMT_A8R8G8B8",
5895	"xSURFACEFMT_A2R10G10B10",
5896	"xSURFACEFMT_X1R5G5B5",
5897	"xSURFACEFMT_A1R5G5B5",
5898	"xSURFACEFMT_A4R4G4B4",
5899	"xSURFACEFMT_R5G6B5",
5900	"xSURFACEFMT_LUMINANCE16",
5901	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5902	"xSURFACEFMT_ALPHA8",
5903	"xSURFACEFMT_LUMINANCE8",
5904	"xSURFACEFMT_Z_D16",
5905	"xSURFACEFMT_Z_D24S8",
5906	"xSURFACEFMT_Z_D24X8",
5907	"xSURFACEFMT_DXT1",
5908	"xSURFACEFMT_DXT2",
5909	"xSURFACEFMT_DXT3",
5910	"xSURFACEFMT_DXT4",
5911	"xSURFACEFMT_DXT5",
5912	"xSURFACEFMT_BUMPX8L8V8U8",
5913	"xSURFACEFMT_A2W10V10U10",
5914	"xSURFACEFMT_BUMPU8V8",
5915	"xSURFACEFMT_Q8W8V8U8",
5916	"xSURFACEFMT_CxV8U8",
5917	"xSURFACEFMT_R_S10E5",
5918	"xSURFACEFMT_R_S23E8",
5919	"xSURFACEFMT_RG_S10E5",
5920	"xSURFACEFMT_RG_S23E8",
5921	"xSURFACEFMT_ARGB_S10E5",
5922	"xSURFACEFMT_ARGB_S23E8",
5923	"xMISSING62",
5924	"xMAX_VERTEX_SHADER_TEXTURES",
5925	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5926	"xSURFACEFMT_V16U16",
5927	"xSURFACEFMT_G16R16",
5928	"xSURFACEFMT_A16B16G16R16",
5929	"xSURFACEFMT_UYVY",
5930	"xSURFACEFMT_YUY2",
5931	"xMULTISAMPLE_NONMASKABLESAMPLES",
5932	"xMULTISAMPLE_MASKABLESAMPLES",
5933	"xALPHATOCOVERAGE",
5934	"xSUPERSAMPLE",
5935	"xAUTOGENMIPMAPS",
5936	"xSURFACEFMT_NV12",
5937	"xSURFACEFMT_AYUV",
5938	"xMAX_CONTEXT_IDS",
5939	"xMAX_SURFACE_IDS",
5940	"xSURFACEFMT_Z_DF16",
5941	"xSURFACEFMT_Z_DF24",
5942	"xSURFACEFMT_Z_D24S8_INT",
5943	"xSURFACEFMT_BC4_UNORM",
5944	"xSURFACEFMT_BC5_UNORM", /* 83 */
5945	};
5946
5947	/**
5948	* Initializes the host 3D capabilities in FIFO.
5949	*
5950	* @returns VBox status code.
5951	* @param pThis The VGA instance.
5952	*/
5953	static void vmsvgaInitFifo3DCaps(PVGASTATE pThis)
5954	{
5955	/** @todo Probably query the capabilities once and cache in a memory buffer. */
5956	bool fSavedBuffering = RTLogRelSetBuffering(true);
5957	SVGA3dCapsRecord *pCaps;
5958	SVGA3dCapPair *pData;
5959	uint32_t idxCap = 0;
5960
5961	/* 3d hardware version; latest and greatest */
5962	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5963	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5964
5965	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5966	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5967	pData = (SVGA3dCapPair *)&pCaps->data;
5968
5969	/* Fill out all 3d capabilities. */
5970	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5971	{
5972	uint32_t val = 0;
5973
5974	int rc = vmsvga3dQueryCaps(pThis, i, &val);
5975	if (RT_SUCCESS(rc))
5976	{
5977	pData[idxCap][0] = i;
5978	pData[idxCap][1] = val;
5979	idxCap++;
5980	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
5981	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
5982	else
5983	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
5984	&g_apszVmSvgaDevCapNames[i][1]));
5985	}
5986	else
5987	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
5988	}
5989	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5990	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5991
5992	/* Mark end of record array. */
5993	pCaps->header.length = 0;
5994
5995	RTLogRelSetBuffering(fSavedBuffering);
5996	}
5997
5998	# endif
5999
6000	/**
6001	* Resets the SVGA hardware state
6002	*
6003	* @returns VBox status code.
6004	* @param pDevIns The device instance.
6005	*/
6006	int vmsvgaReset(PPDMDEVINS pDevIns)
6007	{
6008	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6009	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
6010
6011	/* Reset before init? */
6012	if (!pSVGAState)
6013	return VINF_SUCCESS;
6014
6015	Log(("vmsvgaReset\n"));
6016
6017	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6018	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6019	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6020
6021	/* Reset other stuff. */
6022	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6023	RT_ZERO(pThis->svga.au32ScratchRegion);
6024
6025	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6026	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6027
6028	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6029
6030	/* Initialize FIFO and register capabilities. */
6031	vmsvgaInitCaps(pThis);
6032
6033	# ifdef VBOX_WITH_VMSVGA3D
6034	if (pThis->svga.f3DEnabled)
6035	vmsvgaInitFifo3DCaps(pThis);
6036	# endif
6037
6038	/* VRAM tracking is enabled by default during bootup. */
6039	pThis->svga.fVRAMTracking = true;
6040	pThis->svga.fEnabled = false;
6041
6042	/* Invalidate current settings. */
6043	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6044	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6045	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6046	pThis->svga.cbScanline = 0;
6047	pThis->svga.u32PitchLock = 0;
6048
6049	return rc;
6050	}
6051
6052	/**
6053	* Cleans up the SVGA hardware state
6054	*
6055	* @returns VBox status code.
6056	* @param pDevIns The device instance.
6057	*/
6058	int vmsvgaDestruct(PPDMDEVINS pDevIns)
6059	{
6060	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6061
6062	/*
6063	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6064	*/
6065	if (pThis->svga.pFIFOIOThread)
6066	{
6067	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
6068	AssertLogRelRC(rc);
6069
6070	rc = PDMDevHlpThreadDestroy(pDevIns, pThis->svga.pFIFOIOThread, NULL);
6071	AssertLogRelRC(rc);
6072	pThis->svga.pFIFOIOThread = NULL;
6073	}
6074
6075	/*
6076	* Destroy the special SVGA state.
6077	*/
6078	if (pThis->svga.pSvgaR3State)
6079	{
6080	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6081
6082	RTMemFree(pThis->svga.pSvgaR3State);
6083	pThis->svga.pSvgaR3State = NULL;
6084	}
6085
6086	/*
6087	* Free our resources residing in the VGA state.
6088	*/
6089	if (pThis->svga.pbVgaFrameBufferR3)
6090	{
6091	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
6092	pThis->svga.pbVgaFrameBufferR3 = NULL;
6093	}
6094	if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
6095	{
6096	RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
6097	pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
6098	}
6099	if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
6100	{
6101	SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
6102	pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
6103	}
6104
6105	return VINF_SUCCESS;
6106	}
6107
6108	/**
6109	* Initialize the SVGA hardware state
6110	*
6111	* @returns VBox status code.
6112	* @param pDevIns The device instance.
6113	*/
6114	int vmsvgaInit(PPDMDEVINS pDevIns)
6115	{
6116	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6117	PVMSVGAR3STATE pSVGAState;
6118	int rc;
6119
6120	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6121	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6122
6123	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6124
6125	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6126	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6127	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6128
6129	/* Create event semaphore. */
6130	pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
6131
6132	rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
6133	if (RT_FAILURE(rc))
6134	{
6135	Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
6136	return rc;
6137	}
6138
6139	/* Create event semaphore. */
6140	rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
6141	if (RT_FAILURE(rc))
6142	{
6143	Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
6144	return rc;
6145	}
6146
6147	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6148	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
6149
6150	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6151	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6152
6153	pSVGAState = pThis->svga.pSvgaR3State;
6154
6155	/* Initialize FIFO and register capabilities. */
6156	vmsvgaInitCaps(pThis);
6157
6158	# ifdef VBOX_WITH_VMSVGA3D
6159	if (pThis->svga.f3DEnabled)
6160	{
6161	rc = vmsvga3dInit(pThis);
6162	if (RT_FAILURE(rc))
6163	{
6164	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6165	pThis->svga.f3DEnabled = false;
6166	}
6167	}
6168	# endif
6169	/* VRAM tracking is enabled by default during bootup. */
6170	pThis->svga.fVRAMTracking = true;
6171
6172	/* Invalidate current settings. */
6173	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6174	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6175	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6176	pThis->svga.cbScanline = 0;
6177
6178	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6179	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6180	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6181	{
6182	pThis->svga.u32MaxWidth -= 256;
6183	pThis->svga.u32MaxHeight -= 256;
6184	}
6185	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6186
6187	# ifdef DEBUG_GMR_ACCESS
6188	/* Register the GMR access handler type. */
6189	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
6190	vmsvgaR3GMRAccessHandler,
6191	NULL, NULL, NULL,
6192	NULL, NULL, NULL,
6193	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6194	AssertRCReturn(rc, rc);
6195	# endif
6196
6197	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6198	/* Register the FIFO access handler type. In addition to
6199	debugging FIFO access, this is also used to facilitate
6200	extended fifo thread sleeps. */
6201	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6202	# ifdef DEBUG_FIFO_ACCESS
6203	PGMPHYSHANDLERKIND_ALL,
6204	# else
6205	PGMPHYSHANDLERKIND_WRITE,
6206	# endif
6207	vmsvgaR3FIFOAccessHandler,
6208	NULL, NULL, NULL,
6209	NULL, NULL, NULL,
6210	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6211	AssertRCReturn(rc, rc);
6212	# endif
6213
6214	/* Create the async IO thread. */
6215	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
6216	RTTHREADTYPE_IO, "VMSVGA FIFO");
6217	if (RT_FAILURE(rc))
6218	{
6219	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6220	return rc;
6221	}
6222
6223	/*
6224	* Statistics.
6225	*/
6226	#define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6227	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6228	#define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6229	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6230	#ifdef VBOX_WITH_STATISTICS
6231	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6232	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6233	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6234	#endif
6235	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6236	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6237	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6238	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6239	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6240	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6241	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6242	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6243	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6244	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6245	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6246	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6247	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6248	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6249	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6250	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6251	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6252	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6253	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6254	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6255	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6256	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6257	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6258	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6259	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6260	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6261	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6262	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6263	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6264	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6265	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6266	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6267	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6268	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6269	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6270	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6271	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6272	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6273	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6274	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6275	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6276	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6277	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6278	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6279	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6280	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6281	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6282	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6283	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6284	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6285	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6286	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6287	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6288
6289	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6290	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6291	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6292	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6293	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6294	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6295	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6296	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6297	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6298	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6299	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6300	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6301	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6302	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6303	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6304	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6305	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6306	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6307	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6308	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6309	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6310	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6311	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6312	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6313	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6314	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6315	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6316	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6317	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6318	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6319	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6320	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6321
6322	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6323	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6324	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6325	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6326	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6327	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6328	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6329	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6330	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6331	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6332	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6333	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6334	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6335	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6336	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6337	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6338	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6339	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6340	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6341	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6342	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6343	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6344	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6345	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6346	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6347	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6348	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6349	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6350	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6351	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6352	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6353	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6354	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6355	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6356	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6357	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6358	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6359	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6360	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6361	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6362	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6363	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6364	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6365	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6366	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6367	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6368	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6369	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6370	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6371
6372	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6373	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6374	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6375	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6376	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6377	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6378	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6379	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6380	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6381	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6382	# endif
6383	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6384	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6385	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6386	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6387	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6388
6389	#undef REG_CNT
6390	#undef REG_PRF
6391
6392	/*
6393	* Info handlers.
6394	*/
6395	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6396	# ifdef VBOX_WITH_VMSVGA3D
6397	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6398	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6399	"VMSVGA 3d surface details. "
6400	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6401	vmsvgaR3Info3dSurface);
6402	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6403	"VMSVGA 3d surface details and bitmap: "
6404	"sid[>dir]",
6405	vmsvgaR3Info3dSurfaceBmp);
6406	# endif
6407
6408	return VINF_SUCCESS;
6409	}
6410
6411	/**
6412	* Power On notification.
6413	*
6414	* @returns VBox status code.
6415	* @param pDevIns The device instance data.
6416	*
6417	* @remarks Caller enters the device critical section.
6418	*/
6419	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6420	{
6421	# ifdef VBOX_WITH_VMSVGA3D
6422	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6423	if (pThis->svga.f3DEnabled)
6424	{
6425	int rc = vmsvga3dPowerOn(pThis);
6426
6427	if (RT_SUCCESS(rc))
6428	{
6429	/* Initialize FIFO 3D capabilities. */
6430	vmsvgaInitFifo3DCaps(pThis);
6431	}
6432	}
6433	# else /* !VBOX_WITH_VMSVGA3D */
6434	RT_NOREF(pDevIns);
6435	# endif /* !VBOX_WITH_VMSVGA3D */
6436	}
6437
6438	#endif /* IN_RING3 */
6439

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 82079

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