VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevPCNet.cpp@ 10690

Last change on this file since 10690 was 9212, checked in by vboxsync, 17 years ago

Major changes for sizeof(RTGCPTR) == uint64_t.
Introduced RCPTRTYPE for pointers valid in raw mode only (RTGCPTR32).

Disabled by default. Enable by adding VBOX_WITH_64_BITS_GUESTS to your LocalConfig.kmk.
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  • Property svn:keywords set to Author Date Id Revision
File size: 190.3 KB
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1/* $Id: DevPCNet.cpp 9212 2008-05-29 09:38:38Z vboxsync $ */
2/** @file
3 * AMD PCnet-PCI II / PCnet-FAST III (Am79C970A / Am79C973) Ethernet Controller Emulation.
4 */
5
6/*
7 * Copyright (C) 2006-2008 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 * --------------------------------------------------------------------
21 *
22 * This code is based on:
23 *
24 * AMD PC-Net II (Am79C970A) emulation
25 *
26 * Copyright (c) 2004 Antony T Curtis
27 *
28 * Permission is hereby granted, free of charge, to any person obtaining a copy
29 * of this software and associated documentation files (the "Software"), to deal
30 * in the Software without restriction, including without limitation the rights
31 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32 * copies of the Software, and to permit persons to whom the Software is
33 * furnished to do so, subject to the following conditions:
34 *
35 * The above copyright notice and this permission notice shall be included in
36 * all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44 * THE SOFTWARE.
45 */
46
47/* This software was written to be compatible with the specification:
48 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
49 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
50 */
51
52/*******************************************************************************
53* Header Files *
54*******************************************************************************/
55#define LOG_GROUP LOG_GROUP_DEV_PCNET
56#include <VBox/pdmdev.h>
57#include <VBox/pgm.h>
58#include <VBox/vm.h> /* for VM_IS_EMT */
59#include <VBox/DevPCNet.h>
60#include <iprt/asm.h>
61#include <iprt/assert.h>
62#include <iprt/critsect.h>
63#include <iprt/string.h>
64#include <iprt/time.h>
65#ifdef IN_RING3
66# include <iprt/mem.h>
67# include <iprt/semaphore.h>
68#endif
69
70#include "Builtins.h"
71
72/* Enable this to catch writes to the ring descriptors instead of using excessive polling */
73/* #define PCNET_NO_POLLING */
74
75/* Enable to handle frequent io reads in the guest context (recommended) */
76#define PCNET_GC_ENABLED
77
78/* Experimental: queue TX packets */
79//#define PCNET_QUEUE_SEND_PACKETS
80
81#if defined(LOG_ENABLED)
82#define PCNET_DEBUG_IO
83#define PCNET_DEBUG_BCR
84#define PCNET_DEBUG_CSR
85#define PCNET_DEBUG_RMD
86#define PCNET_DEBUG_TMD
87#define PCNET_DEBUG_MATCH
88#define PCNET_DEBUG_MII
89#endif
90
91#define PCNET_IOPORT_SIZE 0x20
92#define PCNET_PNPMMIO_SIZE 0x20
93
94#define PCNET_SAVEDSTATE_VERSION 10
95
96#define BCR_MAX_RAP 50
97#define MII_MAX_REG 32
98#define CSR_MAX_REG 128
99
100/* Maximum number of times we report a link down to the guest (failure to send frame) */
101#define PCNET_MAX_LINKDOWN_REPORTED 3
102
103/* Maximum frame size we handle */
104#define MAX_FRAME 1536
105
106
107typedef struct PCNetState_st PCNetState;
108
109struct PCNetState_st
110{
111 PCIDEVICE PciDev;
112#ifndef PCNET_NO_POLLING
113 /** Poll timer (address for host context) */
114 R3R0PTRTYPE(PTMTIMER) pTimerPollHC;
115 /** Poll timer (address for guest context) */
116 RCPTRTYPE(PTMTIMER) pTimerPollGC;
117#endif
118
119#if HC_ARCH_BITS == 64
120 uint32_t Alignment1;
121#endif
122
123 /** Software Interrupt timer (address for host context) */
124 R3R0PTRTYPE(PTMTIMER) pTimerSoftIntHC;
125 /** Software Interrupt timer (address for guest context) */
126 RCPTRTYPE(PTMTIMER) pTimerSoftIntGC;
127
128 /** Register Address Pointer */
129 uint32_t u32RAP;
130 /** Internal interrupt service */
131 int32_t iISR;
132 /** ??? */
133 uint32_t u32Lnkst;
134 /** Address of the RX descriptor table (ring). Loaded at init. */
135 RTGCPHYS32 GCRDRA;
136 /** Address of the TX descriptor table (ring). Loaded at init. */
137 RTGCPHYS32 GCTDRA;
138 uint8_t aPROM[16];
139 uint16_t aCSR[CSR_MAX_REG];
140 uint16_t aBCR[BCR_MAX_RAP];
141 uint16_t aMII[MII_MAX_REG];
142 uint16_t u16CSR0LastSeenByGuest;
143 uint16_t Alignment2[HC_ARCH_BITS == 32 ? 2 : 4];
144 /** Last time we polled the queues */
145 uint64_t u64LastPoll;
146
147 /** Size of current send frame */
148 uint32_t cbSendFrame;
149#if HC_ARCH_BITS == 64
150 uint32_t Alignment3;
151#endif
152 /** Buffer address of current send frame */
153 R3PTRTYPE(uint8_t *) pvSendFrame;
154 /** The xmit buffer. */
155 uint8_t abSendBuf[4096];
156 /** The recv buffer. */
157 uint8_t abRecvBuf[4096];
158
159 /** Pending send packet counter. */
160 uint32_t cPendingSends;
161
162 /** Size of a RX/TX descriptor (8 or 16 bytes according to SWSTYLE */
163 int iLog2DescSize;
164 /** Bits 16..23 in 16-bit mode */
165 RTGCPHYS32 GCUpperPhys;
166
167 /** Transmit signaller */
168 RCPTRTYPE(PPDMQUEUE) pXmitQueueGC;
169 R3R0PTRTYPE(PPDMQUEUE) pXmitQueueHC;
170
171 /** Receive signaller */
172 R3R0PTRTYPE(PPDMQUEUE) pCanRxQueueHC;
173 RCPTRTYPE(PPDMQUEUE) pCanRxQueueGC;
174 /** Pointer to the device instance. */
175 RCPTRTYPE(PPDMDEVINS) pDevInsGC;
176 /** Pointer to the device instance. */
177 R3R0PTRTYPE(PPDMDEVINS) pDevInsHC;
178 /** Restore timer.
179 * This is used to disconnect and reconnect the link after a restore. */
180 PTMTIMERR3 pTimerRestore;
181 /** Pointer to the connector of the attached network driver. */
182 R3PTRTYPE(PPDMINETWORKCONNECTOR) pDrv;
183 /** Pointer to the attached network driver. */
184 R3PTRTYPE(PPDMIBASE) pDrvBase;
185 /** The base interface. */
186 PDMIBASE IBase;
187 /** The network port interface. */
188 PDMINETWORKPORT INetworkPort;
189 /** The network config port interface. */
190 PDMINETWORKCONFIG INetworkConfig;
191 /** Base address of the MMIO region. */
192 RTGCPHYS32 MMIOBase;
193 /** Base port of the I/O space region. */
194 RTIOPORT IOPortBase;
195 /** If set the link is currently up. */
196 bool fLinkUp;
197 /** If set the link is temporarily down because of a saved state load. */
198 bool fLinkTempDown;
199
200 /** Number of times we've reported the link down. */
201 RTUINT cLinkDownReported;
202 /** The configured MAC address. */
203 PDMMAC MacConfigured;
204 /** Alignment padding. */
205 uint8_t Alignment4[HC_ARCH_BITS == 64 ? 6 : 2];
206
207 /** The LED. */
208 PDMLED Led;
209 /** The LED ports. */
210 PDMILEDPORTS ILeds;
211 /** Partner of ILeds. */
212 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
213
214 /** Async send thread */
215 RTSEMEVENT hSendEventSem;
216 /** The Async send thread. */
217 PPDMTHREAD pSendThread;
218
219 /** Access critical section. */
220 PDMCRITSECT CritSect;
221 /** Event semaphore for blocking on receive. */
222 RTSEMEVENT hEventOutOfRxSpace;
223 /** We are waiting/about to start waiting for more receive buffers. */
224 bool volatile fMaybeOutOfSpace;
225 /** True if we signal the guest that RX packets are missing. */
226 bool fSignalRxMiss;
227 uint8_t Alignment5[HC_ARCH_BITS == 64 ? 6 : 2];
228
229#ifdef PCNET_NO_POLLING
230 RTGCPHYS32 TDRAPhysOld;
231 uint32_t cbTDRAOld;
232
233 RTGCPHYS32 RDRAPhysOld;
234 uint32_t cbRDRAOld;
235
236 DECLGCCALLBACKMEMBER(int, pfnEMInterpretInstructionGC, (PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize));
237 DECLR0CALLBACKMEMBER(int, pfnEMInterpretInstructionR0, (PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize));
238#endif
239
240 /** The host context of the shared memory used for the private interface. */
241 R3R0PTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIOHC;
242 /** The hypervisor/guest context of the shared memory used for the private interface. */
243 RCPTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIOGC;
244
245#if HC_ARCH_BITS == 64
246 uint32_t Alignment6;
247#endif
248
249 /** True if host and guest admitted to use the private interface. */
250 bool fPrivIfEnabled;
251 bool fGCEnabled;
252 bool fR0Enabled;
253 bool fAm79C973;
254 uint32_t u32LinkSpeed;
255
256#ifdef PCNET_QUEUE_SEND_PACKETS
257 #define PCNET_MAX_XMIT_SLOTS 128
258 #define PCNET_MAX_XMIT_SLOTS_MASK (PCNET_MAX_XMIT_SLOTS-1)
259
260 uint32_t iXmitRingBufProd;
261 uint32_t iXmitRingBufCons;
262 /* XXX currently atomic operations on this variable are overkill */
263 volatile int32_t cXmitRingBufPending;
264 uint16_t cbXmitRingBuffer[PCNET_MAX_XMIT_SLOTS];
265 R3PTRTYPE(uint8_t *) apXmitRingBuffer[PCNET_MAX_XMIT_SLOTS];
266#endif
267
268 STAMCOUNTER StatReceiveBytes;
269 STAMCOUNTER StatTransmitBytes;
270#ifdef VBOX_WITH_STATISTICS
271 STAMPROFILEADV StatMMIOReadGC;
272 STAMPROFILEADV StatMMIOReadHC;
273 STAMPROFILEADV StatMMIOWriteGC;
274 STAMPROFILEADV StatMMIOWriteHC;
275 STAMPROFILEADV StatAPROMRead;
276 STAMPROFILEADV StatAPROMWrite;
277 STAMPROFILEADV StatIOReadGC;
278 STAMPROFILEADV StatIOReadHC;
279 STAMPROFILEADV StatIOWriteGC;
280 STAMPROFILEADV StatIOWriteHC;
281 STAMPROFILEADV StatTimer;
282 STAMPROFILEADV StatReceive;
283 STAMPROFILEADV StatTransmit;
284 STAMPROFILEADV StatTransmitSend;
285 STAMPROFILEADV StatTdtePollGC;
286 STAMPROFILEADV StatTdtePollHC;
287 STAMPROFILEADV StatTmdStoreGC;
288 STAMPROFILEADV StatTmdStoreHC;
289 STAMPROFILEADV StatRdtePollGC;
290 STAMPROFILEADV StatRdtePollHC;
291 STAMPROFILE StatRxOverflow;
292 STAMCOUNTER StatRxOverflowWakeup;
293 STAMCOUNTER aStatXmitFlush[16];
294 STAMCOUNTER aStatXmitChainCounts[16];
295 STAMCOUNTER StatXmitSkipCurrent;
296 STAMPROFILEADV StatInterrupt;
297 STAMPROFILEADV StatPollTimer;
298 STAMCOUNTER StatMIIReads;
299# ifdef PCNET_NO_POLLING
300 STAMCOUNTER StatRCVRingWrite;
301 STAMCOUNTER StatTXRingWrite;
302 STAMCOUNTER StatRingWriteHC;
303 STAMCOUNTER StatRingWriteR0;
304 STAMCOUNTER StatRingWriteGC;
305
306 STAMCOUNTER StatRingWriteFailedHC;
307 STAMCOUNTER StatRingWriteFailedR0;
308 STAMCOUNTER StatRingWriteFailedGC;
309
310 STAMCOUNTER StatRingWriteOutsideHC;
311 STAMCOUNTER StatRingWriteOutsideR0;
312 STAMCOUNTER StatRingWriteOutsideGC;
313# endif
314#endif /* VBOX_WITH_STATISTICS */
315};
316
317#define PCNETSTATE_2_DEVINS(pPCNet) ((pPCNet)->CTXSUFF(pDevIns))
318#define PCIDEV_2_PCNETSTATE(pPciDev) ((PCNetState *)(pPciDev))
319#define PCNET_INST_NR (PCNETSTATE_2_DEVINS(pData)->iInstance)
320
321/* BUS CONFIGURATION REGISTERS */
322#define BCR_MSRDA 0
323#define BCR_MSWRA 1
324#define BCR_MC 2
325#define BCR_RESERVED3 3
326#define BCR_LNKST 4
327#define BCR_LED1 5
328#define BCR_LED2 6
329#define BCR_LED3 7
330#define BCR_RESERVED8 8
331#define BCR_FDC 9
332/* 10 - 15 = reserved */
333#define BCR_IOBASEL 16 /* Reserved */
334#define BCR_IOBASEU 16 /* Reserved */
335#define BCR_BSBC 18
336#define BCR_EECAS 19
337#define BCR_SWS 20
338#define BCR_INTCON 21 /* Reserved */
339#define BCR_PLAT 22
340#define BCR_PCISVID 23
341#define BCR_PCISID 24
342#define BCR_SRAMSIZ 25
343#define BCR_SRAMB 26
344#define BCR_SRAMIC 27
345#define BCR_EBADDRL 28
346#define BCR_EBADDRU 29
347#define BCR_EBD 30
348#define BCR_STVAL 31
349#define BCR_MIICAS 32
350#define BCR_MIIADDR 33
351#define BCR_MIIMDR 34
352#define BCR_PCIVID 35
353#define BCR_PMC_A 36
354#define BCR_DATA0 37
355#define BCR_DATA1 38
356#define BCR_DATA2 39
357#define BCR_DATA3 40
358#define BCR_DATA4 41
359#define BCR_DATA5 42
360#define BCR_DATA6 43
361#define BCR_DATA7 44
362#define BCR_PMR1 45
363#define BCR_PMR2 46
364#define BCR_PMR3 47
365
366#define BCR_DWIO(S) !!((S)->aBCR[BCR_BSBC] & 0x0080)
367#define BCR_SSIZE32(S) !!((S)->aBCR[BCR_SWS ] & 0x0100)
368#define BCR_SWSTYLE(S) ((S)->aBCR[BCR_SWS ] & 0x00FF)
369
370#define CSR_INIT(S) !!((S)->aCSR[0] & 0x0001) /**< Init assertion */
371#define CSR_STRT(S) !!((S)->aCSR[0] & 0x0002) /**< Start assertion */
372#define CSR_STOP(S) !!((S)->aCSR[0] & 0x0004) /**< Stop assertion */
373#define CSR_TDMD(S) !!((S)->aCSR[0] & 0x0008) /**< Transmit demand. (perform xmit poll now (readable, settable, not clearable) */
374#define CSR_TXON(S) !!((S)->aCSR[0] & 0x0010) /**< Transmit on (readonly) */
375#define CSR_RXON(S) !!((S)->aCSR[0] & 0x0020) /**< Receive On */
376#define CSR_INEA(S) !!((S)->aCSR[0] & 0x0040) /**< Interrupt Enable */
377#define CSR_LAPPEN(S) !!((S)->aCSR[3] & 0x0020) /**< Look Ahead Packet Processing Enable */
378#define CSR_DXSUFLO(S) !!((S)->aCSR[3] & 0x0040) /**< Disable Transmit Stop on Underflow error */
379#define CSR_ASTRP_RCV(S) !!((S)->aCSR[4] & 0x0400) /**< Auto Strip Receive */
380#define CSR_DPOLL(S) !!((S)->aCSR[4] & 0x1000) /**< Disable Transmit Polling */
381#define CSR_SPND(S) !!((S)->aCSR[5] & 0x0001) /**< Suspend */
382#define CSR_LTINTEN(S) !!((S)->aCSR[5] & 0x4000) /**< Last Transmit Interrupt Enable */
383#define CSR_TOKINTD(S) !!((S)->aCSR[5] & 0x8000) /**< Transmit OK Interrupt Disable */
384
385#define CSR_STINT !!((S)->aCSR[7] & 0x0800) /**< Software Timer Interrupt */
386#define CSR_STINTE !!((S)->aCSR[7] & 0x0400) /**< Software Timer Interrupt Enable */
387
388#define CSR_DRX(S) !!((S)->aCSR[15] & 0x0001) /**< Disable Receiver */
389#define CSR_DTX(S) !!((S)->aCSR[15] & 0x0002) /**< Disable Transmit */
390#define CSR_LOOP(S) !!((S)->aCSR[15] & 0x0004) /**< Loopback Enable */
391#define CSR_DRCVPA(S) !!((S)->aCSR[15] & 0x2000) /**< Disable Receive Physical Address */
392#define CSR_DRCVBC(S) !!((S)->aCSR[15] & 0x4000) /**< Disable Receive Broadcast */
393#define CSR_PROM(S) !!((S)->aCSR[15] & 0x8000) /**< Promiscuous Mode */
394
395#if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)
396#error fix macros (and more in this file) for big-endian machines
397#endif
398
399#define CSR_IADR(S) (*(uint32_t*)((S)->aCSR + 1)) /**< Initialization Block Address */
400#define CSR_CRBA(S) (*(uint32_t*)((S)->aCSR + 18)) /**< Current Receive Buffer Address */
401#define CSR_CXBA(S) (*(uint32_t*)((S)->aCSR + 20)) /**< Current Transmit Buffer Address */
402#define CSR_NRBA(S) (*(uint32_t*)((S)->aCSR + 22)) /**< Next Receive Buffer Address */
403#define CSR_BADR(S) (*(uint32_t*)((S)->aCSR + 24)) /**< Base Address of Receive Ring */
404#define CSR_NRDA(S) (*(uint32_t*)((S)->aCSR + 26)) /**< Next Receive Descriptor Address */
405#define CSR_CRDA(S) (*(uint32_t*)((S)->aCSR + 28)) /**< Current Receive Descriptor Address */
406#define CSR_BADX(S) (*(uint32_t*)((S)->aCSR + 30)) /**< Base Address of Transmit Descriptor */
407#define CSR_NXDA(S) (*(uint32_t*)((S)->aCSR + 32)) /**< Next Transmit Descriptor Address */
408#define CSR_CXDA(S) (*(uint32_t*)((S)->aCSR + 34)) /**< Current Transmit Descriptor Address */
409#define CSR_NNRD(S) (*(uint32_t*)((S)->aCSR + 36)) /**< Next Next Receive Descriptor Address */
410#define CSR_NNXD(S) (*(uint32_t*)((S)->aCSR + 38)) /**< Next Next Transmit Descriptor Address */
411#define CSR_CRBC(S) ((S)->aCSR[40]) /**< Current Receive Byte Count */
412#define CSR_CRST(S) ((S)->aCSR[41]) /**< Current Receive Status */
413#define CSR_CXBC(S) ((S)->aCSR[42]) /**< Current Transmit Byte Count */
414#define CSR_CXST(S) ((S)->aCSR[43]) /**< Current transmit status */
415#define CSR_NRBC(S) ((S)->aCSR[44]) /**< Next Receive Byte Count */
416#define CSR_NRST(S) ((S)->aCSR[45]) /**< Next Receive Status */
417#define CSR_POLL(S) ((S)->aCSR[46]) /**< Transmit Poll Time Counter */
418#define CSR_PINT(S) ((S)->aCSR[47]) /**< Transmit Polling Interval */
419#define CSR_PXDA(S) (*(uint32_t*)((S)->aCSR + 60)) /**< Previous Transmit Descriptor Address*/
420#define CSR_PXBC(S) ((S)->aCSR[62]) /**< Previous Transmit Byte Count */
421#define CSR_PXST(S) ((S)->aCSR[63]) /**< Previous Transmit Status */
422#define CSR_NXBA(S) (*(uint32_t*)((S)->aCSR + 64)) /**< Next Transmit Buffer Address */
423#define CSR_NXBC(S) ((S)->aCSR[66]) /**< Next Transmit Byte Count */
424#define CSR_NXST(S) ((S)->aCSR[67]) /**< Next Transmit Status */
425#define CSR_RCVRC(S) ((S)->aCSR[72]) /**< Receive Descriptor Ring Counter */
426#define CSR_XMTRC(S) ((S)->aCSR[74]) /**< Transmit Descriptor Ring Counter */
427#define CSR_RCVRL(S) ((S)->aCSR[76]) /**< Receive Descriptor Ring Length */
428#define CSR_XMTRL(S) ((S)->aCSR[78]) /**< Transmit Descriptor Ring Length */
429#define CSR_MISSC(S) ((S)->aCSR[112]) /**< Missed Frame Count */
430
431#define PHYSADDR(S,A) ((A) | (S)->GCUpperPhys)
432
433/* Version for the PCnet/FAST III 79C973 card */
434#define CSR_VERSION_LOW_79C973 0x5003 /* the lower two bits must be 11b for AMD */
435#define CSR_VERSION_LOW_79C970A 0x1003 /* the lower two bits must be 11b for AMD */
436#define CSR_VERSION_HIGH 0x0262
437
438/** @todo All structs: big endian? */
439
440struct INITBLK16
441{
442 uint16_t mode; /**< copied into csr15 */
443 uint16_t padr1; /**< MAC 0..15 */
444 uint16_t padr2; /**< MAC 16..32 */
445 uint16_t padr3; /**< MAC 33..47 */
446 uint16_t ladrf1; /**< logical address filter 0..15 */
447 uint16_t ladrf2; /**< logical address filter 16..31 */
448 uint16_t ladrf3; /**< logical address filter 32..47 */
449 uint16_t ladrf4; /**< logical address filter 48..63 */
450 uint32_t rdra:24; /**< address of receive descriptor ring */
451 uint32_t res1:5; /**< reserved */
452 uint32_t rlen:3; /**< number of receive descriptor ring entries */
453 uint32_t tdra:24; /**< address of transmit descriptor ring */
454 uint32_t res2:5; /**< reserved */
455 uint32_t tlen:3; /**< number of transmit descriptor ring entries */
456};
457AssertCompileSize(INITBLK16, 24);
458
459/** bird: I've changed the type for the bitfields. They should only be 16-bit all together.
460 * frank: I've changed the bitfiled types to uint32_t to prevent compiler warnings. */
461struct INITBLK32
462{
463 uint16_t mode; /**< copied into csr15 */
464 uint16_t res1:4; /**< reserved */
465 uint16_t rlen:4; /**< number of receive descriptor ring entries */
466 uint16_t res2:4; /**< reserved */
467 uint16_t tlen:4; /**< number of transmit descriptor ring entries */
468 uint16_t padr1; /**< MAC 0..15 */
469 uint16_t padr2; /**< MAC 16..31 */
470 uint16_t padr3; /**< MAC 32..47 */
471 uint16_t res3; /**< reserved */
472 uint16_t ladrf1; /**< logical address filter 0..15 */
473 uint16_t ladrf2; /**< logical address filter 16..31 */
474 uint16_t ladrf3; /**< logibal address filter 32..47 */
475 uint16_t ladrf4; /**< logical address filter 48..63 */
476 uint32_t rdra; /**< address of receive descriptor ring */
477 uint32_t tdra; /**< address of transmit descriptor ring */
478};
479AssertCompileSize(INITBLK32, 28);
480
481/** Transmit Message Descriptor */
482typedef struct TMD
483{
484 struct
485 {
486 uint32_t tbadr; /**< transmit buffer address */
487 } tmd0;
488 struct
489 {
490 uint32_t bcnt:12; /**< buffer byte count (two's complement) */
491 uint32_t ones:4; /**< must be 1111b */
492 uint32_t res:7; /**< reserved */
493 uint32_t bpe:1; /**< bus parity error */
494 uint32_t enp:1; /**< end of packet */
495 uint32_t stp:1; /**< start of packet */
496 uint32_t def:1; /**< deferred */
497 uint32_t one:1; /**< exactly one retry was needed to transmit a frame */
498 uint32_t ltint:1; /**< suppress interrupts after successful transmission */
499 uint32_t nofcs:1; /**< when set, the state of DXMTFCS is ignored and
500 transmitter FCS generation is activated. */
501 uint32_t err:1; /**< error occured */
502 uint32_t own:1; /**< 0=owned by guest driver, 1=owned by controller */
503 } tmd1;
504 struct
505 {
506 uint32_t trc:4; /**< transmit retry count */
507 uint32_t res:12; /**< reserved */
508 uint32_t tdr:10; /**< ??? */
509 uint32_t rtry:1; /**< retry error */
510 uint32_t lcar:1; /**< loss of carrier */
511 uint32_t lcol:1; /**< late collision */
512 uint32_t exdef:1; /**< excessive deferral */
513 uint32_t uflo:1; /**< underflow error */
514 uint32_t buff:1; /**< out of buffers (ENP not found) */
515 } tmd2;
516 struct
517 {
518 uint32_t res; /**< reserved for user defined space */
519 } tmd3;
520} TMD;
521AssertCompileSize(TMD, 16);
522
523/** Receive Message Descriptor */
524typedef struct RMD
525{
526 struct
527 {
528 uint32_t rbadr; /**< receive buffer address */
529 } rmd0;
530 struct
531 {
532 uint32_t bcnt:12; /**< buffer byte count (two's complement) */
533 uint32_t ones:4; /**< must be 1111b */
534 uint32_t res:4; /**< reserved */
535 uint32_t bam:1; /**< broadcast address match */
536 uint32_t lafm:1; /**< logical filter address match */
537 uint32_t pam:1; /**< physcial address match */
538 uint32_t bpe:1; /**< bus parity error */
539 uint32_t enp:1; /**< end of packet */
540 uint32_t stp:1; /**< start of packet */
541 uint32_t buff:1; /**< buffer error */
542 uint32_t crc:1; /**< crc error on incoming frame */
543 uint32_t oflo:1; /**< overflow error (lost all or part of incoming frame) */
544 uint32_t fram:1; /**< frame error */
545 uint32_t err:1; /**< error occured */
546 uint32_t own:1; /**< 0=owned by guest driver, 1=owned by controller */
547 } rmd1;
548 struct
549 {
550 uint32_t mcnt:12; /**< message byte count */
551 uint32_t zeros:4; /**< 0000b */
552 uint32_t rpc:8; /**< receive frame tag */
553 uint32_t rcc:8; /**< receive frame tag + reserved */
554 } rmd2;
555 struct
556 {
557 uint32_t res; /**< reserved for user defined space */
558 } rmd3;
559} RMD;
560AssertCompileSize(RMD, 16);
561
562
563#ifndef VBOX_DEVICE_STRUCT_TESTCASE
564/*******************************************************************************
565* Internal Functions *
566*******************************************************************************/
567#define PRINT_TMD(T) Log2(( \
568 "TMD0 : TBADR=%#010x\n" \
569 "TMD1 : OWN=%d, ERR=%d, FCS=%d, LTI=%d, " \
570 "ONE=%d, DEF=%d, STP=%d, ENP=%d,\n" \
571 " BPE=%d, BCNT=%d\n" \
572 "TMD2 : BUF=%d, UFL=%d, EXD=%d, LCO=%d, " \
573 "LCA=%d, RTR=%d,\n" \
574 " TDR=%d, TRC=%d\n", \
575 (T)->tmd0.tbadr, \
576 (T)->tmd1.own, (T)->tmd1.err, (T)->tmd1.nofcs, \
577 (T)->tmd1.ltint, (T)->tmd1.one, (T)->tmd1.def, \
578 (T)->tmd1.stp, (T)->tmd1.enp, (T)->tmd1.bpe, \
579 4096-(T)->tmd1.bcnt, \
580 (T)->tmd2.buff, (T)->tmd2.uflo, (T)->tmd2.exdef,\
581 (T)->tmd2.lcol, (T)->tmd2.lcar, (T)->tmd2.rtry, \
582 (T)->tmd2.tdr, (T)->tmd2.trc))
583
584#define PRINT_RMD(R) Log2(( \
585 "RMD0 : RBADR=%#010x\n" \
586 "RMD1 : OWN=%d, ERR=%d, FRAM=%d, OFLO=%d, " \
587 "CRC=%d, BUFF=%d, STP=%d, ENP=%d,\n " \
588 "BPE=%d, PAM=%d, LAFM=%d, BAM=%d, ONES=%d, BCNT=%d\n" \
589 "RMD2 : RCC=%d, RPC=%d, MCNT=%d, ZEROS=%d\n", \
590 (R)->rmd0.rbadr, \
591 (R)->rmd1.own, (R)->rmd1.err, (R)->rmd1.fram, \
592 (R)->rmd1.oflo, (R)->rmd1.crc, (R)->rmd1.buff, \
593 (R)->rmd1.stp, (R)->rmd1.enp, (R)->rmd1.bpe, \
594 (R)->rmd1.pam, (R)->rmd1.lafm, (R)->rmd1.bam, \
595 (R)->rmd1.ones, 4096-(R)->rmd1.bcnt, \
596 (R)->rmd2.rcc, (R)->rmd2.rpc, (R)->rmd2.mcnt, \
597 (R)->rmd2.zeros))
598
599#if defined(PCNET_QUEUE_SEND_PACKETS) && defined(IN_RING3)
600static int pcnetSyncTransmit(PCNetState *pData);
601#endif
602static void pcnetPollTimerStart(PCNetState *pData);
603
604/**
605 * Load transmit message descriptor
606 * Make sure we read the own flag first.
607 *
608 * @param pData adapter private data
609 * @param addr physical address of the descriptor
610 * @param fRetIfNotOwn return immediately after reading the own flag if we don't own the descriptor
611 * @return true if we own the descriptor, false otherwise
612 */
613DECLINLINE(bool) pcnetTmdLoad(PCNetState *pData, TMD *tmd, RTGCPHYS32 addr, bool fRetIfNotOwn)
614{
615 PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pData);
616 uint8_t ownbyte;
617
618 if (pData->fPrivIfEnabled)
619 {
620 /* RX/TX descriptors shared between host and guest => direct copy */
621 uint8_t *pv = (uint8_t*)pData->CTXSUFF(pSharedMMIO)
622 + (addr - pData->GCTDRA)
623 + pData->CTXSUFF(pSharedMMIO)->V.V1.offTxDescriptors;
624 if (!(pv[7] & 0x80) && fRetIfNotOwn)
625 return false;
626 memcpy(tmd, pv, 16);
627 return true;
628 }
629 else if (RT_UNLIKELY(BCR_SWSTYLE(pData) == 0))
630 {
631 uint16_t xda[4];
632
633 PDMDevHlpPhysRead(pDevIns, addr+3, &ownbyte, 1);
634 if (!(ownbyte & 0x80) && fRetIfNotOwn)
635 return false;
636 PDMDevHlpPhysRead(pDevIns, addr, (void*)&xda[0], sizeof(xda));
637 ((uint32_t *)tmd)[0] = (uint32_t)xda[0] | ((uint32_t)(xda[1] & 0x00ff) << 16);
638 ((uint32_t *)tmd)[1] = (uint32_t)xda[2] | ((uint32_t)(xda[1] & 0xff00) << 16);
639 ((uint32_t *)tmd)[2] = (uint32_t)xda[3] << 16;
640 ((uint32_t *)tmd)[3] = 0;
641 }
642 else if (RT_LIKELY(BCR_SWSTYLE(pData) != 3))
643 {
644 PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
645 if (!(ownbyte & 0x80) && fRetIfNotOwn)
646 return false;
647 PDMDevHlpPhysRead(pDevIns, addr, (void*)tmd, 16);
648 }
649 else
650 {
651 uint32_t xda[4];
652 PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
653 if (!(ownbyte & 0x80) && fRetIfNotOwn)
654 return false;
655 PDMDevHlpPhysRead(pDevIns, addr, (void*)&xda[0], sizeof(xda));
656 ((uint32_t *)tmd)[0] = xda[2];
657 ((uint32_t *)tmd)[1] = xda[1];
658 ((uint32_t *)tmd)[2] = xda[0];
659 ((uint32_t *)tmd)[3] = xda[3];
660 }
661 /* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */
662#ifdef DEBUG
663 if (tmd->tmd1.own == 1 && !(ownbyte & 0x80))
664 Log(("pcnetTmdLoad: own bit flipped while reading!!\n"));
665#endif
666 if (!(ownbyte & 0x80))
667 tmd->tmd1.own = 0;
668
669 return !!tmd->tmd1.own;
670}
671
672/**
673 * Store transmit message descriptor and hand it over to the host (the VM guest).
674 * Make sure that all data are transmitted before we clear the own flag.
675 */
676DECLINLINE(void) pcnetTmdStorePassHost(PCNetState *pData, TMD *tmd, RTGCPHYS32 addr)
677{
678 STAM_PROFILE_ADV_START(&pData->CTXSUFF(StatTmdStore), a);
679 PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pData);
680 if (pData->fPrivIfEnabled)
681 {
682 /* RX/TX descriptors shared between host and guest => direct copy */
683 uint8_t *pv = (uint8_t*)pData->CTXSUFF(pSharedMMIO)
684 + (addr - pData->GCTDRA)
685 + pData->CTXSUFF(pSharedMMIO)->V.V1.offTxDescriptors;
686 memcpy(pv, tmd, 16);
687 pv[7] &= ~0x80;
688 }
689 else if (RT_UNLIKELY(BCR_SWSTYLE(pData) == 0))
690 {
691 uint16_t xda[4];
692 xda[0] = ((uint32_t *)tmd)[0] & 0xffff;
693 xda[1] = ((((uint32_t *)tmd)[0] >> 16) & 0xff) | ((((uint32_t *)tmd)[1]>>16) & 0xff00);
694 xda[2] = ((uint32_t *)tmd)[1] & 0xffff;
695 xda[3] = ((uint32_t *)tmd)[2] >> 16;
696 xda[1] |= 0x8000;
697 PDMDevHlpPhysWrite(pDevIns, addr, (void*)&xda[0], sizeof(xda));
698 xda[1] &= ~0x8000;
699 PDMDevHlpPhysWrite(pDevIns, addr+3, (uint8_t*)xda + 3, 1);
700 }
701 else if (RT_LIKELY(BCR_SWSTYLE(pData) != 3))
702 {
703 ((uint32_t*)tmd)[1] |= 0x80000000;
704 PDMDevHlpPhysWrite(pDevIns, addr, (void*)tmd, 16);
705 ((uint32_t*)tmd)[1] &= ~0x80000000;
706 PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)tmd + 7, 1);
707 }
708 else
709 {
710 uint32_t xda[4];
711 xda[0] = ((uint32_t *)tmd)[2];
712 xda[1] = ((uint32_t *)tmd)[1];
713 xda[2] = ((uint32_t *)tmd)[0];
714 xda[3] = ((uint32_t *)tmd)[3];
715 xda[1] |= 0x80000000;
716 PDMDevHlpPhysWrite(pDevIns, addr, (void*)&xda[0], sizeof(xda));
717 xda[1] &= ~0x80000000;
718 PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)xda + 7, 1);
719 }
720 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatTmdStore), a);
721}
722
723/**
724 * Load receive message descriptor
725 * Make sure we read the own flag first.
726 *
727 * @param pData adapter private data
728 * @param addr physical address of the descriptor
729 * @param fRetIfNotOwn return immediately after reading the own flag if we don't own the descriptor
730 * @return true if we own the descriptor, false otherwise
731 */
732DECLINLINE(int) pcnetRmdLoad(PCNetState *pData, RMD *rmd, RTGCPHYS32 addr, bool fRetIfNotOwn)
733{
734 PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pData);
735 uint8_t ownbyte;
736
737 if (pData->fPrivIfEnabled)
738 {
739 /* RX/TX descriptors shared between host and guest => direct copy */
740 uint8_t *pb = (uint8_t*)pData->CTXSUFF(pSharedMMIO)
741 + (addr - pData->GCRDRA)
742 + pData->CTXSUFF(pSharedMMIO)->V.V1.offRxDescriptors;
743 if (!(pb[7] & 0x80) && fRetIfNotOwn)
744 return false;
745 memcpy(rmd, pb, 16);
746 return true;
747 }
748 else if (RT_UNLIKELY(BCR_SWSTYLE(pData) == 0))
749 {
750 uint16_t rda[4];
751 PDMDevHlpPhysRead(pDevIns, addr+3, &ownbyte, 1);
752 if (!(ownbyte & 0x80) && fRetIfNotOwn)
753 return false;
754 PDMDevHlpPhysRead(pDevIns, addr, (void*)&rda[0], sizeof(rda));
755 ((uint32_t *)rmd)[0] = (uint32_t)rda[0] | ((rda[1] & 0x00ff) << 16);
756 ((uint32_t *)rmd)[1] = (uint32_t)rda[2] | ((rda[1] & 0xff00) << 16);
757 ((uint32_t *)rmd)[2] = (uint32_t)rda[3];
758 ((uint32_t *)rmd)[3] = 0;
759 }
760 else if (RT_LIKELY(BCR_SWSTYLE(pData) != 3))
761 {
762 PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
763 if (!(ownbyte & 0x80) && fRetIfNotOwn)
764 return false;
765 PDMDevHlpPhysRead(pDevIns, addr, (void*)rmd, 16);
766 }
767 else
768 {
769 uint32_t rda[4];
770 PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
771 if (!(ownbyte & 0x80) && fRetIfNotOwn)
772 return false;
773 PDMDevHlpPhysRead(pDevIns, addr, (void*)&rda[0], sizeof(rda));
774 ((uint32_t *)rmd)[0] = rda[2];
775 ((uint32_t *)rmd)[1] = rda[1];
776 ((uint32_t *)rmd)[2] = rda[0];
777 ((uint32_t *)rmd)[3] = rda[3];
778 }
779 /* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */
780#ifdef DEBUG
781 if (rmd->rmd1.own == 1 && !(ownbyte & 0x80))
782 Log(("pcnetRmdLoad: own bit flipped while reading!!\n"));
783#endif
784 if (!(ownbyte & 0x80))
785 rmd->rmd1.own = 0;
786
787 return !!rmd->rmd1.own;
788}
789
790/**
791 * Store receive message descriptor and hand it over to the host (the VM guest).
792 * Make sure that all data are transmitted before we clear the own flag.
793 */
794DECLINLINE(void) pcnetRmdStorePassHost(PCNetState *pData, RMD *rmd, RTGCPHYS32 addr)
795{
796 PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pData);
797 if (pData->fPrivIfEnabled)
798 {
799 /* RX/TX descriptors shared between host and guest => direct copy */
800 uint8_t *pv = (uint8_t*)pData->CTXSUFF(pSharedMMIO)
801 + (addr - pData->GCRDRA)
802 + pData->CTXSUFF(pSharedMMIO)->V.V1.offRxDescriptors;
803 memcpy(pv, rmd, 16);
804 pv[7] &= ~0x80;
805 }
806 else if (RT_UNLIKELY(BCR_SWSTYLE(pData) == 0))
807 {
808 uint16_t rda[4];
809 rda[0] = ((uint32_t *)rmd)[0] & 0xffff;
810 rda[1] = ((((uint32_t *)rmd)[0]>>16) & 0xff) | ((((uint32_t *)rmd)[1]>>16) & 0xff00);
811 rda[2] = ((uint32_t *)rmd)[1] & 0xffff;
812 rda[3] = ((uint32_t *)rmd)[2] & 0xffff;
813 rda[1] |= 0x8000;
814 PDMDevHlpPhysWrite(pDevIns, addr, (void*)&rda[0], sizeof(rda));
815 rda[1] &= ~0x8000;
816 PDMDevHlpPhysWrite(pDevIns, addr+3, (uint8_t*)rda + 3, 1);
817 }
818 else if (RT_LIKELY(BCR_SWSTYLE(pData) != 3))
819 {
820 ((uint32_t*)rmd)[1] |= 0x80000000;
821 PDMDevHlpPhysWrite(pDevIns, addr, (void*)rmd, 16);
822 ((uint32_t*)rmd)[1] &= ~0x80000000;
823 PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)rmd + 7, 1);
824 }
825 else
826 {
827 uint32_t rda[4];
828 rda[0] = ((uint32_t *)rmd)[2];
829 rda[1] = ((uint32_t *)rmd)[1];
830 rda[2] = ((uint32_t *)rmd)[0];
831 rda[3] = ((uint32_t *)rmd)[3];
832 rda[1] |= 0x80000000;
833 PDMDevHlpPhysWrite(pDevIns, addr, (void*)&rda[0], sizeof(rda));
834 rda[1] &= ~0x80000000;
835 PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)rda + 7, 1);
836 }
837}
838
839/** Checks if it's a bad (as in invalid) RMD.*/
840#define IS_RMD_BAD(rmd) ((rmd).rmd1.ones != 15 || (rmd).rmd2.zeros != 0)
841
842/** The network card is the owner of the RDTE/TDTE, actually it is this driver */
843#define CARD_IS_OWNER(desc) (((desc) & 0x8000))
844
845/** The host is the owner of the RDTE/TDTE -- actually the VM guest. */
846#define HOST_IS_OWNER(desc) (!((desc) & 0x8000))
847
848#ifndef ETHER_IS_MULTICAST /* Net/Open BSD macro it seems */
849#define ETHER_IS_MULTICAST(a) ((*(uint8_t *)(a)) & 1)
850#endif
851
852#define ETHER_ADDR_LEN ETH_ALEN
853#define ETH_ALEN 6
854#pragma pack(1)
855struct ether_header
856{
857 uint8_t ether_dhost[ETH_ALEN]; /**< destination ethernet address */
858 uint8_t ether_shost[ETH_ALEN]; /**< source ethernet address */
859 uint16_t ether_type; /**< packet type ID field */
860};
861#pragma pack()
862
863#define PRINT_PKTHDR(BUF) do { \
864 struct ether_header *hdr = (struct ether_header *)(BUF); \
865 Log(("#%d packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, " \
866 "shost=%02x:%02x:%02x:%02x:%02x:%02x, " \
867 "type=%#06x (bcast=%d)\n", PCNET_INST_NR, \
868 hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], \
869 hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], \
870 hdr->ether_shost[0],hdr->ether_shost[1],hdr->ether_shost[2], \
871 hdr->ether_shost[3],hdr->ether_shost[4],hdr->ether_shost[5], \
872 htons(hdr->ether_type), \
873 !!ETHER_IS_MULTICAST(hdr->ether_dhost))); \
874} while (0)
875
876
877#ifdef IN_RING3
878
879/**
880 * Initialize the shared memory for the private guest interface.
881 *
882 * @note Changing this layout will break SSM for guests using the private guest interface!
883 */
884static void pcnetInitSharedMemory(PCNetState *pData)
885{
886 /* Clear the entire block for pcnetReset usage. */
887 memset(pData->pSharedMMIOHC, 0, PCNET_GUEST_SHARED_MEMORY_SIZE);
888
889 pData->pSharedMMIOHC->u32Version = PCNET_GUEST_INTERFACE_VERSION;
890 uint32_t off = 2048; /* Leave some space for more fields within the header */
891
892 /*
893 * The Descriptor arrays.
894 */
895 pData->pSharedMMIOHC->V.V1.offTxDescriptors = off;
896 off = RT_ALIGN(off + PCNET_GUEST_TX_DESCRIPTOR_SIZE * PCNET_GUEST_MAX_TX_DESCRIPTORS, 32);
897
898 pData->pSharedMMIOHC->V.V1.offRxDescriptors = off;
899 off = RT_ALIGN(off + PCNET_GUEST_RX_DESCRIPTOR_SIZE * PCNET_GUEST_MAX_RX_DESCRIPTORS, 32);
900
901 /* Make sure all the descriptors are mapped into HMA space (and later ring-0). The 8192
902 bytes limit is hardcoded in the PDMDevHlpMMHyperMapMMIO2 call down in pcnetConstruct. */
903 AssertRelease(off <= 8192);
904
905 /*
906 * The buffer arrays.
907 */
908#if 0
909 /* Don't allocate TX buffers since Windows guests cannot use it */
910 pData->pSharedMMIOHC->V.V1.offTxBuffers = off;
911 off = RT_ALIGN(off + PCNET_GUEST_NIC_BUFFER_SIZE * PCNET_GUEST_MAX_TX_DESCRIPTORS, 32);
912#endif
913
914 pData->pSharedMMIOHC->V.V1.offRxBuffers = off;
915 pData->pSharedMMIOHC->fFlags = PCNET_GUEST_FLAGS_ADMIT_HOST;
916 off = RT_ALIGN(off + PCNET_GUEST_NIC_BUFFER_SIZE * PCNET_GUEST_MAX_RX_DESCRIPTORS, 32);
917 AssertRelease(off <= PCNET_GUEST_SHARED_MEMORY_SIZE);
918
919 /* Update the header with the final size. */
920 pData->pSharedMMIOHC->cbUsed = off;
921}
922
923#define MULTICAST_FILTER_LEN 8
924
925DECLINLINE(uint32_t) lnc_mchash(const uint8_t *ether_addr)
926{
927#define LNC_POLYNOMIAL 0xEDB88320UL
928 uint32_t crc = 0xFFFFFFFF;
929 int idx, bit;
930 uint8_t data;
931
932 for (idx = 0; idx < ETHER_ADDR_LEN; idx++)
933 {
934 for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++)
935 {
936 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0);
937 data >>= 1;
938 }
939 }
940 return crc;
941#undef LNC_POLYNOMIAL
942}
943
944#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
945
946/* generated using the AUTODIN II polynomial
947 * x^32 + x^26 + x^23 + x^22 + x^16 +
948 * x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
949 */
950static const uint32_t crctab[256] =
951{
952 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
953 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
954 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
955 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
956 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
957 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
958 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
959 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
960 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
961 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
962 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
963 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
964 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
965 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
966 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
967 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
968 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
969 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
970 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
971 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
972 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
973 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
974 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
975 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
976 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
977 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
978 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
979 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
980 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
981 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
982 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
983 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
984 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
985 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
986 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
987 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
988 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
989 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
990 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
991 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
992 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
993 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
994 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
995 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
996 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
997 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
998 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
999 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
1000 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
1001 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
1002 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
1003 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
1004 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
1005 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
1006 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
1007 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
1008 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
1009 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
1010 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
1011 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
1012 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
1013 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
1014 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
1015 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
1016};
1017
1018DECLINLINE(int) padr_match(PCNetState *pData, const uint8_t *buf, size_t size)
1019{
1020 struct ether_header *hdr = (struct ether_header *)buf;
1021 int result;
1022#if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(PCNET_DEBUG_MATCH)
1023 result = !CSR_DRCVPA(pData) && !memcmp(hdr->ether_dhost, pData->aCSR + 12, 6);
1024#else
1025 uint8_t padr[6];
1026 padr[0] = pData->aCSR[12] & 0xff;
1027 padr[1] = pData->aCSR[12] >> 8;
1028 padr[2] = pData->aCSR[13] & 0xff;
1029 padr[3] = pData->aCSR[13] >> 8;
1030 padr[4] = pData->aCSR[14] & 0xff;
1031 padr[5] = pData->aCSR[14] >> 8;
1032 result = !CSR_DRCVPA(pData) && !memcmp(hdr->ether_dhost, padr, 6);
1033#endif
1034
1035#ifdef PCNET_DEBUG_MATCH
1036 Log(("#%d packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, "
1037 "padr=%02x:%02x:%02x:%02x:%02x:%02x => %d\n", PCNET_INST_NR,
1038 hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2],
1039 hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5],
1040 padr[0],padr[1],padr[2],padr[3],padr[4],padr[5], result));
1041#endif
1042 return result;
1043}
1044
1045DECLINLINE(int) padr_bcast(PCNetState *pData, const uint8_t *buf, size_t size)
1046{
1047 static uint8_t aBCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1048 struct ether_header *hdr = (struct ether_header *)buf;
1049 int result = !CSR_DRCVBC(pData) && !memcmp(hdr->ether_dhost, aBCAST, 6);
1050#ifdef PCNET_DEBUG_MATCH
1051 Log(("#%d padr_bcast result=%d\n", PCNET_INST_NR, result));
1052#endif
1053 return result;
1054}
1055
1056static int ladr_match(PCNetState *pData, const uint8_t *buf, size_t size)
1057{
1058 struct ether_header *hdr = (struct ether_header *)buf;
1059 if (RT_UNLIKELY(hdr->ether_dhost[0] & 0x01) && ((uint64_t *)&pData->aCSR[8])[0] != 0LL)
1060 {
1061 int index;
1062#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
1063 index = lnc_mchash(hdr->ether_dhost) >> 26;
1064 return ((uint8_t*)(pData->aCSR + 8))[index >> 3] & (1 << (index & 7));
1065#else
1066 uint8_t ladr[8];
1067 ladr[0] = pData->aCSR[8] & 0xff;
1068 ladr[1] = pData->aCSR[8] >> 8;
1069 ladr[2] = pData->aCSR[9] & 0xff;
1070 ladr[3] = pData->aCSR[9] >> 8;
1071 ladr[4] = pData->aCSR[10] & 0xff;
1072 ladr[5] = pData->aCSR[10] >> 8;
1073 ladr[6] = pData->aCSR[11] & 0xff;
1074 ladr[7] = pData->aCSR[11] >> 8;
1075 index = lnc_mchash(hdr->ether_dhost) >> 26;
1076 return (ladr[index >> 3] & (1 << (index & 7)));
1077#endif
1078 }
1079 return 0;
1080}
1081
1082#endif /* IN_RING3 */
1083
1084/**
1085 * Get the receive descriptor ring address with a given index.
1086 */
1087DECLINLINE(RTGCPHYS32) pcnetRdraAddr(PCNetState *pData, int idx)
1088{
1089 return pData->GCRDRA + ((CSR_RCVRL(pData) - idx) << pData->iLog2DescSize);
1090}
1091
1092/**
1093 * Get the transmit descriptor ring address with a given index.
1094 */
1095DECLINLINE(RTGCPHYS32) pcnetTdraAddr(PCNetState *pData, int idx)
1096{
1097 return pData->GCTDRA + ((CSR_XMTRL(pData) - idx) << pData->iLog2DescSize);
1098}
1099
1100__BEGIN_DECLS
1101PDMBOTHCBDECL(int) pcnetIOPortRead(PPDMDEVINS pDevIns, void *pvUser,
1102 RTIOPORT Port, uint32_t *pu32, unsigned cb);
1103PDMBOTHCBDECL(int) pcnetIOPortWrite(PPDMDEVINS pDevIns, void *pvUser,
1104 RTIOPORT Port, uint32_t u32, unsigned cb);
1105PDMBOTHCBDECL(int) pcnetIOPortAPromWrite(PPDMDEVINS pDevIns, void *pvUser,
1106 RTIOPORT Port, uint32_t u32, unsigned cb);
1107PDMBOTHCBDECL(int) pcnetIOPortAPromRead(PPDMDEVINS pDevIns, void *pvUser,
1108 RTIOPORT Port, uint32_t *pu32, unsigned cb);
1109PDMBOTHCBDECL(int) pcnetMMIORead(PPDMDEVINS pDevIns, void *pvUser,
1110 RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1111PDMBOTHCBDECL(int) pcnetMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,
1112 RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1113#ifndef IN_RING3
1114DECLEXPORT(int) pcnetHandleRingWrite(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
1115 RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
1116#endif
1117__END_DECLS
1118
1119#undef htonl
1120#define htonl(x) ASMByteSwapU32(x)
1121#undef htons
1122#define htons(x) ( (((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8) )
1123
1124static void pcnetPollRxTx(PCNetState *pData);
1125static void pcnetPollTimer(PCNetState *pData);
1126static void pcnetUpdateIrq(PCNetState *pData);
1127static uint32_t pcnetBCRReadU16(PCNetState *pData, uint32_t u32RAP);
1128static int pcnetBCRWriteU16(PCNetState *pData, uint32_t u32RAP, uint32_t val);
1129
1130
1131#ifdef PCNET_NO_POLLING
1132# ifndef IN_RING3
1133
1134/**
1135 * #PF Virtual Handler callback for Guest write access to the ring descriptor page(pData)
1136 *
1137 * @return VBox status code (appropriate for trap handling and GC return).
1138 * @param pVM VM Handle.
1139 * @param uErrorCode CPU Error code.
1140 * @param pRegFrame Trap register frame.
1141 * @param pvFault The fault address (cr2).
1142 * @param GCPhysFault The GC physical address corresponding to pvFault.
1143 * @param pvUser User argument.
1144 */
1145DECLEXPORT(int) pcnetHandleRingWrite(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
1146 RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1147{
1148 PCNetState *pData = (PCNetState *)pvUser;
1149
1150 Log(("#%d pcnetHandleRingWriteGC: write to %#010x\n", PCNET_INST_NR, GCPhysFault));
1151
1152 uint32_t cb;
1153 int rc = CTXALLSUFF(pData->pfnEMInterpretInstruction)(pVM, pRegFrame, pvFault, &cb);
1154 if (VBOX_SUCCESS(rc) && cb)
1155 {
1156 if ( (GCPhysFault >= pData->GCTDRA && GCPhysFault + cb < pcnetTdraAddr(pData, 0))
1157#ifdef PCNET_MONITOR_RECEIVE_RING
1158 || (GCPhysFault >= pData->GCRDRA && GCPhysFault + cb < pcnetRdraAddr(pData, 0))
1159#endif
1160 )
1161 {
1162 uint32_t offsetTDRA = (GCPhysFault - pData->GCTDRA);
1163
1164 int rc = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
1165 if (VBOX_SUCCESS(rc))
1166 {
1167 STAM_COUNTER_INC(&CTXALLSUFF(pData->StatRingWrite)); ;
1168
1169 /* Check if we can do something now */
1170 pcnetPollRxTx(pData);
1171 pcnetUpdateIrq(pData);
1172
1173 PDMCritSectLeave(&pData->CritSect);
1174 return VINF_SUCCESS;
1175 }
1176 }
1177 else
1178 {
1179 STAM_COUNTER_INC(&CTXALLSUFF(pData->StatRingWriteOutside)); ;
1180 return VINF_SUCCESS; /* outside of the ring range */
1181 }
1182 }
1183 STAM_COUNTER_INC(&CTXALLSUFF(pData->StatRingWriteFailed)); ;
1184 return VINF_IOM_HC_MMIO_WRITE; /* handle in ring3 */
1185}
1186
1187# else /* IN_RING3 */
1188
1189/**
1190 * #PF Handler callback for physical access handler ranges (MMIO among others) in HC.
1191 *
1192 * The handler can not raise any faults, it's mainly for monitoring write access
1193 * to certain pages.
1194 *
1195 * @returns VINF_SUCCESS if the handler have carried out the operation.
1196 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1197 * @param pVM VM Handle.
1198 * @param GCPhys The physical address the guest is writing to.
1199 * @param pvPhys The HC mapping of that address.
1200 * @param pvBuf What the guest is reading/writing.
1201 * @param cbBuf How much it's reading/writing.
1202 * @param enmAccessType The access type.
1203 * @param pvUser User argument.
1204 */
1205static DECLCALLBACK(int) pcnetHandleRingWrite(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf,
1206 size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1207{
1208 PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1209 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
1210
1211 Log(("#%d pcnetHandleRingWrite: write to %#010x\n", PCNET_INST_NR, GCPhys));
1212#ifdef VBOX_WITH_STATISTICS
1213 STAM_COUNTER_INC(&CTXSUFF(pData->StatRingWrite));
1214 if (GCPhys >= pData->GCRDRA && GCPhys < pcnetRdraAddr(pData, 0))
1215 STAM_COUNTER_INC(&pData->StatRCVRingWrite);
1216 else if (GCPhys >= pData->GCTDRA && GCPhys < pcnetTdraAddr(pData, 0))
1217 STAM_COUNTER_INC(&pData->StatTXRingWrite);
1218#endif
1219 /* Perform the actual write */
1220 memcpy((char *)pvPhys, pvBuf, cbBuf);
1221
1222 /* Writes done by our code don't require polling of course */
1223 if (PDMCritSectIsOwner(&pData->CritSect) == false)
1224 {
1225 if ( (GCPhys >= pData->GCTDRA && GCPhys + cbBuf < pcnetTdraAddr(pData, 0))
1226#ifdef PCNET_MONITOR_RECEIVE_RING
1227 || (GCPhys >= pData->GCRDRA && GCPhys + cbBuf < pcnetRdraAddr(pData, 0))
1228#endif
1229 )
1230 {
1231 int rc = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
1232 AssertReleaseRC(rc);
1233 /* Check if we can do something now */
1234 pcnetPollRxTx(pData);
1235 pcnetUpdateIrq(pData);
1236 PDMCritSectLeave(&pData->CritSect);
1237 }
1238 }
1239 return VINF_SUCCESS;
1240}
1241# endif /* !IN_RING3 */
1242#endif /* PCNET_NO_POLLING */
1243
1244static void pcnetSoftReset(PCNetState *pData)
1245{
1246 Log(("#%d pcnetSoftReset:\n", PCNET_INST_NR));
1247
1248 pData->u32Lnkst = 0x40;
1249 pData->GCRDRA = 0;
1250 pData->GCTDRA = 0;
1251 pData->u32RAP = 0;
1252
1253 pData->aBCR[BCR_BSBC] &= ~0x0080;
1254
1255 pData->aCSR[0] = 0x0004;
1256 pData->aCSR[3] = 0x0000;
1257 pData->aCSR[4] = 0x0115;
1258 pData->aCSR[5] = 0x0000;
1259 pData->aCSR[6] = 0x0000;
1260 pData->aCSR[8] = 0;
1261 pData->aCSR[9] = 0;
1262 pData->aCSR[10] = 0;
1263 pData->aCSR[11] = 0;
1264 pData->aCSR[12] = RT_LE2H_U16(((uint16_t *)&pData->aPROM[0])[0]);
1265 pData->aCSR[13] = RT_LE2H_U16(((uint16_t *)&pData->aPROM[0])[1]);
1266 pData->aCSR[14] = RT_LE2H_U16(((uint16_t *)&pData->aPROM[0])[2]);
1267 pData->aCSR[15] &= 0x21c4;
1268 CSR_RCVRC(pData) = 1;
1269 CSR_XMTRC(pData) = 1;
1270 CSR_RCVRL(pData) = 1;
1271 CSR_XMTRL(pData) = 1;
1272 pData->aCSR[80] = 0x1410;
1273 pData->aCSR[88] = pData->fAm79C973 ? CSR_VERSION_LOW_79C973 : CSR_VERSION_LOW_79C970A;
1274 pData->aCSR[89] = CSR_VERSION_HIGH;
1275 pData->aCSR[94] = 0x0000;
1276 pData->aCSR[100] = 0x0200;
1277 pData->aCSR[103] = 0x0105;
1278 pData->aCSR[103] = 0x0105;
1279 CSR_MISSC(pData) = 0;
1280 pData->aCSR[114] = 0x0000;
1281 pData->aCSR[122] = 0x0000;
1282 pData->aCSR[124] = 0x0000;
1283}
1284
1285/**
1286 * Check if we have to send an interrupt to the guest. An interrupt can occur on
1287 * - csr0 (written quite often)
1288 * - csr4 (only written by pcnetSoftReset(), pcnetStop() or by the guest driver)
1289 * - csr5 (only written by pcnetSoftReset(), pcnetStop or by the driver guest)
1290 */
1291static void pcnetUpdateIrq(PCNetState *pData)
1292{
1293 register int iISR = 0;
1294 register uint16_t csr0 = pData->aCSR[0];
1295
1296 csr0 &= ~0x0080; /* clear INTR */
1297
1298 STAM_PROFILE_ADV_START(&pData->StatInterrupt, a);
1299
1300 /* Linux guests set csr4=0x0915
1301 * W2k guests set csr3=0x4940 (disable BABL, MERR, IDON, DXSUFLO */
1302
1303#if 1
1304 if ( ( (csr0 & ~pData->aCSR[3]) & 0x5f00)
1305 || (((pData->aCSR[4]>>1) & ~pData->aCSR[4]) & 0x0115)
1306 || (((pData->aCSR[5]>>1) & pData->aCSR[5]) & 0x0048))
1307#else
1308 if ( ( !(pData->aCSR[3] & 0x4000) && !!(csr0 & 0x4000)) /* BABL */
1309 ||( !(pData->aCSR[3] & 0x1000) && !!(csr0 & 0x1000)) /* MISS */
1310 ||( !(pData->aCSR[3] & 0x0100) && !!(csr0 & 0x0100)) /* IDON */
1311 ||( !(pData->aCSR[3] & 0x0200) && !!(csr0 & 0x0200)) /* TINT */
1312 ||( !(pData->aCSR[3] & 0x0400) && !!(csr0 & 0x0400)) /* RINT */
1313 ||( !(pData->aCSR[3] & 0x0800) && !!(csr0 & 0x0800)) /* MERR */
1314 ||( !(pData->aCSR[4] & 0x0001) && !!(pData->aCSR[4] & 0x0002)) /* JAB */
1315 ||( !(pData->aCSR[4] & 0x0004) && !!(pData->aCSR[4] & 0x0008)) /* TXSTRT */
1316 ||( !(pData->aCSR[4] & 0x0010) && !!(pData->aCSR[4] & 0x0020)) /* RCVO */
1317 ||( !(pData->aCSR[4] & 0x0100) && !!(pData->aCSR[4] & 0x0200)) /* MFCO */
1318 ||(!!(pData->aCSR[5] & 0x0040) && !!(pData->aCSR[5] & 0x0080)) /* EXDINT */
1319 ||(!!(pData->aCSR[5] & 0x0008) && !!(pData->aCSR[5] & 0x0010)) /* MPINT */)
1320#endif
1321 {
1322 iISR = !!(csr0 & 0x0040); /* CSR_INEA */
1323 csr0 |= 0x0080; /* set INTR */
1324 }
1325
1326#ifdef VBOX
1327 if (pData->aCSR[4] & 0x0080) /* UINTCMD */
1328 {
1329 pData->aCSR[4] &= ~0x0080; /* clear UINTCMD */
1330 pData->aCSR[4] |= 0x0040; /* set UINT */
1331 Log(("#%d user int\n", PCNET_INST_NR));
1332 }
1333 if (pData->aCSR[4] & csr0 & 0x0040 /* CSR_INEA */)
1334 {
1335 csr0 |= 0x0080; /* set INTR */
1336 iISR = 1;
1337 }
1338#else /* !VBOX */
1339 if (!!(pData->aCSR[4] & 0x0080) && CSR_INEA(pData)) /* UINTCMD */
1340 {
1341 pData->aCSR[4] &= ~0x0080;
1342 pData->aCSR[4] |= 0x0040; /* set UINT */
1343 csr0 |= 0x0080; /* set INTR */
1344 iISR = 1;
1345 Log(("#%d user int\n", PCNET_INST_NR));
1346 }
1347#endif /* !VBOX */
1348
1349#if 1
1350 if (((pData->aCSR[5]>>1) & pData->aCSR[5]) & 0x0500)
1351#else
1352 if ( (!!(pData->aCSR[5] & 0x0400) && !!(pData->aCSR[5] & 0x0800)) /* SINT */
1353 ||(!!(pData->aCSR[5] & 0x0100) && !!(pData->aCSR[5] & 0x0200)) /* SLPINT */)
1354#endif
1355 {
1356 iISR = 1;
1357 csr0 |= 0x0080; /* INTR */
1358 }
1359
1360 if ((pData->aCSR[7] & 0x0C00) == 0x0C00) /* STINT + STINTE */
1361 iISR = 1;
1362
1363 pData->aCSR[0] = csr0;
1364
1365 Log2(("#%d set irq iISR=%d\n", PCNET_INST_NR, iISR));
1366
1367 /* normal path is to _not_ change the IRQ status */
1368 if (RT_UNLIKELY(iISR != pData->iISR))
1369 {
1370 Log(("#%d INTA=%d\n", PCNET_INST_NR, iISR));
1371 PDMDevHlpPCISetIrqNoWait(PCNETSTATE_2_DEVINS(pData), 0, iISR);
1372 pData->iISR = iISR;
1373 }
1374 STAM_PROFILE_ADV_STOP(&pData->StatInterrupt, a);
1375}
1376
1377/**
1378 * Enable/disable the private guest interface.
1379 */
1380static void pcnetEnablePrivateIf(PCNetState *pData)
1381{
1382 bool fPrivIfEnabled = pData->pSharedMMIOHC
1383 && !!(pData->CTXSUFF(pSharedMMIO)->fFlags & PCNET_GUEST_FLAGS_ADMIT_GUEST);
1384 if (fPrivIfEnabled != pData->fPrivIfEnabled)
1385 {
1386 pData->fPrivIfEnabled = fPrivIfEnabled;
1387 LogRel(("PCNet#%d: %s private interface\n", PCNET_INST_NR, fPrivIfEnabled ? "Enabling" : "Disabling"));
1388 }
1389}
1390
1391#ifdef IN_RING3
1392#ifdef PCNET_NO_POLLING
1393static void pcnetUpdateRingHandlers(PCNetState *pData)
1394{
1395 PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pData);
1396 int rc;
1397
1398 Log(("pcnetUpdateRingHandlers TD %VGp size %#x -> %VGp size %#x\n", pData->TDRAPhysOld, pData->cbTDRAOld, pData->GCTDRA, pcnetTdraAddr(pData, 0)));
1399 Log(("pcnetUpdateRingHandlers RX %VGp size %#x -> %VGp size %#x\n", pData->RDRAPhysOld, pData->cbRDRAOld, pData->GCRDRA, pcnetRdraAddr(pData, 0)));
1400
1401 /** @todo unregister order not correct! */
1402
1403#ifdef PCNET_MONITOR_RECEIVE_RING
1404 if (pData->GCRDRA != pData->RDRAPhysOld || CSR_RCVRL(pData) != pData->cbRDRAOld)
1405 {
1406 if (pData->RDRAPhysOld != 0)
1407 PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns),
1408 pData->RDRAPhysOld & ~PAGE_OFFSET_MASK);
1409
1410 rc = PGMR3HandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
1411 PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1412 pData->GCRDRA & ~PAGE_OFFSET_MASK,
1413 RT_ALIGN(pcnetRdraAddr(pData, 0), PAGE_SIZE) - 1,
1414 pcnetHandleRingWrite, pDevIns,
1415 g_DevicePCNet.szR0Mod, "pcnetHandleRingWrite",
1416 pData->pDevInsHC->pvInstanceDataHC,
1417 g_DevicePCNet.szGCMod, "pcnetHandleRingWrite",
1418 pData->pDevInsHC->pvInstanceDataGC,
1419 "PCNet receive ring write access handler");
1420 AssertRC(rc);
1421
1422 pData->RDRAPhysOld = pData->GCRDRA;
1423 pData->cbRDRAOld = pcnetRdraAddr(pData, 0);
1424 }
1425#endif /* PCNET_MONITOR_RECEIVE_RING */
1426
1427#ifdef PCNET_MONITOR_RECEIVE_RING
1428 /* 3 possibilities:
1429 * 1) TDRA on different physical page as RDRA
1430 * 2) TDRA completely on same physical page as RDRA
1431 * 3) TDRA & RDRA overlap partly with different physical pages
1432 */
1433 RTGCPHYS32 RDRAPageStart = pData->GCRDRA & ~PAGE_OFFSET_MASK;
1434 RTGCPHYS32 RDRAPageEnd = (pcnetRdraAddr(pData, 0) - 1) & ~PAGE_OFFSET_MASK;
1435 RTGCPHYS32 TDRAPageStart = pData->GCTDRA & ~PAGE_OFFSET_MASK;
1436 RTGCPHYS32 TDRAPageEnd = (pcnetTdraAddr(pData, 0) - 1) & ~PAGE_OFFSET_MASK;
1437
1438 if ( RDRAPageStart > TDRAPageEnd
1439 || TDRAPageStart > RDRAPageEnd)
1440 {
1441#endif /* PCNET_MONITOR_RECEIVE_RING */
1442 /* 1) */
1443 if (pData->GCTDRA != pData->TDRAPhysOld || CSR_XMTRL(pData) != pData->cbTDRAOld)
1444 {
1445 if (pData->TDRAPhysOld != 0)
1446 PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns),
1447 pData->TDRAPhysOld & ~PAGE_OFFSET_MASK);
1448
1449 rc = PGMR3HandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
1450 PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1451 pData->GCTDRA & ~PAGE_OFFSET_MASK,
1452 RT_ALIGN(pcnetTdraAddr(pData, 0), PAGE_SIZE) - 1,
1453 pcnetHandleRingWrite, pDevIns,
1454 g_DevicePCNet.szR0Mod, "pcnetHandleRingWrite",
1455 pData->pDevInsHC->pvInstanceDataHC,
1456 g_DevicePCNet.szGCMod, "pcnetHandleRingWrite",
1457 pData->pDevInsHC->pvInstanceDataGC,
1458 "PCNet transmit ring write access handler");
1459 AssertRC(rc);
1460
1461 pData->TDRAPhysOld = pData->GCTDRA;
1462 pData->cbTDRAOld = pcnetTdraAddr(pData, 0);
1463 }
1464#ifdef PCNET_MONITOR_RECEIVE_RING
1465 }
1466 else
1467 if ( RDRAPageStart != TDRAPageStart
1468 && ( TDRAPageStart == RDRAPageEnd
1469 || TDRAPageEnd == RDRAPageStart
1470 )
1471 )
1472 {
1473 /* 3) */
1474 AssertFailed();
1475 }
1476 /* else 2) */
1477#endif
1478}
1479#endif /* PCNET_NO_POLLING */
1480
1481static void pcnetInit(PCNetState *pData)
1482{
1483 PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pData);
1484 Log(("#%d pcnetInit: init_addr=%#010x\n", PCNET_INST_NR, PHYSADDR(pData, CSR_IADR(pData))));
1485
1486 /** @todo Documentation says that RCVRL and XMTRL are stored as two's complement!
1487 * Software is allowed to write these registers directly. */
1488#define PCNET_INIT() do { \
1489 PDMDevHlpPhysRead(pDevIns, PHYSADDR(pData, CSR_IADR(pData)), \
1490 (uint8_t *)&initblk, sizeof(initblk)); \
1491 pData->aCSR[15] = RT_LE2H_U16(initblk.mode); \
1492 CSR_RCVRL(pData) = (initblk.rlen < 9) ? (1 << initblk.rlen) : 512; \
1493 CSR_XMTRL(pData) = (initblk.tlen < 9) ? (1 << initblk.tlen) : 512; \
1494 pData->aCSR[ 6] = (initblk.tlen << 12) | (initblk.rlen << 8); \
1495 pData->aCSR[ 8] = RT_LE2H_U16(initblk.ladrf1); \
1496 pData->aCSR[ 9] = RT_LE2H_U16(initblk.ladrf2); \
1497 pData->aCSR[10] = RT_LE2H_U16(initblk.ladrf3); \
1498 pData->aCSR[11] = RT_LE2H_U16(initblk.ladrf4); \
1499 pData->aCSR[12] = RT_LE2H_U16(initblk.padr1); \
1500 pData->aCSR[13] = RT_LE2H_U16(initblk.padr2); \
1501 pData->aCSR[14] = RT_LE2H_U16(initblk.padr3); \
1502 pData->GCRDRA = PHYSADDR(pData, initblk.rdra); \
1503 pData->GCTDRA = PHYSADDR(pData, initblk.tdra); \
1504} while (0)
1505
1506 pcnetEnablePrivateIf(pData);
1507
1508 if (BCR_SSIZE32(pData))
1509 {
1510 struct INITBLK32 initblk;
1511 pData->GCUpperPhys = 0;
1512 PCNET_INIT();
1513 Log(("#%d initblk.rlen=%#04x, initblk.tlen=%#04x\n",
1514 PCNET_INST_NR, initblk.rlen, initblk.tlen));
1515 }
1516 else
1517 {
1518 struct INITBLK16 initblk;
1519 pData->GCUpperPhys = (0xff00 & (uint32_t)pData->aCSR[2]) << 16;
1520 PCNET_INIT();
1521 Log(("#%d initblk.rlen=%#04x, initblk.tlen=%#04x\n",
1522 PCNET_INST_NR, initblk.rlen, initblk.tlen));
1523 }
1524
1525#undef PCNET_INIT
1526
1527 size_t cbRxBuffers = 0;
1528 for (int i = CSR_RCVRL(pData); i >= 1; i--)
1529 {
1530 RMD rmd;
1531 RTGCPHYS32 addr = pcnetRdraAddr(pData, i);
1532 /* At this time it is not guaranteed that the buffers are already initialized. */
1533 if (pcnetRmdLoad(pData, &rmd, PHYSADDR(pData, addr), false))
1534 cbRxBuffers += 4096-rmd.rmd1.bcnt;
1535 }
1536
1537 /*
1538 * Heuristics: The Solaris pcn driver allocates too few RX buffers (128 buffers of a
1539 * size of 128 bytes are 16KB in summary) leading to frequent RX buffer overflows. In
1540 * that case we don't signal RX overflows through the CSR0_MISS flag as the driver
1541 * re-initializes the device on every miss. Other guests use at least 32 buffers of
1542 * usually 1536 bytes and should therefore not run into condition. If they are still
1543 * short in RX buffers we notify this condition.
1544 */
1545 pData->fSignalRxMiss = (cbRxBuffers == 0 || cbRxBuffers >= 32*_1K);
1546
1547 if (pData->pDrv)
1548 pData->pDrv->pfnSetPromiscuousMode(pData->pDrv, CSR_PROM(pData));
1549
1550 CSR_RCVRC(pData) = CSR_RCVRL(pData);
1551 CSR_XMTRC(pData) = CSR_XMTRL(pData);
1552
1553#ifdef PCNET_NO_POLLING
1554 pcnetUpdateRingHandlers(pData);
1555#endif
1556
1557 /* Reset cached RX and TX states */
1558 CSR_CRST(pData) = CSR_CRBC(pData) = CSR_NRST(pData) = CSR_NRBC(pData) = 0;
1559 CSR_CXST(pData) = CSR_CXBC(pData) = CSR_NXST(pData) = CSR_NXBC(pData) = 0;
1560
1561 LogRel(("PCNet#%d: Init: ss32=%d GCRDRA=%#010x[%d] GCTDRA=%#010x[%d]%s\n",
1562 PCNET_INST_NR, BCR_SSIZE32(pData),
1563 pData->GCRDRA, CSR_RCVRL(pData), pData->GCTDRA, CSR_XMTRL(pData),
1564 !pData->fSignalRxMiss ? " (CSR0_MISS disabled)" : ""));
1565
1566 pData->aCSR[0] |= 0x0101; /* Initialization done */
1567 pData->aCSR[0] &= ~0x0004; /* clear STOP bit */
1568}
1569#endif /* IN_RING3 */
1570
1571/**
1572 * Start RX/TX operation.
1573 */
1574static void pcnetStart(PCNetState *pData)
1575{
1576 Log(("#%d pcnetStart:\n", PCNET_INST_NR));
1577 if (!CSR_DTX(pData))
1578 pData->aCSR[0] |= 0x0010; /* set TXON */
1579 if (!CSR_DRX(pData))
1580 pData->aCSR[0] |= 0x0020; /* set RXON */
1581 pcnetEnablePrivateIf(pData);
1582 pData->aCSR[0] &= ~0x0004; /* clear STOP bit */
1583 pData->aCSR[0] |= 0x0002; /* STRT */
1584 pcnetPollTimerStart(pData); /* start timer if it was stopped */
1585}
1586
1587/**
1588 * Stop RX/TX operation.
1589 */
1590static void pcnetStop(PCNetState *pData)
1591{
1592 Log(("#%d pcnetStop:\n", PCNET_INST_NR));
1593 pData->aCSR[0] &= ~0x7feb;
1594 pData->aCSR[0] |= 0x0014;
1595 pData->aCSR[4] &= ~0x02c2;
1596 pData->aCSR[5] &= ~0x0011;
1597 pcnetEnablePrivateIf(pData);
1598 pcnetPollTimer(pData);
1599}
1600
1601#ifdef IN_RING3
1602static DECLCALLBACK(void) pcnetWakeupReceive(PPDMDEVINS pDevIns)
1603{
1604 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
1605 STAM_COUNTER_INC(&pData->StatRxOverflowWakeup);
1606 if (pData->hEventOutOfRxSpace != NIL_RTSEMEVENT)
1607 RTSemEventSignal(pData->hEventOutOfRxSpace);
1608}
1609
1610static DECLCALLBACK(bool) pcnetCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
1611{
1612 pcnetWakeupReceive(pDevIns);
1613 return true;
1614}
1615#endif /* IN_RING3 */
1616
1617
1618/**
1619 * Poll Receive Descriptor Table Entry and cache the results in the appropriate registers.
1620 * Note: Once a descriptor belongs to the network card (this driver), it cannot be changed
1621 * by the host (the guest driver) anymore. Well, it could but the results are undefined by
1622 * definition.
1623 * @param fSkipCurrent if true, don't scan the current RDTE.
1624 */
1625static void pcnetRdtePoll(PCNetState *pData, bool fSkipCurrent=false)
1626{
1627 STAM_PROFILE_ADV_START(&pData->CTXSUFF(StatRdtePoll), a);
1628 /* assume lack of a next receive descriptor */
1629 CSR_NRST(pData) = 0;
1630
1631 if (RT_LIKELY(pData->GCRDRA))
1632 {
1633 /*
1634 * The current receive message descriptor.
1635 */
1636 RMD rmd;
1637 int i = CSR_RCVRC(pData);
1638 RTGCPHYS32 addr;
1639
1640 if (i < 1)
1641 i = CSR_RCVRL(pData);
1642
1643 if (!fSkipCurrent)
1644 {
1645 addr = pcnetRdraAddr(pData, i);
1646 CSR_CRDA(pData) = CSR_CRBA(pData) = 0;
1647 CSR_CRBC(pData) = CSR_CRST(pData) = 0;
1648 if (!pcnetRmdLoad(pData, &rmd, PHYSADDR(pData, addr), true))
1649 {
1650 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatRdtePoll), a);
1651 return;
1652 }
1653 if (RT_LIKELY(!IS_RMD_BAD(rmd)))
1654 {
1655 CSR_CRDA(pData) = addr; /* Receive Descriptor Address */
1656 CSR_CRBA(pData) = rmd.rmd0.rbadr; /* Receive Buffer Address */
1657 CSR_CRBC(pData) = rmd.rmd1.bcnt; /* Receive Byte Count */
1658 CSR_CRST(pData) = ((uint32_t *)&rmd)[1] >> 16; /* Receive Status */
1659 if (pData->fMaybeOutOfSpace)
1660 {
1661#ifdef IN_RING3
1662 pcnetWakeupReceive(PCNETSTATE_2_DEVINS(pData));
1663#else
1664 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(CTXSUFF(pData->pCanRxQueue));
1665 if (pItem)
1666 PDMQueueInsert(CTXSUFF(pData->pCanRxQueue), pItem);
1667#endif
1668 }
1669 }
1670 else
1671 {
1672 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatRdtePoll), a);
1673 /* This is not problematic since we don't own the descriptor */
1674 LogRel(("PCNet#%d: BAD RMD ENTRIES AT %#010x (i=%d)\n",
1675 PCNET_INST_NR, addr, i));
1676 return;
1677 }
1678 }
1679
1680 /*
1681 * The next descriptor.
1682 */
1683 if (--i < 1)
1684 i = CSR_RCVRL(pData);
1685 addr = pcnetRdraAddr(pData, i);
1686 CSR_NRDA(pData) = CSR_NRBA(pData) = 0;
1687 CSR_NRBC(pData) = 0;
1688 if (!pcnetRmdLoad(pData, &rmd, PHYSADDR(pData, addr), true))
1689 {
1690 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatRdtePoll), a);
1691 return;
1692 }
1693 if (RT_LIKELY(!IS_RMD_BAD(rmd)))
1694 {
1695 CSR_NRDA(pData) = addr; /* Receive Descriptor Address */
1696 CSR_NRBA(pData) = rmd.rmd0.rbadr; /* Receive Buffer Address */
1697 CSR_NRBC(pData) = rmd.rmd1.bcnt; /* Receive Byte Count */
1698 CSR_NRST(pData) = ((uint32_t *)&rmd)[1] >> 16; /* Receive Status */
1699 }
1700 else
1701 {
1702 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatRdtePoll), a);
1703 /* This is not problematic since we don't own the descriptor */
1704 LogRel(("PCNet#%d: BAD RMD ENTRIES + AT %#010x (i=%d)\n",
1705 PCNET_INST_NR, addr, i));
1706 return;
1707 }
1708
1709 /**
1710 * @todo NNRD
1711 */
1712 }
1713 else
1714 {
1715 CSR_CRDA(pData) = CSR_CRBA(pData) = CSR_NRDA(pData) = CSR_NRBA(pData) = 0;
1716 CSR_CRBC(pData) = CSR_NRBC(pData) = CSR_CRST(pData) = 0;
1717 }
1718 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatRdtePoll), a);
1719}
1720
1721/**
1722 * Poll Transmit Descriptor Table Entry
1723 * @return true if transmit descriptors available
1724 */
1725static int pcnetTdtePoll(PCNetState *pData, TMD *tmd)
1726{
1727 STAM_PROFILE_ADV_START(&pData->CTXSUFF(StatTdtePoll), a);
1728 if (RT_LIKELY(pData->GCTDRA))
1729 {
1730 RTGCPHYS32 cxda = pcnetTdraAddr(pData, CSR_XMTRC(pData));
1731
1732 if (!pcnetTmdLoad(pData, tmd, PHYSADDR(pData, cxda), true))
1733 {
1734 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatTdtePoll), a);
1735 return 0;
1736 }
1737
1738 if (RT_UNLIKELY(tmd->tmd1.ones != 15))
1739 {
1740 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatTdtePoll), a);
1741 LogRel(("PCNet#%d: BAD TMD XDA=%#010x\n",
1742 PCNET_INST_NR, PHYSADDR(pData, cxda)));
1743 return 0;
1744 }
1745
1746 /* previous xmit descriptor */
1747 CSR_PXDA(pData) = CSR_CXDA(pData);
1748 CSR_PXBC(pData) = CSR_CXBC(pData);
1749 CSR_PXST(pData) = CSR_CXST(pData);
1750
1751 /* set current trasmit decriptor. */
1752 CSR_CXDA(pData) = cxda;
1753 CSR_CXBC(pData) = tmd->tmd1.bcnt;
1754 CSR_CXST(pData) = ((uint32_t *)tmd)[1] >> 16;
1755 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatTdtePoll), a);
1756 return CARD_IS_OWNER(CSR_CXST(pData));
1757 }
1758 else
1759 {
1760 /** @todo consistency with previous receive descriptor */
1761 CSR_CXDA(pData) = 0;
1762 CSR_CXBC(pData) = CSR_CXST(pData) = 0;
1763 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatTdtePoll), a);
1764 return 0;
1765 }
1766}
1767
1768
1769#ifdef IN_RING3
1770
1771/**
1772 * Write data into guest receive buffers.
1773 */
1774static void pcnetReceiveNoSync(PCNetState *pData, const uint8_t *buf, size_t size)
1775{
1776 PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pData);
1777 int is_padr = 0, is_bcast = 0, is_ladr = 0;
1778 unsigned i;
1779 int pkt_size;
1780
1781 if (RT_UNLIKELY(CSR_DRX(pData) || CSR_STOP(pData) || CSR_SPND(pData) || !size))
1782 return;
1783
1784 /*
1785 * Drop packets if the VM is not running yet/anymore.
1786 */
1787 if (PDMDevHlpVMState(pDevIns) != VMSTATE_RUNNING)
1788 return;
1789
1790 Log(("#%d pcnetReceiveNoSync: size=%d\n", PCNET_INST_NR, size));
1791
1792 /*
1793 * Perform address matching.
1794 */
1795 if ( CSR_PROM(pData)
1796 || (is_padr = padr_match(pData, buf, size))
1797 || (is_bcast = padr_bcast(pData, buf, size))
1798 || (is_ladr = ladr_match(pData, buf, size)))
1799 {
1800 if (HOST_IS_OWNER(CSR_CRST(pData)))
1801 pcnetRdtePoll(pData);
1802 if (RT_UNLIKELY(HOST_IS_OWNER(CSR_CRST(pData))))
1803 {
1804 /* Not owned by controller. This should not be possible as
1805 * we already called pcnetCanReceive(). */
1806 LogRel(("PCNet#%d: no buffer: RCVRC=%d\n",
1807 PCNET_INST_NR, CSR_RCVRC(pData)));
1808 /* Dump the status of all RX descriptors */
1809 const unsigned cb = 1 << pData->iLog2DescSize;
1810 RTGCPHYS32 GCPhys = pData->GCRDRA;
1811 i = CSR_RCVRL(pData);
1812 while (i-- > 0)
1813 {
1814 RMD rmd;
1815 pcnetRmdLoad(pData, &rmd, PHYSADDR(pData, GCPhys), false);
1816 LogRel((" %#010x\n", rmd.rmd1));
1817 GCPhys += cb;
1818 }
1819 pData->aCSR[0] |= 0x1000; /* Set MISS flag */
1820 CSR_MISSC(pData)++;
1821 }
1822 else
1823 {
1824 uint8_t *src = &pData->abRecvBuf[8];
1825 RTGCPHYS32 crda = CSR_CRDA(pData);
1826 RTGCPHYS32 next_crda;
1827 RMD rmd, next_rmd;
1828 int pktcount = 0;
1829
1830 memcpy(src, buf, size);
1831 if (!CSR_ASTRP_RCV(pData))
1832 {
1833 uint32_t fcs = ~0;
1834 uint8_t *p = src;
1835
1836 while (size < 60)
1837 src[size++] = 0;
1838 while (p != &src[size])
1839 CRC(fcs, *p++);
1840 ((uint32_t *)&src[size])[0] = htonl(fcs);
1841 /* FCS at end of packet */
1842 }
1843 size += 4;
1844 pkt_size = size;
1845
1846#ifdef PCNET_DEBUG_MATCH
1847 PRINT_PKTHDR(buf);
1848#endif
1849
1850 pcnetRmdLoad(pData, &rmd, PHYSADDR(pData, crda), false);
1851 /*if (!CSR_LAPPEN(pData))*/
1852 rmd.rmd1.stp = 1;
1853
1854 size_t count = RT_MIN(4096 - (size_t)rmd.rmd1.bcnt, size);
1855 RTGCPHYS32 rbadr = PHYSADDR(pData, rmd.rmd0.rbadr);
1856#if 0
1857 if (pData->fPrivIfEnabled)
1858 {
1859 uint8_t *pb = (uint8_t*)pData->CTXSUFF(pSharedMMIO)
1860 + rbadr - pData->GCRDRA + pData->CTXSUFF(pSharedMMIO)->V.V1.offRxDescriptors;
1861 memcpy(pb, src, count);
1862 }
1863 else
1864#endif
1865 PDMDevHlpPhysWrite(pDevIns, rbadr, src, count);
1866 src += count;
1867 size -= count;
1868 pktcount++;
1869
1870 /* Read current receive descriptor index */
1871 i = CSR_RCVRC(pData);
1872
1873 while (size > 0)
1874 {
1875 /* Read the entire next descriptor as we're likely to need it. */
1876 if (--i < 1)
1877 i = CSR_RCVRL(pData);
1878 next_crda = pcnetRdraAddr(pData, i);
1879
1880 /* Check next descriptor's own bit. If we don't own it, we have
1881 * to quit and write error status into the last descriptor we own.
1882 */
1883 if (!pcnetRmdLoad(pData, &next_rmd, PHYSADDR(pData, next_crda), true))
1884 break;
1885
1886 /* Write back current descriptor, clear the own bit. */
1887 pcnetRmdStorePassHost(pData, &rmd, PHYSADDR(pData, crda));
1888
1889 /* Switch to the next descriptor */
1890 crda = next_crda;
1891 rmd = next_rmd;
1892
1893 count = RT_MIN(4096 - (size_t)rmd.rmd1.bcnt, size);
1894 RTGCPHYS32 rbadr = PHYSADDR(pData, rmd.rmd0.rbadr);
1895#if 0
1896 if (pData->fPrivIfEnabled)
1897 {
1898 uint8_t *pb = (uint8_t*)pData->CTXSUFF(pSharedMMIO)
1899 + rbadr - pData->GCRDRA + pData->CTXSUFF(pSharedMMIO)->V.V1.offRxDescriptors;
1900 memcpy(pb, src, count);
1901 }
1902 else
1903#endif
1904 PDMDevHlpPhysWrite(pDevIns, rbadr, src, count);
1905 src += count;
1906 size -= count;
1907 pktcount++;
1908 }
1909
1910 if (RT_LIKELY(size == 0))
1911 {
1912 rmd.rmd1.enp = 1;
1913 rmd.rmd1.pam = !CSR_PROM(pData) && is_padr;
1914 rmd.rmd1.lafm = !CSR_PROM(pData) && is_ladr;
1915 rmd.rmd1.bam = !CSR_PROM(pData) && is_bcast;
1916 rmd.rmd2.mcnt = pkt_size;
1917
1918 STAM_REL_COUNTER_ADD(&pData->StatReceiveBytes, pkt_size);
1919 }
1920 else
1921 {
1922 Log(("#%d: Overflow by %ubytes\n", PCNET_INST_NR, size));
1923 rmd.rmd1.oflo = 1;
1924 rmd.rmd1.buff = 1;
1925 rmd.rmd1.err = 1;
1926 }
1927
1928 /* write back, clear the own bit */
1929 pcnetRmdStorePassHost(pData, &rmd, PHYSADDR(pData, crda));
1930
1931 pData->aCSR[0] |= 0x0400;
1932
1933 Log(("#%d RCVRC=%d CRDA=%#010x BLKS=%d\n", PCNET_INST_NR,
1934 CSR_RCVRC(pData), PHYSADDR(pData, CSR_CRDA(pData)), pktcount));
1935#ifdef PCNET_DEBUG_RMD
1936 PRINT_RMD(&rmd);
1937#endif
1938
1939 while (pktcount--)
1940 {
1941 if (CSR_RCVRC(pData) < 2)
1942 CSR_RCVRC(pData) = CSR_RCVRL(pData);
1943 else
1944 CSR_RCVRC(pData)--;
1945 }
1946 /* guest driver is owner: force repoll of current and next RDTEs */
1947 CSR_CRST(pData) = 0;
1948 }
1949 }
1950
1951 /* see description of TXDPOLL:
1952 * ``transmit polling will take place following receive activities'' */
1953 pcnetPollRxTx(pData);
1954 pcnetUpdateIrq(pData);
1955}
1956
1957
1958/**
1959 * Checks if the link is up.
1960 * @returns true if the link is up.
1961 * @returns false if the link is down.
1962 */
1963DECLINLINE(bool) pcnetIsLinkUp(PCNetState *pData)
1964{
1965 return pData->pDrv && !pData->fLinkTempDown && pData->fLinkUp;
1966}
1967
1968
1969/**
1970 * Transmit queue consumer
1971 * This is just a very simple way of delaying sending to R3.
1972 *
1973 * @returns Success indicator.
1974 * If false the item will not be removed and the flushing will stop.
1975 * @param pDevIns The device instance.
1976 * @param pItem The item to consume. Upon return this item will be freed.
1977 */
1978static DECLCALLBACK(bool) pcnetXmitQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
1979{
1980 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
1981 NOREF(pItem);
1982
1983 /* Clear counter .*/
1984 ASMAtomicAndU32(&pData->cPendingSends, 0);
1985#ifdef PCNET_QUEUE_SEND_PACKETS
1986 int rc = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
1987 AssertReleaseRC(rc);
1988 pcnetSyncTransmit(pData);
1989 PDMCritSectLeave(&pData->CritSect);
1990#else
1991 int rc = RTSemEventSignal(pData->hSendEventSem);
1992 AssertRC(rc);
1993#endif
1994 return true;
1995}
1996
1997
1998/**
1999 * Scraps the top frame.
2000 * This is done as a precaution against mess left over by on
2001 */
2002DECLINLINE(void) pcnetXmitScrapFrame(PCNetState *pData)
2003{
2004 pData->pvSendFrame = NULL;
2005 pData->cbSendFrame = 0;
2006}
2007
2008
2009/**
2010 * Reads the first part of a frame
2011 */
2012DECLINLINE(void) pcnetXmitRead1st(PCNetState *pData, RTGCPHYS32 GCPhysFrame, const unsigned cbFrame)
2013{
2014 Assert(PDMCritSectIsOwner(&pData->CritSect));
2015 Assert(cbFrame < sizeof(pData->abSendBuf));
2016
2017#ifdef PCNET_QUEUE_SEND_PACKETS
2018 AssertRelease(pData->cXmitRingBufPending < PCNET_MAX_XMIT_SLOTS-1);
2019 pData->pvSendFrame = pData->apXmitRingBuffer[pData->iXmitRingBufProd];
2020#else
2021 pData->pvSendFrame = pData->abSendBuf;
2022#endif
2023 PDMDevHlpPhysRead(pData->CTXSUFF(pDevIns), GCPhysFrame, pData->pvSendFrame, cbFrame);
2024 pData->cbSendFrame = cbFrame;
2025}
2026
2027
2028/**
2029 * Reads more into the current frame.
2030 */
2031DECLINLINE(void) pcnetXmitReadMore(PCNetState *pData, RTGCPHYS32 GCPhysFrame, const unsigned cbFrame)
2032{
2033 Assert(pData->cbSendFrame + cbFrame <= MAX_FRAME);
2034 PDMDevHlpPhysRead(pData->CTXSUFF(pDevIns), GCPhysFrame, pData->pvSendFrame + pData->cbSendFrame, cbFrame);
2035 pData->cbSendFrame += cbFrame;
2036}
2037
2038
2039/**
2040 * Completes the current frame.
2041 * If we've reached the maxium number of frames, they will be flushed.
2042 */
2043DECLINLINE(int) pcnetXmitCompleteFrame(PCNetState *pData)
2044{
2045#ifdef PCNET_QUEUE_SEND_PACKETS
2046 Assert(PDMCritSectIsOwner(&pData->CritSect));
2047 AssertRelease(pData->cXmitRingBufPending < PCNET_MAX_XMIT_SLOTS-1);
2048 Assert(!pData->cbXmitRingBuffer[pData->iXmitRingBufProd]);
2049
2050 pData->cbXmitRingBuffer[pData->iXmitRingBufProd] = (uint16_t)pData->cbSendFrame;
2051 pData->iXmitRingBufProd = (pData->iXmitRingBufProd+1) & PCNET_MAX_XMIT_SLOTS_MASK;
2052 ASMAtomicIncS32(&pData->cXmitRingBufPending);
2053
2054 int rc = RTSemEventSignal(pData->hSendEventSem);
2055 AssertRC(rc);
2056
2057 return VINF_SUCCESS;
2058#else
2059 /* Don't hold the critical section while transmitting data. */
2060 /** @note also avoids deadlocks with NAT as it can call us right back. */
2061 PDMCritSectLeave(&pData->CritSect);
2062
2063 STAM_PROFILE_ADV_START(&pData->StatTransmitSend, a);
2064 if (pData->cbSendFrame > 70) /* unqualified guess */
2065 pData->Led.Asserted.s.fWriting = pData->Led.Actual.s.fWriting = 1;
2066
2067 pData->pDrv->pfnSend(pData->pDrv, pData->pvSendFrame, pData->cbSendFrame);
2068 STAM_REL_COUNTER_ADD(&pData->StatTransmitBytes, pData->cbSendFrame);
2069 pData->Led.Actual.s.fWriting = 0;
2070 STAM_PROFILE_ADV_STOP(&pData->StatTransmitSend, a);
2071
2072 return PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
2073#endif
2074}
2075
2076
2077/**
2078 * Fails a TMD with a link down error.
2079 */
2080static void pcnetXmitFailTMDLinkDown(PCNetState *pData, TMD *pTmd)
2081{
2082 /* make carrier error - hope this is correct. */
2083 pData->cLinkDownReported++;
2084 pTmd->tmd2.lcar = pTmd->tmd1.err = 1;
2085 pData->aCSR[0] |= RT_BIT(15) | RT_BIT(13); /* ERR | CERR */
2086 pData->Led.Asserted.s.fError = pData->Led.Actual.s.fError = 1;
2087 Log(("#%d pcnetTransmit: Signaling send error. swstyle=%#x\n",
2088 PCNET_INST_NR, pData->aBCR[BCR_SWS]));
2089}
2090
2091/**
2092 * Fails a TMD with a generic error.
2093 */
2094static void pcnetXmitFailTMDGeneric(PCNetState *pData, TMD *pTmd)
2095{
2096 /* make carrier error - hope this is correct. */
2097 pTmd->tmd2.lcar = pTmd->tmd1.err = 1;
2098 pData->aCSR[0] |= RT_BIT(15) | RT_BIT(13); /* ERR | CERR */
2099 pData->Led.Asserted.s.fError = pData->Led.Actual.s.fError = 1;
2100 Log(("#%d pcnetTransmit: Signaling send error. swstyle=%#x\n",
2101 PCNET_INST_NR, pData->aBCR[BCR_SWS]));
2102}
2103
2104
2105/**
2106 * Transmit a loopback frame.
2107 */
2108DECLINLINE(void) pcnetXmitLoopbackFrame(PCNetState *pData)
2109{
2110 pData->Led.Asserted.s.fReading = pData->Led.Actual.s.fReading = 1;
2111 if (HOST_IS_OWNER(CSR_CRST(pData)))
2112 pcnetRdtePoll(pData);
2113
2114 Assert(pData->pvSendFrame);
2115 pcnetReceiveNoSync(pData, (const uint8_t *)pData->pvSendFrame, pData->cbSendFrame);
2116 pcnetXmitScrapFrame(pData);
2117 pData->Led.Actual.s.fReading = 0;
2118}
2119
2120/**
2121 * Flushes queued frames.
2122 */
2123DECLINLINE(void) pcnetXmitFlushFrames(PCNetState *pData)
2124{
2125 pcnetXmitQueueConsumer(CTXSUFF(pData->pDevIns), NULL);
2126}
2127
2128#endif /* IN_RING3 */
2129
2130
2131
2132/**
2133 * Try to transmit frames
2134 */
2135static void pcnetTransmit(PCNetState *pData)
2136{
2137 if (RT_UNLIKELY(!CSR_TXON(pData)))
2138 {
2139 pData->aCSR[0] &= ~0x0008; /* Clear TDMD */
2140 return;
2141 }
2142
2143 /*
2144 * Check the current transmit descriptors.
2145 */
2146 TMD tmd;
2147 if (!pcnetTdtePoll(pData, &tmd))
2148 return;
2149
2150 /*
2151 * Clear TDMD.
2152 */
2153 pData->aCSR[0] &= ~0x0008;
2154
2155 /*
2156 * If we're in Ring-3 we should flush the queue now, in GC/R0 we'll queue a flush job.
2157 */
2158#ifdef IN_RING3
2159 pcnetXmitFlushFrames(pData);
2160#else
2161# if 1
2162 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(CTXSUFF(pData->pXmitQueue));
2163 if (RT_UNLIKELY(pItem))
2164 PDMQueueInsert(CTXSUFF(pData->pXmitQueue), pItem);
2165# else
2166 if (ASMAtomicIncU32(&pData->cPendingSends) < 16)
2167 {
2168 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(CTXSUFF(pData->pXmitQueue));
2169 if (RT_UNLIKELY(pItem))
2170 PDMQueueInsert(CTXSUFF(pData->pXmitQueue), pItem);
2171 }
2172 else
2173 PDMQueueFlush(CTXSUFF(pData->pXmitQueue));
2174# endif
2175#endif
2176}
2177
2178#ifdef IN_RING3
2179
2180/**
2181 * Try to transmit frames
2182 */
2183#ifdef PCNET_QUEUE_SEND_PACKETS
2184static int pcnetAsyncTransmit(PCNetState *pData)
2185{
2186 Assert(PDMCritSectIsOwner(&pData->CritSect));
2187 size_t cb;
2188
2189 while ((pData->cXmitRingBufPending > 0))
2190 {
2191 cb = pData->cbXmitRingBuffer[pData->iXmitRingBufCons];
2192
2193 /* Don't hold the critical section while transmitting data. */
2194 /** @note also avoids deadlocks with NAT as it can call us right back. */
2195 PDMCritSectLeave(&pData->CritSect);
2196
2197 STAM_PROFILE_ADV_START(&pData->StatTransmitSend, a);
2198 if (cb > 70) /* unqualified guess */
2199 pData->Led.Asserted.s.fWriting = pData->Led.Actual.s.fWriting = 1;
2200
2201 pData->pDrv->pfnSend(pData->pDrv, pData->apXmitRingBuffer[pData->iXmitRingBufCons], cb);
2202 STAM_REL_COUNTER_ADD(&pData->StatTransmitBytes, cb);
2203 pData->Led.Actual.s.fWriting = 0;
2204 STAM_PROFILE_ADV_STOP(&pData->StatTransmitSend, a);
2205
2206 int rc = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
2207 AssertReleaseRC(rc);
2208
2209 pData->cbXmitRingBuffer[pData->iXmitRingBufCons] = 0;
2210 pData->iXmitRingBufCons = (pData->iXmitRingBufCons+1) & PCNET_MAX_XMIT_SLOTS_MASK;
2211 ASMAtomicDecS32(&pData->cXmitRingBufPending);
2212 }
2213 return VINF_SUCCESS;
2214}
2215
2216static int pcnetSyncTransmit(PCNetState *pData)
2217#else
2218static int pcnetAsyncTransmit(PCNetState *pData)
2219#endif
2220{
2221 unsigned cFlushIrq = 0;
2222
2223 Assert(PDMCritSectIsOwner(&pData->CritSect));
2224
2225 if (RT_UNLIKELY(!CSR_TXON(pData)))
2226 {
2227 pData->aCSR[0] &= ~0x0008; /* Clear TDMD */
2228 return VINF_SUCCESS;
2229 }
2230
2231 /*
2232 * Iterate the transmit descriptors.
2233 */
2234 STAM_PROFILE_ADV_START(&pData->StatTransmit, a);
2235 do
2236 {
2237#ifdef VBOX_WITH_STATISTICS
2238 unsigned cBuffers = 1;
2239#endif
2240 TMD tmd;
2241 if (!pcnetTdtePoll(pData, &tmd))
2242 break;
2243
2244 /* Don't continue sending packets when the link is down. */
2245 if (RT_UNLIKELY( !pcnetIsLinkUp(pData)
2246 && pData->cLinkDownReported > PCNET_MAX_LINKDOWN_REPORTED)
2247 )
2248 break;
2249
2250#ifdef PCNET_DEBUG_TMD
2251 Log2(("#%d TMDLOAD %#010x\n", PCNET_INST_NR, PHYSADDR(pData, CSR_CXDA(pData))));
2252 PRINT_TMD(&tmd);
2253#endif
2254 pcnetXmitScrapFrame(pData);
2255
2256 /*
2257 * The typical case - a complete packet.
2258 */
2259 if (tmd.tmd1.stp && tmd.tmd1.enp)
2260 {
2261 const unsigned cb = 4096 - tmd.tmd1.bcnt;
2262 Log(("#%d pcnetTransmit: stp&enp: cb=%d xmtrc=%#x\n", PCNET_INST_NR, cb, CSR_XMTRC(pData)));
2263
2264 if (RT_LIKELY(pcnetIsLinkUp(pData) || CSR_LOOP(pData)))
2265 {
2266 /* From the manual: ``A zero length buffer is acceptable as
2267 * long as it is not the last buffer in a chain (STP = 0 and
2268 * ENP = 1).'' That means that the first buffer might have a
2269 * zero length if it is not the last one in the chain. */
2270 if (RT_LIKELY(cb <= MAX_FRAME))
2271 {
2272 pcnetXmitRead1st(pData, PHYSADDR(pData, tmd.tmd0.tbadr), cb);
2273 if (CSR_LOOP(pData))
2274 pcnetXmitLoopbackFrame(pData);
2275 else
2276 {
2277 int rc = pcnetXmitCompleteFrame(pData);
2278 AssertRCReturn(rc, rc);
2279 }
2280 }
2281 else if (cb == 4096)
2282 {
2283 /* The Windows NT4 pcnet driver sometimes marks the first
2284 * unused descriptor as owned by us. Ignore that (by
2285 * passing it back). Do not update the ring counter in this
2286 * case (otherwise that driver becomes even more confused,
2287 * which causes transmit to stall for about 10 seconds).
2288 * This is just a workaround, not a final solution. */
2289 /* r=frank: IMHO this is the correct implementation. The
2290 * manual says: ``If the OWN bit is set and the buffer
2291 * length is 0, the OWN bit will be cleared. In the C-LANCE
2292 * the buffer length of 0 is interpreted as a 4096-byte
2293 * buffer.'' */
2294 LogRel(("PCNet#%d: pcnetAsyncTransmit: illegal 4kb frame -> ignoring\n", PCNET_INST_NR));
2295 pcnetTmdStorePassHost(pData, &tmd, PHYSADDR(pData, CSR_CXDA(pData)));
2296 break;
2297 }
2298 else
2299 {
2300 /* Signal error, as this violates the Ethernet specs. */
2301 /** @todo check if the correct error is generated. */
2302 LogRel(("PCNet#%d: pcnetAsyncTransmit: illegal 4kb frame -> signalling error\n", PCNET_INST_NR));
2303
2304 pcnetXmitFailTMDGeneric(pData, &tmd);
2305 }
2306 }
2307 else
2308 pcnetXmitFailTMDLinkDown(pData, &tmd);
2309
2310 /* Write back the TMD and pass it to the host (clear own bit). */
2311 pcnetTmdStorePassHost(pData, &tmd, PHYSADDR(pData, CSR_CXDA(pData)));
2312
2313 /* advance the ring counter register */
2314 if (CSR_XMTRC(pData) < 2)
2315 CSR_XMTRC(pData) = CSR_XMTRL(pData);
2316 else
2317 CSR_XMTRC(pData)--;
2318 }
2319 else if (tmd.tmd1.stp)
2320 {
2321 /*
2322 * Read TMDs until end-of-packet or tdte poll fails (underflow).
2323 */
2324 bool fDropFrame = false;
2325 unsigned cb = 4096 - tmd.tmd1.bcnt;
2326 pcnetXmitRead1st(pData, PHYSADDR(pData, tmd.tmd0.tbadr), cb);
2327 for (;;)
2328 {
2329 /*
2330 * Advance the ring counter register and check the next tmd.
2331 */
2332#ifdef LOG_ENABLED
2333 const uint32_t iStart = CSR_XMTRC(pData);
2334#endif
2335 const uint32_t GCPhysPrevTmd = PHYSADDR(pData, CSR_CXDA(pData));
2336 if (CSR_XMTRC(pData) < 2)
2337 CSR_XMTRC(pData) = CSR_XMTRL(pData);
2338 else
2339 CSR_XMTRC(pData)--;
2340
2341 TMD dummy;
2342 if (!pcnetTdtePoll(pData, &dummy))
2343 {
2344 /*
2345 * Underflow!
2346 */
2347 tmd.tmd2.buff = tmd.tmd2.uflo = tmd.tmd1.err = 1;
2348 pData->aCSR[0] |= 0x0200; /* set TINT */
2349 if (!CSR_DXSUFLO(pData)) /* stop on xmit underflow */
2350 pData->aCSR[0] &= ~0x0010; /* clear TXON */
2351 pcnetTmdStorePassHost(pData, &tmd, GCPhysPrevTmd);
2352 AssertMsgFailed(("pcnetTransmit: Underflow!!!\n"));
2353 break;
2354 }
2355
2356 /* release & save the previous tmd, pass it to the host */
2357 pcnetTmdStorePassHost(pData, &tmd, GCPhysPrevTmd);
2358
2359 /*
2360 * The next tdm.
2361 */
2362#ifdef VBOX_WITH_STATISTICS
2363 cBuffers++;
2364#endif
2365 pcnetTmdLoad(pData, &tmd, PHYSADDR(pData, CSR_CXDA(pData)), false);
2366 cb = 4096 - tmd.tmd1.bcnt;
2367 if ( pData->cbSendFrame + cb < MAX_FRAME
2368 && !fDropFrame)
2369 pcnetXmitReadMore(pData, PHYSADDR(pData, tmd.tmd0.tbadr), cb);
2370 else
2371 {
2372 AssertMsg(fDropFrame, ("pcnetTransmit: Frame is too big!!! %d bytes\n",
2373 pData->cbSendFrame + cb));
2374 fDropFrame = true;
2375 }
2376 if (tmd.tmd1.enp)
2377 {
2378 Log(("#%d pcnetTransmit: stp: cb=%d xmtrc=%#x-%#x\n", PCNET_INST_NR,
2379 pData->cbSendFrame, iStart, CSR_XMTRC(pData)));
2380 if (pcnetIsLinkUp(pData) && !fDropFrame)
2381 {
2382 int rc = pcnetXmitCompleteFrame(pData);
2383 AssertRCReturn(rc, rc);
2384 }
2385 else if (CSR_LOOP(pData) && !fDropFrame)
2386 pcnetXmitLoopbackFrame(pData);
2387 else
2388 {
2389 if (!fDropFrame)
2390 pcnetXmitFailTMDLinkDown(pData, &tmd);
2391 pcnetXmitScrapFrame(pData);
2392 }
2393
2394 /* Write back the TMD, pass it to the host */
2395 pcnetTmdStorePassHost(pData, &tmd, PHYSADDR(pData, CSR_CXDA(pData)));
2396
2397 /* advance the ring counter register */
2398 if (CSR_XMTRC(pData) < 2)
2399 CSR_XMTRC(pData) = CSR_XMTRL(pData);
2400 else
2401 CSR_XMTRC(pData)--;
2402 break;
2403 }
2404 }
2405 }
2406 else
2407 {
2408 /*
2409 * We underflowed in a previous transfer, or the driver is giving us shit.
2410 * Simply stop the transmitting for now.
2411 */
2412 /** @todo according to the specs we're supposed to clear the own bit and move on to the next one. */
2413 Log(("#%d pcnetTransmit: guest is giving us shit!\n", PCNET_INST_NR));
2414 break;
2415 }
2416 /* Update TDMD, TXSTRT and TINT. */
2417 pData->aCSR[0] &= ~0x0008; /* clear TDMD */
2418
2419 pData->aCSR[4] |= 0x0008; /* set TXSTRT */
2420 if ( !CSR_TOKINTD(pData) /* Transmit OK Interrupt Disable, no infl. on errors. */
2421 || (CSR_LTINTEN(pData) && tmd.tmd1.ltint)
2422 || tmd.tmd1.err)
2423 {
2424 cFlushIrq++;
2425 }
2426
2427 /** @todo should we continue after an error (tmd.tmd1.err) or not? */
2428
2429 STAM_COUNTER_INC(&pData->aStatXmitChainCounts[RT_MIN(cBuffers,
2430 ELEMENTS(pData->aStatXmitChainCounts)) - 1]);
2431 } while (CSR_TXON(pData)); /* transfer on */
2432
2433 if (cFlushIrq)
2434 {
2435 STAM_COUNTER_INC(&pData->aStatXmitFlush[RT_MIN(cFlushIrq, ELEMENTS(pData->aStatXmitFlush)) - 1]);
2436 pData->aCSR[0] |= 0x0200; /* set TINT */
2437 pcnetUpdateIrq(pData);
2438 }
2439
2440 STAM_PROFILE_ADV_STOP(&pData->StatTransmit, a);
2441
2442 return VINF_SUCCESS;
2443}
2444
2445
2446/**
2447 * Async I/O thread for delayed sending of packets.
2448 *
2449 * @returns VBox status code. Returning failure will naturally terminate the thread.
2450 * @param pDevIns The pcnet device instance.
2451 * @param pThread The thread.
2452 */
2453static DECLCALLBACK(int) pcnetAsyncSendThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2454{
2455 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
2456
2457 /*
2458 * We can enter this function in two states, initializing or resuming.
2459 *
2460 * The idea about the initializing bit is that we can do per-thread
2461 * initialization while the creator thread can still pick up errors.
2462 * At present, there is nothing to init, or at least nothing that
2463 * need initing in the thread.
2464 */
2465 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2466 return VINF_SUCCESS;
2467
2468 /*
2469 * Stay in the run-loop until we're supposed to leave the
2470 * running state. If something really bad happens, we'll
2471 * quit the loop while in the running state and return
2472 * an error status to PDM and let it terminate the thread.
2473 */
2474 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2475 {
2476 /*
2477 * Block until we've got something to send or is supposed
2478 * to leave the running state.
2479 */
2480 int rc = RTSemEventWait(pData->hSendEventSem, RT_INDEFINITE_WAIT);
2481 AssertRCReturn(rc, rc);
2482 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
2483 break;
2484
2485 /*
2486 * Perform async send. Mind that we might be requested to
2487 * suspended while waiting for the critical section.
2488 */
2489 rc = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
2490 AssertReleaseRCReturn(rc, rc);
2491
2492 if (pThread->enmState == PDMTHREADSTATE_RUNNING)
2493 {
2494 rc = pcnetAsyncTransmit(pData);
2495 AssertReleaseRC(rc);
2496 }
2497
2498 PDMCritSectLeave(&pData->CritSect);
2499 }
2500
2501 /* The thread is being suspended or terminated. */
2502 return VINF_SUCCESS;
2503}
2504
2505
2506/**
2507 * Unblock the send thread so it can respond to a state change.
2508 *
2509 * @returns VBox status code.
2510 * @param pDevIns The pcnet device instance.
2511 * @param pThread The send thread.
2512 */
2513static DECLCALLBACK(int) pcnetAsyncSendThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2514{
2515 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
2516 return RTSemEventSignal(pData->hSendEventSem);
2517}
2518
2519#endif /* IN_RING3 */
2520
2521/**
2522 * Poll for changes in RX and TX descriptor rings.
2523 */
2524static void pcnetPollRxTx(PCNetState *pData)
2525{
2526 if (CSR_RXON(pData))
2527 if (HOST_IS_OWNER(CSR_CRST(pData))) /* Only poll RDTEs if none available */
2528 pcnetRdtePoll(pData);
2529
2530 if (CSR_TDMD(pData) || (CSR_TXON(pData) && !CSR_DPOLL(pData)))
2531 pcnetTransmit(pData);
2532}
2533
2534
2535/**
2536 * Start the poller timer.
2537 * Poll timer interval is fixed to 500Hz. Don't stop it.
2538 * @thread EMT, TAP.
2539 */
2540static void pcnetPollTimerStart(PCNetState *pData)
2541{
2542 TMTimerSetMillies(pData->CTXSUFF(pTimerPoll), 2);
2543}
2544
2545
2546/**
2547 * Update the poller timer.
2548 * @thread EMT.
2549 */
2550static void pcnetPollTimer(PCNetState *pData)
2551{
2552 STAM_PROFILE_ADV_START(&pData->StatPollTimer, a);
2553
2554#ifdef LOG_ENABLED
2555 TMD dummy;
2556 if (CSR_STOP(pData) || CSR_SPND(pData))
2557 Log2(("#%d pcnetPollTimer time=%#010llx CSR_STOP=%d CSR_SPND=%d\n",
2558 PCNET_INST_NR, RTTimeMilliTS(), CSR_STOP(pData), CSR_SPND(pData)));
2559 else
2560 Log2(("#%d pcnetPollTimer time=%#010llx TDMD=%d TXON=%d POLL=%d TDTE=%d TDRA=%#x\n",
2561 PCNET_INST_NR, RTTimeMilliTS(), CSR_TDMD(pData), CSR_TXON(pData),
2562 !CSR_DPOLL(pData), pcnetTdtePoll(pData, &dummy), pData->GCTDRA));
2563 Log2(("#%d pcnetPollTimer: CSR_CXDA=%#x CSR_XMTRL=%d CSR_XMTRC=%d\n",
2564 PCNET_INST_NR, CSR_CXDA(pData), CSR_XMTRL(pData), CSR_XMTRC(pData)));
2565#endif
2566#ifdef PCNET_DEBUG_TMD
2567 if (CSR_CXDA(pData))
2568 {
2569 TMD tmd;
2570 pcnetTmdLoad(pData, &tmd, PHYSADDR(pData, CSR_CXDA(pData)), false);
2571 Log2(("#%d pcnetPollTimer: TMDLOAD %#010x\n", PCNET_INST_NR, PHYSADDR(pData, CSR_CXDA(pData))));
2572 PRINT_TMD(&tmd);
2573 }
2574#endif
2575 if (CSR_TDMD(pData))
2576 pcnetTransmit(pData);
2577
2578 pcnetUpdateIrq(pData);
2579
2580 /* If the receive thread is waiting for new descriptors, poll TX/RX even if polling
2581 * disabled. We wouldn't need to poll for new TX descriptors in that case but it will
2582 * not hurt as waiting for RX descriptors should occur very seldom */
2583 if (RT_LIKELY( !CSR_STOP(pData)
2584 && !CSR_SPND(pData)
2585 && ( !CSR_DPOLL(pData)
2586 || pData->fMaybeOutOfSpace)))
2587 {
2588 /* We ensure that we poll at least every 2ms (500Hz) but not more often than
2589 * 5000 times per second. This way we completely prevent the overhead from
2590 * heavy reprogramming the timer which turned out to be very CPU-intensive.
2591 * The drawback is that csr46 and csr47 are not updated properly anymore
2592 * but so far I have not seen any guest depending on these values. The 2ms
2593 * interval is the default polling interval of the PCNet card (65536/33MHz). */
2594#ifdef PCNET_NO_POLLING
2595 pcnetPollRxTx(pData);
2596#else
2597 uint64_t u64Now = TMTimerGet(pData->CTXSUFF(pTimerPoll));
2598 if (RT_UNLIKELY(u64Now - pData->u64LastPoll > 200000))
2599 {
2600 pData->u64LastPoll = u64Now;
2601 pcnetPollRxTx(pData);
2602 }
2603 if (!TMTimerIsActive(pData->CTXSUFF(pTimerPoll)))
2604 pcnetPollTimerStart(pData);
2605#endif
2606 }
2607 STAM_PROFILE_ADV_STOP(&pData->StatPollTimer, a);
2608}
2609
2610
2611static int pcnetCSRWriteU16(PCNetState *pData, uint32_t u32RAP, uint32_t val)
2612{
2613 int rc = VINF_SUCCESS;
2614#ifdef PCNET_DEBUG_CSR
2615 Log(("#%d pcnetCSRWriteU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
2616#endif
2617 switch (u32RAP)
2618 {
2619 case 0:
2620 {
2621 uint16_t csr0 = pData->aCSR[0];
2622 /* Clear any interrupt flags.
2623 * Don't clear an interrupt flag which was not seen by the guest yet. */
2624 csr0 &= ~(val & 0x7f00 & pData->u16CSR0LastSeenByGuest);
2625 csr0 = (csr0 & ~0x0040) | (val & 0x0048);
2626 val = (val & 0x007f) | (csr0 & 0x7f00);
2627
2628 /* Iff STOP, STRT and INIT are set, clear STRT and INIT */
2629 if ((val & 7) == 7)
2630 val &= ~3;
2631
2632 Log(("#%d CSR0: old=%#06x new=%#06x\n", PCNET_INST_NR, pData->aCSR[0], csr0));
2633
2634#ifndef IN_RING3
2635 if (!(csr0 & 0x0001/*init*/) && (val & 1))
2636 {
2637 Log(("#%d pcnetCSRWriteU16: pcnetInit requested => HC\n", PCNET_INST_NR));
2638 return VINF_IOM_HC_IOPORT_WRITE;
2639 }
2640#endif
2641 pData->aCSR[0] = csr0;
2642
2643 if (!CSR_STOP(pData) && (val & 4))
2644 pcnetStop(pData);
2645
2646#ifdef IN_RING3
2647 if (!CSR_INIT(pData) && (val & 1))
2648 pcnetInit(pData);
2649#endif
2650
2651 if (!CSR_STRT(pData) && (val & 2))
2652 pcnetStart(pData);
2653
2654 if (CSR_TDMD(pData))
2655 pcnetTransmit(pData);
2656
2657 return rc;
2658 }
2659 case 1: /* IADRL */
2660 case 2: /* IADRH */
2661 case 8: /* LADRF 0..15 */
2662 case 9: /* LADRF 16..31 */
2663 case 10: /* LADRF 32..47 */
2664 case 11: /* LADRF 48..63 */
2665 case 12: /* PADR 0..15 */
2666 case 13: /* PADR 16..31 */
2667 case 14: /* PADR 32..47 */
2668 case 18: /* CRBAL */
2669 case 19: /* CRBAU */
2670 case 20: /* CXBAL */
2671 case 21: /* CXBAU */
2672 case 22: /* NRBAL */
2673 case 23: /* NRBAU */
2674 case 26: /* NRDAL */
2675 case 27: /* NRDAU */
2676 case 28: /* CRDAL */
2677 case 29: /* CRDAU */
2678 case 32: /* NXDAL */
2679 case 33: /* NXDAU */
2680 case 34: /* CXDAL */
2681 case 35: /* CXDAU */
2682 case 36: /* NNRDL */
2683 case 37: /* NNRDU */
2684 case 38: /* NNXDL */
2685 case 39: /* NNXDU */
2686 case 40: /* CRBCL */
2687 case 41: /* CRBCU */
2688 case 42: /* CXBCL */
2689 case 43: /* CXBCU */
2690 case 44: /* NRBCL */
2691 case 45: /* NRBCU */
2692 case 46: /* POLL */
2693 case 47: /* POLLINT */
2694 case 72: /* RCVRC */
2695 case 74: /* XMTRC */
2696 case 112: /* MISSC */
2697 if (CSR_STOP(pData) || CSR_SPND(pData))
2698 break;
2699 case 3: /* Interrupt Mask and Deferral Control */
2700 break;
2701 case 4: /* Test and Features Control */
2702 pData->aCSR[4] &= ~(val & 0x026a);
2703 val &= ~0x026a;
2704 val |= pData->aCSR[4] & 0x026a;
2705 break;
2706 case 5: /* Extended Control and Interrupt 1 */
2707 pData->aCSR[5] &= ~(val & 0x0a90);
2708 val &= ~0x0a90;
2709 val |= pData->aCSR[5] & 0x0a90;
2710 break;
2711 case 7: /* Extended Control and Interrupt 2 */
2712 {
2713 uint16_t csr7 = pData->aCSR[7];
2714 csr7 &= ~0x0400 ;
2715 csr7 &= ~(val & 0x0800);
2716 csr7 |= (val & 0x0400);
2717 pData->aCSR[7] = csr7;
2718 return rc;
2719 }
2720 case 15: /* Mode */
2721 if ((pData->aCSR[15] & 0x8000) != (val & 0x8000) && pData->pDrv)
2722 {
2723 Log(("#%d: promiscuous mode changed to %d\n", PCNET_INST_NR, !!(val & 0x8000)));
2724#ifndef IN_RING3
2725 return VINF_IOM_HC_IOPORT_WRITE;
2726#else
2727 /* check for promiscuous mode change */
2728 if (pData->pDrv)
2729 pData->pDrv->pfnSetPromiscuousMode(pData->pDrv, !!(val & 0x8000));
2730#endif
2731 }
2732 break;
2733 case 16: /* IADRL */
2734 return pcnetCSRWriteU16(pData, 1, val);
2735 case 17: /* IADRH */
2736 return pcnetCSRWriteU16(pData, 2, val);
2737
2738 /*
2739 * 24 and 25 are the Base Address of Receive Descriptor.
2740 * We combine and mirror these in GCRDRA.
2741 */
2742 case 24: /* BADRL */
2743 case 25: /* BADRU */
2744 if (!CSR_STOP(pData) && !CSR_SPND(pData))
2745 {
2746 Log(("#%d: WRITE CSR%d, %#06x !!\n", PCNET_INST_NR, u32RAP, val));
2747 return rc;
2748 }
2749 if (u32RAP == 24)
2750 pData->GCRDRA = (pData->GCRDRA & 0xffff0000) | (val & 0x0000ffff);
2751 else
2752 pData->GCRDRA = (pData->GCRDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16);
2753 Log(("#%d: WRITE CSR%d, %#06x => GCRDRA=%08x (alt init)\n", PCNET_INST_NR, u32RAP, val, pData->GCRDRA));
2754 break;
2755
2756 /*
2757 * 30 & 31 are the Base Address of Transmit Descriptor.
2758 * We combine and mirrorthese in GCTDRA.
2759 */
2760 case 30: /* BADXL */
2761 case 31: /* BADXU */
2762 if (!CSR_STOP(pData) && !CSR_SPND(pData))
2763 {
2764 Log(("#%d: WRITE CSR%d, %#06x !!\n", PCNET_INST_NR, u32RAP, val));
2765 return rc;
2766 }
2767 if (u32RAP == 30)
2768 pData->GCTDRA = (pData->GCTDRA & 0xffff0000) | (val & 0x0000ffff);
2769 else
2770 pData->GCTDRA = (pData->GCTDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16);
2771 Log(("#%d: WRITE CSR%d, %#06x => GCTDRA=%08x (alt init)\n", PCNET_INST_NR, u32RAP, val, pData->GCTDRA));
2772 break;
2773
2774 case 58: /* Software Style */
2775 rc = pcnetBCRWriteU16(pData, BCR_SWS, val);
2776 break;
2777
2778 /*
2779 * Registers 76 and 78 aren't stored correctly (see todos), but I'm don't dare
2780 * try fix that right now. So, as a quick hack for 'alt init' I'll just correct them here.
2781 */
2782 case 76: /* RCVRL */ /** @todo call pcnetUpdateRingHandlers */
2783 /** @todo receive ring length is stored in two's complement! */
2784 case 78: /* XMTRL */ /** @todo call pcnetUpdateRingHandlers */
2785 /** @todo transmit ring length is stored in two's complement! */
2786 if (!CSR_STOP(pData) && !CSR_SPND(pData))
2787 {
2788 Log(("#%d: WRITE CSR%d, %#06x !!\n", PCNET_INST_NR, u32RAP, val));
2789 return rc;
2790 }
2791 Log(("#%d: WRITE CSR%d, %#06x (hacked %#06x) (alt init)\n", PCNET_INST_NR,
2792 u32RAP, val, 1 + ~(uint16_t)val));
2793 val = 1 + ~(uint16_t)val;
2794
2795 /*
2796 * HACK ALERT! Set the counter registers too.
2797 */
2798 pData->aCSR[u32RAP - 4] = val;
2799 break;
2800
2801 default:
2802 return rc;
2803 }
2804 pData->aCSR[u32RAP] = val;
2805 return rc;
2806}
2807
2808/**
2809 * Encode a 32-bit link speed into a custom 16-bit floating-point value
2810 */
2811static uint32_t pcnetLinkSpd(uint32_t speed)
2812{
2813 unsigned exp = 0;
2814
2815 while (speed & 0xFFFFE000)
2816 {
2817 speed /= 10;
2818 ++exp;
2819 }
2820 return (exp << 13) | speed;
2821}
2822
2823static uint32_t pcnetCSRReadU16(PCNetState *pData, uint32_t u32RAP)
2824{
2825 uint32_t val;
2826 switch (u32RAP)
2827 {
2828 case 0:
2829 pcnetUpdateIrq(pData);
2830 val = pData->aCSR[0];
2831 val |= (val & 0x7800) ? 0x8000 : 0;
2832 pData->u16CSR0LastSeenByGuest = val;
2833 break;
2834 case 16:
2835 return pcnetCSRReadU16(pData, 1);
2836 case 17:
2837 return pcnetCSRReadU16(pData, 2);
2838 case 58:
2839 return pcnetBCRReadU16(pData, BCR_SWS);
2840 case 68: /* Custom register to pass link speed to driver */
2841 return pcnetLinkSpd(pData->u32LinkSpeed);
2842 case 88:
2843 val = pData->aCSR[89];
2844 val <<= 16;
2845 val |= pData->aCSR[88];
2846 break;
2847 default:
2848 val = pData->aCSR[u32RAP];
2849 }
2850#ifdef PCNET_DEBUG_CSR
2851 Log(("#%d pcnetCSRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
2852#endif
2853 return val;
2854}
2855
2856static int pcnetBCRWriteU16(PCNetState *pData, uint32_t u32RAP, uint32_t val)
2857{
2858 int rc = VINF_SUCCESS;
2859 u32RAP &= 0x7f;
2860#ifdef PCNET_DEBUG_BCR
2861 Log2(("#%d pcnetBCRWriteU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
2862#endif
2863 switch (u32RAP)
2864 {
2865 case BCR_SWS:
2866 if (!(CSR_STOP(pData) || CSR_SPND(pData)))
2867 return rc;
2868 val &= ~0x0300;
2869 switch (val & 0x00ff)
2870 {
2871 default:
2872 Log(("#%d Bad SWSTYLE=%#04x\n", PCNET_INST_NR, val & 0xff));
2873 // fall through
2874 case 0:
2875 val |= 0x0200; /* 16 bit */
2876 pData->iLog2DescSize = 3;
2877 pData->GCUpperPhys = (0xff00 & (uint32_t)pData->aCSR[2]) << 16;
2878 break;
2879 case 1:
2880 val |= 0x0100; /* 32 bit */
2881 pData->iLog2DescSize = 4;
2882 pData->GCUpperPhys = 0;
2883 break;
2884 case 2:
2885 case 3:
2886 val |= 0x0300; /* 32 bit */
2887 pData->iLog2DescSize = 4;
2888 pData->GCUpperPhys = 0;
2889 break;
2890 }
2891 Log(("#%d BCR_SWS=%#06x\n", PCNET_INST_NR, val));
2892 pData->aCSR[58] = val;
2893 /* fall through */
2894 case BCR_LNKST:
2895 case BCR_LED1:
2896 case BCR_LED2:
2897 case BCR_LED3:
2898 case BCR_MC:
2899 case BCR_FDC:
2900 case BCR_BSBC:
2901 case BCR_EECAS:
2902 case BCR_PLAT:
2903 case BCR_MIICAS:
2904 case BCR_MIIADDR:
2905 pData->aBCR[u32RAP] = val;
2906 break;
2907
2908 case BCR_STVAL:
2909 val &= 0xffff;
2910 pData->aBCR[BCR_STVAL] = val;
2911 if (pData->fAm79C973)
2912 TMTimerSetNano(pData->CTXSUFF(pTimerSoftInt), 12800U * val);
2913 break;
2914
2915 case BCR_MIIMDR:
2916 pData->aMII[pData->aBCR[BCR_MIIADDR] & 0x1f] = val;
2917#ifdef PCNET_DEBUG_MII
2918 Log(("#%d pcnet: mii write %d <- %#x\n", PCNET_INST_NR, pData->aBCR[BCR_MIIADDR] & 0x1f, val));
2919#endif
2920 break;
2921
2922 default:
2923 break;
2924 }
2925 return rc;
2926}
2927
2928static uint32_t pcnetMIIReadU16(PCNetState *pData, uint32_t miiaddr)
2929{
2930 uint32_t val;
2931 bool autoneg, duplex, fast;
2932 STAM_COUNTER_INC(&pData->StatMIIReads);
2933
2934 autoneg = (pData->aBCR[BCR_MIICAS] & 0x20) != 0;
2935 duplex = (pData->aBCR[BCR_MIICAS] & 0x10) != 0;
2936 fast = (pData->aBCR[BCR_MIICAS] & 0x08) != 0;
2937
2938 switch (miiaddr)
2939 {
2940 case 0:
2941 /* MII basic mode control register. */
2942 val = 0;
2943 if (autoneg)
2944 val |= 0x1000; /* Enable auto negotiation. */
2945 if (fast)
2946 val |= 0x2000; /* 100 Mbps */
2947 if (duplex) /* Full duplex forced */
2948 val |= 0x0100; /* Full duplex */
2949 break;
2950
2951 case 1:
2952 /* MII basic mode status register. */
2953 val = 0x7800 /* Can do 100mbps FD/HD and 10mbps FD/HD. */
2954 | 0x0040 /* Mgmt frame preamble not required. */
2955 | 0x0020 /* Auto-negotiation complete. */
2956 | 0x0008 /* Able to do auto-negotiation. */
2957 | 0x0004 /* Link up. */
2958 | 0x0001; /* Extended Capability, i.e. registers 4+ valid. */
2959 if (!pData->fLinkUp || pData->fLinkTempDown) {
2960 val &= ~(0x0020 | 0x0004);
2961 pData->cLinkDownReported++;
2962 }
2963 if (!autoneg) {
2964 /* Auto-negotiation disabled. */
2965 val &= ~(0x0020 | 0x0008);
2966 if (duplex)
2967 /* Full duplex forced. */
2968 val &= ~0x2800;
2969 else
2970 /* Half duplex forced. */
2971 val &= ~0x5000;
2972
2973 if (fast)
2974 /* 100 Mbps forced */
2975 val &= ~0x1800;
2976 else
2977 /* 10 Mbps forced */
2978 val &= ~0x6000;
2979 }
2980 break;
2981
2982 case 2:
2983 /* PHY identifier 1. */
2984 val = 0x22; /* Am79C874 PHY */
2985 break;
2986
2987 case 3:
2988 /* PHY identifier 2. */
2989 val = 0x561b; /* Am79C874 PHY */
2990 break;
2991
2992 case 4:
2993 /* Advertisement control register. */
2994 val = 0x01e0 /* Try 100mbps FD/HD and 10mbps FD/HD. */
2995#if 0
2996 // Advertising flow control is a) not the default, and b) confuses
2997 // the link speed detection routine in Windows PCnet driver
2998 | 0x0400 /* Try flow control. */
2999#endif
3000 | 0x0001; /* CSMA selector. */
3001 break;
3002
3003 case 5:
3004 /* Link partner ability register. */
3005 if (pData->fLinkUp && !pData->fLinkTempDown)
3006 val = 0x8000 /* Next page bit. */
3007 | 0x4000 /* Link partner acked us. */
3008 | 0x0400 /* Can do flow control. */
3009 | 0x01e0 /* Can do 100mbps FD/HD and 10mbps FD/HD. */
3010 | 0x0001; /* Use CSMA selector. */
3011 else
3012 {
3013 val = 0;
3014 pData->cLinkDownReported++;
3015 }
3016 break;
3017
3018 case 6:
3019 /* Auto negotiation expansion register. */
3020 if (pData->fLinkUp && !pData->fLinkTempDown)
3021 val = 0x0008 /* Link partner supports npage. */
3022 | 0x0004 /* Enable npage words. */
3023 | 0x0001; /* Can do N-way auto-negotiation. */
3024 else
3025 {
3026 val = 0;
3027 pData->cLinkDownReported++;
3028 }
3029 break;
3030
3031 default:
3032 val = 0;
3033 break;
3034 }
3035
3036#ifdef PCNET_DEBUG_MII
3037 Log(("#%d pcnet: mii read %d -> %#x\n", PCNET_INST_NR, miiaddr, val));
3038#endif
3039 return val;
3040}
3041
3042static uint32_t pcnetBCRReadU16(PCNetState *pData, uint32_t u32RAP)
3043{
3044 uint32_t val;
3045 u32RAP &= 0x7f;
3046 switch (u32RAP)
3047 {
3048 case BCR_LNKST:
3049 case BCR_LED1:
3050 case BCR_LED2:
3051 case BCR_LED3:
3052 val = pData->aBCR[u32RAP] & ~0x8000;
3053 /* Clear LNKSTE if we're not connected or if we've just loaded a VM state. */
3054 if (!pData->pDrv || pData->fLinkTempDown || !pData->fLinkUp)
3055 {
3056 if (u32RAP == 4)
3057 pData->cLinkDownReported++;
3058 val &= ~0x40;
3059 }
3060 val |= (val & 0x017f & pData->u32Lnkst) ? 0x8000 : 0;
3061 break;
3062
3063 case BCR_MIIMDR:
3064 if (pData->fAm79C973 && (pData->aBCR[BCR_MIIADDR] >> 5 & 0x1f) == 0)
3065 {
3066 uint32_t miiaddr = pData->aBCR[BCR_MIIADDR] & 0x1f;
3067 val = pcnetMIIReadU16(pData, miiaddr);
3068 }
3069 else
3070 val = 0xffff;
3071 break;
3072
3073 default:
3074 val = u32RAP < BCR_MAX_RAP ? pData->aBCR[u32RAP] : 0;
3075 break;
3076 }
3077#ifdef PCNET_DEBUG_BCR
3078 Log2(("#%d pcnetBCRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
3079#endif
3080 return val;
3081}
3082
3083#ifdef IN_RING3 /* move down */
3084static void pcnetHardReset(PCNetState *pData)
3085{
3086 int i;
3087 uint16_t checksum;
3088
3089 /* Initialize the PROM */
3090 Assert(sizeof(pData->MacConfigured) == 6);
3091 memcpy(pData->aPROM, &pData->MacConfigured, sizeof(pData->MacConfigured));
3092 pData->aPROM[ 8] = 0x00;
3093 pData->aPROM[ 9] = 0x11;
3094 pData->aPROM[12] = pData->aPROM[13] = 0x00;
3095 pData->aPROM[14] = pData->aPROM[15] = 0x57;
3096
3097 for (i = 0, checksum = 0; i < 16; i++)
3098 checksum += pData->aPROM[i];
3099 *(uint16_t *)&pData->aPROM[12] = RT_H2LE_U16(checksum);
3100
3101 pData->aBCR[BCR_MSRDA] = 0x0005;
3102 pData->aBCR[BCR_MSWRA] = 0x0005;
3103 pData->aBCR[BCR_MC ] = 0x0002;
3104 pData->aBCR[BCR_LNKST] = 0x00c0;
3105 pData->aBCR[BCR_LED1 ] = 0x0084;
3106 pData->aBCR[BCR_LED2 ] = 0x0088;
3107 pData->aBCR[BCR_LED3 ] = 0x0090;
3108 pData->aBCR[BCR_FDC ] = 0x0000;
3109 pData->aBCR[BCR_BSBC ] = 0x9001;
3110 pData->aBCR[BCR_EECAS] = 0x0002;
3111 pData->aBCR[BCR_STVAL] = 0xffff;
3112 pData->aCSR[58 ] = /* CSR58 is an alias for BCR20 */
3113 pData->aBCR[BCR_SWS ] = 0x0200;
3114 pData->iLog2DescSize = 3;
3115 pData->aBCR[BCR_PLAT ] = 0xff06;
3116 pData->aBCR[BCR_MIIADDR ] = 0; /* Internal PHY on Am79C973 would be (0x1e << 5) */
3117 pData->aBCR[BCR_PCIVID] = PCIDevGetVendorId(&pData->PciDev);
3118 pData->aBCR[BCR_PCISID] = PCIDevGetSubSystemId(&pData->PciDev);
3119 pData->aBCR[BCR_PCISVID] = PCIDevGetSubSystemVendorId(&pData->PciDev);
3120
3121 pcnetSoftReset(pData);
3122}
3123#endif /* IN_RING3 */
3124
3125static void pcnetAPROMWriteU8(PCNetState *pData, uint32_t addr, uint32_t val)
3126{
3127 addr &= 0x0f;
3128 val &= 0xff;
3129 Log(("#%d pcnetAPROMWriteU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val));
3130 /* Check APROMWE bit to enable write access */
3131 if (pcnetBCRReadU16(pData, 2) & 0x80)
3132 pData->aPROM[addr] = val;
3133}
3134
3135static uint32_t pcnetAPROMReadU8(PCNetState *pData, uint32_t addr)
3136{
3137 uint32_t val = pData->aPROM[addr &= 0x0f];
3138 Log(("#%d pcnetAPROMReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val));
3139 return val;
3140}
3141
3142static int pcnetIoportWriteU16(PCNetState *pData, uint32_t addr, uint32_t val)
3143{
3144 int rc = VINF_SUCCESS;
3145
3146#ifdef PCNET_DEBUG_IO
3147 Log2(("#%d pcnetIoportWriteU16: addr=%#010x val=%#06x\n", PCNET_INST_NR,
3148 addr, val));
3149#endif
3150 if (RT_LIKELY(!BCR_DWIO(pData)))
3151 {
3152 switch (addr & 0x0f)
3153 {
3154 case 0x00: /* RDP */
3155 pcnetPollTimer(pData);
3156 rc = pcnetCSRWriteU16(pData, pData->u32RAP, val);
3157 pcnetUpdateIrq(pData);
3158 break;
3159 case 0x02: /* RAP */
3160 pData->u32RAP = val & 0x7f;
3161 break;
3162 case 0x06: /* BDP */
3163 rc = pcnetBCRWriteU16(pData, pData->u32RAP, val);
3164 break;
3165 }
3166 }
3167 else
3168 Log(("#%d pcnetIoportWriteU16: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val));
3169
3170 return rc;
3171}
3172
3173static uint32_t pcnetIoportReadU16(PCNetState *pData, uint32_t addr, int *pRC)
3174{
3175 uint32_t val = ~0U;
3176
3177 *pRC = VINF_SUCCESS;
3178
3179 if (RT_LIKELY(!BCR_DWIO(pData)))
3180 {
3181 switch (addr & 0x0f)
3182 {
3183 case 0x00: /* RDP */
3184 /** @note if we're not polling, then the guest will tell us when to poll by setting TDMD in CSR0 */
3185 /** Polling is then useless here and possibly expensive. */
3186 if (!CSR_DPOLL(pData))
3187 pcnetPollTimer(pData);
3188
3189 val = pcnetCSRReadU16(pData, pData->u32RAP);
3190 if (pData->u32RAP == 0) // pcnetUpdateIrq() already called by pcnetCSRReadU16()
3191 goto skip_update_irq;
3192 break;
3193 case 0x02: /* RAP */
3194 val = pData->u32RAP;
3195 goto skip_update_irq;
3196 case 0x04: /* RESET */
3197 pcnetSoftReset(pData);
3198 val = 0;
3199 break;
3200 case 0x06: /* BDP */
3201 val = pcnetBCRReadU16(pData, pData->u32RAP);
3202 break;
3203 }
3204 }
3205 else
3206 Log(("#%d pcnetIoportReadU16: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val & 0xffff));
3207
3208 pcnetUpdateIrq(pData);
3209
3210skip_update_irq:
3211#ifdef PCNET_DEBUG_IO
3212 Log2(("#%d pcnetIoportReadU16: addr=%#010x val=%#06x\n", PCNET_INST_NR, addr, val & 0xffff));
3213#endif
3214 return val;
3215}
3216
3217static int pcnetIoportWriteU32(PCNetState *pData, uint32_t addr, uint32_t val)
3218{
3219 int rc = VINF_SUCCESS;
3220
3221#ifdef PCNET_DEBUG_IO
3222 Log2(("#%d pcnetIoportWriteU32: addr=%#010x val=%#010x\n", PCNET_INST_NR,
3223 addr, val));
3224#endif
3225 if (RT_LIKELY(BCR_DWIO(pData)))
3226 {
3227 switch (addr & 0x0f)
3228 {
3229 case 0x00: /* RDP */
3230 pcnetPollTimer(pData);
3231 rc = pcnetCSRWriteU16(pData, pData->u32RAP, val & 0xffff);
3232 pcnetUpdateIrq(pData);
3233 break;
3234 case 0x04: /* RAP */
3235 pData->u32RAP = val & 0x7f;
3236 break;
3237 case 0x0c: /* BDP */
3238 rc = pcnetBCRWriteU16(pData, pData->u32RAP, val & 0xffff);
3239 break;
3240 }
3241 }
3242 else if ((addr & 0x0f) == 0)
3243 {
3244 /* switch device to dword I/O mode */
3245 pcnetBCRWriteU16(pData, BCR_BSBC, pcnetBCRReadU16(pData, BCR_BSBC) | 0x0080);
3246#ifdef PCNET_DEBUG_IO
3247 Log2(("device switched into dword i/o mode\n"));
3248#endif
3249 }
3250 else
3251 Log(("#%d pcnetIoportWriteU32: addr=%#010x val=%#010x !BCR_DWIO !!\n", PCNET_INST_NR, addr, val));
3252
3253 return rc;
3254}
3255
3256static uint32_t pcnetIoportReadU32(PCNetState *pData, uint32_t addr, int *pRC)
3257{
3258 uint32_t val = ~0U;
3259
3260 *pRC = VINF_SUCCESS;
3261
3262 if (RT_LIKELY(BCR_DWIO(pData)))
3263 {
3264 switch (addr & 0x0f)
3265 {
3266 case 0x00: /* RDP */
3267 /** @note if we're not polling, then the guest will tell us when to poll by setting TDMD in CSR0 */
3268 /** Polling is then useless here and possibly expensive. */
3269 if (!CSR_DPOLL(pData))
3270 pcnetPollTimer(pData);
3271
3272 val = pcnetCSRReadU16(pData, pData->u32RAP);
3273 if (pData->u32RAP == 0) // pcnetUpdateIrq() already called by pcnetCSRReadU16()
3274 goto skip_update_irq;
3275 break;
3276 case 0x04: /* RAP */
3277 val = pData->u32RAP;
3278 goto skip_update_irq;
3279 case 0x08: /* RESET */
3280 pcnetSoftReset(pData);
3281 val = 0;
3282 break;
3283 case 0x0c: /* BDP */
3284 val = pcnetBCRReadU16(pData, pData->u32RAP);
3285 break;
3286 }
3287 }
3288 else
3289 Log(("#%d pcnetIoportReadU32: addr=%#010x val=%#010x !BCR_DWIO !!\n", PCNET_INST_NR, addr, val));
3290 pcnetUpdateIrq(pData);
3291
3292skip_update_irq:
3293#ifdef PCNET_DEBUG_IO
3294 Log2(("#%d pcnetIoportReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val));
3295#endif
3296 return val;
3297}
3298
3299static void pcnetMMIOWriteU8(PCNetState *pData, RTGCPHYS addr, uint32_t val)
3300{
3301#ifdef PCNET_DEBUG_IO
3302 Log2(("#%d pcnetMMIOWriteU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val));
3303#endif
3304 if (!(addr & 0x10))
3305 pcnetAPROMWriteU8(pData, addr, val);
3306}
3307
3308static uint32_t pcnetMMIOReadU8(PCNetState *pData, RTGCPHYS addr)
3309{
3310 uint32_t val = ~0U;
3311 if (!(addr & 0x10))
3312 val = pcnetAPROMReadU8(pData, addr);
3313#ifdef PCNET_DEBUG_IO
3314 Log2(("#%d pcnetMMIOReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val & 0xff));
3315#endif
3316 return val;
3317}
3318
3319static void pcnetMMIOWriteU16(PCNetState *pData, RTGCPHYS addr, uint32_t val)
3320{
3321#ifdef PCNET_DEBUG_IO
3322 Log2(("#%d pcnetMMIOWriteU16: addr=%#010x val=%#06x\n", PCNET_INST_NR, addr, val));
3323#endif
3324 if (addr & 0x10)
3325 pcnetIoportWriteU16(pData, addr & 0x0f, val);
3326 else
3327 {
3328 pcnetAPROMWriteU8(pData, addr, val );
3329 pcnetAPROMWriteU8(pData, addr+1, val >> 8);
3330 }
3331}
3332
3333static uint32_t pcnetMMIOReadU16(PCNetState *pData, RTGCPHYS addr)
3334{
3335 uint32_t val = ~0U;
3336 int rc;
3337
3338 if (addr & 0x10)
3339 val = pcnetIoportReadU16(pData, addr & 0x0f, &rc);
3340 else
3341 {
3342 val = pcnetAPROMReadU8(pData, addr+1);
3343 val <<= 8;
3344 val |= pcnetAPROMReadU8(pData, addr);
3345 }
3346#ifdef PCNET_DEBUG_IO
3347 Log2(("#%d pcnetMMIOReadU16: addr=%#010x val = %#06x\n", PCNET_INST_NR, addr, val & 0xffff));
3348#endif
3349 return val;
3350}
3351
3352static void pcnetMMIOWriteU32(PCNetState *pData, RTGCPHYS addr, uint32_t val)
3353{
3354#ifdef PCNET_DEBUG_IO
3355 Log2(("#%d pcnetMMIOWriteU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val));
3356#endif
3357 if (addr & 0x10)
3358 pcnetIoportWriteU32(pData, addr & 0x0f, val);
3359 else
3360 {
3361 pcnetAPROMWriteU8(pData, addr, val );
3362 pcnetAPROMWriteU8(pData, addr+1, val >> 8);
3363 pcnetAPROMWriteU8(pData, addr+2, val >> 16);
3364 pcnetAPROMWriteU8(pData, addr+3, val >> 24);
3365 }
3366}
3367
3368static uint32_t pcnetMMIOReadU32(PCNetState *pData, RTGCPHYS addr)
3369{
3370 uint32_t val;
3371 int rc;
3372
3373 if (addr & 0x10)
3374 val = pcnetIoportReadU32(pData, addr & 0x0f, &rc);
3375 else
3376 {
3377 val = pcnetAPROMReadU8(pData, addr+3);
3378 val <<= 8;
3379 val |= pcnetAPROMReadU8(pData, addr+2);
3380 val <<= 8;
3381 val |= pcnetAPROMReadU8(pData, addr+1);
3382 val <<= 8;
3383 val |= pcnetAPROMReadU8(pData, addr );
3384 }
3385#ifdef PCNET_DEBUG_IO
3386 Log2(("#%d pcnetMMIOReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val));
3387#endif
3388 return val;
3389}
3390
3391
3392/**
3393 * Port I/O Handler for IN operations.
3394 *
3395 * @returns VBox status code.
3396 *
3397 * @param pDevIns The device instance.
3398 * @param pvUser User argument.
3399 * @param Port Port number used for the IN operation.
3400 * @param pu32 Where to store the result.
3401 * @param cb Number of bytes read.
3402 */
3403PDMBOTHCBDECL(int) pcnetIOPortAPromRead(PPDMDEVINS pDevIns, void *pvUser,
3404 RTIOPORT Port, uint32_t *pu32, unsigned cb)
3405{
3406 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
3407 int rc;
3408
3409 STAM_PROFILE_ADV_START(&pData->StatAPROMRead, a);
3410 rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_IOPORT_WRITE);
3411 if (rc == VINF_SUCCESS)
3412 {
3413
3414 /* FreeBSD is accessing in dwords. */
3415 if (cb == 1)
3416 *pu32 = pcnetAPROMReadU8(pData, Port);
3417 else if (cb == 2 && !BCR_DWIO(pData))
3418 *pu32 = pcnetAPROMReadU8(pData, Port)
3419 | (pcnetAPROMReadU8(pData, Port + 1) << 8);
3420 else if (cb == 4 && BCR_DWIO(pData))
3421 *pu32 = pcnetAPROMReadU8(pData, Port)
3422 | (pcnetAPROMReadU8(pData, Port + 1) << 8)
3423 | (pcnetAPROMReadU8(pData, Port + 2) << 16)
3424 | (pcnetAPROMReadU8(pData, Port + 3) << 24);
3425 else
3426 {
3427 Log(("#%d pcnetIOPortAPromRead: Port=%RTiop cb=%d BCR_DWIO !!\n", PCNET_INST_NR, Port, cb));
3428 rc = VERR_IOM_IOPORT_UNUSED;
3429 }
3430 PDMCritSectLeave(&pData->CritSect);
3431 }
3432 STAM_PROFILE_ADV_STOP(&pData->StatAPROMRead, a);
3433 LogFlow(("#%d pcnetIOPortAPromRead: Port=%RTiop *pu32=%#RX32 cb=%d rc=%Vrc\n", PCNET_INST_NR, Port, *pu32, cb, rc));
3434 return rc;
3435}
3436
3437
3438/**
3439 * Port I/O Handler for OUT operations.
3440 *
3441 * @returns VBox status code.
3442 *
3443 * @param pDevIns The device instance.
3444 * @param pvUser User argument.
3445 * @param Port Port number used for the IN operation.
3446 * @param u32 The value to output.
3447 * @param cb The value size in bytes.
3448 */
3449PDMBOTHCBDECL(int) pcnetIOPortAPromWrite(PPDMDEVINS pDevIns, void *pvUser,
3450 RTIOPORT Port, uint32_t u32, unsigned cb)
3451{
3452 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
3453 int rc;
3454
3455 if (cb == 1)
3456 {
3457 STAM_PROFILE_ADV_START(&pData->StatAPROMWrite, a);
3458 rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_IOPORT_WRITE);
3459 if (RT_LIKELY(rc == VINF_SUCCESS))
3460 {
3461 pcnetAPROMWriteU8(pData, Port, u32);
3462 PDMCritSectLeave(&pData->CritSect);
3463 }
3464 STAM_PROFILE_ADV_STOP(&pData->StatAPROMWrite, a);
3465 }
3466 else
3467 {
3468 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
3469 rc = VINF_SUCCESS;
3470 }
3471 LogFlow(("#%d pcnetIOPortAPromWrite: Port=%RTiop u32=%#RX32 cb=%d rc=%Vrc\n", PCNET_INST_NR, Port, u32, cb, rc));
3472#ifdef LOG_ENABLED
3473 if (rc == VINF_IOM_HC_IOPORT_WRITE)
3474 LogFlow(("#%d => HC\n", PCNET_INST_NR));
3475#endif
3476 return rc;
3477}
3478
3479
3480/**
3481 * Port I/O Handler for IN operations.
3482 *
3483 * @returns VBox status code.
3484 *
3485 * @param pDevIns The device instance.
3486 * @param pvUser User argument.
3487 * @param Port Port number used for the IN operation.
3488 * @param pu32 Where to store the result.
3489 * @param cb Number of bytes read.
3490 */
3491PDMBOTHCBDECL(int) pcnetIOPortRead(PPDMDEVINS pDevIns, void *pvUser,
3492 RTIOPORT Port, uint32_t *pu32, unsigned cb)
3493{
3494 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
3495 int rc = VINF_SUCCESS;
3496
3497 STAM_PROFILE_ADV_START(&pData->CTXSUFF(StatIORead), a);
3498 rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_IOPORT_READ);
3499 if (RT_LIKELY(rc == VINF_SUCCESS))
3500 {
3501 switch (cb)
3502 {
3503 case 2: *pu32 = pcnetIoportReadU16(pData, Port, &rc); break;
3504 case 4: *pu32 = pcnetIoportReadU32(pData, Port, &rc); break;
3505 default:
3506 rc = VERR_IOM_IOPORT_UNUSED;
3507 break;
3508 }
3509 PDMCritSectLeave(&pData->CritSect);
3510 }
3511 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatIORead), a);
3512 Log2(("#%d pcnetIOPortRead: Port=%RTiop *pu32=%#RX32 cb=%d rc=%Vrc\n", PCNET_INST_NR, Port, *pu32, cb, rc));
3513#ifdef LOG_ENABLED
3514 if (rc == VINF_IOM_HC_IOPORT_READ)
3515 LogFlow(("#%d pcnetIOPortRead/critsect failed in GC => HC\n", PCNET_INST_NR));
3516#endif
3517 return rc;
3518}
3519
3520
3521/**
3522 * Port I/O Handler for OUT operations.
3523 *
3524 * @returns VBox status code.
3525 *
3526 * @param pDevIns The device instance.
3527 * @param pvUser User argument.
3528 * @param Port Port number used for the IN operation.
3529 * @param u32 The value to output.
3530 * @param cb The value size in bytes.
3531 */
3532PDMBOTHCBDECL(int) pcnetIOPortWrite(PPDMDEVINS pDevIns, void *pvUser,
3533 RTIOPORT Port, uint32_t u32, unsigned cb)
3534{
3535 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
3536 int rc = VINF_SUCCESS;
3537
3538 STAM_PROFILE_ADV_START(&pData->CTXSUFF(StatIOWrite), a);
3539 rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_IOPORT_WRITE);
3540 if (RT_LIKELY(rc == VINF_SUCCESS))
3541 {
3542 switch (cb)
3543 {
3544 case 2: rc = pcnetIoportWriteU16(pData, Port, u32); break;
3545 case 4: rc = pcnetIoportWriteU32(pData, Port, u32); break;
3546 default:
3547 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
3548 rc = VERR_INTERNAL_ERROR;
3549 break;
3550 }
3551 PDMCritSectLeave(&pData->CritSect);
3552 }
3553 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatIOWrite), a);
3554 Log2(("#%d pcnetIOPortWrite: Port=%RTiop u32=%#RX32 cb=%d rc=%Vrc\n", PCNET_INST_NR, Port, u32, cb, rc));
3555#ifdef LOG_ENABLED
3556 if (rc == VINF_IOM_HC_IOPORT_WRITE)
3557 LogFlow(("#%d pcnetIOPortWrite/critsect failed in GC => HC\n", PCNET_INST_NR));
3558#endif
3559 return rc;
3560}
3561
3562
3563/**
3564 * Memory mapped I/O Handler for read operations.
3565 *
3566 * @returns VBox status code.
3567 *
3568 * @param pDevIns The device instance.
3569 * @param pvUser User argument.
3570 * @param GCPhysAddr Physical address (in GC) where the read starts.
3571 * @param pv Where to store the result.
3572 * @param cb Number of bytes read.
3573 */
3574PDMBOTHCBDECL(int) pcnetMMIORead(PPDMDEVINS pDevIns, void *pvUser,
3575 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3576{
3577 PCNetState *pData = (PCNetState *)pvUser;
3578 int rc = VINF_SUCCESS;
3579
3580 /*
3581 * We have to check the range, because we're page aligning the MMIO stuff presently.
3582 */
3583 if (GCPhysAddr - pData->MMIOBase < PCNET_PNPMMIO_SIZE)
3584 {
3585 STAM_PROFILE_ADV_START(&pData->CTXSUFF(StatMMIORead), a);
3586 rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_MMIO_READ);
3587 if (RT_LIKELY(rc == VINF_SUCCESS))
3588 {
3589 switch (cb)
3590 {
3591 case 1: *(uint8_t *)pv = pcnetMMIOReadU8 (pData, GCPhysAddr); break;
3592 case 2: *(uint16_t *)pv = pcnetMMIOReadU16(pData, GCPhysAddr); break;
3593 case 4: *(uint32_t *)pv = pcnetMMIOReadU32(pData, GCPhysAddr); break;
3594 default:
3595 AssertMsgFailed(("cb=%d\n", cb));
3596 rc = VERR_INTERNAL_ERROR;
3597 break;
3598 }
3599 PDMCritSectLeave(&pData->CritSect);
3600 }
3601 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatMMIORead), a);
3602 }
3603 else
3604 memset(pv, 0, cb);
3605
3606 LogFlow(("#%d pcnetMMIORead: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Vrc\n",
3607 PCNET_INST_NR, pv, cb, pv, cb, GCPhysAddr, rc));
3608#ifdef LOG_ENABLED
3609 if (rc == VINF_IOM_HC_MMIO_READ)
3610 LogFlow(("#%d => HC\n", PCNET_INST_NR));
3611#endif
3612 return rc;
3613}
3614
3615
3616/**
3617 * Port I/O Handler for write operations.
3618 *
3619 * @returns VBox status code.
3620 *
3621 * @param pDevIns The device instance.
3622 * @param pvUser User argument.
3623 * @param GCPhysAddr Physical address (in GC) where the read starts.
3624 * @param pv Where to fetch the result.
3625 * @param cb Number of bytes to write.
3626 */
3627PDMBOTHCBDECL(int) pcnetMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,
3628 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3629{
3630 PCNetState *pData = (PCNetState *)pvUser;
3631 int rc = VINF_SUCCESS;
3632
3633 /*
3634 * We have to check the range, because we're page aligning the MMIO stuff presently.
3635 */
3636 if (GCPhysAddr - pData->MMIOBase < PCNET_PNPMMIO_SIZE)
3637 {
3638 STAM_PROFILE_ADV_START(&pData->CTXSUFF(StatMMIOWrite), a);
3639 rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_MMIO_WRITE);
3640 if (RT_LIKELY(rc == VINF_SUCCESS))
3641 {
3642 switch (cb)
3643 {
3644 case 1: pcnetMMIOWriteU8 (pData, GCPhysAddr, *(uint8_t *)pv); break;
3645 case 2: pcnetMMIOWriteU16(pData, GCPhysAddr, *(uint16_t *)pv); break;
3646 case 4: pcnetMMIOWriteU32(pData, GCPhysAddr, *(uint32_t *)pv); break;
3647 default:
3648 AssertMsgFailed(("cb=%d\n", cb));
3649 rc = VERR_INTERNAL_ERROR;
3650 break;
3651 }
3652 PDMCritSectLeave(&pData->CritSect);
3653 }
3654 // else rc == VINF_IOM_HC_MMIO_WRITE => handle in ring3
3655
3656 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatMMIOWrite), a);
3657 }
3658 LogFlow(("#%d pcnetMMIOWrite: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Vrc\n",
3659 PCNET_INST_NR, pv, cb, pv, cb, GCPhysAddr, rc));
3660#ifdef LOG_ENABLED
3661 if (rc == VINF_IOM_HC_MMIO_WRITE)
3662 LogFlow(("#%d => HC\n", PCNET_INST_NR));
3663#endif
3664 return rc;
3665}
3666
3667
3668#ifdef IN_RING3
3669/**
3670 * Device timer callback function.
3671 *
3672 * @param pDevIns Device instance of the device which registered the timer.
3673 * @param pTimer The timer handle.
3674 * @thread EMT
3675 */
3676static DECLCALLBACK(void) pcnetTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
3677{
3678 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
3679 int rc;
3680
3681 STAM_PROFILE_ADV_START(&pData->StatTimer, a);
3682 rc = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
3683 AssertReleaseRC(rc);
3684
3685 pcnetPollTimer(pData);
3686
3687 PDMCritSectLeave(&pData->CritSect);
3688 STAM_PROFILE_ADV_STOP(&pData->StatTimer, a);
3689}
3690
3691
3692/**
3693 * Software interrupt timer callback function.
3694 *
3695 * @param pDevIns Device instance of the device which registered the timer.
3696 * @param pTimer The timer handle.
3697 * @thread EMT
3698 */
3699static DECLCALLBACK(void) pcnetTimerSoftInt(PPDMDEVINS pDevIns, PTMTIMER pTimer)
3700{
3701 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
3702
3703 pData->aCSR[7] |= 0x0800; /* STINT */
3704 pcnetUpdateIrq(pData);
3705 TMTimerSetNano(pData->CTXSUFF(pTimerSoftInt), 12800U * (pData->aBCR[BCR_STVAL] & 0xffff));
3706}
3707
3708
3709/**
3710 * Restore timer callback.
3711 *
3712 * This is only called when've restored a saved state and temporarily
3713 * disconnected the network link to inform the guest that network connections
3714 * should be considered lost.
3715 *
3716 * @param pDevIns Device instance of the device which registered the timer.
3717 * @param pTimer The timer handle.
3718 */
3719static DECLCALLBACK(void) pcnetTimerRestore(PPDMDEVINS pDevIns, PTMTIMER pTimer)
3720{
3721 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
3722 int rc = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
3723 AssertReleaseRC(rc);
3724
3725 rc = VERR_GENERAL_FAILURE;
3726 if (pData->cLinkDownReported <= PCNET_MAX_LINKDOWN_REPORTED)
3727 rc = TMTimerSetMillies(pData->pTimerRestore, 1500);
3728 if (VBOX_FAILURE(rc))
3729 {
3730 pData->fLinkTempDown = false;
3731 if (pData->fLinkUp)
3732 {
3733 LogRel(("PCNet#%d: The link is back up again after the restore.\n",
3734 pDevIns->iInstance));
3735 Log(("#%d pcnetTimerRestore: Clearing ERR and CERR after load. cLinkDownReported=%d\n",
3736 pDevIns->iInstance, pData->cLinkDownReported));
3737 pData->aCSR[0] &= ~(RT_BIT(15) | RT_BIT(13)); /* ERR | CERR - probably not 100% correct either... */
3738 pData->Led.Actual.s.fError = 0;
3739 }
3740 }
3741 else
3742 Log(("#%d pcnetTimerRestore: cLinkDownReported=%d, wait another 1500ms...\n",
3743 pDevIns->iInstance, pData->cLinkDownReported));
3744
3745 PDMCritSectLeave(&pData->CritSect);
3746}
3747
3748
3749/**
3750 * Callback function for mapping an PCI I/O region.
3751 *
3752 * @return VBox status code.
3753 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
3754 * @param iRegion The region number.
3755 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
3756 * I/O port, else it's a physical address.
3757 * This address is *NOT* relative to pci_mem_base like earlier!
3758 * @param cb Region size.
3759 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3760 */
3761static DECLCALLBACK(int) pcnetIOPortMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion,
3762 RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3763{
3764 int rc;
3765 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3766 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3767 PCNetState *pData = PCIDEV_2_PCNETSTATE(pPciDev);
3768
3769 Assert(enmType == PCI_ADDRESS_SPACE_IO);
3770 Assert(cb >= 0x20);
3771
3772 rc = PDMDevHlpIOPortRegister(pDevIns, Port, 0x10, 0, pcnetIOPortAPromWrite,
3773 pcnetIOPortAPromRead, NULL, NULL, "PCNet ARPOM");
3774 if (VBOX_FAILURE(rc))
3775 return rc;
3776 rc = PDMDevHlpIOPortRegister(pDevIns, Port + 0x10, 0x10, 0, pcnetIOPortWrite,
3777 pcnetIOPortRead, NULL, NULL, "PCNet");
3778 if (VBOX_FAILURE(rc))
3779 return rc;
3780
3781 if (pData->fGCEnabled)
3782 {
3783 rc = PDMDevHlpIOPortRegisterGC(pDevIns, Port, 0x10, 0, "pcnetIOPortAPromWrite",
3784 "pcnetIOPortAPromRead", NULL, NULL, "PCNet aprom");
3785 if (VBOX_FAILURE(rc))
3786 return rc;
3787 rc = PDMDevHlpIOPortRegisterGC(pDevIns, Port + 0x10, 0x10, 0, "pcnetIOPortWrite",
3788 "pcnetIOPortRead", NULL, NULL, "PCNet");
3789 if (VBOX_FAILURE(rc))
3790 return rc;
3791 }
3792 if (pData->fR0Enabled)
3793 {
3794 rc = PDMDevHlpIOPortRegisterR0(pDevIns, Port, 0x10, 0, "pcnetIOPortAPromWrite",
3795 "pcnetIOPortAPromRead", NULL, NULL, "PCNet aprom");
3796 if (VBOX_FAILURE(rc))
3797 return rc;
3798 rc = PDMDevHlpIOPortRegisterR0(pDevIns, Port + 0x10, 0x10, 0, "pcnetIOPortWrite",
3799 "pcnetIOPortRead", NULL, NULL, "PCNet");
3800 if (VBOX_FAILURE(rc))
3801 return rc;
3802 }
3803
3804 pData->IOPortBase = Port;
3805 return VINF_SUCCESS;
3806}
3807
3808
3809/**
3810 * Callback function for mapping the MMIO region.
3811 *
3812 * @return VBox status code.
3813 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
3814 * @param iRegion The region number.
3815 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
3816 * I/O port, else it's a physical address.
3817 * This address is *NOT* relative to pci_mem_base like earlier!
3818 * @param cb Region size.
3819 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3820 */
3821static DECLCALLBACK(int) pcnetMMIOMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion,
3822 RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3823{
3824 PCNetState *pData = PCIDEV_2_PCNETSTATE(pPciDev);
3825 int rc;
3826
3827 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3828 Assert(cb >= PCNET_PNPMMIO_SIZE);
3829
3830 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
3831 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, pData,
3832 pcnetMMIOWrite, pcnetMMIORead, NULL, "PCNet");
3833 if (VBOX_FAILURE(rc))
3834 return rc;
3835 pData->MMIOBase = GCPhysAddress;
3836 return rc;
3837}
3838
3839
3840/**
3841 * Callback function for mapping the MMIO region.
3842 *
3843 * @return VBox status code.
3844 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
3845 * @param iRegion The region number.
3846 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
3847 * I/O port, else it's a physical address.
3848 * This address is *NOT* relative to pci_mem_base like earlier!
3849 * @param cb Region size.
3850 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3851 */
3852static DECLCALLBACK(int) pcnetMMIOSharedMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion,
3853 RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3854{
3855 if (GCPhysAddress != NIL_RTGCPHYS)
3856 return PDMDevHlpMMIO2Map(pPciDev->pDevIns, iRegion, GCPhysAddress);
3857
3858 /* nothing to clean up */
3859 return VINF_SUCCESS;
3860}
3861
3862
3863/**
3864 * PCNET status info callback.
3865 *
3866 * @param pDevIns The device instance.
3867 * @param pHlp The output helpers.
3868 * @param pszArgs The arguments.
3869 */
3870static DECLCALLBACK(void) pcnetInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3871{
3872 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
3873 bool fRcvRing = false;
3874 bool fXmtRing = false;
3875
3876 /*
3877 * Parse args.
3878 */
3879 if (pszArgs)
3880 {
3881 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
3882 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
3883 }
3884
3885 /*
3886 * Show info.
3887 */
3888 pHlp->pfnPrintf(pHlp,
3889 "pcnet #%d: port=%RTiop mmio=%RGp mac-cfg=%.*Rhxs %s\n",
3890 pDevIns->iInstance,
3891 pData->IOPortBase, pData->MMIOBase, sizeof(pData->MacConfigured), &pData->MacConfigured,
3892 pData->fAm79C973 ? "Am79C973" : "Am79C970A", pData->fGCEnabled ? " GC" : "", pData->fR0Enabled ? " R0" : "");
3893
3894 PDMCritSectEnter(&pData->CritSect, VERR_INTERNAL_ERROR); /* Take it here so we know why we're hanging... */
3895
3896 pHlp->pfnPrintf(pHlp,
3897 "CSR0=%#06x:\n",
3898 pData->aCSR[0]);
3899
3900 pHlp->pfnPrintf(pHlp,
3901 "CSR1=%#06x:\n",
3902 pData->aCSR[1]);
3903
3904 pHlp->pfnPrintf(pHlp,
3905 "CSR2=%#06x:\n",
3906 pData->aCSR[2]);
3907
3908 pHlp->pfnPrintf(pHlp,
3909 "CSR3=%#06x: BSWP=%d EMBA=%d DXMT2PD=%d LAPPEN=%d DXSUFLO=%d IDONM=%d TINTM=%d RINTM=%d MERRM=%d MISSM=%d BABLM=%d\n",
3910 pData->aCSR[3],
3911 !!(pData->aCSR[3] & RT_BIT(2)), !!(pData->aCSR[3] & RT_BIT(3)), !!(pData->aCSR[3] & RT_BIT(4)), CSR_LAPPEN(pData),
3912 CSR_DXSUFLO(pData), !!(pData->aCSR[3] & RT_BIT(8)), !!(pData->aCSR[3] & RT_BIT(9)), !!(pData->aCSR[3] & RT_BIT(10)),
3913 !!(pData->aCSR[3] & RT_BIT(11)), !!(pData->aCSR[3] & RT_BIT(12)), !!(pData->aCSR[3] & RT_BIT(14)));
3914
3915 pHlp->pfnPrintf(pHlp,
3916 "CSR4=%#06x: JABM=%d JAB=%d TXSTRM=%d TXSTRT=%d RCVCOOM=%d RCVCCO=%d UINT=%d UINTCMD=%d\n"
3917 " MFCOM=%d MFCO=%d ASTRP_RCV=%d APAD_XMT=%d DPOLL=%d TIMER=%d EMAPLUS=%d EN124=%d\n",
3918 pData->aCSR[4],
3919 !!(pData->aCSR[4] & RT_BIT( 0)), !!(pData->aCSR[4] & RT_BIT( 1)), !!(pData->aCSR[4] & RT_BIT( 2)), !!(pData->aCSR[4] & RT_BIT( 3)),
3920 !!(pData->aCSR[4] & RT_BIT( 4)), !!(pData->aCSR[4] & RT_BIT( 5)), !!(pData->aCSR[4] & RT_BIT( 6)), !!(pData->aCSR[4] & RT_BIT( 7)),
3921 !!(pData->aCSR[4] & RT_BIT( 8)), !!(pData->aCSR[4] & RT_BIT( 9)), !!(pData->aCSR[4] & RT_BIT(10)), !!(pData->aCSR[4] & RT_BIT(11)),
3922 !!(pData->aCSR[4] & RT_BIT(12)), !!(pData->aCSR[4] & RT_BIT(13)), !!(pData->aCSR[4] & RT_BIT(14)), !!(pData->aCSR[4] & RT_BIT(15)));
3923
3924 pHlp->pfnPrintf(pHlp,
3925 "CSR5=%#06x:\n",
3926 pData->aCSR[5]);
3927
3928 pHlp->pfnPrintf(pHlp,
3929 "CSR6=%#06x: RLEN=%#x* TLEN=%#x* [* encoded]\n",
3930 pData->aCSR[6],
3931 (pData->aCSR[6] >> 8) & 0xf, (pData->aCSR[6] >> 12) & 0xf);
3932
3933 pHlp->pfnPrintf(pHlp,
3934 "CSR8..11=%#06x,%#06x,%#06x,%#06x: LADRF=%#018llx\n",
3935 pData->aCSR[8], pData->aCSR[9], pData->aCSR[10], pData->aCSR[11],
3936 (uint64_t)(pData->aCSR[ 8] & 0xffff)
3937 | (uint64_t)(pData->aCSR[ 9] & 0xffff) << 16
3938 | (uint64_t)(pData->aCSR[10] & 0xffff) << 32
3939 | (uint64_t)(pData->aCSR[11] & 0xffff) << 48);
3940
3941 pHlp->pfnPrintf(pHlp,
3942 "CSR12..14=%#06x,%#06x,%#06x: PADR=%02x:%02x:%02x:%02x:%02x:%02x (Current MAC Address)\n",
3943 pData->aCSR[12], pData->aCSR[13], pData->aCSR[14],
3944 pData->aCSR[12] & 0xff,
3945 (pData->aCSR[12] >> 8) & 0xff,
3946 pData->aCSR[13] & 0xff,
3947 (pData->aCSR[13] >> 8) & 0xff,
3948 pData->aCSR[14] & 0xff,
3949 (pData->aCSR[14] >> 8) & 0xff);
3950
3951 pHlp->pfnPrintf(pHlp,
3952 "CSR15=%#06x: DXR=%d DTX=%d LOOP=%d DXMTFCS=%d FCOLL=%d DRTY=%d INTL=%d PORTSEL=%d LTR=%d\n"
3953 " MENDECL=%d DAPC=%d DLNKTST=%d DRCVPV=%d DRCVBC=%d PROM=%d\n",
3954 pData->aCSR[15],
3955 !!(pData->aCSR[15] & RT_BIT( 0)), !!(pData->aCSR[15] & RT_BIT( 1)), !!(pData->aCSR[15] & RT_BIT( 2)), !!(pData->aCSR[15] & RT_BIT( 3)),
3956 !!(pData->aCSR[15] & RT_BIT( 4)), !!(pData->aCSR[15] & RT_BIT( 5)), !!(pData->aCSR[15] & RT_BIT( 6)), (pData->aCSR[15] >> 7) & 3,
3957 !!(pData->aCSR[15] & RT_BIT( 9)), !!(pData->aCSR[15] & RT_BIT(10)), !!(pData->aCSR[15] & RT_BIT(11)),
3958 !!(pData->aCSR[15] & RT_BIT(12)), !!(pData->aCSR[15] & RT_BIT(13)), !!(pData->aCSR[15] & RT_BIT(14)), !!(pData->aCSR[15] & RT_BIT(15)));
3959
3960 pHlp->pfnPrintf(pHlp,
3961 "CSR46=%#06x: POLL=%#06x (Poll Time Counter)\n",
3962 pData->aCSR[46], pData->aCSR[46] & 0xffff);
3963
3964 pHlp->pfnPrintf(pHlp,
3965 "CSR47=%#06x: POLLINT=%#06x (Poll Time Interval)\n",
3966 pData->aCSR[47], pData->aCSR[47] & 0xffff);
3967
3968 pHlp->pfnPrintf(pHlp,
3969 "CSR58=%#06x: SWSTYLE=%d %s SSIZE32=%d CSRPCNET=%d APERRENT=%d\n",
3970 pData->aCSR[58],
3971 pData->aCSR[58] & 0x7f,
3972 (pData->aCSR[58] & 0x7f) == 0 ? "C-LANCE / PCnet-ISA"
3973 : (pData->aCSR[58] & 0x7f) == 1 ? "ILACC"
3974 : (pData->aCSR[58] & 0x7f) == 2 ? "PCNet-PCI II"
3975 : (pData->aCSR[58] & 0x7f) == 3 ? "PCNet-PCI II controller"
3976 : "!!reserved!!",
3977 !!(pData->aCSR[58] & RT_BIT(8)), !!(pData->aCSR[58] & RT_BIT(9)), !!(pData->aCSR[58] & RT_BIT(10)));
3978
3979 pHlp->pfnPrintf(pHlp,
3980 "CSR112=%04RX32: MFC=%04x (Missed receive Frame Count)\n",
3981 pData->aCSR[112], pData->aCSR[112] & 0xffff);
3982
3983 pHlp->pfnPrintf(pHlp,
3984 "CSR122=%04RX32: RCVALGN=%04x (Receive Frame Align)\n",
3985 pData->aCSR[122], !!(pData->aCSR[122] & RT_BIT(0)));
3986
3987 pHlp->pfnPrintf(pHlp,
3988 "CSR124=%04RX32: RPA=%04x (Runt Packet Accept)\n",
3989 pData->aCSR[122], !!(pData->aCSR[122] & RT_BIT(3)));
3990
3991
3992 /*
3993 * Dump the receive ring.
3994 */
3995 pHlp->pfnPrintf(pHlp,
3996 "RCVRL=%04x RCVRC=%04x GCRDRA=%RX32 \n"
3997 "CRDA=%08RX32 CRBA=%08RX32 CRBC=%03x CRST=%04x\n"
3998 "NRDA=%08RX32 NRBA=%08RX32 NRBC=%03x NRST=%04x\n"
3999 "NNRDA=%08RX32\n"
4000 ,
4001 CSR_RCVRL(pData), CSR_RCVRC(pData), pData->GCRDRA,
4002 CSR_CRDA(pData), CSR_CRBA(pData), CSR_CRBC(pData), CSR_CRST(pData),
4003 CSR_NRDA(pData), CSR_NRBA(pData), CSR_NRBC(pData), CSR_NRST(pData),
4004 CSR_NNRD(pData));
4005 if (fRcvRing)
4006 {
4007 const unsigned cb = 1 << pData->iLog2DescSize;
4008 RTGCPHYS32 GCPhys = pData->GCRDRA;
4009 unsigned i = CSR_RCVRL(pData);
4010 while (i-- > 0)
4011 {
4012 RMD rmd;
4013 pcnetRmdLoad(pData, &rmd, PHYSADDR(pData, GCPhys), false);
4014 pHlp->pfnPrintf(pHlp,
4015 "%04x %RGp:%c%c RBADR=%08RX32 BCNT=%03x MCNT=%03x "
4016 "OWN=%d ERR=%d FRAM=%d OFLO=%d CRC=%d BUFF=%d STP=%d ENP=%d BPE=%d "
4017 "PAM=%d LAFM=%d BAM=%d RCC=%02x RPC=%02x ONES=%#x ZEROS=%d\n",
4018 i, GCPhys, i + 1 == CSR_RCVRC(pData) ? '*' : ' ', GCPhys == CSR_CRDA(pData) ? '*' : ' ',
4019 rmd.rmd0.rbadr, 4096 - rmd.rmd1.bcnt, rmd.rmd2.mcnt,
4020 rmd.rmd1.own, rmd.rmd1.err, rmd.rmd1.fram, rmd.rmd1.oflo, rmd.rmd1.crc, rmd.rmd1.buff,
4021 rmd.rmd1.stp, rmd.rmd1.enp, rmd.rmd1.bpe,
4022 rmd.rmd1.pam, rmd.rmd1.lafm, rmd.rmd1.bam, rmd.rmd2.rcc, rmd.rmd2.rpc,
4023 rmd.rmd1.ones, rmd.rmd2.zeros);
4024
4025 GCPhys += cb;
4026 }
4027 }
4028
4029 /*
4030 * Dump the transmit ring.
4031 */
4032 pHlp->pfnPrintf(pHlp,
4033 "XMTRL=%04x XMTRC=%04x GCTDRA=%08RX32 BADX=%08RX32\n"
4034 "PXDA=%08RX32 PXBC=%03x PXST=%04x\n"
4035 "CXDA=%08RX32 CXBA=%08RX32 CXBC=%03x CXST=%04x\n"
4036 "NXDA=%08RX32 NXBA=%08RX32 NXBC=%03x NXST=%04x\n"
4037 "NNXDA=%08RX32\n"
4038 ,
4039 CSR_XMTRL(pData), CSR_XMTRC(pData),
4040 pData->GCTDRA, CSR_BADX(pData),
4041 CSR_PXDA(pData), CSR_PXBC(pData), CSR_PXST(pData),
4042 CSR_CXDA(pData), CSR_CXBA(pData), CSR_CXBC(pData), CSR_CXST(pData),
4043 CSR_NXDA(pData), CSR_NXBA(pData), CSR_NXBC(pData), CSR_NXST(pData),
4044 CSR_NNXD(pData));
4045 if (fXmtRing)
4046 {
4047 const unsigned cb = 1 << pData->iLog2DescSize;
4048 RTGCPHYS32 GCPhys = pData->GCTDRA;
4049 unsigned i = CSR_XMTRL(pData);
4050 while (i-- > 0)
4051 {
4052 TMD tmd;
4053 pcnetTmdLoad(pData, &tmd, PHYSADDR(pData, GCPhys), false);
4054 pHlp->pfnPrintf(pHlp,
4055 "%04x %RGp:%c%c TBADR=%08RX32 BCNT=%03x OWN=%d "
4056 "ERR=%d NOFCS=%d LTINT=%d ONE=%d DEF=%d STP=%d ENP=%d BPE=%d "
4057 "BUFF=%d UFLO=%d EXDEF=%d LCOL=%d LCAR=%d RTRY=%d TDR=%03x TRC=%#x ONES=%#x\n"
4058 ,
4059 i, GCPhys, i + 1 == CSR_XMTRC(pData) ? '*' : ' ', GCPhys == CSR_CXDA(pData) ? '*' : ' ',
4060 tmd.tmd0.tbadr, 4096 - tmd.tmd1.bcnt,
4061 tmd.tmd2.tdr,
4062 tmd.tmd2.trc,
4063 tmd.tmd1.own,
4064 tmd.tmd1.err,
4065 tmd.tmd1.nofcs,
4066 tmd.tmd1.ltint,
4067 tmd.tmd1.one,
4068 tmd.tmd1.def,
4069 tmd.tmd1.stp,
4070 tmd.tmd1.enp,
4071 tmd.tmd1.bpe,
4072 tmd.tmd2.buff,
4073 tmd.tmd2.uflo,
4074 tmd.tmd2.exdef,
4075 tmd.tmd2.lcol,
4076 tmd.tmd2.lcar,
4077 tmd.tmd2.rtry,
4078 tmd.tmd2.tdr,
4079 tmd.tmd2.trc,
4080 tmd.tmd1.ones);
4081
4082 GCPhys += cb;
4083 }
4084 }
4085
4086 PDMCritSectLeave(&pData->CritSect);
4087}
4088
4089
4090/**
4091 * Serializes the receive thread, it may be working inside the critsect.
4092 *
4093 * @returns VBox status code.
4094 * @param pDevIns The device instance.
4095 * @param pSSMHandle The handle to save the state to.
4096 */
4097static DECLCALLBACK(int) pcnetSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
4098{
4099 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
4100
4101 int rc = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
4102 AssertRC(rc);
4103 PDMCritSectLeave(&pData->CritSect);
4104
4105 return VINF_SUCCESS;
4106}
4107
4108
4109/**
4110 * Saves a state of the PC-Net II device.
4111 *
4112 * @returns VBox status code.
4113 * @param pDevIns The device instance.
4114 * @param pSSMHandle The handle to save the state to.
4115 */
4116static DECLCALLBACK(int) pcnetSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
4117{
4118 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
4119 int rc = VINF_SUCCESS;
4120
4121 SSMR3PutBool(pSSMHandle, pData->fLinkUp);
4122 SSMR3PutU32(pSSMHandle, pData->u32RAP);
4123 SSMR3PutS32(pSSMHandle, pData->iISR);
4124 SSMR3PutU32(pSSMHandle, pData->u32Lnkst);
4125 SSMR3PutBool(pSSMHandle, pData->fPrivIfEnabled); /* >= If version 0.9 */
4126 SSMR3PutBool(pSSMHandle, pData->fSignalRxMiss); /* >= If version 0.10 */
4127 SSMR3PutGCPhys32(pSSMHandle, pData->GCRDRA);
4128 SSMR3PutGCPhys32(pSSMHandle, pData->GCTDRA);
4129 SSMR3PutMem(pSSMHandle, pData->aPROM, sizeof(pData->aPROM));
4130 SSMR3PutMem(pSSMHandle, pData->aCSR, sizeof(pData->aCSR));
4131 SSMR3PutMem(pSSMHandle, pData->aBCR, sizeof(pData->aBCR));
4132 SSMR3PutMem(pSSMHandle, pData->aMII, sizeof(pData->aMII));
4133 SSMR3PutU16(pSSMHandle, pData->u16CSR0LastSeenByGuest);
4134 SSMR3PutU64(pSSMHandle, pData->u64LastPoll);
4135 SSMR3PutMem(pSSMHandle, &pData->MacConfigured, sizeof(pData->MacConfigured));
4136 SSMR3PutBool(pSSMHandle, pData->fAm79C973); /* >= If version 0.8 */
4137 SSMR3PutU32(pSSMHandle, pData->u32LinkSpeed);
4138#ifdef PCNET_NO_POLLING
4139 return VINF_SUCCESS;
4140#else
4141 rc = TMR3TimerSave(pData->CTXSUFF(pTimerPoll), pSSMHandle);
4142 if (VBOX_FAILURE(rc))
4143 return rc;
4144#endif
4145 if (pData->fAm79C973)
4146 rc = TMR3TimerSave(pData->CTXSUFF(pTimerSoftInt), pSSMHandle);
4147 return rc;
4148}
4149
4150
4151/**
4152 * Serializes the receive thread, it may be working inside the critsect.
4153 *
4154 * @returns VBox status code.
4155 * @param pDevIns The device instance.
4156 * @param pSSMHandle The handle to save the state to.
4157 */
4158static DECLCALLBACK(int) pcnetLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
4159{
4160 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
4161
4162 int rc = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
4163 AssertRC(rc);
4164 PDMCritSectLeave(&pData->CritSect);
4165
4166 return VINF_SUCCESS;
4167}
4168
4169
4170/**
4171 * Loads a saved PC-Net II device state.
4172 *
4173 * @returns VBox status code.
4174 * @param pDevIns The device instance.
4175 * @param pSSMHandle The handle to the saved state.
4176 * @param u32Version The data unit version number.
4177 */
4178static DECLCALLBACK(int) pcnetLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
4179{
4180 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
4181 PDMMAC Mac;
4182 if ( SSM_VERSION_MAJOR_CHANGED(u32Version, PCNET_SAVEDSTATE_VERSION)
4183 || SSM_VERSION_MINOR(u32Version) < 7)
4184 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4185
4186 /* restore data */
4187 SSMR3GetBool(pSSMHandle, &pData->fLinkUp);
4188 SSMR3GetU32(pSSMHandle, &pData->u32RAP);
4189 SSMR3GetS32(pSSMHandle, &pData->iISR);
4190 SSMR3GetU32(pSSMHandle, &pData->u32Lnkst);
4191 if ( SSM_VERSION_MAJOR(u32Version) > 0
4192 || SSM_VERSION_MINOR(u32Version) >= 9)
4193 {
4194 SSMR3GetBool(pSSMHandle, &pData->fPrivIfEnabled);
4195 if (pData->fPrivIfEnabled)
4196 LogRel(("PCNet#%d: Enabling private interface\n", PCNET_INST_NR));
4197 }
4198 if ( SSM_VERSION_MAJOR(u32Version) > 0
4199 || SSM_VERSION_MINOR(u32Version) >= 10)
4200 {
4201 SSMR3GetBool(pSSMHandle, &pData->fSignalRxMiss);
4202 }
4203 SSMR3GetGCPhys32(pSSMHandle, &pData->GCRDRA);
4204 SSMR3GetGCPhys32(pSSMHandle, &pData->GCTDRA);
4205 SSMR3GetMem(pSSMHandle, &pData->aPROM, sizeof(pData->aPROM));
4206 SSMR3GetMem(pSSMHandle, &pData->aCSR, sizeof(pData->aCSR));
4207 SSMR3GetMem(pSSMHandle, &pData->aBCR, sizeof(pData->aBCR));
4208 SSMR3GetMem(pSSMHandle, &pData->aMII, sizeof(pData->aMII));
4209 SSMR3GetU16(pSSMHandle, &pData->u16CSR0LastSeenByGuest);
4210 SSMR3GetU64(pSSMHandle, &pData->u64LastPoll);
4211 SSMR3GetMem(pSSMHandle, &Mac, sizeof(Mac));
4212 Assert( !memcmp(&Mac, &pData->MacConfigured, sizeof(Mac))
4213 || SSMR3HandleGetAfter(pSSMHandle) == SSMAFTER_DEBUG_IT);
4214 SSMR3GetBool(pSSMHandle, &pData->fAm79C973);
4215 SSMR3GetU32(pSSMHandle, &pData->u32LinkSpeed);
4216#ifndef PCNET_NO_POLLING
4217 TMR3TimerLoad(pData->CTXSUFF(pTimerPoll), pSSMHandle);
4218#endif
4219 if (pData->fAm79C973)
4220 {
4221 if ( SSM_VERSION_MAJOR(u32Version) > 0
4222 || SSM_VERSION_MINOR(u32Version) >= 8)
4223 TMR3TimerLoad(pData->CTXSUFF(pTimerSoftInt), pSSMHandle);
4224 }
4225
4226 pData->iLog2DescSize = BCR_SWSTYLE(pData)
4227 ? 4
4228 : 3;
4229 pData->GCUpperPhys = BCR_SSIZE32(pData)
4230 ? 0
4231 : (0xff00 & (uint32_t)pData->aCSR[2]) << 16;
4232
4233 /* update promiscuous mode. */
4234 if (pData->pDrv)
4235 pData->pDrv->pfnSetPromiscuousMode(pData->pDrv, CSR_PROM(pData));
4236
4237#ifdef PCNET_NO_POLLING
4238 /* Enable physical monitoring again (!) */
4239 pcnetUpdateRingHandlers(pData);
4240#endif
4241 /* Indicate link down to the guest OS that all network connections have been lost. */
4242 if (pData->fLinkUp)
4243 {
4244 pData->fLinkTempDown = true;
4245 pData->cLinkDownReported = 0;
4246 pData->aCSR[0] |= RT_BIT(15) | RT_BIT(13); /* ERR | CERR (this is probably wrong) */
4247 pData->Led.Asserted.s.fError = pData->Led.Actual.s.fError = 1;
4248 return TMTimerSetMillies(pData->pTimerRestore, 5000);
4249 }
4250 return VINF_SUCCESS;
4251}
4252
4253
4254/**
4255 * Queries an interface to the driver.
4256 *
4257 * @returns Pointer to interface.
4258 * @returns NULL if the interface was not supported by the driver.
4259 * @param pInterface Pointer to this interface structure.
4260 * @param enmInterface The requested interface identification.
4261 * @thread Any thread.
4262 */
4263static DECLCALLBACK(void *) pcnetQueryInterface(struct PDMIBASE *pInterface, PDMINTERFACE enmInterface)
4264{
4265 PCNetState *pData = (PCNetState *)((uintptr_t)pInterface - RT_OFFSETOF(PCNetState, IBase));
4266 Assert(&pData->IBase == pInterface);
4267 switch (enmInterface)
4268 {
4269 case PDMINTERFACE_BASE:
4270 return &pData->IBase;
4271 case PDMINTERFACE_NETWORK_PORT:
4272 return &pData->INetworkPort;
4273 case PDMINTERFACE_NETWORK_CONFIG:
4274 return &pData->INetworkConfig;
4275 case PDMINTERFACE_LED_PORTS:
4276 return &pData->ILeds;
4277 default:
4278 return NULL;
4279 }
4280}
4281
4282/** Converts a pointer to PCNetState::INetworkPort to a PCNetState pointer. */
4283#define INETWORKPORT_2_DATA(pInterface) ( (PCNetState *)((uintptr_t)pInterface - RT_OFFSETOF(PCNetState, INetworkPort)) )
4284
4285
4286/**
4287 * Check if the device/driver can receive data now.
4288 * This must be called before the pfnRecieve() method is called.
4289 *
4290 * @returns VBox status code.
4291 * @param pInterface Pointer to the interface structure containing the called function pointer.
4292 */
4293static int pcnetCanReceive(PCNetState *pData)
4294{
4295 int rc = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
4296 AssertReleaseRC(rc);
4297
4298 rc = VERR_NET_NO_BUFFER_SPACE;
4299
4300 if (RT_LIKELY(!CSR_DRX(pData) && !CSR_STOP(pData) && !CSR_SPND(pData)))
4301 {
4302 if (HOST_IS_OWNER(CSR_CRST(pData)) && pData->GCRDRA)
4303 pcnetRdtePoll(pData);
4304
4305 if (RT_UNLIKELY(HOST_IS_OWNER(CSR_CRST(pData))))
4306 {
4307 /** @todo Notify the guest _now_. Will potentially increase the interrupt load */
4308 if (pData->fSignalRxMiss)
4309 pData->aCSR[0] |= 0x1000; /* Set MISS flag */
4310 }
4311 else
4312 rc = VINF_SUCCESS;
4313 }
4314
4315 PDMCritSectLeave(&pData->CritSect);
4316 return rc;
4317}
4318
4319
4320/**
4321 *
4322 */
4323static DECLCALLBACK(int) pcnetWaitReceiveAvail(PPDMINETWORKPORT pInterface, unsigned cMillies)
4324{
4325 PCNetState *pData = INETWORKPORT_2_DATA(pInterface);
4326
4327 int rc = pcnetCanReceive(pData);
4328 if (RT_SUCCESS(rc))
4329 return VINF_SUCCESS;
4330 if (RT_UNLIKELY(cMillies == 0))
4331 return VERR_NET_NO_BUFFER_SPACE;
4332
4333 rc = VERR_INTERRUPTED;
4334 ASMAtomicXchgBool(&pData->fMaybeOutOfSpace, true);
4335 STAM_PROFILE_START(&pData->StatRxOverflow, a);
4336 while (RT_LIKELY(PDMDevHlpVMState(pData->CTXSUFF(pDevIns)) == VMSTATE_RUNNING))
4337 {
4338 int rc2 = pcnetCanReceive(pData);
4339 if (RT_SUCCESS(rc2))
4340 {
4341 rc = VINF_SUCCESS;
4342 break;
4343 }
4344 LogFlow(("pcnetWaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
4345 /* Start the poll timer once which will remain active as long fMaybeOutOfSpace
4346 * is true -- even if (transmit) polling is disabled (CSR_DPOLL). */
4347 rc2 = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
4348 AssertReleaseRC(rc2);
4349 pcnetPollTimerStart(pData);
4350 PDMCritSectLeave(&pData->CritSect);
4351 RTSemEventWait(pData->hEventOutOfRxSpace, cMillies);
4352 }
4353 STAM_PROFILE_STOP(&pData->StatRxOverflow, a);
4354 ASMAtomicXchgBool(&pData->fMaybeOutOfSpace, false);
4355
4356 return rc;
4357}
4358
4359
4360/**
4361 * Receive data from the network.
4362 *
4363 * @returns VBox status code.
4364 * @param pInterface Pointer to the interface structure containing the called function pointer.
4365 * @param pvBuf The available data.
4366 * @param cb Number of bytes available in the buffer.
4367 * @thread EMT
4368 */
4369static DECLCALLBACK(int) pcnetReceive(PPDMINETWORKPORT pInterface, const void *pvBuf, size_t cb)
4370{
4371 PCNetState *pData = INETWORKPORT_2_DATA(pInterface);
4372 int rc;
4373
4374 STAM_PROFILE_ADV_START(&pData->StatReceive, a);
4375 rc = PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY);
4376 AssertReleaseRC(rc);
4377
4378 if (cb > 70) /* unqualified guess */
4379 pData->Led.Asserted.s.fReading = pData->Led.Actual.s.fReading = 1;
4380 pcnetReceiveNoSync(pData, (const uint8_t *)pvBuf, cb);
4381 pData->Led.Actual.s.fReading = 0;
4382
4383 PDMCritSectLeave(&pData->CritSect);
4384 STAM_PROFILE_ADV_STOP(&pData->StatReceive, a);
4385
4386 return VINF_SUCCESS;
4387}
4388
4389/** Converts a pointer to PCNetState::INetworkConfig to a PCNetState pointer. */
4390#define INETWORKCONFIG_2_DATA(pInterface) ( (PCNetState *)((uintptr_t)pInterface - RT_OFFSETOF(PCNetState, INetworkConfig)) )
4391
4392
4393/**
4394 * Gets the current Media Access Control (MAC) address.
4395 *
4396 * @returns VBox status code.
4397 * @param pInterface Pointer to the interface structure containing the called function pointer.
4398 * @param pMac Where to store the MAC address.
4399 * @thread EMT
4400 */
4401static DECLCALLBACK(int) pcnetGetMac(PPDMINETWORKCONFIG pInterface, PPDMMAC pMac)
4402{
4403 PCNetState *pData = INETWORKCONFIG_2_DATA(pInterface);
4404 memcpy(pMac, pData->aPROM, sizeof(*pMac));
4405 return VINF_SUCCESS;
4406}
4407
4408
4409/**
4410 * Gets the new link state.
4411 *
4412 * @returns The current link state.
4413 * @param pInterface Pointer to the interface structure containing the called function pointer.
4414 * @thread EMT
4415 */
4416static DECLCALLBACK(PDMNETWORKLINKSTATE) pcnetGetLinkState(PPDMINETWORKCONFIG pInterface)
4417{
4418 PCNetState *pData = INETWORKCONFIG_2_DATA(pInterface);
4419 if (pData->fLinkUp && !pData->fLinkTempDown)
4420 return PDMNETWORKLINKSTATE_UP;
4421 if (!pData->fLinkUp)
4422 return PDMNETWORKLINKSTATE_DOWN;
4423 if (pData->fLinkTempDown)
4424 return PDMNETWORKLINKSTATE_DOWN_RESUME;
4425 AssertMsgFailed(("Invalid link state!\n"));
4426 return PDMNETWORKLINKSTATE_INVALID;
4427}
4428
4429
4430/**
4431 * Sets the new link state.
4432 *
4433 * @returns VBox status code.
4434 * @param pInterface Pointer to the interface structure containing the called function pointer.
4435 * @param enmState The new link state
4436 * @thread EMT
4437 */
4438static DECLCALLBACK(int) pcnetSetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
4439{
4440 PCNetState *pData = INETWORKCONFIG_2_DATA(pInterface);
4441 bool fLinkUp;
4442 if ( enmState != PDMNETWORKLINKSTATE_DOWN
4443 && enmState != PDMNETWORKLINKSTATE_UP)
4444 {
4445 AssertMsgFailed(("Invalid parameter enmState=%d\n", enmState));
4446 return VERR_INVALID_PARAMETER;
4447 }
4448
4449 /* has the state changed? */
4450 fLinkUp = enmState == PDMNETWORKLINKSTATE_UP;
4451 if (pData->fLinkUp != fLinkUp)
4452 {
4453 pData->fLinkUp = fLinkUp;
4454 if (fLinkUp)
4455 {
4456 /* connect */
4457 pData->aCSR[0] &= ~(RT_BIT(15) | RT_BIT(13)); /* ERR | CERR - probably not 100% correct either... */
4458 pData->Led.Actual.s.fError = 0;
4459 }
4460 else
4461 {
4462 /* disconnect */
4463 pData->cLinkDownReported = 0;
4464 pData->aCSR[0] |= RT_BIT(15) | RT_BIT(13); /* ERR | CERR (this is probably wrong) */
4465 pData->Led.Asserted.s.fError = pData->Led.Actual.s.fError = 1;
4466 }
4467 Assert(!PDMCritSectIsOwner(&pData->CritSect));
4468 pData->pDrv->pfnNotifyLinkChanged(pData->pDrv, enmState);
4469 }
4470 return VINF_SUCCESS;
4471}
4472
4473
4474/**
4475 * Gets the pointer to the status LED of a unit.
4476 *
4477 * @returns VBox status code.
4478 * @param pInterface Pointer to the interface structure containing the called function pointer.
4479 * @param iLUN The unit which status LED we desire.
4480 * @param ppLed Where to store the LED pointer.
4481 */
4482static DECLCALLBACK(int) pcnetQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4483{
4484 PCNetState *pData = (PCNetState *)( (uintptr_t)pInterface - RT_OFFSETOF(PCNetState, ILeds) );
4485 if (iLUN == 0)
4486 {
4487 *ppLed = &pData->Led;
4488 return VINF_SUCCESS;
4489 }
4490 return VERR_PDM_LUN_NOT_FOUND;
4491}
4492
4493
4494/**
4495 * @copydoc FNPDMDEVPOWEROFF
4496 */
4497static DECLCALLBACK(void) pcnetPowerOff(PPDMDEVINS pDevIns)
4498{
4499 /* Poke thread waiting for buffer space. */
4500 pcnetWakeupReceive(pDevIns);
4501}
4502
4503
4504/**
4505 * @copydoc FNPDMDEVSUSPEND
4506 */
4507static DECLCALLBACK(void) pcnetSuspend(PPDMDEVINS pDevIns)
4508{
4509 /* Poke thread waiting for buffer space. */
4510 pcnetWakeupReceive(pDevIns);
4511}
4512
4513
4514/**
4515 * @copydoc FNPDMDEVRESET
4516 */
4517static DECLCALLBACK(void) pcnetReset(PPDMDEVINS pDevIns)
4518{
4519 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
4520 if (pData->fLinkTempDown)
4521 {
4522 pData->cLinkDownReported = 0x10000;
4523 TMTimerStop(pData->pTimerRestore);
4524 pcnetTimerRestore(pDevIns, pData->pTimerRestore);
4525 }
4526 if (pData->pSharedMMIOHC)
4527 pcnetInitSharedMemory(pData);
4528
4529 /** @todo How to flush the queues? */
4530 pcnetHardReset(pData);
4531}
4532
4533
4534/**
4535 * @copydoc FNPDMDEVRELOCATE
4536 */
4537static DECLCALLBACK(void) pcnetRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4538{
4539 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
4540 pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
4541 pData->pXmitQueueGC = PDMQueueGCPtr(pData->pXmitQueueHC);
4542 pData->pCanRxQueueGC = PDMQueueGCPtr(pData->pCanRxQueueHC);
4543 if (pData->pSharedMMIOHC)
4544 pData->pSharedMMIOGC += offDelta;
4545#ifdef PCNET_NO_POLLING
4546 *(RTHCUINTPTR *)&pData->pfnEMInterpretInstructionGC += offDelta;
4547#else
4548 pData->pTimerPollGC = TMTimerGCPtr(pData->pTimerPollHC);
4549#endif
4550 if (pData->fAm79C973)
4551 pData->pTimerSoftIntGC = TMTimerGCPtr(pData->pTimerSoftIntHC);
4552}
4553
4554
4555/**
4556 * Destruct a device instance.
4557 *
4558 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
4559 * resources can be freed correctly.
4560 *
4561 * @returns VBox status.
4562 * @param pDevIns The device instance data.
4563 */
4564static DECLCALLBACK(int) pcnetDestruct(PPDMDEVINS pDevIns)
4565{
4566 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
4567
4568 if (PDMCritSectIsInitialized(&pData->CritSect))
4569 {
4570 /*
4571 * At this point the send thread is suspended and will not enter
4572 * this module again. So, no coordination is needed here and PDM
4573 * will take care of terminating and cleaning up the thread.
4574 */
4575 RTSemEventDestroy(pData->hSendEventSem);
4576 pData->hSendEventSem = NIL_RTSEMEVENT;
4577 RTSemEventSignal(pData->hEventOutOfRxSpace);
4578 RTSemEventDestroy(pData->hEventOutOfRxSpace);
4579 pData->hEventOutOfRxSpace = NIL_RTSEMEVENT;
4580 PDMR3CritSectDelete(&pData->CritSect);
4581 }
4582#ifdef PCNET_QUEUE_SEND_PACKETS
4583 if (pData->apXmitRingBuffer)
4584 RTMemFree(pData->apXmitRingBuffer[0]);
4585#endif
4586 return VINF_SUCCESS;
4587}
4588
4589
4590/**
4591 * Construct a device instance for a VM.
4592 *
4593 * @returns VBox status.
4594 * @param pDevIns The device instance data.
4595 * If the registration structure is needed, pDevIns->pDevReg points to it.
4596 * @param iInstance Instance number. Use this to figure out which registers and such to use.
4597 * The device number is also found in pDevIns->iInstance, but since it's
4598 * likely to be freqently used PDM passes it as parameter.
4599 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
4600 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
4601 * iInstance it's expected to be used a bit in this function.
4602 */
4603static DECLCALLBACK(int) pcnetConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
4604{
4605 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *);
4606 PPDMIBASE pBase;
4607 char szTmp[128];
4608 int rc;
4609
4610 /* up to four instances are supported */
4611 Assert((iInstance >= 0) && (iInstance < 4));
4612
4613 Assert(RT_ELEMENTS(pData->aBCR) == BCR_MAX_RAP);
4614 Assert(RT_ELEMENTS(pData->aMII) == MII_MAX_REG);
4615 Assert(sizeof(pData->abSendBuf) == RT_ALIGN_Z(sizeof(pData->abSendBuf), 16));
4616
4617 /*
4618 * Validate configuration.
4619 */
4620 if (!CFGMR3AreValuesValid(pCfgHandle, "MAC\0CableConnected\0Am79C973\0LineSpeed\0GCEnabled\0R0Enabled\0PrivIfEnabled\0"))
4621 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4622 N_("Invalid configuraton for pcnet device"));
4623
4624 /*
4625 * Read the configuration.
4626 */
4627 rc = CFGMR3QueryBytes(pCfgHandle, "MAC", &pData->MacConfigured, sizeof(pData->MacConfigured));
4628 if (VBOX_FAILURE(rc))
4629 return PDMDEV_SET_ERROR(pDevIns, rc,
4630 N_("Configuration error: Failed to get the \"MAC\" value"));
4631 rc = CFGMR3QueryBool(pCfgHandle, "CableConnected", &pData->fLinkUp);
4632 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4633 pData->fLinkUp = true;
4634 else if (VBOX_FAILURE(rc))
4635 return PDMDEV_SET_ERROR(pDevIns, rc,
4636 N_("Configuration error: Failed to get the \"CableConnected\" value"));
4637
4638 rc = CFGMR3QueryBool(pCfgHandle, "Am79C973", &pData->fAm79C973);
4639 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4640 pData->fAm79C973 = false;
4641 else if (VBOX_FAILURE(rc))
4642 return PDMDEV_SET_ERROR(pDevIns, rc,
4643 N_("Configuration error: Failed to get the \"Am79C973\" value"));
4644
4645 rc = CFGMR3QueryU32(pCfgHandle, "LineSpeed", &pData->u32LinkSpeed);
4646 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4647 pData->u32LinkSpeed = 1000000; /* 1GBit/s (in kbps units)*/
4648 else if (VBOX_FAILURE(rc))
4649 return PDMDEV_SET_ERROR(pDevIns, rc,
4650 N_("Configuration error: Failed to get the \"LineSpeed\" value"));
4651
4652#ifdef PCNET_GC_ENABLED
4653 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &pData->fGCEnabled);
4654 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4655 pData->fGCEnabled = true;
4656 else if (VBOX_FAILURE(rc))
4657 return PDMDEV_SET_ERROR(pDevIns, rc,
4658 N_("Configuration error: Failed to get the \"GCEnabled\" value"));
4659
4660 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &pData->fR0Enabled);
4661 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4662 pData->fR0Enabled = true;
4663 else if (VBOX_FAILURE(rc))
4664 return PDMDEV_SET_ERROR(pDevIns, rc,
4665 N_("Configuration error: Failed to get the \"R0Enabled\" value"));
4666
4667#else /* !PCNET_GC_ENABLED */
4668 pData->fGCEnabled = false;
4669 pData->fR0Enabled = false;
4670#endif /* !PCNET_GC_ENABLED */
4671
4672
4673 /*
4674 * Initialize data (most of it anyway).
4675 */
4676 pData->pDevInsHC = pDevIns;
4677 pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
4678 pData->Led.u32Magic = PDMLED_MAGIC;
4679 /* IBase */
4680 pData->IBase.pfnQueryInterface = pcnetQueryInterface;
4681 /* INeworkPort */
4682 pData->INetworkPort.pfnWaitReceiveAvail = pcnetWaitReceiveAvail;
4683 pData->INetworkPort.pfnReceive = pcnetReceive;
4684 /* INetworkConfig */
4685 pData->INetworkConfig.pfnGetMac = pcnetGetMac;
4686 pData->INetworkConfig.pfnGetLinkState = pcnetGetLinkState;
4687 pData->INetworkConfig.pfnSetLinkState = pcnetSetLinkState;
4688 /* ILeds */
4689 pData->ILeds.pfnQueryStatusLed = pcnetQueryStatusLed;
4690
4691 /* PCI Device */
4692 PCIDevSetVendorId(&pData->PciDev, 0x1022);
4693 PCIDevSetDeviceId(&pData->PciDev, 0x2000);
4694 pData->PciDev.config[0x04] = 0x07; /* command */
4695 pData->PciDev.config[0x05] = 0x00;
4696 pData->PciDev.config[0x06] = 0x80; /* status */
4697 pData->PciDev.config[0x07] = 0x02;
4698 pData->PciDev.config[0x08] = pData->fAm79C973 ? 0x40 : 0x10; /* revision */
4699 pData->PciDev.config[0x09] = 0x00;
4700 pData->PciDev.config[0x0a] = 0x00; /* ethernet network controller */
4701 pData->PciDev.config[0x0b] = 0x02;
4702 pData->PciDev.config[0x0e] = 0x00; /* header_type */
4703
4704 pData->PciDev.config[0x10] = 0x01; /* IO Base */
4705 pData->PciDev.config[0x11] = 0x00;
4706 pData->PciDev.config[0x12] = 0x00;
4707 pData->PciDev.config[0x13] = 0x00;
4708 pData->PciDev.config[0x14] = 0x00; /* MMIO Base */
4709 pData->PciDev.config[0x15] = 0x00;
4710 pData->PciDev.config[0x16] = 0x00;
4711 pData->PciDev.config[0x17] = 0x00;
4712
4713 /* subsystem and subvendor IDs */
4714 pData->PciDev.config[0x2c] = 0x22; /* subsystem vendor id */
4715 pData->PciDev.config[0x2d] = 0x10;
4716 pData->PciDev.config[0x2e] = 0x00; /* subsystem id */
4717 pData->PciDev.config[0x2f] = 0x20;
4718 pData->PciDev.config[0x3d] = 1; /* interrupt pin 0 */
4719 pData->PciDev.config[0x3e] = 0x06;
4720 pData->PciDev.config[0x3f] = 0xff;
4721
4722 /*
4723 * Register the PCI device, its I/O regions, the timer and the saved state item.
4724 */
4725 rc = PDMDevHlpPCIRegister(pDevIns, &pData->PciDev);
4726 if (VBOX_FAILURE(rc))
4727 return rc;
4728 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, PCNET_IOPORT_SIZE,
4729 PCI_ADDRESS_SPACE_IO, pcnetIOPortMap);
4730 if (VBOX_FAILURE(rc))
4731 return rc;
4732 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, PCNET_PNPMMIO_SIZE,
4733 PCI_ADDRESS_SPACE_MEM, pcnetMMIOMap);
4734 if (VBOX_FAILURE(rc))
4735 return rc;
4736
4737 bool fPrivIfEnabled;
4738 rc = CFGMR3QueryBool(pCfgHandle, "PrivIfEnabled", &fPrivIfEnabled);
4739 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4740 fPrivIfEnabled = true;
4741 else if (VBOX_FAILURE(rc))
4742 return PDMDEV_SET_ERROR(pDevIns, rc,
4743 N_("Configuration error: Failed to get the \"PrivIfEnabled\" value"));
4744
4745 if (fPrivIfEnabled)
4746 {
4747 RTGCPTR pGCMapping;
4748
4749 /*
4750 * Initialize shared memory between host and guest for descriptors and RX buffers. Most guests
4751 * should not care if there is an additional PCI ressource but just in case we made this configurable.
4752 */
4753 rc = PDMDevHlpMMIO2Register(pDevIns, 2, PCNET_GUEST_SHARED_MEMORY_SIZE, 0, (void **)&pData->pSharedMMIOHC, "PCNetShMem");
4754 if (VBOX_FAILURE(rc))
4755 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
4756 N_("Failed to allocate %u bytes of memory for the PCNet device"), PCNET_GUEST_SHARED_MEMORY_SIZE);
4757 rc = PDMDevHlpMMHyperMapMMIO2(pDevIns, 2, 0, 8192, "PCNetShMem", &pGCMapping);
4758 if (VBOX_FAILURE(rc))
4759 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
4760 N_("Failed to map 8192 bytes of memory for the PCNet device into the hyper memory"));
4761 pData->pSharedMMIOGC = pGCMapping;
4762 pcnetInitSharedMemory(pData);
4763 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, PCNET_GUEST_SHARED_MEMORY_SIZE,
4764 PCI_ADDRESS_SPACE_MEM, pcnetMMIOSharedMap);
4765 if (VBOX_FAILURE(rc))
4766 return rc;
4767 }
4768
4769#ifdef PCNET_NO_POLLING
4770 rc = PDMR3GetSymbolR0Lazy(PDMDevHlpGetVM(pDevIns), NULL, "EMInterpretInstruction", &pData->pfnEMInterpretInstructionR0);
4771 if (VBOX_SUCCESS(rc))
4772 {
4773 /*
4774 * Resolve the GC handler.
4775 */
4776 RTGCPTR pfnHandlerGC;
4777 rc = PDMR3GetSymbolGCLazy(PDMDevHlpGetVM(pDevIns), NULL, "EMInterpretInstruction", (RTGCPTR *)&pData->pfnEMInterpretInstructionGC);
4778 }
4779 if (VBOX_FAILURE(rc))
4780 {
4781 AssertMsgFailed(("PDMR3GetSymbolGCLazy -> %Vrc\n", rc));
4782 return rc;
4783 }
4784#else
4785 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetTimer,
4786 "PCNet Poll Timer", &pData->pTimerPollHC);
4787 if (VBOX_FAILURE(rc))
4788 {
4789 AssertMsgFailed(("pfnTMTimerCreate pcnetTimer -> %Vrc\n", rc));
4790 return rc;
4791 }
4792#endif
4793 if (pData->fAm79C973)
4794 {
4795 /* Software Interrupt timer */
4796 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetTimerSoftInt,
4797 "PCNet SoftInt Timer", &pData->pTimerSoftIntHC);
4798 if (VBOX_FAILURE(rc))
4799 {
4800 AssertMsgFailed(("pfnTMTimerCreate pcnetTimerSoftInt -> %Vrc\n", rc));
4801 return rc;
4802 }
4803 }
4804 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetTimerRestore,
4805 "PCNet Restore Timer", &pData->pTimerRestore);
4806 if (VBOX_FAILURE(rc))
4807 {
4808 AssertMsgFailed(("pfnTMTimerCreate pcnetTimerRestore -> %Vrc\n", rc));
4809 return rc;
4810 }
4811 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance,
4812 PCNET_SAVEDSTATE_VERSION, sizeof(*pData),
4813 pcnetSavePrep, pcnetSaveExec, NULL,
4814 pcnetLoadPrep, pcnetLoadExec, NULL);
4815 if (VBOX_FAILURE(rc))
4816 return rc;
4817
4818 /*
4819 * Initialize critical section.
4820 * This must of course be done before attaching drivers or anything else which can call us back..
4821 */
4822 char szName[24];
4823 RTStrPrintf(szName, sizeof(szName), "PCNet#%d", iInstance);
4824 rc = PDMDevHlpCritSectInit(pDevIns, &pData->CritSect, szName);
4825 if (VBOX_FAILURE(rc))
4826 return rc;
4827
4828 rc = RTSemEventCreate(&pData->hEventOutOfRxSpace);
4829 AssertRC(rc);
4830
4831 /*
4832 * Create the transmit queue.
4833 */
4834 rc = PDMDevHlpPDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
4835 pcnetXmitQueueConsumer, true, &pData->pXmitQueueHC);
4836 if (VBOX_FAILURE(rc))
4837 return rc;
4838 pData->pXmitQueueGC = PDMQueueGCPtr(pData->pXmitQueueHC);
4839
4840 /*
4841 * Create the RX notifer signaller.
4842 */
4843 rc = PDMDevHlpPDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
4844 pcnetCanRxQueueConsumer, true, &pData->pCanRxQueueHC);
4845 if (VBOX_FAILURE(rc))
4846 return rc;
4847 pData->pCanRxQueueGC = PDMQueueGCPtr(pData->pCanRxQueueHC);
4848
4849 /*
4850 * Register the info item.
4851 */
4852 RTStrPrintf(szTmp, sizeof(szTmp), "pcnet%d", pDevIns->iInstance);
4853 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "PCNET info.", pcnetInfo);
4854
4855 /*
4856 * Attach status driver (optional).
4857 */
4858 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pData->IBase, &pBase, "Status Port");
4859 if (VBOX_SUCCESS(rc))
4860 pData->pLedsConnector = (PPDMILEDCONNECTORS)
4861 pBase->pfnQueryInterface(pBase, PDMINTERFACE_LED_CONNECTORS);
4862 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
4863 {
4864 AssertMsgFailed(("Failed to attach to status driver. rc=%Vrc\n", rc));
4865 return rc;
4866 }
4867
4868 /*
4869 * Attach driver.
4870 */
4871 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pData->IBase, &pData->pDrvBase, "Network Port");
4872 if (VBOX_SUCCESS(rc))
4873 {
4874 if (rc == VINF_NAT_DNS)
4875 {
4876#ifdef RT_OS_LINUX
4877 VMSetRuntimeError(PDMDevHlpGetVM(pDevIns), false, "NoDNSforNAT",
4878 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
4879#else
4880 VMSetRuntimeError(PDMDevHlpGetVM(pDevIns), false, "NoDNSforNAT",
4881 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
4882#endif
4883 }
4884 pData->pDrv = (PPDMINETWORKCONNECTOR)
4885 pData->pDrvBase->pfnQueryInterface(pData->pDrvBase, PDMINTERFACE_NETWORK_CONNECTOR);
4886 if (!pData->pDrv)
4887 {
4888 AssertMsgFailed(("Failed to obtain the PDMINTERFACE_NETWORK_CONNECTOR interface!\n"));
4889 return VERR_PDM_MISSING_INTERFACE_BELOW;
4890 }
4891 }
4892 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4893 Log(("No attached driver!\n"));
4894 else
4895 return rc;
4896
4897 /*
4898 * Reset the device state. (Do after attaching.)
4899 */
4900 pcnetHardReset(pData);
4901
4902 /* Create send queue for the async send thread. */
4903 rc = RTSemEventCreate(&pData->hSendEventSem);
4904 AssertRC(rc);
4905
4906 /* Create asynchronous thread */
4907 rc = PDMDevHlpPDMThreadCreate(pDevIns, &pData->pSendThread, pData, pcnetAsyncSendThread, pcnetAsyncSendThreadWakeUp, 0, RTTHREADTYPE_IO, "PCNET_TX");
4908 AssertRCReturn(rc, rc);
4909
4910 unsigned i;
4911 NOREF(i);
4912
4913#ifdef PCNET_QUEUE_SEND_PACKETS
4914 pData->apXmitRingBuffer[0] = (uint8_t *)RTMemAlloc(PCNET_MAX_XMIT_SLOTS * MAX_FRAME);
4915 for (i = 1; i < PCNET_MAX_XMIT_SLOTS; i++)
4916 pData->apXmitRingBuffer[i] = pData->apXmitRingBuffer[0] + i*MAX_FRAME;
4917#endif
4918
4919#ifdef VBOX_WITH_STATISTICS
4920 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatMMIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in GC", "/Devices/PCNet%d/MMIO/ReadGC", iInstance);
4921 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatMMIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in HC", "/Devices/PCNet%d/MMIO/ReadHC", iInstance);
4922 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatMMIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in GC", "/Devices/PCNet%d/MMIO/WriteGC", iInstance);
4923 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatMMIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in HC", "/Devices/PCNet%d/MMIO/WriteHC", iInstance);
4924 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatAPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling APROM reads", "/Devices/PCNet%d/IO/APROMRead", iInstance);
4925 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatAPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling APROM writes", "/Devices/PCNet%d/IO/APROMWrite", iInstance);
4926 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", "/Devices/PCNet%d/IO/ReadGC", iInstance);
4927 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", "/Devices/PCNet%d/IO/ReadHC", iInstance);
4928 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", "/Devices/PCNet%d/IO/WriteGC", iInstance);
4929 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", "/Devices/PCNet%d/IO/WriteHC", iInstance);
4930 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling Timer", "/Devices/PCNet%d/Timer", iInstance);
4931 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/PCNet%d/Receive", iInstance);
4932 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/PCNet%d/RxOverflow", iInstance);
4933 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRxOverflowWakeup, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Nr of RX overflow wakeups", "/Devices/PCNet%d/RxOverflowWakeup", iInstance);
4934#endif
4935 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/PCNet%d/ReceiveBytes", iInstance);
4936#ifdef VBOX_WITH_STATISTICS
4937 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatTransmit, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in HC", "/Devices/PCNet%d/Transmit/Total", iInstance);
4938#endif
4939 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/PCNet%d/TransmitBytes", iInstance);
4940#ifdef VBOX_WITH_STATISTICS
4941 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatTransmitSend, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet send transmit in HC","/Devices/PCNet%d/Transmit/Send", iInstance);
4942 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatTdtePollGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet TdtePoll in GC", "/Devices/PCNet%d/TdtePollGC", iInstance);
4943 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatTdtePollHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet TdtePoll in HC", "/Devices/PCNet%d/TdtePollHC", iInstance);
4944 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRdtePollGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet RdtePoll in GC", "/Devices/PCNet%d/RdtePollGC", iInstance);
4945 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRdtePollHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet RdtePoll in HC", "/Devices/PCNet%d/RdtePollHC", iInstance);
4946
4947 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatTmdStoreGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet TmdStore in GC", "/Devices/PCNet%d/TmdStoreGC", iInstance);
4948 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatTmdStoreHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet TmdStore in HC", "/Devices/PCNet%d/TmdStoreHC", iInstance);
4949
4950 for (i = 0; i < ELEMENTS(pData->aStatXmitFlush) - 1; i++)
4951 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitFlushIrq/%d", iInstance, i + 1);
4952 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitFlushIrq/%d+", iInstance, i + 1);
4953
4954 for (i = 0; i < ELEMENTS(pData->aStatXmitChainCounts) - 1; i++)
4955 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitChainCounts/%d", iInstance, i + 1);
4956 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitChainCounts/%d+", iInstance, i + 1);
4957
4958 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatXmitSkipCurrent, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/Xmit/Skipped", iInstance, i + 1);
4959
4960 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatInterrupt, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling interrupt checks", "/Devices/PCNet%d/UpdateIRQ", iInstance);
4961 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatPollTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling poll timer", "/Devices/PCNet%d/PollTimer", iInstance);
4962 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatMIIReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of MII reads", "/Devices/PCNet%d/MIIReads", iInstance);
4963# ifdef PCNET_NO_POLLING
4964 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRCVRingWrite, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of receive ring writes", "/Devices/PCNet%d/Ring/RCVWrites", iInstance);
4965 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatTXRingWrite, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of transmit ring writes", "/Devices/PCNet%d/Ring/TXWrites", iInstance);
4966 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteHC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored ring page writes", "/Devices/PCNet%d/Ring/HC/Writes", iInstance);
4967 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteR0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored ring page writes", "/Devices/PCNet%d/Ring/R0/Writes", iInstance);
4968 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored ring page writes", "/Devices/PCNet%d/Ring/GC/Writes", iInstance);
4969 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteFailedHC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/HC/Failed", iInstance);
4970 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteFailedR0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/R0/Failed", iInstance);
4971 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteFailedGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/GC/Failed", iInstance);
4972 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteOutsideHC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring","/Devices/PCNet%d/Ring/HC/Outside", iInstance);
4973 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteOutsideR0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring","/Devices/PCNet%d/Ring/R0/Outside", iInstance);
4974 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteOutsideGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring","/Devices/PCNet%d/Ring/GC/Outside", iInstance);
4975# endif /* PCNET_NO_POLLING */
4976#endif
4977
4978 return VINF_SUCCESS;
4979}
4980
4981
4982/**
4983 * The device registration structure.
4984 */
4985const PDMDEVREG g_DevicePCNet =
4986{
4987 /* u32Version */
4988 PDM_DEVREG_VERSION,
4989 /* szDeviceName */
4990 "pcnet",
4991 /* szGCMod */
4992#ifdef PCNET_GC_ENABLED
4993 "VBoxDDGC.gc",
4994 "VBoxDDR0.r0",
4995#else
4996 "",
4997 "",
4998#endif
4999 /* pszDescription */
5000 "AMD PC-Net II Ethernet controller.\n",
5001 /* fFlags */
5002#ifdef PCNET_GC_ENABLED
5003 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
5004#else
5005 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT,
5006#endif
5007 /* fClass */
5008 PDM_DEVREG_CLASS_NETWORK,
5009 /* cMaxInstances */
5010 4,
5011 /* cbInstance */
5012 sizeof(PCNetState),
5013 /* pfnConstruct */
5014 pcnetConstruct,
5015 /* pfnDestruct */
5016 pcnetDestruct,
5017 /* pfnRelocate */
5018 pcnetRelocate,
5019 /* pfnIOCtl */
5020 NULL,
5021 /* pfnPowerOn */
5022 NULL,
5023 /* pfnReset */
5024 pcnetReset,
5025 /* pfnSuspend */
5026 pcnetSuspend,
5027 /* pfnResume */
5028 NULL,
5029 /* pfnAttach */
5030 NULL,
5031 /* pfnDetach */
5032 NULL,
5033 /* pfnQueryInterface. */
5034 NULL,
5035 /* pfnInitComplete. */
5036 NULL,
5037 /* pfnPowerOff. */
5038 pcnetPowerOff
5039};
5040
5041#endif /* IN_RING3 */
5042#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5043
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