pcibios.inc@ 42791

Last change on this file since 42791 was 42392, checked in by vboxsync, 13 years ago
BIOS: Use new C implementation for 32-bit PCI BIOS, too.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 6.6 KB

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1	;;
2	;; Copyright (C) 2006-2011 Oracle Corporation
3	;;
4	;; This file is part of VirtualBox Open Source Edition (OSE), as
5	;; available from http://www.virtualbox.org. This file is free software;
6	;; you can redistribute it and/or modify it under the terms of the GNU
7	;; General Public License (GPL) as published by the Free Software
8	;; Foundation, in version 2 as it comes in the "COPYING" file of the
9	;; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
10	;; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
11	;; --------------------------------------------------------------------
12	;;
13	;; This code is based on:
14	;;
15	;; ROM BIOS for use with Bochs/Plex86/QEMU emulation environment
16	;;
17	;; Copyright (C) 2002 MandrakeSoft S.A.
18	;;
19	;; MandrakeSoft S.A.
20	;; 43, rue d'Aboukir
21	;; 75002 Paris - France
22	;; http://www.linux-mandrake.com/
23	;; http://www.mandrakesoft.com/
24	;;
25	;; This library is free software; you can redistribute it and/or
26	;; modify it under the terms of the GNU Lesser General Public
27	;; License as published by the Free Software Foundation; either
28	;; version 2 of the License, or (at your option) any later version.
29	;;
30	;; This library is distributed in the hope that it will be useful,
31	;; but WITHOUT ANY WARRANTY; without even the implied warranty of
32	;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
33	;; Lesser General Public License for more details.
34	;;
35	;; You should have received a copy of the GNU Lesser General Public
36	;; License along with this library; if not, write to the Free Software
37	;; Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
38	;;
39	;;
40
41	include pcicfg.inc
42
43	if BX_PCIBIOS
44
45	ifdef DEBUG
46
47	; Publics for easier debugging and disassembly
48
49	public pcibios_init_iomem_bases
50	public pci_init_io_loop1
51	public pci_init_io_loop2
52	public init_io_base
53	public next_pci_base
54	public enable_iomem_space
55	public next_pci_dev
56	public pcibios_init_set_elcr
57	public is_master_pic
58	public pcibios_init_irqs
59	public pci_init_irq_loop1
60	public pci_init_irq_loop2
61	public pci_test_int_pin
62	public pirq_found
63	public next_pci_func
64	public next_pir_entry
65	public pci_init_end
66
67	endif
68
69	.386
70
71	if not BX_ROMBIOS32
72	pci_irq_list:
73	db 11, 10, 9, 5;
74
75	pcibios_init_sel_reg:
76	push eax
77	mov eax, 800000h
78	mov ax, bx
79	shl eax, 8
80	and dl, 0FCh
81	or al, dl
82	mov dx, PCI_CFG1
83	out dx, eax
84	pop eax
85	ret
86
87	pcibios_init_iomem_bases:
88	push bp
89	mov bp, sp
90	mov eax, 0E0000000h ; base for memory init
91	push eax
92	mov ax, 0D000h ; base for i/o init
93	push ax
94	mov ax, 010h ; start at base address #0
95	push ax
96	mov bx, 8
97	pci_init_io_loop1:
98	mov dl, 0
99	call pcibios_init_sel_reg
100	mov dx, PCI_CFG2
101	in ax, dx
102	cmp ax, 0FFFFh
103	jz next_pci_dev
104
105	ifndef VBOX ; This currently breaks restoring a previously saved state. */
106	mov dl, 4 ; disable i/o and memory space access
107	call pcibios_init_sel_reg
108	mov dx, PCI_CFG2
109	in al, dx
110	and al, 0FCh
111	out dx, al
112	pci_init_io_loop2:
113	mov dl, [bp-8]
114	call pcibios_init_sel_reg
115	mov dx, PCI_CFG2
116	in eax, dx
117	test al, 1
118	jnz init_io_base
119
120	mov ecx, eax
121	mov eax, 0FFFFFFFFh
122	out dx, eax
123	in eax, dx
124	cmp eax, ecx
125	je next_pci_base
126	xor eax, 0FFFFFFFFh
127	mov ecx, eax
128	mov eax, [bp-4]
129	out dx, eax
130	add eax, ecx ; calculate next free mem base
131	add eax, 01000000h
132	and eax, 0FF000000h
133	mov [bp-4], eax
134	jmp next_pci_base
135
136	init_io_base:
137	mov cx, ax
138	mov ax, 0FFFFh
139	out dx, eax
140	in eax, dx
141	cmp ax, cx
142	je next_pci_base
143
144	xor ax, 0FFFEh
145	mov cx, ax
146	mov ax, [bp-6]
147	out dx, eax
148	add ax, cx ; calculate next free i/o base
149	add ax, 00100h
150	and ax, 0FF00h
151	mov [bp-6], ax
152	next_pci_base:
153	mov al, [bp-8]
154	add al, 4
155	cmp al, 28h
156	je enable_iomem_space
157
158	mov byte ptr[bp-8], al
159	jmp pci_init_io_loop2
160	endif ; !VBOX
161
162	enable_iomem_space:
163	mov dl, 4 ;; enable i/o and memory space access if available
164	call pcibios_init_sel_reg
165	mov dx, PCI_CFG2
166	in al, dx
167	or al, 7
168	out dx, al
169	ifdef VBOX
170	mov dl, 0 ; check if PCI device is AMD PCNet
171	call pcibios_init_sel_reg
172	mov dx, PCI_CFG2
173	in eax, dx
174	cmp eax, 020001022h
175	jne next_pci_dev
176
177	mov dl, 10h ; get I/O address
178	call pcibios_init_sel_reg
179	mov dx, PCI_CFG2
180	in ax, dx
181	and ax, 0FFFCh
182	mov cx, ax
183	mov dx, cx
184	add dx, 14h ; reset register if PCNet is in word I/O mode
185	in ax, dx ; reset is performed by reading the reset register
186	mov dx, cx
187	add dx, 18h ; reset register if PCNet is in word I/O mode
188	in eax, dx ; reset is performed by reading the reset register
189	endif ; VBOX
190	next_pci_dev:
191	mov byte ptr[bp-8], 10h
192	inc bx
193	cmp bx, 0100h
194	jne pci_init_io_loop1
195	mov sp, bp
196	pop bp
197	ret
198
199	pcibios_init_set_elcr:
200	push ax
201	push cx
202	mov dx, 04D0h
203	test al, 8
204	jz is_master_pic
205
206	inc dx
207	and al, 7
208	is_master_pic:
209	mov cl, al
210	mov bl, 1
211	shl bl, cl
212	in al, dx
213	or al, bl
214	out dx, al
215	pop cx
216	pop ax
217	ret
218
219	pcibios_init_irqs:
220	push ds
221	push bp
222	mov ax, 0F000h
223	mov ds, ax
224	mov dx, 04D0h ;; reset ELCR1 + ELCR2
225	mov al, 0
226	out dx, al
227	inc dx
228	out dx, al
229	mov si, pci_routing_table_structure
230	mov bh, [si+8]
231	mov bl, [si+9]
232	mov dl, 0
233	call pcibios_init_sel_reg
234	mov dx, PCI_CFG2
235	in eax, dx
236	cmp eax, [si+12] ;; check irq router
237	jne pci_init_end
238
239	mov dl, [si+34]
240	call pcibios_init_sel_reg
241	push bx ;; save irq router bus + devfunc
242	mov dx, PCI_CFG2
243	mov ax, 8080h
244	out dx, ax ;; reset PIRQ route control
245	add dx, 2
246	out dx, ax
247	mov ax, [si+6]
248	sub ax, 20h
249	shr ax, 4
250	mov cx, ax
251	add si, 20h ;; set pointer to 1st entry
252	mov bp, sp
253	mov ax, pci_irq_list
254	push ax
255	xor ax, ax
256	push ax
257	pci_init_irq_loop1:
258	mov bh, [si]
259	mov bl, [si+1]
260	pci_init_irq_loop2:
261	mov dl, 0
262	call pcibios_init_sel_reg
263	mov dx, PCI_CFG2
264	in ax, dx
265	cmp ax, 0FFFFh
266	jnz pci_test_int_pin
267
268	test bl, 7
269	jz next_pir_entry
270
271	jmp next_pci_func
272
273	pci_test_int_pin:
274	mov dl, 3Ch
275	call pcibios_init_sel_reg
276	mov dx, PCI_CFG2 + 1 ; TODO: was #0x0cfd - is that right?
277	in al, dx
278	and al, 7
279	jz next_pci_func
280
281	dec al ;; determine pirq reg
282	mov dl, 3
283	mul dl
284	add al, 2
285	xor ah, ah
286	mov bx, ax
287	mov al, [si+bx]
288	mov dl, al
289	mov bx, [bp]
290	call pcibios_init_sel_reg
291	mov dx, PCI_CFG2
292	and al, 3
293	add dl, al
294	in al, dx
295	cmp al, 80h
296	jb pirq_found
297
298	mov bx, [bp-2] ;; pci irq list pointer
299	mov al, [bx]
300	out dx, al
301	inc bx
302	mov [bp-2], bx
303	call pcibios_init_set_elcr
304	pirq_found:
305	mov bh, [si]
306	mov bl, [si+1]
307	add bl, [bp-3] ;; pci function number
308	mov dl, 3Ch
309	call pcibios_init_sel_reg
310	mov dx, PCI_CFG2
311	out dx, al
312	next_pci_func:
313	inc byte ptr[bp-3]
314	inc bl
315	test bl, 7
316	jnz pci_init_irq_loop2
317
318	next_pir_entry:
319	add si, 10h
320	mov byte ptr[bp-3], 0
321	loop pci_init_irq_loop1
322
323	mov sp, bp
324	pop bx
325	pci_init_end:
326	pop bp
327	pop ds
328	ret
329
330	.286
331
332	endif ; !BX_ROMBIOS32
333
334	endif ; BX_PCIBIOS
335

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