VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 81984

Last change on this file since 81984 was 81984, checked in by vboxsync, 5 years ago

DevDMA: Converted I/O port handlers. bugref:9218
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1/* $Id: DevDMA.cpp 81984 2019-11-19 10:43:45Z vboxsync $ */
2/** @file
3 * DevDMA - DMA Controller Device.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 * --------------------------------------------------------------------
17 *
18 * This code is loosely based on:
19 *
20 * QEMU DMA emulation
21 *
22 * Copyright (c) 2003 Vassili Karpov (malc)
23 *
24 * Permission is hereby granted, free of charge, to any person obtaining a copy
25 * of this software and associated documentation files (the "Software"), to deal
26 * in the Software without restriction, including without limitation the rights
27 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28 * copies of the Software, and to permit persons to whom the Software is
29 * furnished to do so, subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice shall be included in
32 * all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40 * THE SOFTWARE.
41 */
42
43
44/*********************************************************************************************************************************
45* Header Files *
46*********************************************************************************************************************************/
47#define LOG_GROUP LOG_GROUP_DEV_DMA
48#include <VBox/vmm/pdmdev.h>
49#include <VBox/err.h>
50
51#include <VBox/log.h>
52#include <iprt/assert.h>
53#include <iprt/string.h>
54
55#include "VBoxDD.h"
56
57
58/** @page pg_dev_dma DMA Overview and notes
59 *
60 * Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
61 * cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
62 * The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
63 * 74LS612 extends addressing to 24 bits. That leads to well known and
64 * inconvenient DMA limitations:
65 * - DMA can only access physical memory under the 16MB line
66 * - DMA transfers must occur within a 64KB/128KB 'page'
67 *
68 * The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
69 * left by one, including the control registers addresses. The DMA register
70 * offsets (except for the page registers) are therefore "double spaced".
71 *
72 * Due to the address shifting, the DMA controller decodes more addresses
73 * than are usually documented, with aliasing. See the ICH8 datasheet.
74 *
75 * In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
76 * preventing the use of memory-to-memory DMA transfers (which use channels
77 * 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
78 * However, it would transfer a single byte at a time, while the CPU can
79 * transfer two (on a 286) or four (on a 386+) bytes at a time. On many
80 * compatibles, memory-to-memory DMA is not even implemented at all, and
81 * therefore has no practical use.
82 *
83 * Auto-init mode is handled implicitly; a device's transfer handler may
84 * return an end count lower than the start count.
85 *
86 * Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
87 * while 'chidx' refers to a DMA channel index within a controller (0-3).
88 *
89 * References:
90 * - IBM Personal Computer AT Technical Reference, 1984
91 * - Intel 8237A-5 Datasheet, 1993
92 * - Frank van Gilluwe, The Undocumented PC, 1994
93 * - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
94 * - Intel ICH8 Datasheet, 2007
95 */
96
97
98/* Saved state versions. */
99#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
100#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
101
102/* State information for a single DMA channel. */
103typedef struct {
104 RTR3PTR pvUser; /* User specific context. */
105 R3PTRTYPE(PFNDMATRANSFERHANDLER) pfnXferHandler; /* Transfer handler for channel. */
106 uint16_t u16BaseAddr; /* Base address for transfers. */
107 uint16_t u16BaseCount; /* Base count for transfers. */
108 uint16_t u16CurAddr; /* Current address. */
109 uint16_t u16CurCount; /* Current count. */
110 uint8_t u8Mode; /* Channel mode. */
111 uint8_t abPadding[7];
112} DMAChannel;
113
114/* State information for a DMA controller (DMA8 or DMA16). */
115typedef struct {
116 DMAChannel ChState[4]; /* Per-channel state. */
117 uint8_t au8Page[8]; /* Page registers (A16-A23). */
118 uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
119 uint8_t u8Command; /* Command register. */
120 uint8_t u8Status; /* Status register. */
121 uint8_t u8Mask; /* Mask register. */
122 uint8_t u8Temp; /* Temporary (mem/mem) register. */
123 uint8_t u8ModeCtr; /* Mode register counter for reads. */
124 bool fHiByte; /* Byte pointer (T/F -> high/low). */
125 uint8_t abPadding0[2];
126 uint32_t is16bit; /* True for 16-bit DMA. */
127 uint8_t abPadding1[4];
128 /** The base abd current address I/O port registration. */
129 IOMIOPORTHANDLE hIoPortBase;
130 /** The control register I/O port registration. */
131 IOMIOPORTHANDLE hIoPortCtl;
132 /** The page registers I/O port registration. */
133 IOMIOPORTHANDLE hIoPortPage;
134 /** The EISA style high page registers I/O port registration. */
135 IOMIOPORTHANDLE hIoPortHi;
136} DMAControl, DMACONTROLLER;
137/** Pointer to the shared DMA controller state. */
138typedef DMACONTROLLER *PDMACONTROLLER;
139
140/* Complete DMA state information. */
141typedef struct {
142 DMAControl DMAC[2]; /* Two DMA controllers. */
143 PPDMDEVINSR3 pDevIns; /* Device instance. */
144 R3PTRTYPE(PCPDMDMACHLP) pHlp; /* PDM DMA helpers. */
145} DMAState, DMASTATE;
146/** Pointer to the shared DMA state information. */
147typedef DMASTATE *PDMASTATE;
148
149/* DMA command register bits. */
150enum {
151 CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
152 CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
153 CMD_DISABLE = 0x04, /* Disable controller. */
154 CMD_COMPRTIME = 0x08, /* Compressed timing. */
155 CMD_ROTPRIO = 0x10, /* Rotating priority. */
156 CMD_EXTWR = 0x20, /* Extended write. */
157 CMD_DREQHI = 0x40, /* DREQ is active high if set. */
158 CMD_DACKHI = 0x80, /* DACK is active high if set. */
159 CMD_UNSUPPORTED = CMD_MEMTOMEM | CMD_ADRHOLD | CMD_COMPRTIME
160 | CMD_EXTWR | CMD_DREQHI | CMD_DACKHI
161};
162
163/* DMA control register offsets for read accesses. */
164enum {
165 CTL_R_STAT, /* Read status registers. */
166 CTL_R_DMAREQ, /* Read DRQ register. */
167 CTL_R_CMD, /* Read command register. */
168 CTL_R_MODE, /* Read mode register. */
169 CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
170 CTL_R_TEMP, /* Read temporary register. */
171 CTL_R_CLRMODE, /* Clear mode register counter. */
172 CTL_R_MASK /* Read all DRQ mask bits. */
173};
174
175/* DMA control register offsets for read accesses. */
176enum {
177 CTL_W_CMD, /* Write command register. */
178 CTL_W_DMAREQ, /* Write DRQ register. */
179 CTL_W_MASKONE, /* Write single DRQ mask bit. */
180 CTL_W_MODE, /* Write mode register. */
181 CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
182 CTL_W_MASTRCLR, /* Master clear. */
183 CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
184 CTL_W_MASK /* Write all DRQ mask bits. */
185};
186
187/* DMA transfer modes. */
188enum {
189 DMODE_DEMAND, /* Demand transfer mode. */
190 DMODE_SINGLE, /* Single transfer mode. */
191 DMODE_BLOCK, /* Block transfer mode. */
192 DMODE_CASCADE /* Cascade mode. */
193};
194
195/* DMA transfer types. */
196enum {
197 DTYPE_VERIFY, /* Verify transfer type. */
198 DTYPE_WRITE, /* Write transfer type. */
199 DTYPE_READ, /* Read transfer type. */
200 DTYPE_ILLEGAL /* Undefined. */
201};
202
203#ifndef VBOX_DEVICE_STRUCT_TESTCASE
204
205
206/* Convert DMA channel number (0-7) to controller number (0-1). */
207#define DMACH2C(c) (c < 4 ? 0 : 1)
208
209#ifdef LOG_ENABLED
210static int const g_aiDmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
211/* Map a DMA page register offset (0-7) to channel index (0-3). */
212# define DMAPG2CX(c) (g_aiDmaChannelMap[c])
213#endif
214
215#ifdef IN_RING3
216static int const g_aiDmaMapChannel[4] = {7, 3, 1, 2};
217/* Map a channel index (0-3) to DMA page register offset (0-7). */
218# define DMACX2PG(c) (g_aiDmaMapChannel[c])
219/* Map a channel number (0-7) to DMA page register offset (0-7). */
220# define DMACH2PG(c) (g_aiDmaMapChannel[c & 3])
221#endif
222
223/* Test the decrement bit of mode register. */
224#define IS_MODE_DEC(c) ((c) & 0x20)
225/* Test the auto-init bit of mode register. */
226#define IS_MODE_AI(c) ((c) & 0x10)
227/* Extract the transfer type bits of mode register. */
228#define GET_MODE_XTYP(c) (((c) & 0x0c) >> 2)
229
230
231/* Perform a master clear (reset) on a DMA controller. */
232static void dmaClear(DMAControl *dc)
233{
234 dc->u8Command = 0;
235 dc->u8Status = 0;
236 dc->u8Temp = 0;
237 dc->u8ModeCtr = 0;
238 dc->fHiByte = false;
239 dc->u8Mask = UINT8_MAX;
240}
241
242
243/** Read the byte pointer and flip it. */
244DECLINLINE(bool) dmaReadBytePtr(DMAControl *dc)
245{
246 bool fHighByte = !!dc->fHiByte;
247 dc->fHiByte ^= 1;
248 return fHighByte;
249}
250
251
252/* DMA address registers writes and reads. */
253
254/**
255 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0-7 & 0xc0-0xcf}
256 */
257static DECLCALLBACK(VBOXSTRICTRC) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
258{
259 RT_NOREF(pDevIns);
260 if (cb == 1)
261 {
262 DMAControl *dc = (DMAControl *)pvUser;
263 DMAChannel *ch;
264 int chidx, reg, is_count;
265
266 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
267 reg = (offPort >> dc->is16bit) & 0x0f;
268 chidx = reg >> 1;
269 is_count = reg & 1;
270 ch = &dc->ChState[chidx];
271 if (dmaReadBytePtr(dc))
272 {
273 /* Write the high byte. */
274 if (is_count)
275 ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
276 else
277 ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
278
279 ch->u16CurCount = 0;
280 ch->u16CurAddr = ch->u16BaseAddr;
281 }
282 else
283 {
284 /* Write the low byte. */
285 if (is_count)
286 ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
287 else
288 ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
289 }
290 Log2(("dmaWriteAddr: offPort %#06x, chidx %d, data %#02x\n", offPort, chidx, u32));
291 }
292 else
293 {
294 /* Likely a guest bug. */
295 Log(("Bad size write to count register %#x (size %d, data %#x)\n", offPort, cb, u32));
296 }
297 return VINF_SUCCESS;
298}
299
300
301/**
302 * @callback_method_impl{FNIOMIOPORTIN, Ports 0-7 & 0xc0-0xcf}
303 */
304static DECLCALLBACK(VBOXSTRICTRC) dmaReadAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
305{
306 RT_NOREF(pDevIns);
307 if (cb == 1)
308 {
309 DMAControl *dc = (DMAControl *)pvUser;
310 DMAChannel *ch;
311 int chidx, reg, val, dir;
312 int bptr;
313
314 reg = (offPort >> dc->is16bit) & 0x0f;
315 chidx = reg >> 1;
316 ch = &dc->ChState[chidx];
317
318 dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
319 if (reg & 1)
320 val = ch->u16BaseCount - ch->u16CurCount;
321 else
322 val = ch->u16CurAddr + ch->u16CurCount * dir;
323
324 bptr = dmaReadBytePtr(dc);
325 *pu32 = RT_LOBYTE(val >> (bptr * 8));
326
327 Log(("Count read: offPort %#06x, reg %#04x, data %#x\n", offPort, reg, val));
328 return VINF_SUCCESS;
329 }
330 return VERR_IOM_IOPORT_UNUSED;
331}
332
333/* DMA control registers writes and reads. */
334
335/**
336 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0x8-0xf & 0xd0-0xdf}
337 */
338static DECLCALLBACK(VBOXSTRICTRC) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
339{
340 RT_NOREF(pDevIns);
341 if (cb == 1)
342 {
343 DMAControl *dc = (DMAControl *)pvUser;
344 unsigned chidx = 0;
345
346 unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
347 Assert((int)reg >= CTL_W_CMD && reg <= CTL_W_MASK);
348 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
349
350 switch (reg) {
351 case CTL_W_CMD:
352 /* Unsupported commands are entirely ignored. */
353 if (u32 & CMD_UNSUPPORTED)
354 {
355 Log(("DMA command %#x is not supported, ignoring!\n", u32));
356 break;
357 }
358 dc->u8Command = u32;
359 break;
360 case CTL_W_DMAREQ:
361 chidx = u32 & 3;
362 if (u32 & 4)
363 dc->u8Status |= 1 << (chidx + 4);
364 else
365 dc->u8Status &= ~(1 << (chidx + 4));
366 dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
367 break;
368 case CTL_W_MASKONE:
369 chidx = u32 & 3;
370 if (u32 & 4)
371 dc->u8Mask |= 1 << chidx;
372 else
373 dc->u8Mask &= ~(1 << chidx);
374 break;
375 case CTL_W_MODE:
376 {
377 int op, opmode;
378
379 chidx = u32 & 3;
380 op = (u32 >> 2) & 3;
381 opmode = (u32 >> 6) & 3;
382 Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
383 chidx, op, IS_MODE_AI(u32) ? "" : "no ",
384 IS_MODE_DEC(u32) ? "de" : "in", opmode));
385
386 dc->ChState[chidx].u8Mode = u32;
387 break;
388 }
389 case CTL_W_CLRBPTR:
390 dc->fHiByte = false;
391 break;
392 case CTL_W_MASTRCLR:
393 dmaClear(dc);
394 break;
395 case CTL_W_CLRMASK:
396 dc->u8Mask = 0;
397 break;
398 case CTL_W_MASK:
399 dc->u8Mask = u32;
400 break;
401 default:
402 Assert(0);
403 break;
404 }
405 Log(("dmaWriteCtl: offPort %#06x, chidx %d, data %#02x\n", offPort, chidx, u32));
406 }
407 else
408 {
409 /* Likely a guest bug. */
410 Log(("Bad size write to controller register %#x (size %d, data %#x)\n", offPort, cb, u32));
411 }
412 return VINF_SUCCESS;
413}
414
415
416/**
417 * @callback_method_impl{FNIOMIOPORTIN, Ports 0x8-0xf & 0xd0-0xdf}
418 */
419static DECLCALLBACK(VBOXSTRICTRC) dmaReadCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
420{
421 RT_NOREF(pDevIns);
422 if (cb == 1)
423 {
424 DMAControl *dc = (DMAControl *)pvUser;
425 uint8_t val = 0;
426
427 unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
428 Assert((int)reg >= CTL_R_STAT && reg <= CTL_R_MASK);
429
430 switch (reg)
431 {
432 case CTL_R_STAT:
433 val = dc->u8Status;
434 dc->u8Status &= 0xf0; /* A read clears all TCs. */
435 break;
436 case CTL_R_DMAREQ:
437 val = (dc->u8Status >> 4) | 0xf0;
438 break;
439 case CTL_R_CMD:
440 val = dc->u8Command;
441 break;
442 case CTL_R_MODE:
443 val = dc->ChState[dc->u8ModeCtr].u8Mode | 3;
444 dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
445 break;
446 case CTL_R_SETBPTR:
447 dc->fHiByte = true;
448 break;
449 case CTL_R_TEMP:
450 val = dc->u8Temp;
451 break;
452 case CTL_R_CLRMODE:
453 dc->u8ModeCtr = 0;
454 break;
455 case CTL_R_MASK:
456 val = dc->u8Mask;
457 break;
458 default:
459 Assert(0);
460 break;
461 }
462
463 Log(("Ctrl read: offPort %#06x, reg %#04x, data %#x\n", offPort, reg, val));
464 *pu32 = val;
465
466 return VINF_SUCCESS;
467 }
468 return VERR_IOM_IOPORT_UNUSED;
469}
470
471
472
473/**
474 * @callback_method_impl{FNIOMIOPORTIN,
475 * DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
476 *
477 * There are 16 R/W page registers for compatibility with the IBM PC/AT; only
478 * some of those registers are used for DMA. The page register accessible via
479 * port 80h may be read to insert small delays or used as a scratch register by
480 * a BIOS.
481 */
482static DECLCALLBACK(VBOXSTRICTRC) dmaReadPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
483{
484 RT_NOREF(pDevIns);
485 DMAControl *dc = (DMAControl *)pvUser;
486 int reg;
487
488 if (cb == 1)
489 {
490 reg = offPort & 7;
491 *pu32 = dc->au8Page[reg];
492 Log2(("Read %#x (byte) from page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
493 return VINF_SUCCESS;
494 }
495
496 if (cb == 2)
497 {
498 reg = offPort & 7;
499 *pu32 = dc->au8Page[reg] | (dc->au8Page[(reg + 1) & 7] << 8);
500 Log2(("Read %#x (word) from page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
501 return VINF_SUCCESS;
502 }
503
504 return VERR_IOM_IOPORT_UNUSED;
505}
506
507
508/**
509 * @callback_method_impl{FNIOMIOPORTOUT,
510 * DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
511 */
512static DECLCALLBACK(VBOXSTRICTRC) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
513{
514 RT_NOREF(pDevIns);
515 DMAControl *dc = (DMAControl *)pvUser;
516 int reg;
517
518 if (cb == 1)
519 {
520 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
521 reg = offPort & 7;
522 dc->au8Page[reg] = u32;
523 dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
524 Log2(("Wrote %#x to page register %#x (channel %d)\n", u32, offPort, DMAPG2CX(reg)));
525 }
526 else if (cb == 2)
527 {
528 Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
529 reg = offPort & 7;
530 dc->au8Page[reg] = u32;
531 dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
532 reg = (offPort + 1) & 7;
533 dc->au8Page[reg] = u32 >> 8;
534 dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
535 }
536 else
537 {
538 /* Likely a guest bug. */
539 Log(("Bad size write to page register %#x (size %d, data %#x)\n", offPort, cb, u32));
540 }
541 return VINF_SUCCESS;
542}
543
544
545/**
546 * @callback_method_impl{FNIOMIOPORTIN,
547 * EISA style high page registers for extending the DMA addresses to cover
548 * the entire 32-bit address space. Ports 0x480-0x487 & 0x488-0x48f}
549 */
550static DECLCALLBACK(VBOXSTRICTRC) dmaReadHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
551{
552 RT_NOREF(pDevIns);
553 if (cb == 1)
554 {
555 DMAControl *dc = (DMAControl *)pvUser;
556 int reg;
557
558 reg = offPort & 7;
559 *pu32 = dc->au8PageHi[reg];
560 Log2(("Read %#x to from high page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
561 return VINF_SUCCESS;
562 }
563 return VERR_IOM_IOPORT_UNUSED;
564}
565
566
567/**
568 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0x480-0x487 & 0x488-0x48f}
569 */
570static DECLCALLBACK(VBOXSTRICTRC) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
571{
572 RT_NOREF(pDevIns);
573 if (cb == 1)
574 {
575 DMAControl *dc = (DMAControl *)pvUser;
576 int reg;
577
578 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
579 reg = offPort & 7;
580 dc->au8PageHi[reg] = u32;
581 Log2(("Wrote %#x to high page register %#x (channel %d)\n", u32, offPort, DMAPG2CX(reg)));
582 }
583 else
584 {
585 /* Likely a guest bug. */
586 Log(("Bad size write to high page register %#x (size %d, data %#x)\n", offPort, cb, u32));
587 }
588 return VINF_SUCCESS;
589}
590
591
592#ifdef IN_RING3
593
594/** Perform any pending transfers on a single DMA channel. */
595static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
596{
597 DMAControl *dc = &pThis->DMAC[ctlidx];
598 DMAChannel *ch = &dc->ChState[chidx];
599 uint32_t start_cnt, end_cnt;
600 int opmode;
601
602 opmode = (ch->u8Mode >> 6) & 3;
603
604 Log3(("DMA address %screment, mode %d\n",
605 IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
606 ch->u8Mode >> 6));
607
608 /* Addresses and counts are shifted for 16-bit channels. */
609 start_cnt = ch->u16CurCount << dc->is16bit;
610 /* NB: The device is responsible for examining the DMA mode and not
611 * transferring more than it should if auto-init is not in use.
612 */
613 end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
614 start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
615 ch->u16CurCount = end_cnt >> dc->is16bit;
616 /* Set the TC (Terminal Count) bit if transfer was completed. */
617 if (ch->u16CurCount == ch->u16BaseCount + 1)
618 switch (opmode)
619 {
620 case DMODE_DEMAND:
621 case DMODE_SINGLE:
622 case DMODE_BLOCK:
623 dc->u8Status |= RT_BIT(chidx);
624 Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
625 break;
626 default:
627 break;
628 }
629 Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
630}
631
632/**
633 * @interface_method_impl{PDMDMAREG,pfnRun}
634 */
635static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
636{
637 DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
638 DMAControl *dc;
639 int ctlidx, chidx, mask;
640 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
641
642 /* Run all controllers and channels. */
643 for (ctlidx = 0; ctlidx < 2; ++ctlidx)
644 {
645 dc = &pThis->DMAC[ctlidx];
646
647 /* If controller is disabled, don't even bother. */
648 if (dc->u8Command & CMD_DISABLE)
649 continue;
650
651 for (chidx = 0; chidx < 4; ++chidx)
652 {
653 mask = 1 << chidx;
654 if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
655 dmaRunChannel(pThis, ctlidx, chidx);
656 }
657 }
658
659 PDMCritSectLeave(pDevIns->pCritSectRoR3);
660 return 0;
661}
662
663/**
664 * @interface_method_impl{PDMDMAREG,pfnRegister}
665 */
666static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
667 PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
668{
669 DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
670 DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
671
672 LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
673
674 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
675 ch->pfnXferHandler = pfnTransferHandler;
676 ch->pvUser = pvUser;
677 PDMCritSectLeave(pDevIns->pCritSectRoR3);
678}
679
680/** Reverse the order of bytes in a memory buffer. */
681static void dmaReverseBuf8(void *buf, unsigned len)
682{
683 uint8_t *pBeg, *pEnd;
684 uint8_t temp;
685
686 pBeg = (uint8_t *)buf;
687 pEnd = pBeg + len - 1;
688 for (len = len / 2; len; --len)
689 {
690 temp = *pBeg;
691 *pBeg++ = *pEnd;
692 *pEnd-- = temp;
693 }
694}
695
696/** Reverse the order of words in a memory buffer. */
697static void dmaReverseBuf16(void *buf, unsigned len)
698{
699 uint16_t *pBeg, *pEnd;
700 uint16_t temp;
701
702 Assert(!(len & 1));
703 len /= 2; /* Convert to word count. */
704 pBeg = (uint16_t *)buf;
705 pEnd = pBeg + len - 1;
706 for (len = len / 2; len; --len)
707 {
708 temp = *pBeg;
709 *pBeg++ = *pEnd;
710 *pEnd-- = temp;
711 }
712}
713
714/**
715 * @interface_method_impl{PDMDMAREG,pfnReadMemory}
716 */
717static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
718 void *pvBuffer, uint32_t off, uint32_t cbBlock)
719{
720 DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
721 DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
722 DMAChannel *ch = &dc->ChState[uChannel & 3];
723 uint32_t page, pagehi;
724 uint32_t addr;
725
726 LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
727
728 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
729
730 /* Build the address for this transfer. */
731 page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
732 pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
733 addr = (pagehi << 24) | (page << 16) | (ch->u16CurAddr << dc->is16bit);
734
735 if (IS_MODE_DEC(ch->u8Mode))
736 {
737 PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
738 if (dc->is16bit)
739 dmaReverseBuf16(pvBuffer, cbBlock);
740 else
741 dmaReverseBuf8(pvBuffer, cbBlock);
742 }
743 else
744 PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
745
746 PDMCritSectLeave(pDevIns->pCritSectRoR3);
747 return cbBlock;
748}
749
750/**
751 * @interface_method_impl{PDMDMAREG,pfnWriteMemory}
752 */
753static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
754 const void *pvBuffer, uint32_t off, uint32_t cbBlock)
755{
756 DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
757 DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
758 DMAChannel *ch = &dc->ChState[uChannel & 3];
759 uint32_t page, pagehi;
760 uint32_t addr;
761
762 LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
763 if (GET_MODE_XTYP(ch->u8Mode) == DTYPE_VERIFY)
764 {
765 Log(("DMA verify transfer, ignoring write.\n"));
766 return cbBlock;
767 }
768
769 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
770
771 /* Build the address for this transfer. */
772 page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
773 pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
774 addr = (pagehi << 24) | (page << 16) | (ch->u16CurAddr << dc->is16bit);
775
776 if (IS_MODE_DEC(ch->u8Mode))
777 {
778 /// @todo This would need a temporary buffer.
779 Assert(0);
780#if 0
781 if (dc->is16bit)
782 dmaReverseBuf16(pvBuffer, cbBlock);
783 else
784 dmaReverseBuf8(pvBuffer, cbBlock);
785#endif
786 PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
787 }
788 else
789 PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
790
791 PDMCritSectLeave(pDevIns->pCritSectRoR3);
792 return cbBlock;
793}
794
795/**
796 * @interface_method_impl{PDMDMAREG,pfnSetDREQ}
797 */
798static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
799{
800 DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
801 DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
802 int chidx;
803
804 LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
805
806 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
807 chidx = uChannel & 3;
808 if (uLevel)
809 dc->u8Status |= 1 << (chidx + 4);
810 else
811 dc->u8Status &= ~(1 << (chidx + 4));
812 PDMCritSectLeave(pDevIns->pCritSectRoR3);
813}
814
815/**
816 * @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
817 */
818static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
819{
820 PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
821
822 LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
823
824 PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
825 uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
826 PDMCritSectLeave(pDevIns->pCritSectRoR3);
827 return u8Mode;
828}
829
830
831/**
832 * @interface_method_impl{PDMDEVREG,pfnReset}
833 */
834static DECLCALLBACK(void) dmaReset(PPDMDEVINS pDevIns)
835{
836 PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
837
838 LogFlow(("dmaReset: pThis=%p\n", pThis));
839
840 /* NB: The page and address registers are unaffected by a reset
841 * and in an undefined state after power-up.
842 */
843 dmaClear(&pThis->DMAC[0]);
844 dmaClear(&pThis->DMAC[1]);
845}
846
847static void dmaSaveController(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, DMAControl *dc)
848{
849 int chidx;
850
851 /* Save controller state... */
852 pHlp->pfnSSMPutU8(pSSM, dc->u8Command);
853 pHlp->pfnSSMPutU8(pSSM, dc->u8Mask);
854 pHlp->pfnSSMPutU8(pSSM, dc->fHiByte);
855 pHlp->pfnSSMPutU32(pSSM, dc->is16bit);
856 pHlp->pfnSSMPutU8(pSSM, dc->u8Status);
857 pHlp->pfnSSMPutU8(pSSM, dc->u8Temp);
858 pHlp->pfnSSMPutU8(pSSM, dc->u8ModeCtr);
859 pHlp->pfnSSMPutMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
860 pHlp->pfnSSMPutMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
861
862 /* ...and all four of its channels. */
863 for (chidx = 0; chidx < 4; ++chidx)
864 {
865 DMAChannel *ch = &dc->ChState[chidx];
866
867 pHlp->pfnSSMPutU16(pSSM, ch->u16CurAddr);
868 pHlp->pfnSSMPutU16(pSSM, ch->u16CurCount);
869 pHlp->pfnSSMPutU16(pSSM, ch->u16BaseAddr);
870 pHlp->pfnSSMPutU16(pSSM, ch->u16BaseCount);
871 pHlp->pfnSSMPutU8(pSSM, ch->u8Mode);
872 }
873}
874
875static int dmaLoadController(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, DMAControl *dc, int version)
876{
877 uint8_t u8val;
878 uint32_t u32val;
879 int chidx;
880
881 pHlp->pfnSSMGetU8(pSSM, &dc->u8Command);
882 pHlp->pfnSSMGetU8(pSSM, &dc->u8Mask);
883 pHlp->pfnSSMGetU8(pSSM, &u8val);
884 dc->fHiByte = !!u8val;
885 pHlp->pfnSSMGetU32(pSSM, &dc->is16bit);
886 if (version > DMA_SAVESTATE_OLD)
887 {
888 pHlp->pfnSSMGetU8(pSSM, &dc->u8Status);
889 pHlp->pfnSSMGetU8(pSSM, &dc->u8Temp);
890 pHlp->pfnSSMGetU8(pSSM, &dc->u8ModeCtr);
891 pHlp->pfnSSMGetMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
892 pHlp->pfnSSMGetMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
893 }
894
895 for (chidx = 0; chidx < 4; ++chidx)
896 {
897 DMAChannel *ch = &dc->ChState[chidx];
898
899 if (version == DMA_SAVESTATE_OLD)
900 {
901 /* Convert from 17-bit to 16-bit format. */
902 pHlp->pfnSSMGetU32(pSSM, &u32val);
903 ch->u16CurAddr = u32val >> dc->is16bit;
904 pHlp->pfnSSMGetU32(pSSM, &u32val);
905 ch->u16CurCount = u32val >> dc->is16bit;
906 }
907 else
908 {
909 pHlp->pfnSSMGetU16(pSSM, &ch->u16CurAddr);
910 pHlp->pfnSSMGetU16(pSSM, &ch->u16CurCount);
911 }
912 pHlp->pfnSSMGetU16(pSSM, &ch->u16BaseAddr);
913 pHlp->pfnSSMGetU16(pSSM, &ch->u16BaseCount);
914 pHlp->pfnSSMGetU8(pSSM, &ch->u8Mode);
915 /* Convert from old save state. */
916 if (version == DMA_SAVESTATE_OLD)
917 {
918 /* Remap page register contents. */
919 pHlp->pfnSSMGetU8(pSSM, &u8val);
920 dc->au8Page[DMACX2PG(chidx)] = u8val;
921 pHlp->pfnSSMGetU8(pSSM, &u8val);
922 dc->au8PageHi[DMACX2PG(chidx)] = u8val;
923 /* Throw away dack, eop. */
924 pHlp->pfnSSMGetU8(pSSM, &u8val);
925 pHlp->pfnSSMGetU8(pSSM, &u8val);
926 }
927 }
928 return 0;
929}
930
931/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
932static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
933{
934 PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
935 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
936
937 dmaSaveController(pHlp, pSSM, &pThis->DMAC[0]);
938 dmaSaveController(pHlp, pSSM, &pThis->DMAC[1]);
939 return VINF_SUCCESS;
940}
941
942/** @callback_method_impl{FNSSMDEVLOADEXEC} */
943static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
944{
945 PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
946 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
947
948 AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
949 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
950
951 dmaLoadController(pHlp, pSSM, &pThis->DMAC[0], uVersion);
952 return dmaLoadController(pHlp, pSSM, &pThis->DMAC[1], uVersion);
953}
954
955/**
956 * @interface_method_impl{PDMDEVREG,pfnConstruct}
957 */
958static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
959{
960 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
961 PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
962 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
963 RT_NOREF(iInstance);
964
965 /*
966 * Initialize data.
967 */
968 pThis->pDevIns = pDevIns;
969
970 DMAControl *pDC8 = &pThis->DMAC[0];
971 DMAControl *pDC16 = &pThis->DMAC[1];
972 pDC8->is16bit = false;
973 pDC16->is16bit = true;
974
975 /*
976 * Validate and read the configuration.
977 */
978 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "HighPageEnable", "");
979
980 bool fHighPage = false;
981 int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HighPageEnable", &fHighPage, false);
982 AssertRCReturn(rc, rc);
983
984 /*
985 * Register I/O callbacks.
986 */
987 /* Base and current address for each channel. */
988 rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x00, 8, dmaWriteAddr, dmaReadAddr, pDC8, "DMA8 Address", NULL, &pDC8->hIoPortBase);
989 AssertLogRelRCReturn(rc, rc);
990 rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xc0, 16, dmaWriteAddr, dmaReadAddr, pDC16, "DMA16 Address", NULL, &pDC16->hIoPortBase);
991 AssertLogRelRCReturn(rc, rc);
992
993 /* Control registers for both DMA controllers. */
994 rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x08, 8, dmaWriteCtl, dmaReadCtl, pDC8, "DMA8 Control", NULL, &pDC8->hIoPortCtl);
995 AssertLogRelRCReturn(rc, rc);
996 rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xd0, 16, dmaWriteCtl, dmaReadCtl, pDC16, "DMA16 Control", NULL, &pDC16->hIoPortCtl);
997 AssertLogRelRCReturn(rc, rc);
998
999 /* Page registers for each channel (plus a few unused ones). */
1000 rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x80, 8, dmaWritePage, dmaReadPage, pDC8, "DMA8 Page", NULL, &pDC8->hIoPortPage);
1001 AssertLogRelRCReturn(rc, rc);
1002 rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x88, 8, dmaWritePage, dmaReadPage, pDC16, "DMA16 Page", NULL, &pDC16->hIoPortPage);
1003 AssertLogRelRCReturn(rc, rc);
1004
1005 /* Optional EISA style high page registers (address bits 24-31). */
1006 if (fHighPage)
1007 {
1008 rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x480, 8, dmaWriteHiPage, dmaReadHiPage, pDC8, "DMA8 Page High", NULL, &pDC8->hIoPortHi);
1009 AssertLogRelRCReturn(rc, rc);
1010 rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x488, 8, dmaWriteHiPage, dmaReadHiPage, pDC16, "DMA16 Page High", NULL, &pDC16->hIoPortHi);
1011 AssertLogRelRCReturn(rc, rc);
1012 }
1013 else
1014 {
1015 pDC8->hIoPortHi = NIL_IOMIOPORTHANDLE;
1016 pDC16->hIoPortHi = NIL_IOMIOPORTHANDLE;
1017 }
1018
1019 /*
1020 * Reset controller state.
1021 */
1022 dmaReset(pDevIns);
1023
1024 /*
1025 * Register ourselves with PDM as the DMA controller.
1026 */
1027 PDMDMACREG Reg;
1028 Reg.u32Version = PDM_DMACREG_VERSION;
1029 Reg.pfnRun = dmaRun;
1030 Reg.pfnRegister = dmaRegister;
1031 Reg.pfnReadMemory = dmaReadMemory;
1032 Reg.pfnWriteMemory = dmaWriteMemory;
1033 Reg.pfnSetDREQ = dmaSetDREQ;
1034 Reg.pfnGetChannelMode = dmaGetChannelMode;
1035
1036 rc = PDMDevHlpDMACRegister(pDevIns, &Reg, &pThis->pHlp);
1037 AssertRCReturn(rc, rc);
1038
1039 /*
1040 * Register the saved state.
1041 */
1042 rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
1043 AssertRCReturn(rc, rc);
1044
1045 return VINF_SUCCESS;
1046}
1047
1048#else /* !IN_RING3 */
1049
1050/**
1051 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1052 */
1053static DECLCALLBACK(int) dmaRZConstruct(PPDMDEVINS pDevIns)
1054{
1055 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1056 PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
1057 int rc;
1058
1059 for (unsigned i = 0; i < RT_ELEMENTS(pThis->DMAC); i++)
1060 {
1061 PDMACONTROLLER pCtl = &pThis->DMAC[i];
1062
1063 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortBase, dmaWriteAddr, dmaReadAddr, pCtl);
1064 AssertLogRelRCReturn(rc, rc);
1065
1066 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortCtl, dmaWriteCtl, dmaReadCtl, pCtl);
1067 AssertLogRelRCReturn(rc, rc);
1068
1069 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortPage, dmaWritePage, dmaReadPage, pCtl);
1070 AssertLogRelRCReturn(rc, rc);
1071
1072 if (pCtl->hIoPortHi != NIL_IOMIOPORTHANDLE)
1073 {
1074 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortHi, dmaWriteHiPage, dmaReadHiPage, pCtl);
1075 AssertLogRelRCReturn(rc, rc);
1076 }
1077 }
1078
1079 return VINF_SUCCESS;
1080}
1081
1082#endif /* !IN_RING3 */
1083
1084/**
1085 * The device registration structure.
1086 */
1087const PDMDEVREG g_DeviceDMA =
1088{
1089 /* .u32Version = */ PDM_DEVREG_VERSION,
1090 /* .uReserved0 = */ 0,
1091 /* .szName = */ "8237A",
1092 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ,
1093 /* .fClass = */ PDM_DEVREG_CLASS_DMA,
1094 /* .cMaxInstances = */ 1,
1095 /* .uSharedVersion = */ 42,
1096 /* .cbInstanceShared = */ sizeof(DMAState),
1097 /* .cbInstanceCC = */ 0,
1098 /* .cbInstanceRC = */ 0,
1099 /* .cMaxPciDevices = */ 0,
1100 /* .cMaxMsixVectors = */ 0,
1101 /* .pszDescription = */ "DMA Controller Device",
1102#if defined(IN_RING3)
1103 /* .pszRCMod = */ "VBoxDDRC.rc",
1104 /* .pszR0Mod = */ "VBoxDDR0.r0",
1105 /* .pfnConstruct = */ dmaConstruct,
1106 /* .pfnDestruct = */ NULL,
1107 /* .pfnRelocate = */ NULL,
1108 /* .pfnMemSetup = */ NULL,
1109 /* .pfnPowerOn = */ NULL,
1110 /* .pfnReset = */ dmaReset,
1111 /* .pfnSuspend = */ NULL,
1112 /* .pfnResume = */ NULL,
1113 /* .pfnAttach = */ NULL,
1114 /* .pfnDetach = */ NULL,
1115 /* .pfnQueryInterface = */ NULL,
1116 /* .pfnInitComplete = */ NULL,
1117 /* .pfnPowerOff = */ NULL,
1118 /* .pfnSoftReset = */ NULL,
1119 /* .pfnReserved0 = */ NULL,
1120 /* .pfnReserved1 = */ NULL,
1121 /* .pfnReserved2 = */ NULL,
1122 /* .pfnReserved3 = */ NULL,
1123 /* .pfnReserved4 = */ NULL,
1124 /* .pfnReserved5 = */ NULL,
1125 /* .pfnReserved6 = */ NULL,
1126 /* .pfnReserved7 = */ NULL,
1127#elif defined(IN_RING0)
1128 /* .pfnEarlyConstruct = */ NULL,
1129 /* .pfnConstruct = */ dmaRZConstruct,
1130 /* .pfnDestruct = */ NULL,
1131 /* .pfnFinalDestruct = */ NULL,
1132 /* .pfnRequest = */ NULL,
1133 /* .pfnReserved0 = */ NULL,
1134 /* .pfnReserved1 = */ NULL,
1135 /* .pfnReserved2 = */ NULL,
1136 /* .pfnReserved3 = */ NULL,
1137 /* .pfnReserved4 = */ NULL,
1138 /* .pfnReserved5 = */ NULL,
1139 /* .pfnReserved6 = */ NULL,
1140 /* .pfnReserved7 = */ NULL,
1141#elif defined(IN_RC)
1142 /* .pfnConstruct = */ dmaRZConstruct,
1143 /* .pfnReserved0 = */ NULL,
1144 /* .pfnReserved1 = */ NULL,
1145 /* .pfnReserved2 = */ NULL,
1146 /* .pfnReserved3 = */ NULL,
1147 /* .pfnReserved4 = */ NULL,
1148 /* .pfnReserved5 = */ NULL,
1149 /* .pfnReserved6 = */ NULL,
1150 /* .pfnReserved7 = */ NULL,
1151#else
1152# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1153#endif
1154 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
1155};
1156
1157#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1158
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