VirtualBox

Ignore:
Timestamp:
Nov 19, 2019 10:43:45 AM (5 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
134783
Message:

DevDMA: Converted I/O port handlers. bugref:9218

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/PC/DevDMA.cpp

    r81979 r81984  
    126126    uint32_t    is16bit;        /* True for 16-bit DMA. */
    127127    uint8_t     abPadding1[4];
    128 } DMAControl;
     128    /** The base abd current address I/O port registration. */
     129    IOMIOPORTHANDLE hIoPortBase;
     130    /** The control register I/O port registration. */
     131    IOMIOPORTHANDLE hIoPortCtl;
     132    /** The page registers I/O port registration. */
     133    IOMIOPORTHANDLE hIoPortPage;
     134    /** The EISA style high page registers I/O port registration. */
     135    IOMIOPORTHANDLE hIoPortHi;
     136} DMAControl, DMACONTROLLER;
     137/** Pointer to the shared DMA controller state. */
     138typedef DMACONTROLLER *PDMACONTROLLER;
    129139
    130140/* Complete DMA state information. */
    … …  
    245255 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0-7 & 0xc0-0xcf}
    246256 */
    247 PDMBOTHCBDECL(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
     257static DECLCALLBACK(VBOXSTRICTRC) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
    248258{
    249259    RT_NOREF(pDevIns);
    … …  
    255265
    256266        Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
    257         reg      = (port >> dc->is16bit) & 0x0f;
     267        reg      = (offPort >> dc->is16bit) & 0x0f;
    258268        chidx    = reg >> 1;
    259269        is_count = reg & 1;
    … …  
    278288                ch->u16BaseAddr  = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
    279289        }
    280         Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
    281               port, chidx, u32));
     290        Log2(("dmaWriteAddr: offPort %#06x, chidx %d, data %#02x\n", offPort, chidx, u32));
    282291    }
    283292    else
    284293    {
    285294        /* Likely a guest bug. */
    286         Log(("Bad size write to count register %#x (size %d, data %#x)\n",
    287              port, cb, u32));
     295        Log(("Bad size write to count register %#x (size %d, data %#x)\n", offPort, cb, u32));
    288296    }
    289297    return VINF_SUCCESS;
    … …  
    294302 * @callback_method_impl{FNIOMIOPORTIN, Ports 0-7 & 0xc0-0xcf}
    295303 */
    296 PDMBOTHCBDECL(int) dmaReadAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb)
     304static DECLCALLBACK(VBOXSTRICTRC) dmaReadAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
    297305{
    298306    RT_NOREF(pDevIns);
    … …  
    304312        int         bptr;
    305313
    306         reg   = (port >> dc->is16bit) & 0x0f;
     314        reg   = (offPort >> dc->is16bit) & 0x0f;
    307315        chidx = reg >> 1;
    308316        ch    = &dc->ChState[chidx];
    … …  
    317325        *pu32 = RT_LOBYTE(val >> (bptr * 8));
    318326
    319         Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
     327        Log(("Count read: offPort %#06x, reg %#04x, data %#x\n", offPort, reg, val));
    320328        return VINF_SUCCESS;
    321329    }
    … …  
    328336 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0x8-0xf & 0xd0-0xdf}
    329337 */
    330 PDMBOTHCBDECL(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
     338static DECLCALLBACK(VBOXSTRICTRC) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
    331339{
    332340    RT_NOREF(pDevIns);
    … …  
    334342    {
    335343        DMAControl  *dc = (DMAControl *)pvUser;
    336         int         chidx = 0;
    337         int         reg;
    338 
    339         reg = ((port >> dc->is16bit) & 0x0f) - 8;
    340         Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
     344        unsigned     chidx = 0;
     345
     346        unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
     347        Assert((int)reg >= CTL_W_CMD && reg <= CTL_W_MASK);
    341348        Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
    342349
    … …  
    396403            break;
    397404        }
    398         Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
    399               port, chidx, u32));
     405        Log(("dmaWriteCtl: offPort %#06x, chidx %d, data %#02x\n", offPort, chidx, u32));
    400406    }
    401407    else
    402408    {
    403409        /* Likely a guest bug. */
    404         Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
    405              port, cb, u32));
     410        Log(("Bad size write to controller register %#x (size %d, data %#x)\n", offPort, cb, u32));
    406411    }
    407412    return VINF_SUCCESS;
    … …  
    412417 * @callback_method_impl{FNIOMIOPORTIN, Ports 0x8-0xf & 0xd0-0xdf}
    413418 */
    414 PDMBOTHCBDECL(int) dmaReadCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb)
     419static DECLCALLBACK(VBOXSTRICTRC) dmaReadCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
    415420{
    416421    RT_NOREF(pDevIns);
    … …  
    419424        DMAControl  *dc = (DMAControl *)pvUser;
    420425        uint8_t     val = 0;
    421         int         reg;
    422 
    423         reg = ((port >> dc->is16bit) & 0x0f) - 8;
    424         Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
     426
     427        unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
     428        Assert((int)reg >= CTL_R_STAT && reg <= CTL_R_MASK);
    425429
    426430        switch (reg)
    … …  
    457461        }
    458462
    459         Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
     463        Log(("Ctrl read: offPort %#06x, reg %#04x, data %#x\n", offPort, reg, val));
    460464        *pu32 = val;
    461465
    … …  
    476480 * a BIOS.
    477481 */
    478 PDMBOTHCBDECL(int) dmaReadPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb)
     482static DECLCALLBACK(VBOXSTRICTRC) dmaReadPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
    479483{
    480484    RT_NOREF(pDevIns);
    … …  
    484488    if (cb == 1)
    485489    {
    486         reg   = port & 7;
     490        reg   = offPort & 7;
    487491        *pu32 = dc->au8Page[reg];
    488         Log2(("Read %#x (byte) from page register %#x (channel %d)\n",
    489               *pu32, port, DMAPG2CX(reg)));
     492        Log2(("Read %#x (byte) from page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
    490493        return VINF_SUCCESS;
    491494    }
    … …  
    493496    if (cb == 2)
    494497    {
    495         reg   = port & 7;
     498        reg   = offPort & 7;
    496499        *pu32 = dc->au8Page[reg] | (dc->au8Page[(reg + 1) & 7] << 8);
    497         Log2(("Read %#x (word) from page register %#x (channel %d)\n",
    498               *pu32, port, DMAPG2CX(reg)));
     500        Log2(("Read %#x (word) from page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
    499501        return VINF_SUCCESS;
    500502    }
    … …  
    508510 *      DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
    509511 */
    510 PDMBOTHCBDECL(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
     512static DECLCALLBACK(VBOXSTRICTRC) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
    511513{
    512514    RT_NOREF(pDevIns);
    … …  
    517519    {
    518520        Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
    519         reg = port & 7;
     521        reg = offPort & 7;
    520522        dc->au8Page[reg]   = u32;
    521523        dc->au8PageHi[reg] = 0;  /* Corresponding high page cleared. */
    522         Log2(("Wrote %#x to page register %#x (channel %d)\n",
    523               u32, port, DMAPG2CX(reg)));
     524        Log2(("Wrote %#x to page register %#x (channel %d)\n", u32, offPort, DMAPG2CX(reg)));
    524525    }
    525526    else if (cb == 2)
    526527    {
    527528        Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
    528         reg = port & 7;
     529        reg = offPort & 7;
    529530        dc->au8Page[reg]   = u32;
    530531        dc->au8PageHi[reg] = 0;  /* Corresponding high page cleared. */
    531         reg = (port + 1) & 7;
     532        reg = (offPort + 1) & 7;
    532533        dc->au8Page[reg]   = u32 >> 8;
    533534        dc->au8PageHi[reg] = 0;  /* Corresponding high page cleared. */
    … …  
    536537    {
    537538        /* Likely a guest bug. */
    538         Log(("Bad size write to page register %#x (size %d, data %#x)\n",
    539              port, cb, u32));
     539        Log(("Bad size write to page register %#x (size %d, data %#x)\n", offPort, cb, u32));
    540540    }
    541541    return VINF_SUCCESS;
    … …  
    548548 *      the entire 32-bit address space.  Ports 0x480-0x487 & 0x488-0x48f}
    549549 */
    550 PDMBOTHCBDECL(int) dmaReadHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb)
     550static DECLCALLBACK(VBOXSTRICTRC) dmaReadHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
    551551{
    552552    RT_NOREF(pDevIns);
    … …  
    556556        int         reg;
    557557
    558         reg   = port & 7;
     558        reg   = offPort & 7;
    559559        *pu32 = dc->au8PageHi[reg];
    560         Log2(("Read %#x to from high page register %#x (channel %d)\n",
    561               *pu32, port, DMAPG2CX(reg)));
     560        Log2(("Read %#x to from high page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
    562561        return VINF_SUCCESS;
    563562    }
    … …  
    569568 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0x480-0x487 & 0x488-0x48f}
    570569 */
    571 PDMBOTHCBDECL(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
     570static DECLCALLBACK(VBOXSTRICTRC) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
    572571{
    573572    RT_NOREF(pDevIns);
    … …  
    578577
    579578        Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
    580         reg = port & 7;
     579        reg = offPort & 7;
    581580        dc->au8PageHi[reg] = u32;
    582         Log2(("Wrote %#x to high page register %#x (channel %d)\n",
    583               u32, port, DMAPG2CX(reg)));
     581        Log2(("Wrote %#x to high page register %#x (channel %d)\n", u32, offPort, DMAPG2CX(reg)));
    584582    }
    585583    else
    586584    {
    587585        /* Likely a guest bug. */
    588         Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
    589              port, cb, u32));
     586        Log(("Bad size write to high page register %#x (size %d, data %#x)\n", offPort, cb, u32));
    590587    }
    591588    return VINF_SUCCESS;
    … …  
    846843    dmaClear(&pThis->DMAC[0]);
    847844    dmaClear(&pThis->DMAC[1]);
    848 }
    849 
    850 /** Register DMA I/O port handlers. */
    851 static int dmaIORegister(PPDMDEVINS pDevIns, bool fHighPage)
    852 {
    853     DMAState    *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
    854     DMAControl  *dc8   = &pThis->DMAC[0];
    855     DMAControl  *dc16  = &pThis->DMAC[1];
    856     int          rc;
    857 
    858     dc8->is16bit  = false;
    859     dc16->is16bit = true;
    860 
    861     /* Base and current address for each channel. */
    862     rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x00, 8, dc8,       dmaWriteAddr,   dmaReadAddr,   NULL, NULL, "DMA8 Address");
    863     AssertLogRelRCReturn(rc, rc);
    864     rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0xC0, 16, dc16,     dmaWriteAddr,   dmaReadAddr,   NULL, NULL, "DMA16 Address");
    865     AssertLogRelRCReturn(rc, rc);
    866 
    867     /* Control registers for both DMA controllers. */
    868     rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x08, 8, dc8,       dmaWriteCtl,    dmaReadCtl,    NULL, NULL, "DMA8 Control");
    869     AssertLogRelRCReturn(rc, rc);
    870     rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0xD0, 16, dc16,     dmaWriteCtl,    dmaReadCtl,    NULL, NULL, "DMA16 Control");
    871     AssertLogRelRCReturn(rc, rc);
    872 
    873     /* Page registers for each channel (plus a few unused ones). */
    874     rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x80, 8, dc8,       dmaWritePage,   dmaReadPage,   NULL, NULL, "DMA8 Page");
    875     AssertLogRelRCReturn(rc, rc);
    876     rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x88, 8, dc16,      dmaWritePage,   dmaReadPage,   NULL, NULL, "DMA16 Page");
    877     AssertLogRelRCReturn(rc, rc);
    878 
    879     /* Optional EISA style high page registers (address bits 24-31). */
    880     if (fHighPage)
    881     {
    882         rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x480, 8, dc8,  dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
    883         AssertLogRelRCReturn(rc, rc);
    884         rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x488, 8, dc16, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
    885         AssertLogRelRCReturn(rc, rc);
    886     }
    887 
    888     if (pDevIns->fRCEnabled)
    889     {
    890         /*
    891          * Ditto for raw-mode.
    892          */
    893         RTRCPTR RCPtrDc8  = PDMINS_2_DATA_RCPTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[0]);
    894         RTRCPTR RCPtrDc16 = PDMINS_2_DATA_RCPTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[1]);
    895 
    896         /* Base and current address for each channel. */
    897         rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x00, 8, RCPtrDc8,       "dmaWriteAddr",   "dmaReadAddr",   NULL, NULL, "DMA8 Address");
    898         AssertLogRelRCReturn(rc, rc);
    899         rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0xC0, 16, RCPtrDc16,     "dmaWriteAddr",   "dmaReadAddr",   NULL, NULL, "DMA16 Address");
    900         AssertLogRelRCReturn(rc, rc);
    901 
    902         /* Control registers for both DMA controllers. */
    903         rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x08, 8, RCPtrDc8,       "dmaWriteCtl",    "dmaReadCtl",    NULL, NULL, "DMA8 Control");
    904         AssertLogRelRCReturn(rc, rc);
    905         rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0xD0, 16, RCPtrDc16,     "dmaWriteCtl",    "dmaReadCtl",    NULL, NULL, "DMA16 Control");
    906         AssertLogRelRCReturn(rc, rc);
    907 
    908         /* Page registers for each channel (plus a few unused ones). */
    909         rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x80, 8, RCPtrDc8,       "dmaWritePage",   "dmaReadPage",   NULL, NULL, "DMA8 Page");
    910         AssertLogRelRCReturn(rc, rc);
    911         rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x88, 8, RCPtrDc16,      "dmaWritePage",   "dmaReadPage",   NULL, NULL, "DMA16 Page");
    912         AssertLogRelRCReturn(rc, rc);
    913 
    914         /* Optional EISA style high page registers (address bits 24-31). */
    915         if (fHighPage)
    916         {
    917             rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x480, 8, RCPtrDc8,  "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA8 Page High");
    918             AssertLogRelRCReturn(rc, rc);
    919             rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x488, 8, RCPtrDc16, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA16 Page High");
    920             AssertLogRelRCReturn(rc, rc);
    921         }
    922     }
    923     if (pDevIns->fR0Enabled)
    924     {
    925         /*
    926          * Ditto for ring-0.
    927          */
    928         RTR0PTR R0PtrDc8  = PDMINS_2_DATA_R0PTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[0]);
    929         RTR0PTR R0PtrDc16 = PDMINS_2_DATA_R0PTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[1]);
    930 
    931         /* Base and current address for each channel. */
    932         rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x00, 8, R0PtrDc8,       "dmaWriteAddr",   "dmaReadAddr",   NULL, NULL, "DMA8 Address");
    933         AssertLogRelRCReturn(rc, rc);
    934         rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0xC0, 16, R0PtrDc16,     "dmaWriteAddr",   "dmaReadAddr",   NULL, NULL, "DMA16 Address");
    935         AssertLogRelRCReturn(rc, rc);
    936 
    937         /* Control registers for both DMA controllers. */
    938         rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x08, 8, R0PtrDc8,       "dmaWriteCtl",    "dmaReadCtl",    NULL, NULL, "DMA8 Control");
    939         AssertLogRelRCReturn(rc, rc);
    940         rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0xD0, 16, R0PtrDc16,     "dmaWriteCtl",    "dmaReadCtl",    NULL, NULL, "DMA16 Control");
    941         AssertLogRelRCReturn(rc, rc);
    942 
    943         /* Page registers for each channel (plus a few unused ones). */
    944         rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x80, 8, R0PtrDc8,       "dmaWritePage",   "dmaReadPage",   NULL, NULL, "DMA8 Page");
    945         AssertLogRelRCReturn(rc, rc);
    946         rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x88, 8, R0PtrDc16,      "dmaWritePage",   "dmaReadPage",   NULL, NULL, "DMA16 Page");
    947         AssertLogRelRCReturn(rc, rc);
    948 
    949         /* Optional EISA style high page registers (address bits 24-31). */
    950         if (fHighPage)
    951         {
    952             rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x480, 8, R0PtrDc8,  "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA8 Page High");
    953             AssertLogRelRCReturn(rc, rc);
    954             rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x488, 8, R0PtrDc16, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA16 Page High");
    955             AssertLogRelRCReturn(rc, rc);
    956         }
    957     }
    958 
    959     return VINF_SUCCESS;
    960845}
    961846
    … …  
    1083968    pThis->pDevIns = pDevIns;
    1084969
     970    DMAControl  *pDC8   = &pThis->DMAC[0];
     971    DMAControl  *pDC16  = &pThis->DMAC[1];
     972    pDC8->is16bit  = false;
     973    pDC16->is16bit = true;
     974
    1085975    /*
    1086976     * Validate and read the configuration.
    … …  
    1090980    bool fHighPage = false;
    1091981    int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HighPageEnable", &fHighPage, false);
    1092     AssertReturn(rc, rc);
     982    AssertRCReturn(rc, rc);
    1093983
    1094984    /*
    1095985     * Register I/O callbacks.
    1096986     */
    1097     rc = dmaIORegister(pDevIns, fHighPage);
     987    /* Base and current address for each channel. */
     988    rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x00, 8,  dmaWriteAddr, dmaReadAddr,  pDC8, "DMA8 Address",  NULL,  &pDC8->hIoPortBase);
    1098989    AssertLogRelRCReturn(rc, rc);
     990    rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xc0, 16, dmaWriteAddr, dmaReadAddr, pDC16, "DMA16 Address", NULL, &pDC16->hIoPortBase);
     991    AssertLogRelRCReturn(rc, rc);
     992
     993    /* Control registers for both DMA controllers. */
     994    rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x08, 8,  dmaWriteCtl,  dmaReadCtl,   pDC8, "DMA8 Control",  NULL, &pDC8->hIoPortCtl);
     995    AssertLogRelRCReturn(rc, rc);
     996    rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xd0, 16, dmaWriteCtl,  dmaReadCtl,  pDC16, "DMA16 Control", NULL, &pDC16->hIoPortCtl);
     997    AssertLogRelRCReturn(rc, rc);
     998
     999    /* Page registers for each channel (plus a few unused ones). */
     1000    rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x80, 8, dmaWritePage, dmaReadPage,   pDC8, "DMA8 Page",     NULL, &pDC8->hIoPortPage);
     1001    AssertLogRelRCReturn(rc, rc);
     1002    rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x88, 8, dmaWritePage, dmaReadPage,  pDC16, "DMA16 Page",    NULL, &pDC16->hIoPortPage);
     1003    AssertLogRelRCReturn(rc, rc);
     1004
     1005    /* Optional EISA style high page registers (address bits 24-31). */
     1006    if (fHighPage)
     1007    {
     1008        rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x480, 8, dmaWriteHiPage, dmaReadHiPage, pDC8,  "DMA8 Page High",  NULL,  &pDC8->hIoPortHi);
     1009        AssertLogRelRCReturn(rc, rc);
     1010        rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x488, 8, dmaWriteHiPage, dmaReadHiPage, pDC16, "DMA16 Page High", NULL, &pDC16->hIoPortHi);
     1011        AssertLogRelRCReturn(rc, rc);
     1012    }
     1013    else
     1014    {
     1015        pDC8->hIoPortHi  = NIL_IOMIOPORTHANDLE;
     1016        pDC16->hIoPortHi = NIL_IOMIOPORTHANDLE;
     1017    }
    10991018
    11001019    /*
    … …  
    11161035
    11171036    rc = PDMDevHlpDMACRegister(pDevIns, &Reg, &pThis->pHlp);
    1118     AssertReturn(rc, rc);
     1037    AssertRCReturn(rc, rc);
    11191038
    11201039    /*
    … …  
    11221041     */
    11231042    rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
    1124     AssertReturn(rc, rc);
     1043    AssertRCReturn(rc, rc);
    11251044
    11261045    return VINF_SUCCESS;
    11271046}
    11281047
    1129 #endif /* IN_RING3 */
     1048#else  /* !IN_RING3 */
     1049
     1050/**
     1051 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
     1052 */
     1053static DECLCALLBACK(int) dmaRZConstruct(PPDMDEVINS pDevIns)
     1054{
     1055    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
     1056    PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
     1057    int rc;
     1058
     1059    for (unsigned i = 0; i < RT_ELEMENTS(pThis->DMAC); i++)
     1060    {
     1061        PDMACONTROLLER pCtl = &pThis->DMAC[i];
     1062
     1063        rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortBase, dmaWriteAddr, dmaReadAddr, pCtl);
     1064        AssertLogRelRCReturn(rc, rc);
     1065
     1066        rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortCtl, dmaWriteCtl,  dmaReadCtl,   pCtl);
     1067        AssertLogRelRCReturn(rc, rc);
     1068
     1069        rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortPage, dmaWritePage, dmaReadPage,   pCtl);
     1070        AssertLogRelRCReturn(rc, rc);
     1071
     1072        if (pCtl->hIoPortHi != NIL_IOMIOPORTHANDLE)
     1073        {
     1074            rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortHi, dmaWriteHiPage, dmaReadHiPage, pCtl);
     1075            AssertLogRelRCReturn(rc, rc);
     1076        }
     1077    }
     1078
     1079    return VINF_SUCCESS;
     1080}
     1081
     1082#endif /* !IN_RING3 */
    11301083
    11311084/**
    … …  
    11741127#elif defined(IN_RING0)
    11751128    /* .pfnEarlyConstruct = */      NULL,
    1176     /* .pfnConstruct = */           NULL,
     1129    /* .pfnConstruct = */           dmaRZConstruct,
    11771130    /* .pfnDestruct = */            NULL,
    11781131    /* .pfnFinalDestruct = */       NULL,
    … …  
    11871140    /* .pfnReserved7 = */           NULL,
    11881141#elif defined(IN_RC)
    1189     /* .pfnConstruct = */           NULL,
     1142    /* .pfnConstruct = */           dmaRZConstruct,
    11901143    /* .pfnReserved0 = */           NULL,
    11911144    /* .pfnReserved1 = */           NULL,
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