DevIoApic.cpp@ 88638

Last change on this file since 88638 was 88638, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 Refactor some PDM-IOMMU interfaces to differentiate between device present vs. device instance available in current context (ring-0/ring-3). This should help us to support IOMMU as ring-3-only device in the future. Still more work to do in that regard (PDM task queue), but one step at a time.
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1	/* $Id: DevIoApic.cpp 88638 2021-04-22 05:40:05Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/pci.h>
27	#include <VBox/vmm/pdmdev.h>
28
29	#include "VBoxDD.h"
30	#include <iprt/x86.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** The current IO APIC saved state version. */
38	#define IOAPIC_SAVED_STATE_VERSION 2
39	/** The saved state version used by VirtualBox 5.0 and
40	* earlier. */
41	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
42
43	/** Implementation specified by the "Intel I/O Controller Hub 9
44	* (ICH9) Family" */
45	#define IOAPIC_VERSION_ICH9 0x20
46	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
47	Controller" */
48	#define IOAPIC_VERSION_82093AA 0x11
49
50	/** The default MMIO base physical address. */
51	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
52	/** The size of the MMIO range. */
53	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
54	/** The mask for getting direct registers from physical address. */
55	#define IOAPIC_MMIO_REG_MASK 0xff
56
57	/** The number of interrupt input pins. */
58	#define IOAPIC_NUM_INTR_PINS 24
59	/** Maximum redirection entires. */
60	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
61	/** Reduced RTEs used by SIO.A (82379AB). */
62	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
63
64	/** Version register - Gets the version. */
65	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
66	/** Version register - Gets the maximum redirection entry. */
67	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
68	/** Version register - Gets whether Pin Assertion Register (PRQ) is
69	* supported. */
70	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
71
72	/** Index register - Valid write mask. */
73	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
74
75	/** Arbitration register - Gets the ID. */
76	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
77
78	/** ID register - Gets the ID. */
79	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
80
81	/** Redirection table entry - Vector. */
82	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
83	/** Redirection table entry - Delivery mode. */
84	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
85	/** Redirection table entry - Destination mode. */
86	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
87	/** Redirection table entry - Delivery status. */
88	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
89	/** Redirection table entry - Interrupt input pin polarity. */
90	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
91	/** Redirection table entry - Remote IRR. */
92	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
93	/** Redirection table entry - Trigger Mode. */
94	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
95	/** Redirection table entry - the mask bit number. */
96	#define IOAPIC_RTE_MASK_BIT 16
97	/** Redirection table entry - the mask. */
98	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
99	/** Redirection table entry - Extended Destination ID. */
100	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
101	/** Redirection table entry - Destination. */
102	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
103
104	/** Redirection table entry - Gets the destination. */
105	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
106	/** Redirection table entry - Gets the mask flag. */
107	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
108	/** Redirection table entry - Checks whether it's masked. */
109	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
110	/** Redirection table entry - Gets the trigger mode. */
111	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
112	/** Redirection table entry - Gets the remote IRR flag. */
113	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
114	/** Redirection table entry - Gets the interrupt pin polarity. */
115	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
116	/** Redirection table entry - Gets the delivery status. */
117	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
118	/** Redirection table entry - Gets the destination mode. */
119	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
120	/** Redirection table entry - Gets the delivery mode. */
121	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
122	/** Redirection table entry - Gets the vector. */
123	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
124
125	/** Redirection table entry - Valid write mask for 82093AA. */
126	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
127	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
128	\| IOAPIC_RTE_VECTOR)
129	/** Redirection table entry - Valid read mask for 82093AA. */
130	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
131	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
132	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
133
134	/** Redirection table entry - Valid write mask for ICH9. */
135	/** @note The remote IRR bit has been reverted to read-only as it turns out the
136	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
137	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
138	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
139	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
140	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
141	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
142	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
143	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
144	\| IOAPIC_RTE_VECTOR)
145
146	/** Redirection table entry - Trigger mode edge. */
147	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
148	/** Redirection table entry - Trigger mode level. */
149	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
150	/** Redirection table entry - Destination mode physical. */
151	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
152	/** Redirection table entry - Destination mode logical. */
153	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
154
155
156	/** Index of indirect registers in the I/O APIC register table. */
157	#define IOAPIC_INDIRECT_INDEX_ID 0x0
158	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
159	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
160	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
161	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
162	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
163
164	/** Offset of direct registers in the I/O APIC MMIO space. */
165	#define IOAPIC_DIRECT_OFF_INDEX 0x00
166	#define IOAPIC_DIRECT_OFF_DATA 0x10
167	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
168
169	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
170	#define IOAPIC_WITH_PDM_CRITSECT
171	#ifdef IOAPIC_WITH_PDM_CRITSECT
172	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
173	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
174	#else
175	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
176	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
177	#endif
178
179
180	/*********************************************************************************************************************************
181	* Structures and Typedefs *
182	*********************************************************************************************************************************/
183	/**
184	* The shared I/O APIC device state.
185	*/
186	typedef struct IOAPIC
187	{
188	/** The ID register. */
189	uint8_t volatile u8Id;
190	/** The index register. */
191	uint8_t volatile u8Index;
192	/** Number of CPUs. */
193	uint8_t cCpus;
194	/** I/O APIC version. */
195	uint8_t u8ApicVer;
196	/** I/O APIC ID mask. */
197	uint8_t u8IdMask;
198	/** Maximum Redirection Table Entry (RTE) Entry. */
199	uint8_t u8MaxRte;
200	/** Last valid RTE indirect register index. */
201	uint8_t u8LastRteRegIdx;
202	/* Alignment padding. */
203	uint8_t u8Padding0[1];
204	/** Redirection table entry - Valid write mask. */
205	uint64_t u64RteWriteMask;
206	/** Redirection table entry - Valid read mask. */
207	uint64_t u64RteReadMask;
208
209	/** The redirection table registers. */
210	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
211	/** The IRQ tags and source IDs for each pin (tracing purposes). */
212	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
213
214	/** The internal IRR reflecting state of the interrupt lines. */
215	uint32_t uIrr;
216	/** Alignment padding. */
217	uint32_t u32Padding2;
218
219	#ifndef IOAPIC_WITH_PDM_CRITSECT
220	/** The critsect for updating to the RTEs. */
221	PDMCRITSECT CritSect;
222	#endif
223
224	/** The MMIO region. */
225	IOMMMIOHANDLE hMmio;
226
227	#ifdef VBOX_WITH_STATISTICS
228	/** Number of MMIO reads in RZ. */
229	STAMCOUNTER StatMmioReadRZ;
230	/** Number of MMIO reads in R3. */
231	STAMCOUNTER StatMmioReadR3;
232
233	/** Number of MMIO writes in RZ. */
234	STAMCOUNTER StatMmioWriteRZ;
235	/** Number of MMIO writes in R3. */
236	STAMCOUNTER StatMmioWriteR3;
237
238	/** Number of SetIrq calls in RZ. */
239	STAMCOUNTER StatSetIrqRZ;
240	/** Number of SetIrq calls in R3. */
241	STAMCOUNTER StatSetIrqR3;
242
243	/** Number of SetEoi calls in RZ. */
244	STAMCOUNTER StatSetEoiRZ;
245	/** Number of SetEoi calls in R3. */
246	STAMCOUNTER StatSetEoiR3;
247
248	/** Number of redundant edge-triggered interrupts. */
249	STAMCOUNTER StatRedundantEdgeIntr;
250	/** Number of redundant level-triggered interrupts. */
251	STAMCOUNTER StatRedundantLevelIntr;
252	/** Number of suppressed level-triggered interrupts (by remote IRR). */
253	STAMCOUNTER StatSuppressedLevelIntr;
254	/** Number of IOMMU remapped interrupts (signaled by RTE). */
255	STAMCOUNTER StatIommuRemappedIntr;
256	/** Number of IOMMU discarded interrupts (signaled by RTE). */
257	STAMCOUNTER StatIommuDiscardedIntr;
258	/** Number of IOMMU remapped MSIs. */
259	STAMCOUNTER StatIommuRemappedMsi;
260	/** Number of IOMMU denied or failed MSIs. */
261	STAMCOUNTER StatIommuDiscardedMsi;
262	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
263	STAMCOUNTER StatEoiContention;
264	/** Number of returns to ring-3 due to Set RTE lock contention. */
265	STAMCOUNTER StatSetRteContention;
266	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
267	STAMCOUNTER StatLevelIrqSent;
268	/** Number of EOIs received for level-triggered interrupts from the local
269	* APIC(s). */
270	STAMCOUNTER StatEoiReceived;
271	#endif
272	/** Per-vector stats. */
273	STAMCOUNTER aStatVectors[256];
274	} IOAPIC;
275	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
276	/** Pointer to shared IOAPIC data. */
277	typedef IOAPIC *PIOAPIC;
278	/** Pointer to const shared IOAPIC data. */
279	typedef IOAPIC const *PCIOAPIC;
280
281
282	/**
283	* The I/O APIC device state for ring-3.
284	*/
285	typedef struct IOAPICR3
286	{
287	/** The IOAPIC helpers. */
288	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
289	} IOAPICR3;
290	/** Pointer to the I/O APIC device state for ring-3. */
291	typedef IOAPICR3 *PIOAPICR3;
292
293
294	/**
295	* The I/O APIC device state for ring-0.
296	*/
297	typedef struct IOAPICR0
298	{
299	/** The IOAPIC helpers. */
300	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
301	} IOAPICR0;
302	/** Pointer to the I/O APIC device state for ring-0. */
303	typedef IOAPICR0 *PIOAPICR0;
304
305
306	/**
307	* The I/O APIC device state for raw-mode.
308	*/
309	typedef struct IOAPICRC
310	{
311	/** The IOAPIC helpers. */
312	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
313	} IOAPICRC;
314	/** Pointer to the I/O APIC device state for raw-mode. */
315	typedef IOAPICRC *PIOAPICRC;
316
317
318	/** The I/O APIC device state for the current context. */
319	typedef CTX_SUFF(IOAPIC) IOAPICCC;
320	/** Pointer to the I/O APIC device state for the current context. */
321	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
322
323
324	/**
325	* xAPIC interrupt.
326	*/
327	typedef struct XAPICINTR
328	{
329	/** The interrupt vector. */
330	uint8_t u8Vector;
331	/** The destination (mask or ID). */
332	uint8_t u8Dest;
333	/** The destination mode. */
334	uint8_t u8DestMode;
335	/** Delivery mode. */
336	uint8_t u8DeliveryMode;
337	/** Trigger mode. */
338	uint8_t u8TriggerMode;
339	/** Redirection hint. */
340	uint8_t u8RedirHint;
341	/** Polarity. */
342	uint8_t u8Polarity;
343	/** Padding. */
344	uint8_t abPadding0;
345	} XAPICINTR;
346	/** Pointer to an I/O xAPIC interrupt struct. */
347	typedef XAPICINTR *PXAPICINTR;
348	/** Pointer to a const xAPIC interrupt struct. */
349	typedef XAPICINTR const *PCXAPICINTR;
350
351
352	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
353
354	/**
355	* Gets the arbitration register.
356	*
357	* @returns The arbitration.
358	*/
359	DECLINLINE(uint32_t) ioapicGetArb(void)
360	{
361	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
362	return 0;
363	}
364
365
366	/**
367	* Gets the version register.
368	*
369	* @returns The version.
370	*/
371	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
372	{
373	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
374	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
375	return uValue;
376	}
377
378
379	/**
380	* Sets the ID register.
381	*
382	* @param pThis The shared I/O APIC device state.
383	* @param uValue The value to set.
384	*/
385	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
386	{
387	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
388	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
389	}
390
391
392	/**
393	* Gets the ID register.
394	*
395	* @returns The ID.
396	* @param pThis The shared I/O APIC device state.
397	*/
398	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
399	{
400	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
401	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
402	return uValue;
403	}
404
405
406	/**
407	* Sets the index register.
408	*
409	* @param pThis The shared I/O APIC device state.
410	* @param uValue The value to set.
411	*/
412	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
413	{
414	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
415	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
416	}
417
418
419	/**
420	* Gets the index register.
421	*
422	* @returns The index value.
423	*/
424	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
425	{
426	uint32_t const uValue = pThis->u8Index;
427	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
428	return uValue;
429	}
430
431
432	/**
433	* Converts an MSI message to an APIC interrupt.
434	*
435	* @param pMsi The MSI message to convert.
436	* @param pIntr Where to store the APIC interrupt.
437	*/
438	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
439	{
440	/*
441	* Parse the message from the physical address and data
442	* See Intel spec. 10.11.1 "Message Address Register Format".
443	* See Intel spec. 10.11.2 "Message Data Register Format".
444	*/
445	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
446	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
447	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
448
449	pIntr->u8Vector = pMsi->Data.n.u8Vector;
450	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
451	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
452	}
453
454
455	#ifdef VBOX_WITH_IOMMU_AMD
456	/**
457	* Convert an APIC interrupt to an MSI message.
458	*
459	* @param pIntr The APIC interrupt to convert.
460	* @param pMsi Where to store the MSI message.
461	*/
462	DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
463	{
464	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
465	pMsi->Addr.n.u8DestId = pIntr->u8Dest;
466	pMsi->Addr.n.u1RedirHint = pIntr->u8RedirHint;
467	pMsi->Addr.n.u1DestMode = pIntr->u8DestMode;
468
469	pMsi->Data.n.u8Vector = pIntr->u8Vector;
470	pMsi->Data.n.u3DeliveryMode = pIntr->u8DeliveryMode;
471	pMsi->Data.n.u1TriggerMode = pIntr->u8TriggerMode;
472
473	/* pMsi->Data.n.u1Level = ??? */
474	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
475	* possible in theory? Maybe document this more explicitly... */
476	}
477	#endif
478
479
480	/**
481	* Signals the next pending interrupt for the specified Redirection Table Entry
482	* (RTE).
483	*
484	* @param pDevIns The device instance.
485	* @param pThis The shared I/O APIC device state.
486	* @param pThisCC The I/O APIC device state for the current context.
487	* @param idxRte The index of the RTE (validated).
488	*
489	* @remarks It is the responsibility of the caller to verify that an interrupt is
490	* pending for the pin corresponding to the RTE before calling this
491	* function.
492	*/
493	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte)
494	{
495	#ifndef IOAPIC_WITH_PDM_CRITSECT
496	Assert(PDMCritSectIsOwner(&pThis->CritSect));
497	#endif
498
499	/*
500	* Ensure the interrupt isn't masked.
501	*/
502	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
503	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
504	{
505	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
506	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
507	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
508	{
509	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
510	if (u8RemoteIrr)
511	{
512	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
513	return;
514	}
515	}
516
517	XAPICINTR ApicIntr;
518	RT_ZERO(ApicIntr);
519	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
520	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
521	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
522	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
523	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
524	ApicIntr.u8TriggerMode = u8TriggerMode;
525	ApicIntr.u8RedirHint = 0;
526
527	#ifdef VBOX_WITH_IOMMU_AMD
528	/*
529	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
530	* For line-based interrupts we must use the southbridge I/O APIC's BDF as
531	* the origin of the interrupt, see @bugref{9654#c74}.
532	*/
533	MSIMSG MsiOut;
534	MSIMSG MsiIn;
535	RT_ZERO(MsiOut);
536	RT_ZERO(MsiIn);
537	ioapicGetMsiFromApicIntr(&ApicIntr, &MsiIn);
538	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, VBOX_PCI_BDF_SB_IOAPIC, &MsiIn, &MsiOut);
539	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
540	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
541	MsiOut = MsiIn;
542	else if (RT_SUCCESS(rcRemap))
543	STAM_COUNTER_INC(&pThis->StatIommuRemappedIntr);
544	else
545	{
546	STAM_COUNTER_INC(&pThis->StatIommuDiscardedIntr);
547	return;
548	}
549
550	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
551
552	# ifdef RT_STRICT
553	if (RT_SUCCESS(rcRemap))
554	{
555	Assert(ApicIntr.u8Polarity == IOAPIC_RTE_GET_POLARITY(u64Rte)); /* Ensure polarity hasn't changed. */
556	Assert(ApicIntr.u8TriggerMode == u8TriggerMode); /* Ensure trigger mode hasn't changed. */
557	}
558	# endif
559	#endif
560
561	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
562	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
563	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
564	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
565	ApicIntr.u8Vector, ApicIntr.u8Vector));
566
567	/*
568	* Deliver to the local APIC via the system/3-wire-APIC bus.
569	*/
570	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
571	ApicIntr.u8Dest,
572	ApicIntr.u8DestMode,
573	ApicIntr.u8DeliveryMode,
574	ApicIntr.u8Vector,
575	ApicIntr.u8Polarity,
576	ApicIntr.u8TriggerMode,
577	u32TagSrc);
578	/* Can't reschedule to R3. */
579	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
580	#ifdef DEBUG_ramshankar
581	if (rc == VERR_APIC_INTR_DISCARDED)
582	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
583	#endif
584
585	/*
586	* For level-triggered interrupts, we set the remote IRR bit to indicate
587	* the local APIC has accepted the interrupt.
588	*
589	* For edge-triggered interrupts, we should not clear the IRR bit as it
590	* should remain intact to reflect the state of the interrupt line.
591	* The device will explicitly transition to inactive state via the
592	* ioapicSetIrq() callback.
593	*/
594	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
595	&& rc == VINF_SUCCESS)
596	{
597	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
598	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
599	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
600	}
601	}
602	}
603
604
605	/**
606	* Gets the redirection table entry.
607	*
608	* @returns The redirection table entry.
609	* @param pThis The shared I/O APIC device state.
610	* @param uIndex The index value.
611	*/
612	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
613	{
614	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
615	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
616	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
617	UINT32_MAX);
618	uint32_t uValue;
619	if (!(uIndex & 1))
620	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
621	else
622	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
623
624	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
625	return uValue;
626	}
627
628
629	/**
630	* Sets the redirection table entry.
631	*
632	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
633	* @param pDevIns The device instance.
634	* @param pThis The shared I/O APIC device state.
635	* @param pThisCC The I/O APIC device state for the current context.
636	* @param uIndex The index value.
637	* @param uValue The value to set.
638	*/
639	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
640	uint32_t uIndex, uint32_t uValue)
641	{
642	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
643	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
644	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
645	VINF_SUCCESS);
646
647	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
648	if (rc == VINF_SUCCESS)
649	{
650	/*
651	* Write the low or high 32-bit value into the specified 64-bit RTE register,
652	* update only the valid, writable bits.
653	*
654	* We need to preserve the read-only bits as it can have dire consequences
655	* otherwise, see @bugref{8386#c24}.
656	*/
657	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
658	if (!(uIndex & 1))
659	{
660	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
661	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
662	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
663	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
664	}
665	else
666	{
667	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
668	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
669	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
670	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
671	}
672
673	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
674
675	/*
676	* Signal the next pending interrupt for this RTE.
677	*/
678	uint32_t const uPinMask = UINT32_C(1) << idxRte;
679	if (pThis->uIrr & uPinMask)
680	{
681	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: Signalling pending interrupt. idxRte=%u\n", idxRte));
682	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
683	}
684
685	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
686	}
687	else
688	STAM_COUNTER_INC(&pThis->StatSetRteContention);
689
690	return rc;
691	}
692
693
694	/**
695	* Gets the data register.
696	*
697	* @returns The data value.
698	* @param pThis The shared I/O APIC device state.
699	*/
700	static uint32_t ioapicGetData(PCIOAPIC pThis)
701	{
702	uint8_t const uIndex = pThis->u8Index;
703	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
704	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
705	&& uIndex <= pThis->u8LastRteRegIdx)
706	return ioapicGetRedirTableEntry(pThis, uIndex);
707
708	uint32_t uValue;
709	switch (uIndex)
710	{
711	case IOAPIC_INDIRECT_INDEX_ID:
712	uValue = ioapicGetId(pThis);
713	break;
714
715	case IOAPIC_INDIRECT_INDEX_VERSION:
716	uValue = ioapicGetVersion(pThis);
717	break;
718
719	case IOAPIC_INDIRECT_INDEX_ARB:
720	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
721	{
722	uValue = ioapicGetArb();
723	break;
724	}
725	RT_FALL_THRU();
726
727	default:
728	uValue = UINT32_C(0xffffffff);
729	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
730	break;
731	}
732	return uValue;
733	}
734
735
736	/**
737	* Sets the data register.
738	*
739	* @returns Strict VBox status code.
740	* @param pDevIns The device instance.
741	* @param pThis The shared I/O APIC device state.
742	* @param pThisCC The I/O APIC device state for the current context.
743	* @param uValue The value to set.
744	*/
745	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
746	{
747	uint8_t const uIndex = pThis->u8Index;
748	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
749	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
750
751	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
752	&& uIndex <= pThis->u8LastRteRegIdx)
753	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
754
755	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
756	ioapicSetId(pThis, uValue);
757	else
758	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
759
760	return VINF_SUCCESS;
761	}
762
763
764	/**
765	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
766	*/
767	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
768	{
769	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
770	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
771	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
772	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
773
774	bool fRemoteIrrCleared = false;
775	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
776	if (rc == VINF_SUCCESS)
777	{
778	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
779	{
780	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
781	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
782	{
783	#ifdef DEBUG_ramshankar
784	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
785	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
786	#endif
787	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
788	fRemoteIrrCleared = true;
789	STAM_COUNTER_INC(&pThis->StatEoiReceived);
790	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
791
792	/*
793	* Signal the next pending interrupt for this RTE.
794	*/
795	uint32_t const uPinMask = UINT32_C(1) << idxRte;
796	if (pThis->uIrr & uPinMask)
797	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
798	}
799	}
800
801	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
802	#ifndef VBOX_WITH_IOMMU_AMD
803	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
804	#endif
805	}
806	else
807	STAM_COUNTER_INC(&pThis->StatEoiContention);
808
809	return rc;
810	}
811
812
813	/**
814	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
815	*/
816	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
817	{
818	RT_NOREF(uBusDevFn); /** @todo r=ramshankar: Remove this argument if it's also unnecessary with Intel IOMMU. */
819	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
820	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
821	pThis->uIrr \|= a_PinMask; \
822	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_idxRte)); \
823	} while (0)
824
825	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
826	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
827	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
828
829	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
830
831	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
832	{
833	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
834	AssertRC(rc);
835
836	uint8_t const idxRte = iIrq;
837	uint32_t const uPinMask = UINT32_C(1) << idxRte;
838	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
839	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
840
841	bool fActive = RT_BOOL(iLevel & 1);
842	/** @todo Polarity is busted elsewhere, we need to fix that
843	* first. See @bugref{8386#c7}. */
844	#if 0
845	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
846	fActive ^= u8Polarity; */
847	#endif
848	if (!fActive)
849	{
850	pThis->uIrr &= ~uPinMask;
851	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
852	return;
853	}
854
855	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
856	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
857	if (!fFlipFlop)
858	{
859	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
860	{
861	/*
862	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
863	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
864	*/
865	if (!uPrevIrr)
866	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
867	else
868	{
869	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
870	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
871	}
872	}
873	else
874	{
875	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
876
877	/*
878	* For level-triggered interrupts, redundant interrupts are not a problem
879	* and will eventually be delivered anyway after an EOI, but our PDM devices
880	* should not typically call us with no change to the level.
881	*/
882	if (!uPrevIrr)
883	{ /* likely */ }
884	else
885	{
886	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
887	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
888	}
889
890	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
891	}
892	}
893	else
894	{
895	/*
896	* The device is flip-flopping the interrupt line, which implies we should de-assert
897	* and assert the interrupt line. The interrupt line is left in the asserted state
898	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
899	* hence just the assert is done.
900	*/
901	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
902	}
903
904	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
905	}
906	#undef IOAPIC_ASSERT_IRQ
907	}
908
909
910	/**
911	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
912	*/
913	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
914	{
915	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
916	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
917	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
918
919	XAPICINTR ApicIntr;
920	RT_ZERO(ApicIntr);
921
922	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
923	/*
924	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
925	*
926	* If the Bus:Dev:Fn isn't valid, it is ASSUMED the device generating the
927	* MSI may be the IOMMU itself and hence is not subject to remapping.
928	*
929	* For AMD IOMMUs, since it's a full fledged PCI device, the BDF will be
930	* valid but will be handled by VERR_IOMMU_CANNOT_CALL_SELF case.
931	*/
932	if (PCIBDF_IS_VALID(uBusDevFn))
933	{
934	MSIMSG MsiOut;
935	RT_ZERO(MsiOut);
936	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
937	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
938	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
939	MsiOut = *pMsi;
940	else if (RT_SUCCESS(rcRemap))
941	STAM_COUNTER_INC(&pThis->StatIommuRemappedMsi);
942	else
943	{
944	STAM_COUNTER_INC(&pThis->StatIommuDiscardedMsi);
945	return;
946	}
947	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
948	}
949	else
950	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
951	#else
952	NOREF(uBusDevFn);
953	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
954	#endif
955
956	/*
957	* Deliver to the local APIC via the system/3-wire-APIC bus.
958	*/
959	STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
960
961	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
962	ApicIntr.u8Dest,
963	ApicIntr.u8DestMode,
964	ApicIntr.u8DeliveryMode,
965	ApicIntr.u8Vector,
966	0 /* u8Polarity - N/A */,
967	ApicIntr.u8TriggerMode,
968	uTagSrc);
969	/* Can't reschedule to R3. */
970	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
971	}
972
973
974	/**
975	* @callback_method_impl{FNIOMMMIONEWREAD}
976	*/
977	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
978	{
979	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
980	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
981	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
982	RT_NOREF_PV(pvUser);
983
984	VBOXSTRICTRC rc = VINF_SUCCESS;
985	uint32_t puValue = (uint32_t )pv;
986	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
987	switch (offReg)
988	{
989	case IOAPIC_DIRECT_OFF_INDEX:
990	*puValue = ioapicGetIndex(pThis);
991	break;
992
993	case IOAPIC_DIRECT_OFF_DATA:
994	*puValue = ioapicGetData(pThis);
995	break;
996
997	default:
998	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
999	rc = VINF_IOM_MMIO_UNUSED_FF;
1000	break;
1001	}
1002
1003	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
1004	return rc;
1005	}
1006
1007
1008	/**
1009	* @callback_method_impl{FNIOMMMIONEWWRITE}
1010	*/
1011	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1012	{
1013	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1014	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1015	RT_NOREF_PV(pvUser);
1016
1017	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1018
1019	Assert(!(off & 3));
1020	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1021
1022	VBOXSTRICTRC rc = VINF_SUCCESS;
1023	uint32_t const uValue = (uint32_t const )pv;
1024	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
1025
1026	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
1027	switch (offReg)
1028	{
1029	case IOAPIC_DIRECT_OFF_INDEX:
1030	ioapicSetIndex(pThis, uValue);
1031	break;
1032
1033	case IOAPIC_DIRECT_OFF_DATA:
1034	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
1035	break;
1036
1037	case IOAPIC_DIRECT_OFF_EOI:
1038	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
1039	rc = ioapicSetEoi(pDevIns, uValue);
1040	else
1041	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1042	break;
1043
1044	default:
1045	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1046	break;
1047	}
1048
1049	return rc;
1050	}
1051
1052
1053	#ifdef IN_RING3
1054
1055	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1056	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1057	{
1058	RT_NOREF(pDesc);
1059	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1060	return VINF_SUCCESS;
1061	}
1062
1063
1064	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1065	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1066	{
1067	RT_NOREF(pDesc, pfMask);
1068	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1069	return VINF_SUCCESS;
1070	}
1071
1072
1073	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1074	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1075	{
1076	RT_NOREF(pDesc);
1077	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1078	return VINF_SUCCESS;
1079	}
1080
1081
1082	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1083	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1084	{
1085	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1086	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1087	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1088	RT_NOREF(pDesc, pfMask);
1089	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1090	}
1091
1092
1093	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1094	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1095	{
1096	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1097	RT_NOREF(pDesc);
1098	pValue->u32 = ioapicGetVersion(pThis);
1099	return VINF_SUCCESS;
1100	}
1101
1102
1103	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1104	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1105	{
1106	RT_NOREF(pvUser, pDesc);
1107	pValue->u32 = ioapicGetArb();
1108	return VINF_SUCCESS;
1109	}
1110
1111
1112	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1113	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1114	{
1115	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1116	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1117	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1118	return VINF_SUCCESS;
1119	}
1120
1121
1122	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1123	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1124	{
1125	RT_NOREF(pfMask);
1126	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1127	/* No locks, no checks, just do it. */
1128	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1129	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1130	return VINF_SUCCESS;
1131	}
1132
1133
1134	/** IOREDTBLn sub fields. */
1135	static DBGFREGSUBFIELD const g_aRteSubs[] =
1136	{
1137	{ "vector", 0, 8, 0, 0, NULL, NULL },
1138	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1139	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1140	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1141	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1142	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1143	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1144	{ "mask", 16, 1, 0, 0, NULL, NULL },
1145	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1146	{ "dest", 56, 8, 0, 0, NULL, NULL },
1147	DBGFREGSUBFIELD_TERMINATOR()
1148	};
1149
1150
1151	/** Register descriptors for DBGF. */
1152	static DBGFREGDESC const g_aRegDesc[] =
1153	{
1154	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1155	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1156	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1157	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1158	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1159	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1160	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1161	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1162	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1163	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1164	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1165	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1166	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1167	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1168	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1169	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1170	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1171	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1172	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1173	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1174	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1175	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1176	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1177	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1178	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1179	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1180	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1181	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1182	DBGFREGDESC_TERMINATOR()
1183	};
1184
1185
1186	/**
1187	* @callback_method_impl{FNDBGFHANDLERDEV}
1188	*/
1189	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1190	{
1191	RT_NOREF(pszArgs);
1192	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1193	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1194
1195	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1196
1197	uint32_t const uId = ioapicGetId(pThis);
1198	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1199	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1200
1201	uint32_t const uVer = ioapicGetVersion(pThis);
1202	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1203	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1204	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1205	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1206
1207	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1208	{
1209	uint32_t const uArb = ioapicGetArb();
1210	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1211	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1212	}
1213
1214	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1215
1216	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1217	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1218
1219	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1220	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1221	{
1222	static const char * const s_apszDeliveryModes[] =
1223	{
1224	"Fixed ",
1225	"LowPri",
1226	"SMI ",
1227	"Rsvd ",
1228	"NMI ",
1229	"INIT ",
1230	"Rsvd ",
1231	"ExtINT"
1232	};
1233
1234	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1235	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1236	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1237	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1238	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1239	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1240	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1241	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1242	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1243	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1244	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1245	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1246
1247	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1248	idxRte,
1249	pszDestMode,
1250	uDest,
1251	uMask,
1252	(pThis->uIrr >> idxRte) & 1,
1253	pszTriggerMode,
1254	uRemoteIrr,
1255	pszPolarity,
1256	pszDeliveryStatus,
1257	pszDeliveryMode,
1258	uVector,
1259	u64Rte);
1260	}
1261	}
1262
1263
1264	/**
1265	* @copydoc FNSSMDEVSAVEEXEC
1266	*/
1267	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1268	{
1269	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1270	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1271	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1272
1273	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1274	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1275	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1276	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1277	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1278
1279	return VINF_SUCCESS;
1280	}
1281
1282
1283	/**
1284	* @copydoc FNSSMDEVLOADEXEC
1285	*/
1286	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1287	{
1288	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1289	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1290	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1291
1292	Assert(uPass == SSM_PASS_FINAL);
1293	NOREF(uPass);
1294
1295	/* Weed out invalid versions. */
1296	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1297	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1298	{
1299	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1300	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1301	}
1302
1303	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1304	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1305
1306	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1307	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1308	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1309	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1310
1311	return VINF_SUCCESS;
1312	}
1313
1314
1315	/**
1316	* @interface_method_impl{PDMDEVREG,pfnReset}
1317	*/
1318	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1319	{
1320	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1321	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1322	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1323
1324	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1325	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1326
1327	pThis->uIrr = 0;
1328	pThis->u8Index = 0;
1329	pThis->u8Id = 0;
1330
1331	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1332	{
1333	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1334	pThis->au32TagSrc[idxRte] = 0;
1335	}
1336
1337	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1338	}
1339
1340
1341	/**
1342	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1343	*/
1344	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1345	{
1346	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1347	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1348
1349	pThisRC->pIoApicHlp += offDelta;
1350	}
1351
1352
1353	/**
1354	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1355	*/
1356	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1357	{
1358	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1359	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1360	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1361
1362	# ifndef IOAPIC_WITH_PDM_CRITSECT
1363	/*
1364	* Destroy the RTE critical section.
1365	*/
1366	if (PDMCritSectIsInitialized(&pThis->CritSect))
1367	PDMR3CritSectDelete(&pThis->CritSect);
1368	# else
1369	RT_NOREF_PV(pThis);
1370	# endif
1371
1372	return VINF_SUCCESS;
1373	}
1374
1375
1376	/**
1377	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1378	*/
1379	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1380	{
1381	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1382	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1383	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1384	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1385	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1386	Assert(iInstance == 0); RT_NOREF(iInstance);
1387
1388	/*
1389	* Validate and read the configuration.
1390	*/
1391	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType", "");
1392
1393	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0
1394	upsets some guest which we haven't yet been tested. */
1395	uint32_t cCpus;
1396	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1397	if (RT_FAILURE(rc))
1398	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1399	pThis->cCpus = (uint8_t)cCpus;
1400
1401	char szChipType[16];
1402	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1403	if (RT_FAILURE(rc))
1404	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1405
1406	if (!strcmp(szChipType, "ICH9"))
1407	{
1408	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1409	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1410	pThis->u8IdMask = 0xff;
1411	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1412	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1413	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1414	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1415	}
1416	else if (!strcmp(szChipType, "82093AA"))
1417	{
1418	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1419	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1420	pThis->u8IdMask = 0x0f;
1421	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1422	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1423	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1424	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1425	}
1426	else if (!strcmp(szChipType, "82379AB"))
1427	{
1428	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1429	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1430	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1431	pThis->u8IdMask = 0x0f;
1432	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1433	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1434	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1435	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1436	}
1437	else
1438	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1439	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1440	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1441
1442	/*
1443	* We will use our own critical section for the IOAPIC device.
1444	*/
1445	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1446	AssertRCReturn(rc, rc);
1447
1448	# ifndef IOAPIC_WITH_PDM_CRITSECT
1449	/*
1450	* Setup the critical section to protect concurrent writes to the RTEs.
1451	*/
1452	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1453	AssertRCReturn(rc, rc);
1454	# endif
1455
1456	/*
1457	* Register the IOAPIC.
1458	*/
1459	PDMIOAPICREG IoApicReg;
1460	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1461	IoApicReg.pfnSetIrq = ioapicSetIrq;
1462	IoApicReg.pfnSendMsi = ioapicSendMsi;
1463	IoApicReg.pfnSetEoi = ioapicSetEoi;
1464	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1465	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1466	AssertRCReturn(rc, rc);
1467
1468	/*
1469	* Register MMIO region.
1470	*/
1471	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1472	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1473	AssertRCReturn(rc, rc);
1474
1475	/*
1476	* Register the saved state.
1477	*/
1478	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1479	AssertRCReturn(rc, rc);
1480
1481	/*
1482	* Register debugger info item.
1483	*/
1484	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1485	AssertRCReturn(rc, rc);
1486
1487	/*
1488	* Register debugger register access.
1489	*/
1490	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1491	AssertRCReturn(rc, rc);
1492
1493	# ifdef VBOX_WITH_STATISTICS
1494	/*
1495	* Statistics.
1496	*/
1497	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1498	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1499	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1500	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1501
1502	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1503	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1504	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1505	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1506
1507	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1508	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1509	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1510
1511	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedIntr, STAMTYPE_COUNTER, "Iommu/RemappedIntr", STAMUNIT_OCCURENCES, "Number of interrupts remapped by the IOMMU.");
1512	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedMsi, STAMTYPE_COUNTER, "Iommu/RemappedMsi", STAMUNIT_OCCURENCES, "Number of MSIs remapped by the IOMMU.");
1513	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedIntr, STAMTYPE_COUNTER, "Iommu/DiscardedIntr", STAMUNIT_OCCURENCES, "Number of interrupts discarded by the IOMMU.");
1514	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi, STAMTYPE_COUNTER, "Iommu/DiscardedMsi", STAMUNIT_OCCURENCES, "Number of MSIs discarded by the IOMMU.");
1515
1516	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1517	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1518
1519	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1520	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1521	# endif
1522	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
1523	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1524	"Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
1525
1526	/*
1527	* Init. the device state.
1528	*/
1529	LogRel(("IOAPIC: Using implementation 2.0! I/O APIC version is %d.%d\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0F));
1530	ioapicR3Reset(pDevIns);
1531
1532	return VINF_SUCCESS;
1533	}
1534
1535	#else /* !IN_RING3 */
1536
1537	/**
1538	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1539	*/
1540	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1541	{
1542	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1543	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1544	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1545
1546	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1547	AssertRCReturn(rc, rc);
1548
1549	PDMIOAPICREG IoApicReg;
1550	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1551	IoApicReg.pfnSetIrq = ioapicSetIrq;
1552	IoApicReg.pfnSendMsi = ioapicSendMsi;
1553	IoApicReg.pfnSetEoi = ioapicSetEoi;
1554	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1555	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1556	AssertRCReturn(rc, rc);
1557
1558	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1559	AssertRCReturn(rc, rc);
1560
1561	return VINF_SUCCESS;
1562	}
1563
1564	#endif /* !IN_RING3 */
1565
1566	/**
1567	* IO APIC device registration structure.
1568	*/
1569	const PDMDEVREG g_DeviceIOAPIC =
1570	{
1571	/* .u32Version = */ PDM_DEVREG_VERSION,
1572	/* .uReserved0 = */ 0,
1573	/* .szName = */ "ioapic",
1574	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1575	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1576	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1577	/* .cMaxInstances = */ 1,
1578	/* .uSharedVersion = */ 42,
1579	/* .cbInstanceShared = */ sizeof(IOAPIC),
1580	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1581	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1582	/* .cMaxPciDevices = */ 0,
1583	/* .cMaxMsixVectors = */ 0,
1584	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1585	#if defined(IN_RING3)
1586	/* .pszRCMod = */ "VBoxDDRC.rc",
1587	/* .pszR0Mod = */ "VBoxDDR0.r0",
1588	/* .pfnConstruct = */ ioapicR3Construct,
1589	/* .pfnDestruct = */ ioapicR3Destruct,
1590	/* .pfnRelocate = */ ioapicR3Relocate,
1591	/* .pfnMemSetup = */ NULL,
1592	/* .pfnPowerOn = */ NULL,
1593	/* .pfnReset = */ ioapicR3Reset,
1594	/* .pfnSuspend = */ NULL,
1595	/* .pfnResume = */ NULL,
1596	/* .pfnAttach = */ NULL,
1597	/* .pfnDetach = */ NULL,
1598	/* .pfnQueryInterface = */ NULL,
1599	/* .pfnInitComplete = */ NULL,
1600	/* .pfnPowerOff = */ NULL,
1601	/* .pfnSoftReset = */ NULL,
1602	/* .pfnReserved0 = */ NULL,
1603	/* .pfnReserved1 = */ NULL,
1604	/* .pfnReserved2 = */ NULL,
1605	/* .pfnReserved3 = */ NULL,
1606	/* .pfnReserved4 = */ NULL,
1607	/* .pfnReserved5 = */ NULL,
1608	/* .pfnReserved6 = */ NULL,
1609	/* .pfnReserved7 = */ NULL,
1610	#elif defined(IN_RING0)
1611	/* .pfnEarlyConstruct = */ NULL,
1612	/* .pfnConstruct = */ ioapicRZConstruct,
1613	/* .pfnDestruct = */ NULL,
1614	/* .pfnFinalDestruct = */ NULL,
1615	/* .pfnRequest = */ NULL,
1616	/* .pfnReserved0 = */ NULL,
1617	/* .pfnReserved1 = */ NULL,
1618	/* .pfnReserved2 = */ NULL,
1619	/* .pfnReserved3 = */ NULL,
1620	/* .pfnReserved4 = */ NULL,
1621	/* .pfnReserved5 = */ NULL,
1622	/* .pfnReserved6 = */ NULL,
1623	/* .pfnReserved7 = */ NULL,
1624	#elif defined(IN_RC)
1625	/* .pfnConstruct = */ ioapicRZConstruct,
1626	/* .pfnReserved0 = */ NULL,
1627	/* .pfnReserved1 = */ NULL,
1628	/* .pfnReserved2 = */ NULL,
1629	/* .pfnReserved3 = */ NULL,
1630	/* .pfnReserved4 = */ NULL,
1631	/* .pfnReserved5 = */ NULL,
1632	/* .pfnReserved6 = */ NULL,
1633	/* .pfnReserved7 = */ NULL,
1634	#else
1635	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1636	#endif
1637	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1638	};
1639
1640
1641	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1642

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 88638

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