DevIoApic.cpp@ 90309

Last change on this file since 90309 was 90309, checked in by vboxsync, 3 years ago
DevIoApic: Tenative fix for re-triggering edge interrupts in EOI callback. bugref:10073 oem2ticketref:43
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1	/* $Id: DevIoApic.cpp 90309 2021-07-23 14:04:22Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/pci.h>
27	#include <VBox/vmm/pdmdev.h>
28
29	#include "VBoxDD.h"
30	#include <iprt/x86.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** The current IO APIC saved state version. */
38	#define IOAPIC_SAVED_STATE_VERSION 2
39	/** The saved state version used by VirtualBox 5.0 and
40	* earlier. */
41	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
42
43	/** Implementation specified by the "Intel I/O Controller Hub 9
44	* (ICH9) Family" */
45	#define IOAPIC_VERSION_ICH9 0x20
46	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
47	Controller" */
48	#define IOAPIC_VERSION_82093AA 0x11
49
50	/** The default MMIO base physical address. */
51	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
52	/** The size of the MMIO range. */
53	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
54	/** The mask for getting direct registers from physical address. */
55	#define IOAPIC_MMIO_REG_MASK 0xff
56
57	/** The number of interrupt input pins. */
58	#define IOAPIC_NUM_INTR_PINS 24
59	/** Maximum redirection entires. */
60	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
61	/** Reduced RTEs used by SIO.A (82379AB). */
62	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
63
64	/** Version register - Gets the version. */
65	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
66	/** Version register - Gets the maximum redirection entry. */
67	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
68	/** Version register - Gets whether Pin Assertion Register (PRQ) is
69	* supported. */
70	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
71
72	/** Index register - Valid write mask. */
73	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
74
75	/** Arbitration register - Gets the ID. */
76	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
77
78	/** ID register - Gets the ID. */
79	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
80
81	/** Redirection table entry - Vector. */
82	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
83	/** Redirection table entry - Delivery mode. */
84	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
85	/** Redirection table entry - Destination mode. */
86	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
87	/** Redirection table entry - Delivery status. */
88	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
89	/** Redirection table entry - Interrupt input pin polarity. */
90	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
91	/** Redirection table entry - Remote IRR. */
92	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
93	/** Redirection table entry - Trigger Mode. */
94	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
95	/** Redirection table entry - Number of bits to shift to get the Mask. */
96	#define IOAPIC_RTE_MASK_BIT 16
97	/** Redirection table entry - The Mask. */
98	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
99	/** Redirection table entry - Extended Destination ID. */
100	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
101	/** Redirection table entry - Destination. */
102	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
103
104	/** Redirection table entry - Gets the destination. */
105	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
106	/** Redirection table entry - Gets the mask flag. */
107	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
108	/** Redirection table entry - Checks whether it's masked. */
109	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
110	/** Redirection table entry - Gets the trigger mode. */
111	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
112	/** Redirection table entry - Gets the remote IRR flag. */
113	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
114	/** Redirection table entry - Gets the interrupt pin polarity. */
115	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
116	/** Redirection table entry - Gets the delivery status. */
117	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
118	/** Redirection table entry - Gets the destination mode. */
119	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
120	/** Redirection table entry - Gets the delivery mode. */
121	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
122	/** Redirection table entry - Gets the vector. */
123	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
124
125	/** @name DMAR variant interpretation of RTE fields.
126	* @{ */
127	/** Redirection table entry - Number of bits to shift to get Interrupt
128	* Index[14:0]. */
129	#define IOAPIC_RTE_INTR_INDEX_LO_BIT 49
130	/** Redirection table entry - Interrupt Index[14:0]. */
131	#define IOAPIC_RTE_INTR_INDEX_LO UINT64_C(0xfffe000000000000)
132	/** Redirection table entry - Number of bits to shift to get interrupt format. */
133	#define IOAPIC_RTE_INTR_FORMAT_BIT 48
134	/** Redirection table entry - Interrupt format. */
135	#define IOAPIC_RTE_INTR_FORMAT RT_BIT_64(IOAPIC_RTE_INTR_FORMAT_BIT)
136	/** Redirection table entry - Number of bits to shift to get Interrupt Index[15]. */
137	#define IOAPIC_RTE_INTR_INDEX_HI_BIT 11
138	/** Redirection table entry - Interrupt Index[15]. */
139	#define IOAPIC_RTE_INTR_INDEX_HI RT_BIT_64(11)
140
141	/** Redirection table entry - Gets the Interrupt Index[14:0]. */
142	#define IOAPIC_RTE_GET_INTR_INDEX_LO(a_Reg) ((a_Reg) >> IOAPIC_RTE_INTR_INDEX_LO_BIT)
143	/** Redirection table entry - Gets the Interrupt format. */
144	#define IOAPIC_RTE_GET_INTR_FORMAT(a_Reg) (((a_Reg) >> IOAPIC_RTE_INTR_FORMAT_BIT) & 0x1)
145	/** Redirection table entry - Gets the Interrupt Index[15]. */
146	#define IOAPIC_RTE_GET_INTR_INDEX_HI(a_Reg) (((a_Reg) >> IOAPIC_RTE_INTR_INDEX_HI_BIT) & 0x1)
147	/** @} */
148
149	/** Redirection table entry - Valid write mask for 82093AA. */
150	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
151	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
152	\| IOAPIC_RTE_VECTOR)
153	/** Redirection table entry - Valid read mask for 82093AA. */
154	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
155	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
156	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
157
158	/** Redirection table entry - Valid write mask for ICH9. */
159	/** @note The remote IRR bit has been reverted to read-only as it turns out the
160	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
161	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
162	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
163	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
164	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
165	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
166	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
167	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
168	\| IOAPIC_RTE_VECTOR)
169
170	/** Redirection table entry - Valid write mask for DMAR variant. */
171	#define IOAPIC_RTE_VALID_WRITE_MASK_DMAR ( IOAPIC_RTE_INTR_INDEX_LO \| IOAPIC_RTE_INTR_FORMAT \| IOAPIC_RTE_MASK \
172	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_INTR_INDEX_HI \
173	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
174	/** Redirection table entry - Valid read mask for DMAR variant. */
175	#define IOAPIC_RTE_VALID_READ_MASK_DMAR ( IOAPIC_RTE_INTR_INDEX_LO \| IOAPIC_RTE_INTR_FORMAT \| IOAPIC_RTE_MASK \
176	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
177	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_INTR_INDEX_HI \| IOAPIC_RTE_DELIVERY_MODE \
178	\| IOAPIC_RTE_VECTOR)
179
180	/** Redirection table entry - Trigger mode edge. */
181	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
182	/** Redirection table entry - Trigger mode level. */
183	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
184	/** Redirection table entry - Destination mode physical. */
185	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
186	/** Redirection table entry - Destination mode logical. */
187	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
188
189
190	/** Index of indirect registers in the I/O APIC register table. */
191	#define IOAPIC_INDIRECT_INDEX_ID 0x0
192	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
193	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
194	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
195	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
196	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
197
198	/** Offset of direct registers in the I/O APIC MMIO space. */
199	#define IOAPIC_DIRECT_OFF_INDEX 0x00
200	#define IOAPIC_DIRECT_OFF_DATA 0x10
201	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
202
203	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
204	#define IOAPIC_WITH_PDM_CRITSECT
205	#ifdef IOAPIC_WITH_PDM_CRITSECT
206	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
207	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
208	# define IOAPIC_LOCK_IS_OWNER(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnLockIsOwner((a_pDevIns))
209	#else
210	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
211	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
212	# define IOAPIC_LOCK_IS_OWNER(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectIsOwner((a_pDevIns), &(a_pThis)->CritSect)
213	#endif
214
215
216	/*********************************************************************************************************************************
217	* Structures and Typedefs *
218	*********************************************************************************************************************************/
219	/**
220	* I/O APIC chipset (and variants) we support.
221	*/
222	typedef enum IOAPICTYPE
223	{
224	IOAPICTYPE_ICH9 = 1,
225	IOAPICTYPE_DMAR,
226	IOAPICTYPE_82093AA,
227	IOAPICTYPE_82379AB,
228	IOAPICTYPE_32BIT_HACK = 0x7fffffff
229	} IOAPICTYPE;
230	AssertCompileSize(IOAPICTYPE, 4);
231
232	/**
233	* The shared I/O APIC device state.
234	*/
235	typedef struct IOAPIC
236	{
237	/** The ID register. */
238	uint8_t volatile u8Id;
239	/** The index register. */
240	uint8_t volatile u8Index;
241	/** Number of CPUs. */
242	uint8_t cCpus;
243	/** I/O APIC version. */
244	uint8_t u8ApicVer;
245	/** I/O APIC ID mask. */
246	uint8_t u8IdMask;
247	/** Maximum Redirection Table Entry (RTE) Entry. */
248	uint8_t u8MaxRte;
249	/** Last valid RTE indirect register index. */
250	uint8_t u8LastRteRegIdx;
251	/* Alignment padding. */
252	uint8_t u8Padding0[1];
253	/** Redirection table entry - Valid write mask. */
254	uint64_t u64RteWriteMask;
255	/** Redirection table entry - Valid read mask. */
256	uint64_t u64RteReadMask;
257
258	/** The redirection table registers. */
259	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
260	/** The IRQ tags and source IDs for each pin (tracing purposes). */
261	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
262	/** Bitmap keeping the flip-flop-ness of pending interrupts. */
263	uint64_t bmFlipFlop[(IOAPIC_NUM_INTR_PINS + 63) / 64];
264
265	/** The internal IRR reflecting state of the interrupt lines. */
266	uint32_t uIrr;
267	/** The I/O APIC chipset type. */
268	IOAPICTYPE enmType;
269	/** The I/O APIC PCI address. */
270	PCIBDF uPciAddress;
271	/** Padding. */
272	uint32_t uPadding0;
273
274	#ifndef IOAPIC_WITH_PDM_CRITSECT
275	/** The critsect for updating to the RTEs. */
276	PDMCRITSECT CritSect;
277	#endif
278
279	/** The MMIO region. */
280	IOMMMIOHANDLE hMmio;
281
282	#ifdef VBOX_WITH_STATISTICS
283	/** Number of MMIO reads in RZ. */
284	STAMCOUNTER StatMmioReadRZ;
285	/** Number of MMIO reads in R3. */
286	STAMCOUNTER StatMmioReadR3;
287
288	/** Number of MMIO writes in RZ. */
289	STAMCOUNTER StatMmioWriteRZ;
290	/** Number of MMIO writes in R3. */
291	STAMCOUNTER StatMmioWriteR3;
292
293	/** Number of SetIrq calls in RZ. */
294	STAMCOUNTER StatSetIrqRZ;
295	/** Number of SetIrq calls in R3. */
296	STAMCOUNTER StatSetIrqR3;
297
298	/** Number of SetEoi calls in RZ. */
299	STAMCOUNTER StatSetEoiRZ;
300	/** Number of SetEoi calls in R3. */
301	STAMCOUNTER StatSetEoiR3;
302
303	/** Number of redundant edge-triggered interrupts. */
304	STAMCOUNTER StatRedundantEdgeIntr;
305	/** Number of redundant level-triggered interrupts. */
306	STAMCOUNTER StatRedundantLevelIntr;
307	/** Number of suppressed level-triggered interrupts (by remote IRR). */
308	STAMCOUNTER StatSuppressedLevelIntr;
309	/** Number of IOMMU remapped interrupts (signaled by RTE). */
310	STAMCOUNTER StatIommuRemappedIntr;
311	/** Number of IOMMU discarded interrupts (signaled by RTE). */
312	STAMCOUNTER StatIommuDiscardedIntr;
313	/** Number of IOMMU remapped MSIs. */
314	STAMCOUNTER StatIommuRemappedMsi;
315	/** Number of IOMMU denied or failed MSIs. */
316	STAMCOUNTER StatIommuDiscardedMsi;
317	/** Number of returns to ring-3 due to Set RTE lock contention. */
318	STAMCOUNTER StatSetRteContention;
319	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
320	STAMCOUNTER StatLevelIrqSent;
321	/** Number of EOIs received for level-triggered interrupts from the local
322	* APIC(s). */
323	STAMCOUNTER StatEoiReceived;
324	/** The time an interrupt level spent in the pending state. */
325	STAMPROFILEADV aStatLevelAct[IOAPIC_NUM_INTR_PINS];
326	#endif
327	/** Per-vector stats. */
328	STAMCOUNTER aStatVectors[256];
329	} IOAPIC;
330	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
331	/** Pointer to shared IOAPIC data. */
332	typedef IOAPIC *PIOAPIC;
333	/** Pointer to const shared IOAPIC data. */
334	typedef IOAPIC const *PCIOAPIC;
335
336
337	/**
338	* The I/O APIC device state for ring-3.
339	*/
340	typedef struct IOAPICR3
341	{
342	/** The IOAPIC helpers. */
343	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
344	} IOAPICR3;
345	/** Pointer to the I/O APIC device state for ring-3. */
346	typedef IOAPICR3 *PIOAPICR3;
347
348
349	/**
350	* The I/O APIC device state for ring-0.
351	*/
352	typedef struct IOAPICR0
353	{
354	/** The IOAPIC helpers. */
355	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
356	} IOAPICR0;
357	/** Pointer to the I/O APIC device state for ring-0. */
358	typedef IOAPICR0 *PIOAPICR0;
359
360
361	/**
362	* The I/O APIC device state for raw-mode.
363	*/
364	typedef struct IOAPICRC
365	{
366	/** The IOAPIC helpers. */
367	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
368	} IOAPICRC;
369	/** Pointer to the I/O APIC device state for raw-mode. */
370	typedef IOAPICRC *PIOAPICRC;
371
372
373	/** The I/O APIC device state for the current context. */
374	typedef CTX_SUFF(IOAPIC) IOAPICCC;
375	/** Pointer to the I/O APIC device state for the current context. */
376	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
377
378
379	/**
380	* xAPIC interrupt.
381	*/
382	typedef struct XAPICINTR
383	{
384	/** The interrupt vector. */
385	uint8_t u8Vector;
386	/** The destination (mask or ID). */
387	uint8_t u8Dest;
388	/** The destination mode. */
389	uint8_t u8DestMode;
390	/** Delivery mode. */
391	uint8_t u8DeliveryMode;
392	/** Trigger mode. */
393	uint8_t u8TriggerMode;
394	/** Redirection hint. */
395	uint8_t u8RedirHint;
396	/** Polarity. */
397	uint8_t u8Polarity;
398	/** Padding. */
399	uint8_t abPadding0;
400	} XAPICINTR;
401	/** Pointer to an I/O xAPIC interrupt struct. */
402	typedef XAPICINTR *PXAPICINTR;
403	/** Pointer to a const xAPIC interrupt struct. */
404	typedef XAPICINTR const *PCXAPICINTR;
405
406
407	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
408
409	/**
410	* Gets the arbitration register.
411	*
412	* @returns The arbitration.
413	*/
414	DECLINLINE(uint32_t) ioapicGetArb(void)
415	{
416	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
417	return 0;
418	}
419
420
421	/**
422	* Gets the version register.
423	*
424	* @returns The version.
425	*/
426	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
427	{
428	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
429	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
430	return uValue;
431	}
432
433
434	/**
435	* Sets the ID register.
436	*
437	* @param pThis The shared I/O APIC device state.
438	* @param uValue The value to set.
439	*/
440	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
441	{
442	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
443	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
444	}
445
446
447	/**
448	* Gets the ID register.
449	*
450	* @returns The ID.
451	* @param pThis The shared I/O APIC device state.
452	*/
453	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
454	{
455	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
456	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
457	return uValue;
458	}
459
460
461	/**
462	* Sets the index register.
463	*
464	* @param pThis The shared I/O APIC device state.
465	* @param uValue The value to set.
466	*/
467	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
468	{
469	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
470	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
471	}
472
473
474	/**
475	* Gets the index register.
476	*
477	* @returns The index value.
478	*/
479	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
480	{
481	uint32_t const uValue = pThis->u8Index;
482	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
483	return uValue;
484	}
485
486
487	/**
488	* Converts an MSI message to an APIC interrupt.
489	*
490	* @param pMsi The MSI message to convert.
491	* @param pIntr Where to store the APIC interrupt.
492	*/
493	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
494	{
495	/*
496	* Parse the message from the physical address and data.
497	* Do -not- zero out other fields in the APIC interrupt.
498	*
499	* See Intel spec. 10.11.1 "Message Address Register Format".
500	* See Intel spec. 10.11.2 "Message Data Register Format".
501	*/
502	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
503	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
504	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
505
506	pIntr->u8Vector = pMsi->Data.n.u8Vector;
507	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
508	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
509	}
510
511
512	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
513	/**
514	* Convert an RTE into an MSI message.
515	*
516	* @param u64Rte The RTE to convert.
517	* @param enmType The I/O APIC chipset type.
518	* @param pMsi Where to store the MSI message.
519	*/
520	DECLINLINE(void) ioapicGetMsiFromRte(uint64_t u64Rte, IOAPICTYPE enmType, PMSIMSG pMsi)
521	{
522	bool const fRemappable = IOAPIC_RTE_GET_INTR_FORMAT(u64Rte);
523	if (!fRemappable)
524	{
525	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
526	pMsi->Addr.n.u8DestId = IOAPIC_RTE_GET_DEST(u64Rte);
527	pMsi->Addr.n.u1RedirHint = 0;
528	pMsi->Addr.n.u1DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
529
530	pMsi->Data.n.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
531	pMsi->Data.n.u3DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
532	pMsi->Data.n.u1TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
533	/* pMsi->Data.n.u1Level = ??? */
534	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
535	* possible in theory? Maybe document this more explicitly... */
536	}
537	else
538	{
539	Assert(enmType == IOAPICTYPE_DMAR);
540	NOREF(enmType);
541
542	/*
543	* The spec. mentions that SHV will be 0 when delivery mode is 0 (fixed), but
544	* not what SHV will be if delivery mode is not 0. I ASSUME copying delivery
545	* mode into SHV here is what hardware actually does.
546	*
547	* See Intel VT-d spec. 5.1.5.1 "I/OxAPIC Programming".
548	*/
549	pMsi->Addr.dmar_remap.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
550	pMsi->Addr.dmar_remap.u14IntrIndexLo = IOAPIC_RTE_GET_INTR_INDEX_LO(u64Rte);
551	pMsi->Addr.dmar_remap.fIntrFormat = 1;
552	pMsi->Addr.dmar_remap.fShv = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
553	pMsi->Addr.dmar_remap.u1IntrIndexHi = IOAPIC_RTE_GET_INTR_INDEX_HI(u64Rte);
554
555	pMsi->Data.dmar_remap.u16SubHandle = 0;
556	}
557	}
558	#endif
559
560
561	/**
562	* Signals the next pending interrupt for the specified Redirection Table Entry
563	* (RTE).
564	*
565	* @param pDevIns The device instance.
566	* @param pThis The shared I/O APIC device state.
567	* @param pThisCC The I/O APIC device state for the current context.
568	* @param idxRte The index of the RTE (validated).
569	*
570	* @remarks It is the responsibility of the caller to verify that an interrupt is
571	* pending for the pin corresponding to the RTE before calling this
572	* function.
573	*/
574	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte)
575	{
576	Assert(IOAPIC_LOCK_IS_OWNER(pDevIns, pThis, pThisCC));
577
578	/*
579	* Ensure the interrupt isn't masked.
580	*/
581	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
582	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
583	{ /* likely */ }
584	else
585	return;
586
587	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
588	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
589	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
590	{
591	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
592	if (u8RemoteIrr)
593	{
594	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
595	return;
596	}
597	}
598
599	XAPICINTR ApicIntr;
600	RT_ZERO(ApicIntr);
601	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
602	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
603	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
604	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
605	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
606	ApicIntr.u8TriggerMode = u8TriggerMode;
607	//ApicIntr.u8RedirHint = 0;
608
609	/** @todo We might be able to release the IOAPIC(PDM) lock here and re-acquire it
610	* before setting the remote IRR bit below. The APIC and IOMMU should not
611	* require the caller to hold the PDM lock. */
612
613	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
614	/*
615	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
616	* For line-based interrupts we must use the southbridge I/O APIC's BDF as
617	* the origin of the interrupt, see @bugref{9654#c74}.
618	*/
619	MSIMSG MsiIn;
620	RT_ZERO(MsiIn);
621	ioapicGetMsiFromRte(u64Rte, pThis->enmType, &MsiIn);
622
623	MSIMSG MsiOut;
624	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, pThis->uPciAddress, &MsiIn, &MsiOut);
625	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
626	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
627	{ /* likely - assuming majority of VMs don't have IOMMU configured. */ }
628	else if (RT_SUCCESS(rcRemap))
629	{
630	/* Update the APIC interrupt with the remapped data. */
631	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
632
633	/* Ensure polarity hasn't changed (trigger mode might change with Intel IOMMUs). */
634	Assert(ApicIntr.u8Polarity == IOAPIC_RTE_GET_POLARITY(u64Rte));
635	STAM_COUNTER_INC(&pThis->StatIommuRemappedIntr);
636	}
637	else
638	{
639	STAM_COUNTER_INC(&pThis->StatIommuDiscardedIntr);
640	return;
641	}
642	#endif
643
644	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
645	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
646	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
647	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
648	ApicIntr.u8Vector, ApicIntr.u8Vector));
649
650	/*
651	* Deliver to the local APIC via the system/3-wire-APIC bus.
652	*/
653	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
654	ApicIntr.u8Dest,
655	ApicIntr.u8DestMode,
656	ApicIntr.u8DeliveryMode,
657	ApicIntr.u8Vector,
658	ApicIntr.u8Polarity,
659	ApicIntr.u8TriggerMode,
660	u32TagSrc);
661	/* Can't reschedule to R3. */
662	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
663	#ifdef DEBUG_ramshankar
664	if (rc == VERR_APIC_INTR_DISCARDED)
665	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
666	#endif
667
668	if (rc == VINF_SUCCESS)
669	{
670	/*
671	* For level-triggered interrupts, we set the remote IRR bit to indicate
672	* the local APIC has accepted the interrupt.
673	*
674	* For edge-triggered interrupts, we should not clear the IRR bit as it
675	* should remain intact to reflect the state of the interrupt line.
676	* The device will explicitly transition to inactive state via the
677	* ioapicSetIrq() callback.
678	*/
679	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
680	{
681	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
682	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
683	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
684	STAM_PROFILE_ADV_START(&pThis->aStatLevelAct[idxRte], a);
685	}
686	/*
687	* Edge-triggered flip-flops gets cleaned up here as the device code will
688	* not do any explicit ioapicSetIrq and we won't receive any EOI either.
689	*/
690	else if (ASMBitTest(pThis->bmFlipFlop, idxRte))
691	{
692	Log2(("IOAPIC: Clearing IRR for edge flip-flop %#x uTagSrc=%#x\n", idxRte, pThis->au32TagSrc[idxRte]));
693	pThis->au32TagSrc[idxRte] = 0;
694	pThis->uIrr &= ~RT_BIT_32(idxRte);
695	}
696	}
697	}
698
699
700	/**
701	* Gets the redirection table entry.
702	*
703	* @returns The redirection table entry.
704	* @param pThis The shared I/O APIC device state.
705	* @param uIndex The index value.
706	*/
707	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
708	{
709	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
710	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
711	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
712	UINT32_MAX);
713	uint32_t uValue;
714	if (!(uIndex & 1))
715	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
716	else
717	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
718
719	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
720	return uValue;
721	}
722
723
724	/**
725	* Sets the redirection table entry.
726	*
727	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
728	* @param pDevIns The device instance.
729	* @param pThis The shared I/O APIC device state.
730	* @param pThisCC The I/O APIC device state for the current context.
731	* @param uIndex The index value.
732	* @param uValue The value to set.
733	*/
734	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
735	uint32_t uIndex, uint32_t uValue)
736	{
737	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
738	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
739	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
740	VINF_SUCCESS);
741
742	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
743	if (rc == VINF_SUCCESS)
744	{
745	/*
746	* Write the low or high 32-bit value into the specified 64-bit RTE register,
747	* update only the valid, writable bits.
748	*
749	* We need to preserve the read-only bits as it can have dire consequences
750	* otherwise, see @bugref{8386#c24}.
751	*/
752	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
753	if (!(uIndex & 1))
754	{
755	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
756	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
757	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
758	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
759	}
760	else
761	{
762	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
763	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
764	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
765	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
766	}
767
768	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
769
770	/*
771	* Signal the next pending interrupt for this RTE.
772	*/
773	uint32_t const uPinMask = UINT32_C(1) << idxRte;
774	if (pThis->uIrr & uPinMask)
775	{
776	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: Signalling pending interrupt. idxRte=%u\n", idxRte));
777	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
778	}
779
780	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
781	}
782	else
783	STAM_COUNTER_INC(&pThis->StatSetRteContention);
784
785	return rc;
786	}
787
788
789	/**
790	* Gets the data register.
791	*
792	* @returns The data value.
793	* @param pThis The shared I/O APIC device state.
794	*/
795	static uint32_t ioapicGetData(PCIOAPIC pThis)
796	{
797	uint8_t const uIndex = pThis->u8Index;
798	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
799	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
800	&& uIndex <= pThis->u8LastRteRegIdx)
801	return ioapicGetRedirTableEntry(pThis, uIndex);
802
803	uint32_t uValue;
804	switch (uIndex)
805	{
806	case IOAPIC_INDIRECT_INDEX_ID:
807	uValue = ioapicGetId(pThis);
808	break;
809
810	case IOAPIC_INDIRECT_INDEX_VERSION:
811	uValue = ioapicGetVersion(pThis);
812	break;
813
814	case IOAPIC_INDIRECT_INDEX_ARB:
815	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
816	{
817	uValue = ioapicGetArb();
818	break;
819	}
820	RT_FALL_THRU();
821
822	default:
823	uValue = UINT32_C(0xffffffff);
824	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
825	break;
826	}
827	return uValue;
828	}
829
830
831	/**
832	* Sets the data register.
833	*
834	* @returns Strict VBox status code.
835	* @param pDevIns The device instance.
836	* @param pThis The shared I/O APIC device state.
837	* @param pThisCC The I/O APIC device state for the current context.
838	* @param uValue The value to set.
839	*/
840	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
841	{
842	uint8_t const uIndex = pThis->u8Index;
843	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
844	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
845
846	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
847	&& uIndex <= pThis->u8LastRteRegIdx)
848	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
849
850	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
851	ioapicSetId(pThis, uValue);
852	else
853	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
854
855	return VINF_SUCCESS;
856	}
857
858
859	/**
860	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
861	*/
862	static DECLCALLBACK(void) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
863	{
864	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
865	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
866
867	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
868	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
869
870	bool fRemoteIrrCleared = false;
871	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
872	AssertRC(rc);
873
874	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
875	{
876	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
877	/** @todo r=bird: bugref:10073: I've changed it to ignore edge triggered
878	* entries here since the APIC will only call us for those? Not doing so
879	* confuses ended up with spurious HPET/RTC IRQs in SMP linux because of it
880	* sharing the vector with a level-triggered IRQ (like vboxguest) delivered on a
881	* different CPU.
882	*
883	* Maybe we should also/instead filter on the source APIC number? */
884	if ( IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector
885	&& IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) != IOAPIC_RTE_TRIGGER_MODE_EDGE)
886	{
887	#ifdef DEBUG_ramshankar
888	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
889	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
890	#endif
891	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
892	fRemoteIrrCleared = true;
893	STAM_PROFILE_ADV_STOP(&pThis->aStatLevelAct[idxRte], a);
894	STAM_COUNTER_INC(&pThis->StatEoiReceived);
895	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
896
897	/*
898	* Signal the next pending interrupt for this RTE.
899	*/
900	uint32_t const uPinMask = UINT32_C(1) << idxRte;
901	if (pThis->uIrr & uPinMask)
902	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
903	}
904	}
905
906	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
907
908	#ifndef VBOX_WITH_IOMMU_AMD
909	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
910	#endif
911	}
912
913
914	/**
915	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
916	*/
917	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
918	{
919	RT_NOREF(uBusDevFn); /** @todo r=ramshankar: Remove this argument if it's also unnecessary with Intel IOMMU. */
920	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask, a_fForceTag) do { \
921	pThis->au32TagSrc[(a_idxRte)] = (a_fForceTag) \|\| !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
922	pThis->uIrr \|= a_PinMask; \
923	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_idxRte)); \
924	} while (0)
925
926	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
927	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
928	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
929
930	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
931
932	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
933	{
934	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
935	AssertRC(rc);
936
937	uint8_t const idxRte = iIrq;
938	uint32_t const uPinMask = UINT32_C(1) << idxRte;
939	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
940	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
941
942	bool fActive = RT_BOOL(iLevel & 1);
943	/** @todo Polarity is busted elsewhere, we need to fix that
944	* first. See @bugref{8386#c7}. */
945	#if 0
946	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
947	fActive ^= u8Polarity; */
948	#endif
949	if (!fActive)
950	{
951	pThis->uIrr &= ~uPinMask;
952	pThis->au32TagSrc[idxRte] = 0;
953	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
954	return;
955	}
956
957	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
958	if (!fFlipFlop)
959	{
960	ASMBitClear(pThis->bmFlipFlop, idxRte);
961
962	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
963	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
964	{
965	/*
966	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
967	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
968	*/
969	if (!uPrevIrr)
970	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask, false);
971	else
972	{
973	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
974	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
975	}
976	}
977	else
978	{
979	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
980
981	/*
982	* For level-triggered interrupts, redundant interrupts are not a problem
983	* and will eventually be delivered anyway after an EOI, but our PDM devices
984	* should not typically call us with no change to the level.
985	*/
986	if (!uPrevIrr)
987	{ /* likely */ }
988	else
989	{
990	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
991	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
992	}
993
994	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask, false);
995	}
996	}
997	else
998	{
999	/*
1000	* The device is flip-flopping the interrupt line, which implies we should de-assert
1001	* and assert the interrupt line. The interrupt line is left in the asserted state
1002	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
1003	* hence just the assert is done.
1004	*/
1005	ASMBitSet(pThis->bmFlipFlop, idxRte);
1006	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask, true);
1007	}
1008
1009	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1010	}
1011	#undef IOAPIC_ASSERT_IRQ
1012	}
1013
1014
1015	/**
1016	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
1017	*/
1018	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
1019	{
1020	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1021	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1022	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32 uTagSrc=%#x\n",
1023	uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32, uTagSrc));
1024
1025	XAPICINTR ApicIntr;
1026	RT_ZERO(ApicIntr);
1027
1028	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
1029	/*
1030	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
1031	*
1032	* If the Bus:Dev:Fn isn't valid, it is ASSUMED the device generating the
1033	* MSI is the IOMMU itself and hence isn't subjected to remapping. This
1034	* is the case with Intel IOMMUs.
1035	*
1036	* AMD IOMMUs are full fledged PCI devices, hence the BDF will be a
1037	* valid PCI slot, but interrupts generated by the IOMMU will be handled
1038	* by VERR_IOMMU_CANNOT_CALL_SELF case.
1039	*/
1040	MSIMSG MsiOut;
1041	if (PCIBDF_IS_VALID(uBusDevFn))
1042	{
1043	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
1044	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
1045	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
1046	{ /* likely - assuming majority of VMs don't have IOMMU configured. */ }
1047	else if (RT_SUCCESS(rcRemap))
1048	{
1049	STAM_COUNTER_INC(&pThis->StatIommuRemappedMsi);
1050	pMsi = &MsiOut;
1051	}
1052	else
1053	{
1054	STAM_COUNTER_INC(&pThis->StatIommuDiscardedMsi);
1055	return;
1056	}
1057	}
1058	#else
1059	NOREF(uBusDevFn);
1060	#endif
1061
1062	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
1063
1064	/*
1065	* Deliver to the local APIC via the system/3-wire-APIC bus.
1066	*/
1067	STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
1068
1069	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
1070	ApicIntr.u8Dest,
1071	ApicIntr.u8DestMode,
1072	ApicIntr.u8DeliveryMode,
1073	ApicIntr.u8Vector,
1074	0 /* u8Polarity - N/A */,
1075	ApicIntr.u8TriggerMode,
1076	uTagSrc);
1077	/* Can't reschedule to R3. */
1078	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
1079	}
1080
1081
1082	/**
1083	* @callback_method_impl{FNIOMMMIONEWREAD}
1084	*/
1085	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1086	{
1087	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1088	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
1089	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1090	RT_NOREF_PV(pvUser);
1091
1092	VBOXSTRICTRC rc = VINF_SUCCESS;
1093	uint32_t puValue = (uint32_t )pv;
1094	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
1095	switch (offReg)
1096	{
1097	case IOAPIC_DIRECT_OFF_INDEX:
1098	*puValue = ioapicGetIndex(pThis);
1099	break;
1100
1101	case IOAPIC_DIRECT_OFF_DATA:
1102	*puValue = ioapicGetData(pThis);
1103	break;
1104
1105	default:
1106	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1107	rc = VINF_IOM_MMIO_UNUSED_FF;
1108	break;
1109	}
1110
1111	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
1112	return rc;
1113	}
1114
1115
1116	/**
1117	* @callback_method_impl{FNIOMMMIONEWWRITE}
1118	*/
1119	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1120	{
1121	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1122	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1123	RT_NOREF_PV(pvUser);
1124
1125	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1126
1127	Assert(!(off & 3));
1128	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1129
1130	VBOXSTRICTRC rc = VINF_SUCCESS;
1131	uint32_t const uValue = (uint32_t const )pv;
1132	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
1133
1134	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
1135	switch (offReg)
1136	{
1137	case IOAPIC_DIRECT_OFF_INDEX:
1138	ioapicSetIndex(pThis, uValue);
1139	break;
1140
1141	case IOAPIC_DIRECT_OFF_DATA:
1142	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
1143	break;
1144
1145	case IOAPIC_DIRECT_OFF_EOI:
1146	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
1147	ioapicSetEoi(pDevIns, uValue);
1148	else
1149	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1150	break;
1151
1152	default:
1153	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1154	break;
1155	}
1156
1157	return rc;
1158	}
1159
1160
1161	#ifdef IN_RING3
1162
1163	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1164	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1165	{
1166	RT_NOREF(pDesc);
1167	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1168	return VINF_SUCCESS;
1169	}
1170
1171
1172	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1173	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1174	{
1175	RT_NOREF(pDesc, pfMask);
1176	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1177	return VINF_SUCCESS;
1178	}
1179
1180
1181	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1182	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1183	{
1184	RT_NOREF(pDesc);
1185	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1186	return VINF_SUCCESS;
1187	}
1188
1189
1190	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1191	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1192	{
1193	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1194	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1195	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1196	RT_NOREF(pDesc, pfMask);
1197	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1198	}
1199
1200
1201	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1202	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1203	{
1204	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1205	RT_NOREF(pDesc);
1206	pValue->u32 = ioapicGetVersion(pThis);
1207	return VINF_SUCCESS;
1208	}
1209
1210
1211	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1212	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1213	{
1214	RT_NOREF(pvUser, pDesc);
1215	pValue->u32 = ioapicGetArb();
1216	return VINF_SUCCESS;
1217	}
1218
1219
1220	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1221	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1222	{
1223	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1224	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1225	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1226	return VINF_SUCCESS;
1227	}
1228
1229
1230	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1231	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1232	{
1233	RT_NOREF(pfMask);
1234	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1235	/* No locks, no checks, just do it. */
1236	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1237	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1238	return VINF_SUCCESS;
1239	}
1240
1241
1242	/** IOREDTBLn sub fields. */
1243	static DBGFREGSUBFIELD const g_aRteSubs[] =
1244	{
1245	{ "vector", 0, 8, 0, 0, NULL, NULL },
1246	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1247	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1248	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1249	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1250	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1251	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1252	{ "mask", 16, 1, 0, 0, NULL, NULL },
1253	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1254	{ "dest", 56, 8, 0, 0, NULL, NULL },
1255	DBGFREGSUBFIELD_TERMINATOR()
1256	};
1257
1258
1259	/** Register descriptors for DBGF. */
1260	static DBGFREGDESC const g_aRegDesc[] =
1261	{
1262	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1263	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1264	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1265	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1266	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1267	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1268	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1269	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1270	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1271	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1272	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1273	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1274	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1275	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1276	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1277	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1278	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1279	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1280	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1281	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1282	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1283	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1284	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1285	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1286	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1287	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1288	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1289	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1290	DBGFREGDESC_TERMINATOR()
1291	};
1292
1293
1294	/**
1295	* @callback_method_impl{FNDBGFHANDLERDEV}
1296	*/
1297	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1298	{
1299	RT_NOREF(pszArgs);
1300	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1301	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1302
1303	bool const fLegacy = RTStrCmp(pszArgs, "legacy") == 0;
1304
1305	static const char * const s_apszDeliveryModes[] =
1306	{
1307	" fixed",
1308	"lowpri",
1309	" smi",
1310	" rsvd",
1311	" nmi",
1312	" init",
1313	" rsvd",
1314	"extint"
1315	};
1316	static const char * const s_apszDestMode[] = { "phys", "log " };
1317	static const char * const s_apszTrigMode[] = { " edge", "level" };
1318	static const char * const s_apszPolarity[] = { "acthi", "actlo" };
1319	static const char * const s_apszDeliveryStatus[] = { "idle", "pend" };
1320
1321	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1322
1323	uint32_t const uId = ioapicGetId(pThis);
1324	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1325	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1326
1327	uint32_t const uVer = ioapicGetVersion(pThis);
1328	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1329	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1330	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1331	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1332
1333	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1334	{
1335	uint32_t const uArb = ioapicGetArb();
1336	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1337	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1338	}
1339
1340	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1341
1342	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1343	if ( pThis->enmType != IOAPICTYPE_DMAR
1344	\|\| fLegacy)
1345	{
1346	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector rte\n");
1347	pHlp->pfnPrintf(pHlp, " ---------------------------------------------------------------------------------------------\n");
1348
1349	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1350	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1351	{
1352	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1353	const char *pszDestMode = s_apszDestMode[IOAPIC_RTE_GET_DEST_MODE(u64Rte)];
1354	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1355	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1356	const char *pszTriggerMode = s_apszTrigMode[IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte)];
1357	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1358	const char *pszPolarity = s_apszPolarity[IOAPIC_RTE_GET_POLARITY(u64Rte)];
1359	const char *pszDeliveryStatus = s_apszDeliveryStatus[IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte)];
1360	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1361	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1362	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1363	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1364
1365	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1366	idxRte,
1367	pszDestMode,
1368	uDest,
1369	uMask,
1370	(pThis->uIrr >> idxRte) & 1,
1371	pszTriggerMode,
1372	uRemoteIrr,
1373	pszPolarity,
1374	pszDeliveryStatus,
1375	pszDeliveryMode,
1376	uVector,
1377	u64Rte);
1378	}
1379	}
1380	else
1381	{
1382	pHlp->pfnPrintf(pHlp, " idx intr_idx fmt mask irr trigger rirr polar dlvr_st dlvr_mode vector rte\n");
1383	pHlp->pfnPrintf(pHlp, " ----------------------------------------------------------------------------------------\n");
1384
1385	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1386	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1387	{
1388	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1389	const uint16_t idxIntrLo = IOAPIC_RTE_GET_INTR_INDEX_LO(u64Rte);
1390	const uint8_t fIntrFormat = IOAPIC_RTE_GET_INTR_FORMAT(u64Rte);
1391	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1392	const char *pszTriggerMode = s_apszTrigMode[IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte)];
1393	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1394	const char *pszPolarity = s_apszPolarity[IOAPIC_RTE_GET_POLARITY(u64Rte)];
1395	const char *pszDeliveryStatus = s_apszDeliveryStatus[IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte)];
1396	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1397	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1398	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1399	const uint16_t idxIntrHi = IOAPIC_RTE_GET_INTR_INDEX_HI(u64Rte);
1400	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1401	const uint16_t idxIntr = idxIntrLo \| (idxIntrHi << 15);
1402	pHlp->pfnPrintf(pHlp, " %02d %4u %u %u %u %s %u %s %s %s %3u (%016llx)\n",
1403	idxRte,
1404	idxIntr,
1405	fIntrFormat,
1406	uMask,
1407	(pThis->uIrr >> idxRte) & 1,
1408	pszTriggerMode,
1409	uRemoteIrr,
1410	pszPolarity,
1411	pszDeliveryStatus,
1412	pszDeliveryMode,
1413	uVector,
1414	u64Rte);
1415	}
1416	}
1417	}
1418
1419
1420	/**
1421	* @copydoc FNSSMDEVSAVEEXEC
1422	*/
1423	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1424	{
1425	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1426	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1427	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1428
1429	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1430	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1431	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1432	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1433	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1434
1435	return VINF_SUCCESS;
1436	}
1437
1438
1439	/**
1440	* @copydoc FNSSMDEVLOADEXEC
1441	*/
1442	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1443	{
1444	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1445	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1446	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1447
1448	Assert(uPass == SSM_PASS_FINAL);
1449	NOREF(uPass);
1450
1451	/* Weed out invalid versions. */
1452	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1453	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1454	{
1455	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1456	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1457	}
1458
1459	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1460	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1461
1462	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1463	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1464	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1465	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1466
1467	return VINF_SUCCESS;
1468	}
1469
1470
1471	/**
1472	* @interface_method_impl{PDMDEVREG,pfnReset}
1473	*/
1474	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1475	{
1476	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1477	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1478	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1479
1480	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1481	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1482
1483	pThis->uIrr = 0;
1484	pThis->u8Index = 0;
1485	pThis->u8Id = 0;
1486
1487	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1488	{
1489	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1490	pThis->au32TagSrc[idxRte] = 0;
1491	}
1492
1493	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1494	}
1495
1496
1497	/**
1498	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1499	*/
1500	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1501	{
1502	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1503	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1504
1505	pThisRC->pIoApicHlp += offDelta;
1506	}
1507
1508
1509	/**
1510	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1511	*/
1512	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1513	{
1514	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1515	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1516	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1517
1518	# ifndef IOAPIC_WITH_PDM_CRITSECT
1519	/*
1520	* Destroy the RTE critical section.
1521	*/
1522	if (PDMCritSectIsInitialized(&pThis->CritSect))
1523	PDMR3CritSectDelete(&pThis->CritSect);
1524	# else
1525	RT_NOREF_PV(pThis);
1526	# endif
1527
1528	return VINF_SUCCESS;
1529	}
1530
1531
1532	/**
1533	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1534	*/
1535	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1536	{
1537	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1538	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1539	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1540	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1541	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1542	Assert(iInstance == 0); RT_NOREF(iInstance);
1543
1544	/*
1545	* Validate and read the configuration.
1546	*/
1547	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType\|PCIAddress", "");
1548
1549	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0
1550	upsets some guest which we haven't yet been tested. */
1551	uint32_t cCpus;
1552	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1553	if (RT_FAILURE(rc))
1554	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1555	pThis->cCpus = (uint8_t)cCpus;
1556
1557	char szChipType[16];
1558	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1559	if (RT_FAILURE(rc))
1560	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1561
1562	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "PCIAddress", &pThis->uPciAddress, NIL_PCIBDF);
1563	if (RT_FAILURE(rc))
1564	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query 32-bit integer \"PCIAddress\""));
1565
1566	if (!strcmp(szChipType, "ICH9"))
1567	{
1568	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1569	pThis->enmType = IOAPICTYPE_ICH9;
1570	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1571	pThis->u8IdMask = 0xff;
1572	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1573	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1574	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1575	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1576	}
1577	else if (!strcmp(szChipType, "DMAR"))
1578	{
1579	/* Intel DMAR compatible I/O APIC integrated into ICH southbridges. */
1580	/* Identical to ICH9, but interprets RTEs and MSI address and data fields differently. */
1581	pThis->enmType = IOAPICTYPE_DMAR;
1582	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1583	pThis->u8IdMask = 0xff;
1584	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1585	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1586	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_DMAR;
1587	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_DMAR;
1588	}
1589	else if (!strcmp(szChipType, "82093AA"))
1590	{
1591	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1592	pThis->enmType = IOAPICTYPE_82093AA;
1593	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1594	pThis->u8IdMask = 0x0f;
1595	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1596	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1597	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1598	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1599	}
1600	else if (!strcmp(szChipType, "82379AB"))
1601	{
1602	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1603	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1604	pThis->enmType = IOAPICTYPE_82379AB;
1605	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1606	pThis->u8IdMask = 0x0f;
1607	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1608	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1609	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1610	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1611	}
1612	else
1613	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1614	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1615	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1616
1617	/*
1618	* We will use our own critical section for the IOAPIC device.
1619	*/
1620	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1621	AssertRCReturn(rc, rc);
1622
1623	# ifndef IOAPIC_WITH_PDM_CRITSECT
1624	/*
1625	* Setup the critical section to protect concurrent writes to the RTEs.
1626	*/
1627	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1628	AssertRCReturn(rc, rc);
1629	# endif
1630
1631	/*
1632	* Register the IOAPIC.
1633	*/
1634	PDMIOAPICREG IoApicReg;
1635	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1636	IoApicReg.pfnSetIrq = ioapicSetIrq;
1637	IoApicReg.pfnSendMsi = ioapicSendMsi;
1638	IoApicReg.pfnSetEoi = ioapicSetEoi;
1639	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1640	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1641	AssertRCReturn(rc, rc);
1642	AssertPtr(pThisCC->pIoApicHlp->pfnApicBusDeliver);
1643	AssertPtr(pThisCC->pIoApicHlp->pfnLock);
1644	AssertPtr(pThisCC->pIoApicHlp->pfnUnlock);
1645	AssertPtr(pThisCC->pIoApicHlp->pfnLockIsOwner);
1646	AssertPtr(pThisCC->pIoApicHlp->pfnIommuMsiRemap);
1647
1648	/*
1649	* Register MMIO region.
1650	*/
1651	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1652	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1653	AssertRCReturn(rc, rc);
1654
1655	/*
1656	* Register the saved state.
1657	*/
1658	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1659	AssertRCReturn(rc, rc);
1660
1661	/*
1662	* Register debugger info item.
1663	*/
1664	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1665	AssertRCReturn(rc, rc);
1666
1667	/*
1668	* Register debugger register access.
1669	*/
1670	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1671	AssertRCReturn(rc, rc);
1672
1673	# ifdef VBOX_WITH_STATISTICS
1674	/*
1675	* Statistics.
1676	*/
1677	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1678	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1679	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1680	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1681
1682	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1683	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1684	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1685	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1686
1687	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1688	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1689	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1690
1691	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedIntr, STAMTYPE_COUNTER, "Iommu/RemappedIntr", STAMUNIT_OCCURENCES, "Number of interrupts remapped by the IOMMU.");
1692	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedMsi, STAMTYPE_COUNTER, "Iommu/RemappedMsi", STAMUNIT_OCCURENCES, "Number of MSIs remapped by the IOMMU.");
1693	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedIntr, STAMTYPE_COUNTER, "Iommu/DiscardedIntr", STAMUNIT_OCCURENCES, "Number of interrupts discarded by the IOMMU.");
1694	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi, STAMTYPE_COUNTER, "Iommu/DiscardedMsi", STAMUNIT_OCCURENCES, "Number of MSIs discarded by the IOMMU.");
1695
1696	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1697
1698	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1699	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1700
1701	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatLevelAct); ++i)
1702	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatLevelAct[i], STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Time spent in the level active state", "IntPending/%02x", i);
1703	# endif
1704	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
1705	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1706	"Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
1707
1708	/*
1709	* Init. the device state.
1710	*/
1711	LogRel(("IOAPIC: Version=%d.%d ChipType=%s\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0f, szChipType));
1712	ioapicR3Reset(pDevIns);
1713
1714	return VINF_SUCCESS;
1715	}
1716
1717	#else /* !IN_RING3 */
1718
1719	/**
1720	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1721	*/
1722	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1723	{
1724	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1725	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1726	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1727
1728	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1729	AssertRCReturn(rc, rc);
1730
1731	PDMIOAPICREG IoApicReg;
1732	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1733	IoApicReg.pfnSetIrq = ioapicSetIrq;
1734	IoApicReg.pfnSendMsi = ioapicSendMsi;
1735	IoApicReg.pfnSetEoi = ioapicSetEoi;
1736	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1737	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1738	AssertRCReturn(rc, rc);
1739	AssertPtr(pThisCC->pIoApicHlp->pfnApicBusDeliver);
1740	AssertPtr(pThisCC->pIoApicHlp->pfnLock);
1741	AssertPtr(pThisCC->pIoApicHlp->pfnUnlock);
1742	AssertPtr(pThisCC->pIoApicHlp->pfnLockIsOwner);
1743	AssertPtr(pThisCC->pIoApicHlp->pfnIommuMsiRemap);
1744
1745	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1746	AssertRCReturn(rc, rc);
1747
1748	return VINF_SUCCESS;
1749	}
1750
1751	#endif /* !IN_RING3 */
1752
1753	/**
1754	* IO APIC device registration structure.
1755	*/
1756	const PDMDEVREG g_DeviceIOAPIC =
1757	{
1758	/* .u32Version = */ PDM_DEVREG_VERSION,
1759	/* .uReserved0 = */ 0,
1760	/* .szName = */ "ioapic",
1761	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1762	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1763	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1764	/* .cMaxInstances = */ 1,
1765	/* .uSharedVersion = */ 42,
1766	/* .cbInstanceShared = */ sizeof(IOAPIC),
1767	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1768	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1769	/* .cMaxPciDevices = */ 0,
1770	/* .cMaxMsixVectors = */ 0,
1771	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1772	#if defined(IN_RING3)
1773	/* .pszRCMod = */ "VBoxDDRC.rc",
1774	/* .pszR0Mod = */ "VBoxDDR0.r0",
1775	/* .pfnConstruct = */ ioapicR3Construct,
1776	/* .pfnDestruct = */ ioapicR3Destruct,
1777	/* .pfnRelocate = */ ioapicR3Relocate,
1778	/* .pfnMemSetup = */ NULL,
1779	/* .pfnPowerOn = */ NULL,
1780	/* .pfnReset = */ ioapicR3Reset,
1781	/* .pfnSuspend = */ NULL,
1782	/* .pfnResume = */ NULL,
1783	/* .pfnAttach = */ NULL,
1784	/* .pfnDetach = */ NULL,
1785	/* .pfnQueryInterface = */ NULL,
1786	/* .pfnInitComplete = */ NULL,
1787	/* .pfnPowerOff = */ NULL,
1788	/* .pfnSoftReset = */ NULL,
1789	/* .pfnReserved0 = */ NULL,
1790	/* .pfnReserved1 = */ NULL,
1791	/* .pfnReserved2 = */ NULL,
1792	/* .pfnReserved3 = */ NULL,
1793	/* .pfnReserved4 = */ NULL,
1794	/* .pfnReserved5 = */ NULL,
1795	/* .pfnReserved6 = */ NULL,
1796	/* .pfnReserved7 = */ NULL,
1797	#elif defined(IN_RING0)
1798	/* .pfnEarlyConstruct = */ NULL,
1799	/* .pfnConstruct = */ ioapicRZConstruct,
1800	/* .pfnDestruct = */ NULL,
1801	/* .pfnFinalDestruct = */ NULL,
1802	/* .pfnRequest = */ NULL,
1803	/* .pfnReserved0 = */ NULL,
1804	/* .pfnReserved1 = */ NULL,
1805	/* .pfnReserved2 = */ NULL,
1806	/* .pfnReserved3 = */ NULL,
1807	/* .pfnReserved4 = */ NULL,
1808	/* .pfnReserved5 = */ NULL,
1809	/* .pfnReserved6 = */ NULL,
1810	/* .pfnReserved7 = */ NULL,
1811	#elif defined(IN_RC)
1812	/* .pfnConstruct = */ ioapicRZConstruct,
1813	/* .pfnReserved0 = */ NULL,
1814	/* .pfnReserved1 = */ NULL,
1815	/* .pfnReserved2 = */ NULL,
1816	/* .pfnReserved3 = */ NULL,
1817	/* .pfnReserved4 = */ NULL,
1818	/* .pfnReserved5 = */ NULL,
1819	/* .pfnReserved6 = */ NULL,
1820	/* .pfnReserved7 = */ NULL,
1821	#else
1822	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1823	#endif
1824	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1825	};
1826
1827
1828	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1829

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 90309

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