| 1 | /* $Id: DevLPC.cpp 64393 2016-10-24 14:42:05Z vboxsync $ */
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| 2 | /** @file
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| 3 | * DevLPC - LPC device emulation
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| 4 | *
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| 5 | * @todo This needs to be _replaced_ by a proper chipset device one day. There
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| 6 | * are less than 10 C/C++ statements in this file doing active emulation.
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| 7 | */
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| 8 |
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| 9 | /*
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| 10 | * Copyright (C) 2006-2016 Oracle Corporation
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| 11 | *
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| 12 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 13 | * available from http://www.virtualbox.org. This file is free software;
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| 14 | * you can redistribute it and/or modify it under the terms of the GNU
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| 15 | * General Public License (GPL) as published by the Free Software
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| 16 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 17 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 18 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 19 | * --------------------------------------------------------------------
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| 20 | *
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| 21 | * This code is based on:
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| 22 | *
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| 23 | * Low Pin Count emulation
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| 24 | *
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| 25 | * Copyright (c) 2007 Alexander Graf
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| 26 | *
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| 27 | * This library is free software; you can redistribute it and/or
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| 28 | * modify it under the terms of the GNU Lesser General Public
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| 29 | * License as published by the Free Software Foundation; either
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| 30 | * version 2 of the License, or (at your option) any later version.
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| 31 | *
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| 32 | * This library is distributed in the hope that it will be useful,
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| 33 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 34 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 35 | * Lesser General Public License for more details.
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| 36 | *
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| 37 | * You should have received a copy of the GNU Lesser General Public
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| 38 | * License along with this library; if not, write to the Free Software
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| 39 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 40 | *
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| 41 | * *****************************************************************
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| 42 | *
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| 43 | * This driver emulates an ICH-7 LPC partially. The LPC is basically the
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| 44 | * same as the ISA-bridge in the existing PIIX implementation, but
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| 45 | * more recent and includes support for HPET and Power Management.
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| 46 | *
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| 47 | */
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| 48 |
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| 49 |
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| 50 | /*********************************************************************************************************************************
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| 51 | * Header Files *
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| 52 | *********************************************************************************************************************************/
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| 53 | #define LOG_GROUP LOG_GROUP_DEV_LPC
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| 54 | #include <VBox/vmm/pdmdev.h>
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| 55 | #include <VBox/log.h>
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| 56 | #include <VBox/vmm/stam.h>
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| 57 | #include <iprt/assert.h>
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| 58 | #include <iprt/string.h>
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| 59 |
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| 60 | #include "VBoxDD2.h"
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| 61 |
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| 62 | #define RCBA_BASE UINT32_C(0xFED1C000)
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| 63 |
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| 64 | typedef struct
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| 65 | {
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| 66 | /** PCI device structure. */
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| 67 | PDMPCIDEV dev;
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| 68 |
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| 69 | /** Pointer to the device instance. - R3 ptr. */
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| 70 | PPDMDEVINSR3 pDevIns;
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| 71 |
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| 72 | /* So far, not much of a state */
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| 73 | } LPCState;
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| 74 |
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| 75 |
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| 76 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
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| 77 |
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| 78 |
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| 79 | static uint32_t rcba_ram_readl(LPCState* s, RTGCPHYS addr)
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| 80 | {
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| 81 | RT_NOREF1(s);
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| 82 | Log(("rcba_read at %llx\n", (uint64_t)addr));
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| 83 | int32_t iIndex = (addr - RCBA_BASE);
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| 84 | uint32_t value = 0;
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| 85 |
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| 86 | /* This is the HPET config pointer, HPAS in DSDT */
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| 87 | switch (iIndex)
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| 88 | {
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| 89 | case 0x3404:
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| 90 | Log(("rcba_read HPET_CONFIG_POINTER\n"));
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| 91 | value = 0xf0; /* enabled at 0xfed00000 */
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| 92 | break;
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| 93 | case 0x3410:
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| 94 | /* This is the HPET config pointer */
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| 95 | Log(("rcba_read GCS\n"));
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| 96 | value = 0;
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| 97 | break;
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| 98 | default:
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| 99 | Log(("Unknown RCBA read\n"));
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| 100 | break;
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| 101 | }
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| 102 |
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| 103 | return value;
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| 104 | }
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| 105 |
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| 106 | static void rcba_ram_writel(LPCState* s, RTGCPHYS addr, uint32_t value)
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| 107 | {
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| 108 | RT_NOREF2(s, value);
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| 109 | Log(("rcba_write %llx = %#x\n", (uint64_t)addr, value));
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| 110 | int32_t iIndex = (addr - RCBA_BASE);
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| 111 |
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| 112 | switch (iIndex)
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| 113 | {
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| 114 | case 0x3410:
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| 115 | Log(("rcba_write GCS\n"));
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| 116 | break;
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| 117 | default:
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| 118 | Log(("Unknown RCBA write\n"));
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| 119 | break;
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| 120 | }
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| 121 | }
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| 122 |
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| 123 | /**
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| 124 | * I/O handler for memory-mapped read operations.
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| 125 | *
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| 126 | * @returns VBox status code.
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| 127 | *
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| 128 | * @param pDevIns The device instance.
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| 129 | * @param pvUser User argument.
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| 130 | * @param GCPhysAddr Physical address (in GC) where the read starts.
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| 131 | * @param pv Where to store the result.
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| 132 | * @param cb Number of bytes read.
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| 133 | * @thread EMT
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| 134 | */
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| 135 | PDMBOTHCBDECL(int) lpcMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
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| 136 | {
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| 137 | RT_NOREF2(pvUser, cb);
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| 138 | LPCState *s = PDMINS_2_DATA(pDevIns, LPCState*);
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| 139 | Assert(cb == 4); Assert(!(GCPhysAddr & 3));
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| 140 | *(uint32_t*)pv = rcba_ram_readl(s, GCPhysAddr);
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| 141 | return VINF_SUCCESS;
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| 142 | }
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| 143 |
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| 144 | /**
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| 145 | * Memory mapped I/O Handler for write operations.
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| 146 | *
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| 147 | * @returns VBox status code.
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| 148 | *
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| 149 | * @param pDevIns The device instance.
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| 150 | * @param pvUser User argument.
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| 151 | * @param GCPhysAddr Physical address (in GC) where the read starts.
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| 152 | * @param pv Where to fetch the value.
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| 153 | * @param cb Number of bytes to write.
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| 154 | * @thread EMT
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| 155 | */
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| 156 | PDMBOTHCBDECL(int) lpcMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
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| 157 | {
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| 158 | RT_NOREF1(pvUser);
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| 159 | LPCState *s = PDMINS_2_DATA(pDevIns, LPCState*);
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| 160 |
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| 161 | switch (cb)
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| 162 | {
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| 163 | case 1:
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| 164 | case 2:
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| 165 | break;
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| 166 | case 4:
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| 167 | rcba_ram_writel(s, GCPhysAddr, *(uint32_t *)pv);
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| 168 | break;
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| 169 |
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| 170 | default:
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| 171 | AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
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| 172 | return VERR_INTERNAL_ERROR;
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| 173 | }
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| 174 | return VINF_SUCCESS;
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| 175 | }
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| 176 |
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| 177 | #ifdef IN_RING3
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| 178 |
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| 179 | /**
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| 180 | * Info handler, device version.
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| 181 | *
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| 182 | * @param pDevIns Device instance which registered the info.
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| 183 | * @param pHlp Callback functions for doing output.
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| 184 | * @param pszArgs Argument string. Optional and specific to the handler.
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| 185 | */
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| 186 | static DECLCALLBACK(void) lpcInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
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| 187 | {
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| 188 | RT_NOREF1(pszArgs);
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| 189 | LPCState *pThis = PDMINS_2_DATA(pDevIns, LPCState *);
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| 190 | LogFlow(("lpcInfo: \n"));
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| 191 |
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| 192 | if (pThis->dev.abConfig[0xde] == 0xbe && pThis->dev.abConfig[0xad] == 0xef)
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| 193 | pHlp->pfnPrintf(pHlp, "APIC backdoor activated\n");
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| 194 | else
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| 195 | pHlp->pfnPrintf(pHlp, "APIC backdoor closed: %02x %02x\n",
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| 196 | pThis->dev.abConfig[0xde], pThis->dev.abConfig[0xad]);
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| 197 |
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| 198 |
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| 199 | for (int iLine = 0; iLine < 8; ++iLine)
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| 200 | {
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| 201 |
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| 202 | int iBase = iLine < 4 ? 0x60 : 0x64;
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| 203 | uint8_t iMap = PCIDevGetByte(&pThis->dev, iBase + iLine);
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| 204 |
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| 205 | if ((iMap & 0x80) != 0)
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| 206 | pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + iLine);
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| 207 | else
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| 208 | pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + iLine, iMap & 0xf);
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| 209 | }
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| 210 | }
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| 211 |
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| 212 | /**
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| 213 | * @interface_method_impl{PDMDEVREG,pfnConstruct}
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| 214 | */
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| 215 | static DECLCALLBACK(int) lpcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
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| 216 | {
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| 217 | RT_NOREF2(iInstance, pCfg);
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| 218 | PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
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| 219 | LPCState *pThis = PDMINS_2_DATA(pDevIns, LPCState *);
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| 220 | int rc;
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| 221 | Assert(iInstance == 0);
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| 222 |
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| 223 | pThis->pDevIns = pDevIns;
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| 224 |
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| 225 | /*
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| 226 | * Register the PCI device.
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| 227 | */
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| 228 | PCIDevSetVendorId (&pThis->dev, 0x8086); /* Intel */
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| 229 | PCIDevSetDeviceId (&pThis->dev, 0x27b9);
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| 230 | PCIDevSetCommand (&pThis->dev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
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| 231 | PCIDevSetRevisionId (&pThis->dev, 0x02);
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| 232 | PCIDevSetClassSub (&pThis->dev, 0x01); /* PCI-to-ISA Bridge */
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| 233 | PCIDevSetClassBase (&pThis->dev, 0x06); /* Bridge */
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| 234 | PCIDevSetHeaderType (&pThis->dev, 0x80); /* normal, multifunction device (so that other devices can be its functions) */
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| 235 | PCIDevSetSubSystemVendorId(&pThis->dev, 0x8086);
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| 236 | PCIDevSetSubSystemId (&pThis->dev, 0x7270);
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| 237 | PCIDevSetInterruptPin (&pThis->dev, 0x00); /* The LPC device itself generates no interrupts */
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| 238 | PCIDevSetStatus (&pThis->dev, 0x0200); /* PCI_status_devsel_medium */
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| 239 |
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| 240 | /** @todo rewrite using PCI accessors; Update, rewrite this device from
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| 241 | * scratch! Possibly against ICH9 or something else matching our
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| 242 | * chipset of choice. (Note that the exteremely partial emulation here
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| 243 | * is supposed to be of ICH7 if what's on the top of the file is
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| 244 | * anything to go by.) */
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| 245 | /* See p. 427 of ICH9 specification for register description */
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| 246 |
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| 247 | /* 40h - 43h PMBASE 40-43 ACPI Base Address */
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| 248 | pThis->dev.abConfig[0x40] = 0x01; /* IO space */
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| 249 | pThis->dev.abConfig[0x41] = 0x80; /* base address / 128, see DevACPI.cpp */
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| 250 |
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| 251 | /* 44h ACPI_CNTL ACPI Control */
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| 252 | pThis->dev.abConfig[0x44] = 0x00 | (1<<7); /* SCI is IRQ9, ACPI enabled */
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| 253 | /* 48h–4Bh GPIOBASE GPIO Base Address */
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| 254 |
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| 255 | /* 4C GC GPIO Control */
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| 256 | pThis->dev.abConfig[0x4c] = 0x4d;
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| 257 | /* ???? */
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| 258 | pThis->dev.abConfig[0x4e] = 0x03;
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| 259 | pThis->dev.abConfig[0x4f] = 0x00;
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| 260 |
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| 261 | /* 60h-63h PIRQ[n]_ROUT PIRQ[A-D] Routing Control */
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| 262 | pThis->dev.abConfig[0x60] = 0x0b; /* PCI A -> IRQ 11 */
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| 263 | pThis->dev.abConfig[0x61] = 0x09; /* PCI B -> IRQ 9 */
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| 264 | pThis->dev.abConfig[0x62] = 0x0b; /* PCI C -> IRQ 11 */
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| 265 | pThis->dev.abConfig[0x63] = 0x09; /* PCI D -> IRQ 9 */
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| 266 |
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| 267 | /* 64h SIRQ_CNTL Serial IRQ Control 10h R/W, RO */
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| 268 | pThis->dev.abConfig[0x64] = 0x10;
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| 269 |
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| 270 | /* 68h-6Bh PIRQ[n]_ROUT PIRQ[E-H] Routing Control */
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| 271 | pThis->dev.abConfig[0x68] = 0x80;
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| 272 | pThis->dev.abConfig[0x69] = 0x80;
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| 273 | pThis->dev.abConfig[0x6A] = 0x80;
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| 274 | pThis->dev.abConfig[0x6B] = 0x80;
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| 275 |
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| 276 | /* 6C-6Dh LPC_IBDF IOxAPIC Bus:Device:Function 00F8h R/W */
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| 277 | pThis->dev.abConfig[0x70] = 0x80;
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| 278 | pThis->dev.abConfig[0x76] = 0x0c;
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| 279 | pThis->dev.abConfig[0x77] = 0x0c;
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| 280 | pThis->dev.abConfig[0x78] = 0x02;
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| 281 | pThis->dev.abConfig[0x79] = 0x00;
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| 282 | /* 80h LPC_I/O_DEC I/O Decode Ranges 0000h R/W */
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| 283 | /* 82h-83h LPC_EN LPC I/F Enables 0000h R/W */
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| 284 | /* 84h-87h GEN1_DEC LPC I/F Generic Decode Range 1 00000000h R/W */
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| 285 | /* 88h-8Bh GEN2_DEC LPC I/F Generic Decode Range 2 00000000h R/W */
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| 286 | /* 8Ch-8Eh GEN3_DEC LPC I/F Generic Decode Range 3 00000000h R/W */
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| 287 | /* 90h-93h GEN4_DEC LPC I/F Generic Decode Range 4 00000000h R/W */
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| 288 |
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| 289 | /* A0h-CFh Power Management */
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| 290 | pThis->dev.abConfig[0xa0] = 0x08;
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| 291 | pThis->dev.abConfig[0xa2] = 0x00;
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| 292 | pThis->dev.abConfig[0xa3] = 0x00;
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| 293 | pThis->dev.abConfig[0xa4] = 0x00;
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| 294 | pThis->dev.abConfig[0xa5] = 0x00;
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| 295 | pThis->dev.abConfig[0xa6] = 0x00;
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| 296 | pThis->dev.abConfig[0xa7] = 0x00;
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| 297 | pThis->dev.abConfig[0xa8] = 0x0f;
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| 298 | pThis->dev.abConfig[0xaa] = 0x00;
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| 299 | pThis->dev.abConfig[0xab] = 0x00;
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| 300 | pThis->dev.abConfig[0xac] = 0x00;
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| 301 | pThis->dev.abConfig[0xae] = 0x00;
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| 302 |
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| 303 | /* D0h-D3h FWH_SEL1 Firmware Hub Select 1 */
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| 304 | /* D4h-D5h FWH_SEL2 Firmware Hub Select 2 */
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| 305 | /* D8h-D9h FWH_DEC_EN1 Firmware Hub Decode Enable 1 */
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| 306 | /* DCh BIOS_CNTL BIOS Control */
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| 307 | /* E0h-E1h FDCAP Feature Detection Capability ID */
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| 308 | /* E2h FDLEN Feature Detection Capability Length */
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| 309 | /* E3h FDVER Feature Detection Version */
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| 310 | /* E4h-EBh FDVCT Feature Vector Description */
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| 311 |
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| 312 | /* F0h-F3h RCBA Root Complex Base Address */
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| 313 | pThis->dev.abConfig[0xf0] = RT_BYTE1(RCBA_BASE | 1); /* enabled */
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| 314 | pThis->dev.abConfig[0xf1] = RT_BYTE2(RCBA_BASE);
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| 315 | pThis->dev.abConfig[0xf2] = RT_BYTE3(RCBA_BASE);
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| 316 | pThis->dev.abConfig[0xf3] = RT_BYTE4(RCBA_BASE);
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| 317 |
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| 318 | rc = PDMDevHlpPCIRegisterEx(pDevIns, &pThis->dev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_NOT_MANDATORY_NO,
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| 319 | 31 /*uPciDevNo*/, 0 /*uPciFunNo*/, "lpc");
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| 320 | if (RT_FAILURE(rc))
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| 321 | return rc;
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| 322 |
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| 323 | /*
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| 324 | * Register the MMIO regions.
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| 325 | */
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| 326 | rc = PDMDevHlpMMIORegister(pDevIns, RCBA_BASE, 0x4000, pThis,
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| 327 | IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
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| 328 | lpcMMIOWrite, lpcMMIORead, "LPC Memory");
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| 329 | if (RT_FAILURE(rc))
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| 330 | return rc;
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| 331 |
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| 332 | /* No state in the LPC right now */
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| 333 |
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| 334 | /**
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| 335 | * @todo: Register statistics.
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| 336 | */
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| 337 | PDMDevHlpDBGFInfoRegister(pDevIns, "lpc", "Display LPC status. (no arguments)", lpcInfo);
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| 338 |
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| 339 | return VINF_SUCCESS;
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| 340 | }
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| 341 |
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| 342 |
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| 343 | /**
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| 344 | * The device registration structure.
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| 345 | */
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| 346 | const PDMDEVREG g_DeviceLPC =
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| 347 | {
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| 348 | /* u32Version */
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| 349 | PDM_DEVREG_VERSION,
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| 350 | /* szName */
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| 351 | "lpc",
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| 352 | /* szRCMod */
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| 353 | "VBoxDD2RC.rc",
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| 354 | /* szR0Mod */
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| 355 | "VBoxDD2R0.r0",
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| 356 | /* pszDescription */
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| 357 | "Low Pin Count (LPC) Bus",
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| 358 | /* fFlags */
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| 359 | PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36,
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| 360 | /* fClass */
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| 361 | PDM_DEVREG_CLASS_MISC,
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| 362 | /* cMaxInstances */
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| 363 | 1,
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|---|
| 364 | /* cbInstance */
|
|---|
| 365 | sizeof(LPCState),
|
|---|
| 366 | /* pfnConstruct */
|
|---|
| 367 | lpcConstruct,
|
|---|
| 368 | /* pfnDestruct */
|
|---|
| 369 | NULL,
|
|---|
| 370 | /* pfnRelocate */
|
|---|
| 371 | NULL,
|
|---|
| 372 | /* pfnMemSetup */
|
|---|
| 373 | NULL,
|
|---|
| 374 | /* pfnPowerOn */
|
|---|
| 375 | NULL,
|
|---|
| 376 | /* pfnReset */
|
|---|
| 377 | NULL,
|
|---|
| 378 | /* pfnSuspend */
|
|---|
| 379 | NULL,
|
|---|
| 380 | /* pfnResume */
|
|---|
| 381 | NULL,
|
|---|
| 382 | /* pfnAttach */
|
|---|
| 383 | NULL,
|
|---|
| 384 | /* pfnDetach */
|
|---|
| 385 | NULL,
|
|---|
| 386 | /* pfnQueryInterface. */
|
|---|
| 387 | NULL,
|
|---|
| 388 | /* pfnInitComplete */
|
|---|
| 389 | NULL,
|
|---|
| 390 | /* pfnPowerOff */
|
|---|
| 391 | NULL,
|
|---|
| 392 | /* pfnSoftReset */
|
|---|
| 393 | NULL,
|
|---|
| 394 | /* u32VersionEnd */
|
|---|
| 395 | PDM_DEVREG_VERSION
|
|---|
| 396 | };
|
|---|
| 397 |
|
|---|
| 398 | #endif /* IN_RING3 */
|
|---|
| 399 |
|
|---|
| 400 | #endif /* VBOX_DEVICE_STRUCT_TESTCASE */
|
|---|
