DevPit-i8254.cpp@ 81900

Last change on this file since 81900 was 81900, checked in by vboxsync, 5 years ago
DevPit-i8254: Converted the timer to new handle based interface. Eliminated pPitR3 and friends in the channels. bugref:9218
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1	/* $Id: DevPit-i8254.cpp 81900 2019-11-16 20:10:15Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_PIT
48	#include <VBox/vmm/pdmdev.h>
49	#include <VBox/log.h>
50	#include <VBox/vmm/stam.h>
51	#include <iprt/assert.h>
52	#include <iprt/asm-math.h>
53
54	#ifdef IN_RING3
55	# ifdef RT_OS_LINUX
56	# include <fcntl.h>
57	# include <errno.h>
58	# include <unistd.h>
59	# include <stdio.h>
60	# include <linux/kd.h>
61	# include <linux/input.h>
62	# include <sys/ioctl.h>
63	# endif
64	# include <iprt/alloc.h>
65	# include <iprt/string.h>
66	# include <iprt/uuid.h>
67	#endif /* IN_RING3 */
68
69	#include "VBoxDD.h"
70
71
72	/*********************************************************************************************************************************
73	* Defined Constants And Macros *
74	*********************************************************************************************************************************/
75	/** The PIT frequency. */
76	#define PIT_FREQ 1193182
77
78	#define RW_STATE_LSB 1
79	#define RW_STATE_MSB 2
80	#define RW_STATE_WORD0 3
81	#define RW_STATE_WORD1 4
82
83	/** The current saved state version. */
84	#define PIT_SAVED_STATE_VERSION 4
85	/** The saved state version used by VirtualBox 3.1 and earlier.
86	* This did not include disable by HPET flag. */
87	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
88	/** The saved state version used by VirtualBox 3.0 and earlier.
89	* This did not include the config part. */
90	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
91
92	/** @def FAKE_REFRESH_CLOCK
93	* Define this to flip the 15usec refresh bit on every read.
94	* If not defined, it will be flipped correctly. */
95	/* #define FAKE_REFRESH_CLOCK */
96	#ifdef DOXYGEN_RUNNING
97	# define FAKE_REFRESH_CLOCK
98	#endif
99
100	/** The effective counter mode - if bit 1 is set, bit 2 is ignored. */
101	#define EFFECTIVE_MODE(x) ((x) & ~(((x) & 2) << 1))
102
103
104	/**
105	* Acquires the PIT lock or returns.
106	*/
107	#define DEVPIT_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
108	do { \
109	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (a_rcBusy)); \
110	if (rcLock != VINF_SUCCESS) \
111	return rcLock; \
112	} while (0)
113
114	/**
115	* Releases the PIT lock.
116	*/
117	#define DEVPIT_UNLOCK(a_pDevIns, a_pThis) \
118	do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
119
120
121	/**
122	* Acquires the TM lock and PIT lock, returns on failure.
123	*/
124	#define DEVPIT_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
125	do { \
126	int rcLock = PDMDevHlpTimerLock((a_pDevIns), (a_pThis)->channels[0].hTimer, (a_rcBusy)); \
127	if (rcLock != VINF_SUCCESS) \
128	return rcLock; \
129	rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (a_rcBusy)); \
130	if (rcLock != VINF_SUCCESS) \
131	{ \
132	PDMDevHlpTimerUnlock((a_pDevIns), (a_pThis)->channels[0].hTimer); \
133	return rcLock; \
134	} \
135	} while (0)
136
137	#ifdef IN_RING3
138	/**
139	* Acquires the TM lock and PIT lock, ignores failures.
140	*/
141	# define DEVPIT_R3_LOCK_BOTH(a_pDevIns, a_pThis) \
142	do { \
143	PDMDevHlpTimerLock((a_pDevIns), (a_pThis)->channels[0].hTimer, VERR_IGNORED); \
144	PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
145	} while (0)
146	#endif /* IN_RING3 */
147
148	/**
149	* Releases the PIT lock and TM lock.
150	*/
151	#define DEVPIT_UNLOCK_BOTH(a_pDevIns, a_pThis) \
152	do { \
153	PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); \
154	PDMDevHlpTimerUnlock((a_pDevIns), (a_pThis)->channels[0].hTimer); \
155	} while (0)
156
157
158
159	/*********************************************************************************************************************************
160	* Structures and Typedefs *
161	*********************************************************************************************************************************/
162	/**
163	* The state of one PIT channel.
164	*/
165	typedef struct PITCHANNEL
166	{
167	/** The timer.
168	* @note Only channel 0 has a timer. */
169	TMTIMERHANDLE hTimer;
170	/** The virtual time stamp at the last reload (only used in mode 2 for now). */
171	uint64_t u64ReloadTS;
172	/** The actual time of the next tick.
173	* As apposed to the next_transition_time which contains the correct time of the next tick. */
174	uint64_t u64NextTS;
175
176	/** (count_load_time is only set by PDMDevHlpTimerGet() which returns uint64_t) */
177	uint64_t count_load_time;
178	/* irq handling */
179	int64_t next_transition_time;
180	int32_t irq;
181	/** Number of release log entries. Used to prevent flooding. */
182	uint8_t cRelLogEntries;
183	/** The channel number. */
184	uint8_t iChan;
185	uint8_t abAlignment[2];
186
187	uint32_t count; /* can be 65536 */
188	uint16_t latched_count;
189	uint8_t count_latched;
190	uint8_t status_latched;
191
192	uint8_t status;
193	uint8_t read_state;
194	uint8_t write_state;
195	uint8_t write_latch;
196
197	uint8_t rw_mode;
198	uint8_t mode;
199	uint8_t bcd; /* not supported */
200	uint8_t gate; /* timer start */
201
202	} PITCHANNEL;
203	/** Pointer to the state of one PIT channel. */
204	typedef PITCHANNEL *PPITCHANNEL;
205
206	/** Speaker emulation state. */
207	typedef enum PITSPEAKEREMU
208	{
209	PIT_SPEAKER_EMU_NONE = 0,
210	PIT_SPEAKER_EMU_CONSOLE,
211	PIT_SPEAKER_EMU_EVDEV,
212	PIT_SPEAKER_EMU_TTY
213	} PITSPEAKEREMU;
214
215	/**
216	* The whole PIT state.
217	*/
218	typedef struct PITSTATE
219	{
220	/** Channel state. Must come first? */
221	PITCHANNEL channels[3];
222	/** Speaker data. */
223	int32_t speaker_data_on;
224	#ifdef FAKE_REFRESH_CLOCK
225	/** Refresh dummy. */
226	int32_t dummy_refresh_clock;
227	#else
228	uint32_t Alignment1;
229	#endif
230	/** Config: I/O port base. */
231	RTIOPORT IOPortBaseCfg;
232	/** Config: Speaker enabled. */
233	bool fSpeakerCfg;
234	/** Disconnect PIT from the interrupt controllers if requested by HPET. */
235	bool fDisabledByHpet;
236	/** Config: What to do with speaker activity. */
237	PITSPEAKEREMU enmSpeakerEmu;
238	#ifdef RT_OS_LINUX
239	/** File handle for host speaker functionality. */
240	int hHostSpeaker;
241	int afAlignment2;
242	#endif
243	/** PIT port interface. */
244	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
245	/** Pointer to the device instance. */
246	PPDMDEVINSR3 pDevIns;
247	/** Number of IRQs that's been raised. */
248	STAMCOUNTER StatPITIrq;
249	/** Profiling the timer callback handler. */
250	STAMPROFILEADV StatPITHandler;
251	/** Critical section protecting the state. */
252	PDMCRITSECT CritSect;
253	} PITSTATE;
254	/** Pointer to the PIT device state. */
255	typedef PITSTATE *PPITSTATE;
256
257
258	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
259
260
261	/*********************************************************************************************************************************
262	* Internal Functions *
263	*********************************************************************************************************************************/
264	#ifdef IN_RING3
265	static void pit_irq_timer_update(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan,
266	uint64_t current_time, uint64_t now, bool in_timer);
267	#endif
268
269
270	#ifdef IN_RING3
271	# ifdef RT_OS_LINUX
272	static int pitTryDeviceOpen(const char *pszPath, int flags)
273	{
274	int fd = open(pszPath, flags);
275	if (fd == -1)
276	LogRel(("PIT: speaker: cannot open \"%s\", errno=%d\n", pszPath, errno));
277	else
278	LogRel(("PIT: speaker: opened \"%s\"\n", pszPath));
279	return fd;
280	}
281
282	static int pitTryDeviceOpenSanitizeIoctl(const char *pszPath, int flags)
283	{
284	int fd = open(pszPath, flags);
285	if (fd == -1)
286	LogRel(("PIT: speaker: cannot open \"%s\", errno=%d\n", pszPath, errno));
287	else
288	{
289	int errno_eviocgsnd0 = 0;
290	int errno_kiocsound = 0;
291	if (ioctl(fd, EVIOCGSND(0)) == -1)
292	{
293	errno_eviocgsnd0 = errno;
294	if (ioctl(fd, KIOCSOUND, 1) == -1)
295	errno_kiocsound = errno;
296	else
297	ioctl(fd, KIOCSOUND, 0);
298	}
299	if (errno_eviocgsnd0 && errno_kiocsound)
300	{
301	LogRel(("PIT: speaker: cannot use \"%s\", ioctl failed errno=%d/errno=%d\n", pszPath, errno_eviocgsnd0, errno_kiocsound));
302	close(fd);
303	fd = -1;
304	}
305	else
306	LogRel(("PIT: speaker: opened \"%s\"\n", pszPath));
307	}
308	return fd;
309	}
310	# endif /* RT_OS_LINUX */
311	#endif /* IN_RING3 */
312
313	static int pit_get_count(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan)
314	{
315	uint64_t d;
316	TMTIMERHANDLE hTimer = pThis->channels[0].hTimer;
317	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
318
319	if (EFFECTIVE_MODE(pChan->mode) == 2)
320	{
321	if (pChan->u64NextTS == UINT64_MAX)
322	{
323	d = ASMMultU64ByU32DivByU32(PDMDevHlpTimerGet(pDevIns, hTimer) - pChan->count_load_time,
324	PIT_FREQ, PDMDevHlpTimerGetFreq(pDevIns, hTimer));
325	return pChan->count - (d % pChan->count); /** @todo check this value. */
326	}
327	uint64_t Interval = pChan->u64NextTS - pChan->u64ReloadTS;
328	if (!Interval)
329	return pChan->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
330	d = PDMDevHlpTimerGet(pDevIns, hTimer);
331	d = ASMMultU64ByU32DivByU32(d - pChan->u64ReloadTS, pChan->count, Interval);
332	if (d >= pChan->count)
333	return 1;
334	return pChan->count - d;
335	}
336
337	d = ASMMultU64ByU32DivByU32(PDMDevHlpTimerGet(pDevIns, hTimer) - pChan->count_load_time,
338	PIT_FREQ, PDMDevHlpTimerGetFreq(pDevIns, hTimer));
339	int counter;
340	switch (EFFECTIVE_MODE(pChan->mode))
341	{
342	case 0:
343	case 1:
344	case 4:
345	case 5:
346	counter = (pChan->count - d) & 0xffff;
347	break;
348	case 3:
349	/* XXX: may be incorrect for odd counts */
350	counter = pChan->count - ((2 * d) % pChan->count);
351	break;
352	default:
353	counter = pChan->count - (d % pChan->count);
354	break;
355	}
356	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
357	return counter;
358	}
359
360	/* get pit output bit */
361	static int pit_get_out1(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan, int64_t current_time)
362	{
363	TMTIMERHANDLE hTimer = pThis->channels[0].hTimer;
364	uint64_t d;
365	int out;
366
367	d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, PDMDevHlpTimerGetFreq(pDevIns, hTimer));
368	switch (EFFECTIVE_MODE(pChan->mode))
369	{
370	default:
371	case 0:
372	out = (d >= pChan->count);
373	break;
374	case 1:
375	out = (d < pChan->count);
376	break;
377	case 2:
378	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, pChan->count, (unsigned)(d % pChan->count)));
379	if ((d % pChan->count) == 0 && d != 0)
380	out = 1;
381	else
382	out = 0;
383	break;
384	case 3:
385	out = (d % pChan->count) < ((pChan->count + 1) >> 1);
386	break;
387	case 4:
388	case 5:
389	out = (d != pChan->count);
390	break;
391	}
392	return out;
393	}
394
395
396	static int pit_get_out(PPDMDEVINS pDevIns, PPITSTATE pThis, int channel, int64_t current_time)
397	{
398	PPITCHANNEL pChan = &pThis->channels[channel];
399	return pit_get_out1(pDevIns, pThis, pChan, current_time);
400	}
401
402
403	static int pit_get_gate(PPITSTATE pThis, int channel)
404	{
405	PPITCHANNEL pChan = &pThis->channels[channel];
406	return pChan->gate;
407	}
408
409
410	/* if already latched, do not latch again */
411	static void pit_latch_count(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan)
412	{
413	if (!pChan->count_latched)
414	{
415	pChan->latched_count = pit_get_count(pDevIns, pThis, pChan);
416	pChan->count_latched = pChan->rw_mode;
417	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
418	pChan->latched_count, ASMMultU64ByU32DivByU32(pChan->count - pChan->latched_count, 1000000000, PIT_FREQ),
419	pChan->count, pChan->mode));
420	}
421	}
422
423	#ifdef IN_RING3
424
425	/* val must be 0 or 1 */
426	static void pit_set_gate(PPDMDEVINS pDevIns, PPITSTATE pThis, int channel, int val)
427	{
428	PPITCHANNEL pChan = &pThis->channels[channel];
429	TMTIMERHANDLE hTimer = pThis->channels[0].hTimer;
430
431	Assert((val & 1) == val);
432	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
433
434	switch (EFFECTIVE_MODE(pChan->mode))
435	{
436	default:
437	case 0:
438	case 4:
439	/* XXX: just disable/enable counting */
440	break;
441	case 1:
442	case 5:
443	if (pChan->gate < val)
444	{
445	/* restart counting on rising edge */
446	Log(("pit_set_gate: restarting mode %d\n", pChan->mode));
447	pChan->count_load_time = PDMDevHlpTimerGet(pDevIns, hTimer);
448	pit_irq_timer_update(pDevIns, pThis, pChan, pChan->count_load_time, pChan->count_load_time, false);
449	}
450	break;
451	case 2:
452	case 3:
453	if (pChan->gate < val)
454	{
455	/* restart counting on rising edge */
456	Log(("pit_set_gate: restarting mode %d\n", pChan->mode));
457	pChan->count_load_time = pChan->u64ReloadTS = PDMDevHlpTimerGet(pDevIns, hTimer);
458	pit_irq_timer_update(pDevIns, pThis, pChan, pChan->count_load_time, pChan->count_load_time, false);
459	}
460	/* XXX: disable/enable counting */
461	break;
462	}
463	pChan->gate = val;
464	}
465
466	static void pit_load_count(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan, int val)
467	{
468	TMTIMERHANDLE hTimer = pThis->channels[0].hTimer;
469	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
470
471	if (val == 0)
472	val = 0x10000;
473	pChan->count_load_time = pChan->u64ReloadTS = PDMDevHlpTimerGet(pDevIns, hTimer);
474	pChan->count = val;
475	pit_irq_timer_update(pDevIns, pThis, pChan, pChan->count_load_time, pChan->count_load_time, false);
476
477	/* log the new rate (ch 0 only). */
478	if (pChan->hTimer != NIL_TMTIMERHANDLE /* ch 0 */)
479	{
480	if (pChan->cRelLogEntries < 32)
481	{
482	pChan->cRelLogEntries++;
483	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
484	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
485	}
486	else
487	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
488	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
489	PDMDevHlpTimerSetFrequencyHint(pDevIns, hTimer, PIT_FREQ / pChan->count);
490	}
491	else
492	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
493	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100,
494	pChan - &pThis->channels[0]));
495	}
496
497	/* return -1 if no transition will occur. */
498	static int64_t pit_get_next_transition_time(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan, uint64_t current_time)
499	{
500	TMTIMERHANDLE hTimer = pThis->channels[0].hTimer;
501	uint64_t d, next_time, base;
502	uint32_t period2;
503
504	d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, PDMDevHlpTimerGetFreq(pDevIns, hTimer));
505	switch (EFFECTIVE_MODE(pChan->mode))
506	{
507	default:
508	case 0:
509	case 1:
510	if (d < pChan->count)
511	next_time = pChan->count;
512	else
513	return -1;
514	break;
515
516	/*
517	* Mode 2: The period is 'count' PIT ticks.
518	* When the counter reaches 1 we set the output low (for channel 0 that
519	* means lowering IRQ0). On the next tick, where we should be decrementing
520	* from 1 to 0, the count is loaded and the output goes high (channel 0
521	* means raising IRQ0 again and triggering timer interrupt).
522	*
523	* In VirtualBox we compress the pulse and flip-flop the IRQ line at the
524	* end of the period, which signals an interrupt at the exact same time.
525	*/
526	case 2:
527	base = (d / pChan->count) * pChan->count;
528	#ifndef VBOX /* see above */
529	if ((d - base) == 0 && d != 0)
530	next_time = base + pChan->count - 1;
531	else
532	#endif
533	next_time = base + pChan->count;
534	break;
535	case 3:
536	base = (d / pChan->count) * pChan->count;
537	period2 = ((pChan->count + 1) >> 1);
538	if ((d - base) < period2)
539	next_time = base + period2;
540	else
541	next_time = base + pChan->count;
542	break;
543
544	/* Modes 4 and 5 generate a short pulse at the end of the time delay. This
545	* is similar to mode 2, except modes 4/5 aren't periodic. We use the same
546	* optimization - only use one timer callback and pulse the IRQ.
547	* Note: Tickless Linux kernels use PIT mode 4 with 'nolapic'.
548	*/
549	case 4:
550	case 5:
551	#ifdef VBOX
552	if (d <= pChan->count)
553	next_time = pChan->count;
554	#else
555	if (d < pChan->count)
556	next_time = pChan->count;
557	else if (d == pChan->count)
558	next_time = pChan->count + 1;
559	#endif
560	else
561	return -1;
562	break;
563	}
564
565	/* convert to timer units */
566	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
567	ASMMultU64ByU32DivByU32(next_time, PDMDevHlpTimerGetFreq(pDevIns, hTimer), PIT_FREQ), pChan->mode, pChan->count));
568	next_time = pChan->count_load_time + ASMMultU64ByU32DivByU32(next_time, PDMDevHlpTimerGetFreq(pDevIns, hTimer), PIT_FREQ);
569
570	/* fix potential rounding problems */
571	if (next_time <= current_time)
572	next_time = current_time;
573
574	/* Add one to next_time; if we don't, integer truncation will cause
575	* the algorithm to think that at the end of each period, it'pChan still
576	* within the first one instead of at the beginning of the next one.
577	*/
578	return next_time + 1;
579	}
580
581	static void pit_irq_timer_update(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan,
582	uint64_t current_time, uint64_t now, bool in_timer)
583	{
584	int64_t expire_time;
585	int irq_level;
586	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->channels[0].hTimer));
587
588	if (pChan->hTimer == NIL_TMTIMERHANDLE)
589	return;
590	expire_time = pit_get_next_transition_time(pDevIns, pThis, pChan, current_time);
591	irq_level = pit_get_out1(pDevIns, pThis, pChan, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
592
593	/* If PIT is disabled by HPET - simply disconnect ticks from interrupt controllers,
594	* but do not modify other aspects of device operation.
595	*/
596	if (!pThis->fDisabledByHpet)
597	{
598	switch (EFFECTIVE_MODE(pChan->mode))
599	{
600	case 2:
601	case 4:
602	case 5:
603	/* We just flip-flop the IRQ line to save an extra timer call,
604	* which isn't generally required. However, the pulse is only
605	* generated when running on the timer callback (and thus on
606	* the trailing edge of the output signal pulse).
607	*/
608	if (in_timer)
609	{
610	PDMDevHlpISASetIrq(pDevIns, pChan->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
611	break;
612	}
613	RT_FALL_THRU();
614	default:
615	PDMDevHlpISASetIrq(pDevIns, pChan->irq, irq_level);
616	break;
617	}
618	}
619
620	if (irq_level)
621	{
622	pChan->u64ReloadTS = now;
623	STAM_COUNTER_INC(&pThis->StatPITIrq);
624	}
625
626	if (expire_time != -1)
627	{
628	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
629	pChan->u64NextTS = expire_time;
630	PDMDevHlpTimerSet(pDevIns, pChan->hTimer, pChan->u64NextTS);
631	}
632	else
633	{
634	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", pChan->mode, pChan->count, irq_level));
635	PDMDevHlpTimerStop(pDevIns, pChan->hTimer);
636	pChan->u64NextTS = UINT64_MAX;
637	}
638	pChan->next_transition_time = expire_time;
639	}
640
641	#endif /* IN_RING3 */
642
643
644	/**
645	* @callback_method_impl{FNIOMIOPORTIN}
646	*/
647	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
648	{
649	Log2(("pitIOPortRead: uPort=%#x cb=%x\n", uPort, cb));
650	NOREF(pvUser);
651	uPort &= 3;
652	if (cb != 1 \|\| uPort == 3)
653	{
654	Log(("pitIOPortRead: uPort=%#x cb=%x *pu32=unused!\n", uPort, cb));
655	return VERR_IOM_IOPORT_UNUSED;
656	}
657	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
658
659	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
660	PPITCHANNEL pChan = &pThis->channels[uPort];
661	int ret;
662
663	DEVPIT_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
664	if (pChan->status_latched)
665	{
666	pChan->status_latched = 0;
667	ret = pChan->status;
668	DEVPIT_UNLOCK(pDevIns, pThis);
669	}
670	else if (pChan->count_latched)
671	{
672	switch (pChan->count_latched)
673	{
674	default:
675	case RW_STATE_LSB:
676	ret = pChan->latched_count & 0xff;
677	pChan->count_latched = 0;
678	break;
679	case RW_STATE_MSB:
680	ret = pChan->latched_count >> 8;
681	pChan->count_latched = 0;
682	break;
683	case RW_STATE_WORD0:
684	ret = pChan->latched_count & 0xff;
685	pChan->count_latched = RW_STATE_MSB;
686	break;
687	}
688	DEVPIT_UNLOCK(pDevIns, pThis);
689	}
690	else
691	{
692	DEVPIT_UNLOCK(pDevIns, pThis);
693	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
694	int count;
695	switch (pChan->read_state)
696	{
697	default:
698	case RW_STATE_LSB:
699	count = pit_get_count(pDevIns, pThis, pChan);
700	ret = count & 0xff;
701	break;
702	case RW_STATE_MSB:
703	count = pit_get_count(pDevIns, pThis, pChan);
704	ret = (count >> 8) & 0xff;
705	break;
706	case RW_STATE_WORD0:
707	count = pit_get_count(pDevIns, pThis, pChan);
708	ret = count & 0xff;
709	pChan->read_state = RW_STATE_WORD1;
710	break;
711	case RW_STATE_WORD1:
712	count = pit_get_count(pDevIns, pThis, pChan);
713	ret = (count >> 8) & 0xff;
714	pChan->read_state = RW_STATE_WORD0;
715	break;
716	}
717	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
718	}
719
720	*pu32 = ret;
721	Log2(("pitIOPortRead: uPort=%#x cb=%x pu32=%#04x\n", uPort, cb, pu32));
722	return VINF_SUCCESS;
723	}
724
725
726	/**
727	* @callback_method_impl{FNIOMIOPORTOUT}
728	*/
729	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
730	{
731	Log2(("pitIOPortWrite: uPort=%#x cb=%x u32=%#04x\n", uPort, cb, u32));
732	NOREF(pvUser);
733	if (cb != 1)
734	return VINF_SUCCESS;
735
736	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
737	uPort &= 3;
738	if (uPort == 3)
739	{
740	/*
741	* Port 43h - Mode/Command Register.
742	* 7 6 5 4 3 2 1 0
743	* * * . . . . . . Select channel: 0 0 = Channel 0
744	* 0 1 = Channel 1
745	* 1 0 = Channel 2
746	* 1 1 = Read-back command (8254 only)
747	* (Illegal on 8253)
748	* (Illegal on PS/2 {JAM})
749	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
750	* 0 1 = Access mode: lobyte only
751	* 1 0 = Access mode: hibyte only
752	* 1 1 = Access mode: lobyte/hibyte
753	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
754	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
755	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
756	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
757	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
758	*/
759	unsigned channel = (u32 >> 6) & 0x3;
760	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
761	if (channel == 3)
762	{
763	/* read-back command */
764	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
765	for (channel = 0; channel < RT_ELEMENTS(pThis->channels); channel++)
766	{
767	PPITCHANNEL pChan = &pThis->channels[channel];
768	if (u32 & (2 << channel))
769	{
770	if (!(u32 & 0x20))
771	pit_latch_count(pDevIns, pThis, pChan);
772	if (!(u32 & 0x10) && !pChan->status_latched)
773	{
774	/* status latch */
775	/* XXX: add BCD and null count */
776	pChan->status = (pit_get_out1(pDevIns, pThis, pChan,
777	PDMDevHlpTimerGet(pDevIns, pThis->channels[0].hTimer)) << 7)
778	\| (pChan->rw_mode << 4)
779	\| (pChan->mode << 1)
780	\| pChan->bcd;
781	pChan->status_latched = 1;
782	}
783	}
784	}
785	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
786	}
787	else
788	{
789	PPITCHANNEL pChan = &pThis->channels[channel];
790	unsigned access = (u32 >> 4) & 3;
791	if (access == 0)
792	{
793	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
794	pit_latch_count(pDevIns, pThis, pChan);
795	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
796	}
797	else
798	{
799	DEVPIT_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
800	pChan->rw_mode = access;
801	pChan->read_state = access;
802	pChan->write_state = access;
803
804	pChan->mode = (u32 >> 1) & 7;
805	pChan->bcd = u32 & 1;
806	/* XXX: update irq timer ? */
807	DEVPIT_UNLOCK(pDevIns, pThis);
808	}
809	}
810	}
811	else
812	{
813	#ifndef IN_RING3
814	/** @todo There is no reason not to do this in all contexts these
815	* days... */
816	return VINF_IOM_R3_IOPORT_WRITE;
817	#else /* IN_RING3 */
818	/*
819	* Port 40-42h - Channel Data Ports.
820	*/
821	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
822	PPITCHANNEL pChan = &pThis->channels[uPort];
823	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
824	switch (pChan->write_state)
825	{
826	default:
827	case RW_STATE_LSB:
828	pit_load_count(pDevIns, pThis, pChan, u32);
829	break;
830	case RW_STATE_MSB:
831	pit_load_count(pDevIns, pThis, pChan, u32 << 8);
832	break;
833	case RW_STATE_WORD0:
834	pChan->write_latch = u32;
835	pChan->write_state = RW_STATE_WORD1;
836	break;
837	case RW_STATE_WORD1:
838	pit_load_count(pDevIns, pThis, pChan, pChan->write_latch \| (u32 << 8));
839	pChan->write_state = RW_STATE_WORD0;
840	break;
841	}
842	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
843	#endif /* !IN_RING3 */
844	}
845	return VINF_SUCCESS;
846	}
847
848
849	/**
850	* @callback_method_impl{FNIOMIOPORTIN, Speaker}
851	*/
852	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
853	{
854	RT_NOREF(pvUser, uPort);
855	if (cb == 1)
856	{
857	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
858	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
859
860	const uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->channels[0].hTimer);
861	Assert(PDMDevHlpTimerGetFreq(pDevIns, pThis->channels[0].hTimer) == 1000000000); /* lazy bird. */
862
863	/* bit 6,7 Parity error stuff. */
864	/* bit 5 - mirrors timer 2 output condition. */
865	const int fOut = pit_get_out(pDevIns, pThis, 2, u64Now);
866	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 u-op Chan.
867	ASSUMES ns timer freq, see assertion above. */
868	#ifndef FAKE_REFRESH_CLOCK
869	const int fRefresh = (u64Now / 15085) & 1;
870	#else
871	pThis->dummy_refresh_clock ^= 1;
872	const int fRefresh = pThis->dummy_refresh_clock;
873	#endif
874	/* bit 2,3 NMI / parity status stuff. */
875	/* bit 1 - speaker data status */
876	const int fSpeakerStatus = pThis->speaker_data_on;
877	/* bit 0 - timer 2 clock gate to speaker status. */
878	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
879
880	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
881
882	*pu32 = fTimer2GateStatus
883	\| (fSpeakerStatus << 1)
884	\| (fRefresh << 4)
885	\| (fOut << 5);
886	Log(("pitIOPortSpeakerRead: uPort=%#x cb=%x pu32=%#x\n", uPort, cb, pu32));
887	return VINF_SUCCESS;
888	}
889	Log(("pitIOPortSpeakerRead: uPort=%#x cb=%x *pu32=unused!\n", uPort, cb));
890	return VERR_IOM_IOPORT_UNUSED;
891	}
892
893	#ifdef IN_RING3
894
895	/**
896	* @callback_method_impl{FNIOMIOPORTOUT, Speaker}
897	*/
898	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
899	{
900	RT_NOREF(pvUser, uPort);
901	if (cb == 1)
902	{
903	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
904	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VERR_IGNORED);
905
906	pThis->speaker_data_on = (u32 >> 1) & 1;
907	pit_set_gate(pDevIns, pThis, 2, u32 & 1);
908
909	/** @todo r=klaus move this to a (system-specific) driver, which can
910	* abstract the details, and if necessary create a thread to minimize
911	* impact on VM execution. */
912	# ifdef RT_OS_LINUX
913	if (pThis->enmSpeakerEmu != PIT_SPEAKER_EMU_NONE)
914	{
915	PPITCHANNEL pChan = &pThis->channels[2];
916	if (pThis->speaker_data_on)
917	{
918	Log2Func(("starting beep freq=%d\n", PIT_FREQ / pChan->count));
919	switch (pThis->enmSpeakerEmu)
920	{
921	case PIT_SPEAKER_EMU_CONSOLE:
922	{
923	int res;
924	res = ioctl(pThis->hHostSpeaker, KIOCSOUND, pChan->count);
925	if (res == -1)
926	{
927	LogRel(("PIT: speaker: ioctl failed errno=%d, disabling emulation\n", errno));
928	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
929	}
930	break;
931	}
932	case PIT_SPEAKER_EMU_EVDEV:
933	{
934	struct input_event e;
935	e.type = EV_SND;
936	e.code = SND_TONE;
937	e.value = PIT_FREQ / pChan->count;
938	int res = write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
939	NOREF(res);
940	break;
941	}
942	case PIT_SPEAKER_EMU_TTY:
943	{
944	int res = write(pThis->hHostSpeaker, "\a", 1);
945	NOREF(res);
946	break;
947	}
948	case PIT_SPEAKER_EMU_NONE:
949	break;
950	default:
951	Log2Func(("unknown speaker emulation %d, disabling emulation\n", pThis->enmSpeakerEmu));
952	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
953	}
954	}
955	else
956	{
957	Log2Func(("stopping beep\n"));
958	switch (pThis->enmSpeakerEmu)
959	{
960	case PIT_SPEAKER_EMU_CONSOLE:
961	/* No error checking here. The Linux device driver
962	* implementation considers it an error (errno=22,
963	* EINVAL) to stop sound if it hasn't been started.
964	* Of course we could detect this by checking only
965	* for enabled->disabled transitions and ignoring
966	* disabled->disabled ones, but it's not worth the
967	* effort. */
968	ioctl(pThis->hHostSpeaker, KIOCSOUND, 0);
969	break;
970	case PIT_SPEAKER_EMU_EVDEV:
971	{
972	struct input_event e;
973	e.type = EV_SND;
974	e.code = SND_TONE;
975	e.value = 0;
976	int res = write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
977	NOREF(res);
978	break;
979	}
980	case PIT_SPEAKER_EMU_TTY:
981	break;
982	case PIT_SPEAKER_EMU_NONE:
983	break;
984	default:
985	Log2Func(("unknown speaker emulation %d, disabling emulation\n", pThis->enmSpeakerEmu));
986	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
987	}
988	}
989	}
990	# endif /* RT_OS_LINUX */
991
992	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
993	}
994	Log(("pitIOPortSpeakerWrite: uPort=%#x cb=%x u32=%#x\n", uPort, cb, u32));
995	return VINF_SUCCESS;
996	}
997
998
999	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
1000
1001	/**
1002	* @callback_method_impl{FNSSMDEVLIVEEXEC}
1003	*/
1004	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1005	{
1006	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1007	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1008	RT_NOREF(uPass);
1009	pHlp->pfnSSMPutIOPort(pSSM, pThis->IOPortBaseCfg);
1010	pHlp->pfnSSMPutU8( pSSM, pThis->channels[0].irq);
1011	pHlp->pfnSSMPutBool( pSSM, pThis->fSpeakerCfg);
1012	return VINF_SSM_DONT_CALL_AGAIN;
1013	}
1014
1015
1016	/**
1017	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1018	*/
1019	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1020	{
1021	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1022	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1023	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1024
1025	/* The config. */
1026	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
1027
1028	/* The state. */
1029	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1030	{
1031	PPITCHANNEL pChan = &pThis->channels[i];
1032	pHlp->pfnSSMPutU32(pSSM, pChan->count);
1033	pHlp->pfnSSMPutU16(pSSM, pChan->latched_count);
1034	pHlp->pfnSSMPutU8(pSSM, pChan->count_latched);
1035	pHlp->pfnSSMPutU8(pSSM, pChan->status_latched);
1036	pHlp->pfnSSMPutU8(pSSM, pChan->status);
1037	pHlp->pfnSSMPutU8(pSSM, pChan->read_state);
1038	pHlp->pfnSSMPutU8(pSSM, pChan->write_state);
1039	pHlp->pfnSSMPutU8(pSSM, pChan->write_latch);
1040	pHlp->pfnSSMPutU8(pSSM, pChan->rw_mode);
1041	pHlp->pfnSSMPutU8(pSSM, pChan->mode);
1042	pHlp->pfnSSMPutU8(pSSM, pChan->bcd);
1043	pHlp->pfnSSMPutU8(pSSM, pChan->gate);
1044	pHlp->pfnSSMPutU64(pSSM, pChan->count_load_time);
1045	pHlp->pfnSSMPutU64(pSSM, pChan->u64NextTS);
1046	pHlp->pfnSSMPutU64(pSSM, pChan->u64ReloadTS);
1047	pHlp->pfnSSMPutS64(pSSM, pChan->next_transition_time);
1048	if (pChan->hTimer)
1049	PDMDevHlpTimerSave(pDevIns, pChan->hTimer, pSSM);
1050	}
1051
1052	pHlp->pfnSSMPutS32(pSSM, pThis->speaker_data_on);
1053	#ifdef FAKE_REFRESH_CLOCK
1054	pHlp->pfnSSMPutS32(pSSM, pThis->dummy_refresh_clock);
1055	#else
1056	pHlp->pfnSSMPutS32(pSSM, 0);
1057	#endif
1058
1059	pHlp->pfnSSMPutBool(pSSM, pThis->fDisabledByHpet);
1060
1061	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1062	return VINF_SUCCESS;
1063	}
1064
1065
1066	/**
1067	* @callback_method_impl{FNSSMDEVLOADEXEC}
1068	*/
1069	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1070	{
1071	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1072	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1073	int rc;
1074
1075	if ( uVersion != PIT_SAVED_STATE_VERSION
1076	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
1077	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
1078	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1079
1080	/* The config. */
1081	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
1082	{
1083	RTIOPORT IOPortBaseCfg;
1084	rc = pHlp->pfnSSMGetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
1085	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
1086	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
1087	IOPortBaseCfg, pThis->IOPortBaseCfg);
1088
1089	uint8_t u8Irq;
1090	rc = pHlp->pfnSSMGetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
1091	if (u8Irq != pThis->channels[0].irq)
1092	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
1093	u8Irq, pThis->channels[0].irq);
1094
1095	bool fSpeakerCfg;
1096	rc = pHlp->pfnSSMGetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
1097	if (fSpeakerCfg != pThis->fSpeakerCfg)
1098	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
1099	fSpeakerCfg, pThis->fSpeakerCfg);
1100	}
1101
1102	if (uPass != SSM_PASS_FINAL)
1103	return VINF_SUCCESS;
1104
1105	/* The state. */
1106	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1107	{
1108	PPITCHANNEL pChan = &pThis->channels[i];
1109	pHlp->pfnSSMGetU32(pSSM, &pChan->count);
1110	pHlp->pfnSSMGetU16(pSSM, &pChan->latched_count);
1111	pHlp->pfnSSMGetU8(pSSM, &pChan->count_latched);
1112	pHlp->pfnSSMGetU8(pSSM, &pChan->status_latched);
1113	pHlp->pfnSSMGetU8(pSSM, &pChan->status);
1114	pHlp->pfnSSMGetU8(pSSM, &pChan->read_state);
1115	pHlp->pfnSSMGetU8(pSSM, &pChan->write_state);
1116	pHlp->pfnSSMGetU8(pSSM, &pChan->write_latch);
1117	pHlp->pfnSSMGetU8(pSSM, &pChan->rw_mode);
1118	pHlp->pfnSSMGetU8(pSSM, &pChan->mode);
1119	pHlp->pfnSSMGetU8(pSSM, &pChan->bcd);
1120	pHlp->pfnSSMGetU8(pSSM, &pChan->gate);
1121	pHlp->pfnSSMGetU64(pSSM, &pChan->count_load_time);
1122	pHlp->pfnSSMGetU64(pSSM, &pChan->u64NextTS);
1123	pHlp->pfnSSMGetU64(pSSM, &pChan->u64ReloadTS);
1124	pHlp->pfnSSMGetS64(pSSM, &pChan->next_transition_time);
1125	if (pChan->hTimer)
1126	{
1127	PDMDevHlpTimerLoad(pDevIns, pChan->hTimer, pSSM);
1128	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
1129	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100, i));
1130	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1131	PDMDevHlpTimerSetFrequencyHint(pDevIns, pChan->hTimer, PIT_FREQ / pChan->count);
1132	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1133	}
1134	pThis->channels[i].cRelLogEntries = 0;
1135	}
1136
1137	pHlp->pfnSSMGetS32(pSSM, &pThis->speaker_data_on);
1138	#ifdef FAKE_REFRESH_CLOCK
1139	pHlp->pfnSSMGetS32(pSSM, &pThis->dummy_refresh_clock);
1140	#else
1141	int32_t u32Dummy;
1142	pHlp->pfnSSMGetS32(pSSM, &u32Dummy);
1143	#endif
1144	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
1145	pHlp->pfnSSMGetBool(pSSM, &pThis->fDisabledByHpet);
1146
1147	return VINF_SUCCESS;
1148	}
1149
1150
1151	/* -=-=-=-=-=- Timer -=-=-=-=-=- */
1152
1153	/**
1154	* @callback_method_impl{FNTMTIMERDEV}
1155	* @param pvUser Pointer to the PIT channel state.
1156	*/
1157	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1158	{
1159	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1160	PPITCHANNEL pChan = (PPITCHANNEL)pvUser;
1161	RT_NOREF(pTimer);
1162	STAM_PROFILE_ADV_START(&pThis->StatPITHandler, a);
1163
1164	Log(("pitTimer\n"));
1165	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1166	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pChan->hTimer));
1167
1168	pit_irq_timer_update(pDevIns, pThis, pChan, pChan->next_transition_time, PDMDevHlpTimerGet(pDevIns, pChan->hTimer), true);
1169
1170	STAM_PROFILE_ADV_STOP(&pThis->StatPITHandler, a);
1171	}
1172
1173
1174	/* -=-=-=-=-=- Debug Info -=-=-=-=-=- */
1175
1176	/**
1177	* @callback_method_impl{FNDBGFHANDLERDEV}
1178	*/
1179	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1180	{
1181	RT_NOREF(pszArgs);
1182	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1183	unsigned i;
1184	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1185	{
1186	const PITCHANNEL *pChan = &pThis->channels[i];
1187
1188	pHlp->pfnPrintf(pHlp,
1189	"PIT (i8254) channel %d status: irq=%#x\n"
1190	" count=%08x" " latched_count=%04x count_latched=%02x\n"
1191	" status=%02x status_latched=%02x read_state=%02x\n"
1192	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
1193	" mode=%02x bcd=%02x gate=%02x\n"
1194	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
1195	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
1196	,
1197	i, pChan->irq,
1198	pChan->count, pChan->latched_count, pChan->count_latched,
1199	pChan->status, pChan->status_latched, pChan->read_state,
1200	pChan->write_state, pChan->write_latch, pChan->rw_mode,
1201	pChan->mode, pChan->bcd, pChan->gate,
1202	pChan->count_load_time, pChan->next_transition_time,
1203	pChan->u64ReloadTS, pChan->u64NextTS);
1204	}
1205	#ifdef FAKE_REFRESH_CLOCK
1206	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
1207	pThis->speaker_data_on, pThis->dummy_refresh_clock);
1208	#else
1209	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
1210	#endif
1211	if (pThis->fDisabledByHpet)
1212	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
1213	}
1214
1215
1216	/* -=-=-=-=-=- IHpetLegacyNotify -=-=-=-=-=- */
1217
1218	/**
1219	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
1220	*/
1221	static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
1222	{
1223	PPITSTATE pThis = RT_FROM_MEMBER(pInterface, PITSTATE, IHpetLegacyNotify);
1224	PPDMDEVINS pDevIns = pThis->pDevIns;
1225	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1226
1227	pThis->fDisabledByHpet = fActivated;
1228
1229	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1230	}
1231
1232
1233	/* -=-=-=-=-=- PDMDEVINS::IBase -=-=-=-=-=- */
1234
1235	/**
1236	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1237	*/
1238	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
1239	{
1240	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
1241	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1242	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
1243	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
1244	return NULL;
1245	}
1246
1247
1248	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1249
1250	/**
1251	* @interface_method_impl{PDMDEVREG,pfnReset}
1252	*/
1253	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
1254	{
1255	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1256	LogFlow(("pitReset: \n"));
1257
1258	DEVPIT_R3_LOCK_BOTH(pDevIns, pThis);
1259
1260	pThis->fDisabledByHpet = false;
1261
1262	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1263	{
1264	PPITCHANNEL pChan = &pThis->channels[i];
1265
1266	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1267	pChan->latched_count = 0;
1268	pChan->count_latched = 0;
1269	pChan->status_latched = 0;
1270	pChan->status = 0;
1271	pChan->read_state = 0;
1272	pChan->write_state = 0;
1273	pChan->write_latch = 0;
1274	pChan->rw_mode = 0;
1275	pChan->bcd = 0;
1276	#endif
1277	pChan->u64NextTS = UINT64_MAX;
1278	pChan->cRelLogEntries = 0;
1279	pChan->mode = 3;
1280	pChan->gate = (i != 2);
1281	pit_load_count(pDevIns, pThis, pChan, 0);
1282	}
1283
1284	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
1285	}
1286
1287
1288	/**
1289	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1290	*/
1291	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1292	{
1293	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1294	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1295	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1296	int rc;
1297	uint8_t u8Irq;
1298	uint16_t u16Base;
1299	bool fSpeaker;
1300	unsigned i;
1301	Assert(iInstance == 0);
1302
1303	/*
1304	* Validate and read the configuration.
1305	*/
1306	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Irq\|Base\|SpeakerEnabled\|PassthroughSpeaker\|PassthroughSpeakerDevice", "");
1307
1308	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Irq", &u8Irq, 0);
1309	if (RT_FAILURE(rc))
1310	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1311
1312	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Base", &u16Base, 0x40);
1313	if (RT_FAILURE(rc))
1314	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1315
1316	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1317	if (RT_FAILURE(rc))
1318	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1319
1320	uint8_t uPassthroughSpeaker;
1321	char *pszPassthroughSpeakerDevice = NULL;
1322	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "PassthroughSpeaker", &uPassthroughSpeaker, 0);
1323	if (RT_FAILURE(rc))
1324	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: failed to read PassthroughSpeaker as uint8_t"));
1325	if (uPassthroughSpeaker)
1326	{
1327	rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "PassthroughSpeakerDevice", &pszPassthroughSpeakerDevice, NULL);
1328	if (RT_FAILURE(rc))
1329	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: failed to read PassthroughSpeakerDevice as string"));
1330	}
1331
1332	/*
1333	* Init the data.
1334	*/
1335	pThis->pDevIns = pDevIns;
1336	pThis->IOPortBaseCfg = u16Base;
1337	pThis->fSpeakerCfg = fSpeaker;
1338	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
1339	if (uPassthroughSpeaker)
1340	{
1341	/** @todo r=klaus move this to a (system-specific) driver */
1342	#ifdef RT_OS_LINUX
1343	int fd = -1;
1344	if ((uPassthroughSpeaker == 1 \|\| uPassthroughSpeaker == 100) && fd == -1)
1345	fd = pitTryDeviceOpenSanitizeIoctl("/dev/input/by-path/platform-pcspkr-event-spkr", O_WRONLY);
1346	if ((uPassthroughSpeaker == 2 \|\| uPassthroughSpeaker == 100) && fd == -1)
1347	fd = pitTryDeviceOpenSanitizeIoctl("/dev/tty", O_WRONLY);
1348	if ((uPassthroughSpeaker == 3 \|\| uPassthroughSpeaker == 100) && fd == -1)
1349	{
1350	fd = pitTryDeviceOpenSanitizeIoctl("/dev/tty0", O_WRONLY);
1351	if (fd == -1)
1352	fd = pitTryDeviceOpenSanitizeIoctl("/dev/vc/0", O_WRONLY);
1353	}
1354	if ((uPassthroughSpeaker == 9 \|\| uPassthroughSpeaker == 100) && pszPassthroughSpeakerDevice && fd == -1)
1355	fd = pitTryDeviceOpenSanitizeIoctl(pszPassthroughSpeakerDevice, O_WRONLY);
1356	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE && fd != -1)
1357	{
1358	pThis->hHostSpeaker = fd;
1359	if (ioctl(fd, EVIOCGSND(0)) != -1)
1360	{
1361	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_EVDEV;
1362	LogRel(("PIT: speaker: emulation mode evdev\n"));
1363	}
1364	else
1365	{
1366	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_CONSOLE;
1367	LogRel(("PIT: speaker: emulation mode console\n"));
1368	}
1369	}
1370	if ((uPassthroughSpeaker == 70 \|\| uPassthroughSpeaker == 100) && fd == -1)
1371	fd = pitTryDeviceOpen("/dev/tty", O_WRONLY);
1372	if ((uPassthroughSpeaker == 79 \|\| uPassthroughSpeaker == 100) && pszPassthroughSpeakerDevice && fd == -1)
1373	fd = pitTryDeviceOpen(pszPassthroughSpeakerDevice, O_WRONLY);
1374	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE && fd != -1)
1375	{
1376	pThis->hHostSpeaker = fd;
1377	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_TTY;
1378	LogRel(("PIT: speaker: emulation mode tty\n"));
1379	}
1380	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE)
1381	{
1382	Assert(fd == -1);
1383	LogRel(("PIT: speaker: no emulation possible\n"));
1384	}
1385	#else
1386	LogRel(("PIT: speaker: emulation deactivated\n"));
1387	#endif
1388	if (pszPassthroughSpeakerDevice)
1389	{
1390	PDMDevHlpMMHeapFree(pDevIns, pszPassthroughSpeakerDevice);
1391	pszPassthroughSpeakerDevice = NULL;
1392	}
1393	}
1394	pThis->channels[0].irq = u8Irq;
1395	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1396	{
1397	pThis->channels[i].hTimer = NIL_TMTIMERHANDLE;
1398	pThis->channels[i].iChan = i;
1399	}
1400
1401	/*
1402	* Interfaces
1403	*/
1404	/* IBase */
1405	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1406	/* IHpetLegacyNotify */
1407	pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1408
1409	/*
1410	* We do our own locking. This must be done before creating timers.
1411	*/
1412	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "pit#%u", iInstance);
1413	AssertRCReturn(rc, rc);
1414
1415	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1416	AssertRCReturn(rc, rc);
1417
1418	/*
1419	* Create the timer, make it take our critsect.
1420	*/
1421	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1422	TMTIMER_FLAGS_NO_CRIT_SECT, "i8254 Programmable Interval Timer", &pThis->channels[0].hTimer);
1423	AssertRCReturn(rc, rc);
1424	rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->channels[0].hTimer, &pThis->CritSect);
1425	AssertRCReturn(rc, rc);
1426
1427	/*
1428	* Register I/O ports.
1429	*/
1430	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1431	if (RT_FAILURE(rc))
1432	return rc;
1433	if (pDevIns->fRCEnabled)
1434	{
1435	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1436	if (RT_FAILURE(rc))
1437	return rc;
1438	}
1439	if (pDevIns->fR0Enabled)
1440	{
1441	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1442	if (RT_FAILURE(rc))
1443	return rc;
1444	}
1445
1446	if (fSpeaker)
1447	{
1448	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1449	if (RT_FAILURE(rc))
1450	return rc;
1451	if (pDevIns->fRCEnabled)
1452	{
1453	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1454	if (RT_FAILURE(rc))
1455	return rc;
1456	}
1457	}
1458
1459	/*
1460	* Saved state.
1461	*/
1462	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1463	if (RT_FAILURE(rc))
1464	return rc;
1465
1466	/*
1467	* Initialize the device state.
1468	*/
1469	pitReset(pDevIns);
1470
1471	/*
1472	* Register statistics and debug info.
1473	*/
1474	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1475	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1476
1477	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1478
1479	return VINF_SUCCESS;
1480	}
1481
1482	#endif /* IN_RING3 */
1483
1484	/**
1485	* The device registration structure.
1486	*/
1487	const PDMDEVREG g_DeviceI8254 =
1488	{
1489	/* .u32Version = */ PDM_DEVREG_VERSION,
1490	/* .uReserved0 = */ 0,
1491	/* .szName = */ "i8254",
1492	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ,
1493	/* .fClass = */ PDM_DEVREG_CLASS_PIT,
1494	/* .cMaxInstances = */ 1,
1495	/* .uSharedVersion = */ 42,
1496	/* .cbInstanceShared = */ sizeof(PITSTATE),
1497	/* .cbInstanceCC = */ 0,
1498	/* .cbInstanceRC = */ 0,
1499	/* .cMaxPciDevices = */ 0,
1500	/* .cMaxMsixVectors = */ 0,
1501	/* .pszDescription = */ "Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1502	#if defined(IN_RING3)
1503	/* .pszRCMod = */ "VBoxDDRC.rc",
1504	/* .pszR0Mod = */ "VBoxDDR0.r0",
1505	/* .pfnConstruct = */ pitConstruct,
1506	/* .pfnDestruct = */ NULL,
1507	/* .pfnRelocate = */ NULL,
1508	/* .pfnMemSetup = */ NULL,
1509	/* .pfnPowerOn = */ NULL,
1510	/* .pfnReset = */ pitReset,
1511	/* .pfnSuspend = */ NULL,
1512	/* .pfnResume = */ NULL,
1513	/* .pfnAttach = */ NULL,
1514	/* .pfnDetach = */ NULL,
1515	/* .pfnQueryInterface = */ NULL,
1516	/* .pfnInitComplete = */ NULL,
1517	/* .pfnPowerOff = */ NULL,
1518	/* .pfnSoftReset = */ NULL,
1519	/* .pfnReserved0 = */ NULL,
1520	/* .pfnReserved1 = */ NULL,
1521	/* .pfnReserved2 = */ NULL,
1522	/* .pfnReserved3 = */ NULL,
1523	/* .pfnReserved4 = */ NULL,
1524	/* .pfnReserved5 = */ NULL,
1525	/* .pfnReserved6 = */ NULL,
1526	/* .pfnReserved7 = */ NULL,
1527	#elif defined(IN_RING0)
1528	/* .pfnEarlyConstruct = */ NULL,
1529	/* .pfnConstruct = */ NULL,
1530	/* .pfnDestruct = */ NULL,
1531	/* .pfnFinalDestruct = */ NULL,
1532	/* .pfnRequest = */ NULL,
1533	/* .pfnReserved0 = */ NULL,
1534	/* .pfnReserved1 = */ NULL,
1535	/* .pfnReserved2 = */ NULL,
1536	/* .pfnReserved3 = */ NULL,
1537	/* .pfnReserved4 = */ NULL,
1538	/* .pfnReserved5 = */ NULL,
1539	/* .pfnReserved6 = */ NULL,
1540	/* .pfnReserved7 = */ NULL,
1541	#elif defined(IN_RC)
1542	/* .pfnConstruct = */ NULL,
1543	/* .pfnReserved0 = */ NULL,
1544	/* .pfnReserved1 = */ NULL,
1545	/* .pfnReserved2 = */ NULL,
1546	/* .pfnReserved3 = */ NULL,
1547	/* .pfnReserved4 = */ NULL,
1548	/* .pfnReserved5 = */ NULL,
1549	/* .pfnReserved6 = */ NULL,
1550	/* .pfnReserved7 = */ NULL,
1551	#else
1552	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1553	#endif
1554	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1555	};
1556
1557	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 81900

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