VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 106757

Last change on this file since 106757 was 106754, checked in by vboxsync, 3 months ago

Disassembler: Decode SIMD ldnp/stnp (no allocate register pair) instructions, bugref:10394
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File size: 10.7 KB
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1/* $Id: DisasmInternal-armv8.h 106754 2024-10-28 14:31:35Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseImmZero,
58 kDisParmParseGprZr,
59 kDisParmParseGprZr32,
60 kDisParmParseGprZr64,
61 kDisParmParseGprSp,
62 kDisParmParseGprOff,
63 kDisParmParseAddrGprSp,
64 kDisParmParseRegFixed31,
65 kDisParmParseImmsImmrN,
66 kDisParmParseHw,
67 kDisParmParseCond,
68 kDisParmParsePState,
69 kDisParmParseCRnCRm,
70 kDisParmParseSysReg,
71 kDisParmParseSh12,
72 kDisParmParseImmTbz,
73 kDisParmParseShift,
74 kDisParmParseShiftAmount,
75 kDisParmParseImmMemOff,
76 kDisParmParseSImmMemOff,
77 kDisParmParseSImmMemOffUnscaled,
78 kDisParmParseOption,
79 kDisParmParseS,
80 kDisParmParseSetPreIndexed,
81 kDisParmParseSetPostIndexed,
82 kDisParmParseFpType,
83 kDisParmParseFpReg,
84 kDisParmParseFpScale,
85 kDisParmParseFpFixupFCvt,
86 kDisParmParseSimdRegSize,
87 kDisParmParseSimdRegSize32,
88 kDisParmParseSimdRegSize64,
89 kDisParmParseSimdRegSize128,
90 kDisParmParseSimdRegScalar,
91 kDisParmParseImmHImmB,
92 kDisParmParseSf,
93 kDisParmParseImmX16,
94 kDisParmParseMax
95} DISPARMPARSEIDX;
96/** @} */
97
98
99/**
100 * Decoder step.
101 */
102typedef struct DISARMV8INSNPARAM
103{
104 /** The parser to use for the decode step. */
105 DISPARMPARSEIDX idxParse;
106 /** Bit index at which the field starts. */
107 uint8_t idxBitStart;
108 /** Size of the bit field. */
109 uint8_t cBits;
110 /** The parameter this decoder param contributes to. */
111 uint8_t idxParam;
112} DISARMV8INSNPARAM;
113typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
114typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
115
116#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
117#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
118 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
119
120#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
121
122
123/**
124 * Opcode structure.
125 */
126typedef struct DISARMV8OPCODE
127{
128 /** The value of the fixed bits of the instruction. */
129 uint32_t fValue;
130 /** Special flags for the opcode. */
131 uint32_t fFlags;
132 /** Pointer to an alternative decoder overriding the default one for the instruction class. */
133 PCDISARMV8INSNPARAM paDecode;
134 /** The generic opcode structure. */
135 DISOPCODE Opc;
136} DISARMV8OPCODE;
137/** Pointer to a const opcode. */
138typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
139
140
141/**
142 * Opcode decode index.
143 */
144typedef enum DISARMV8OPCDECODE
145{
146 kDisArmV8OpcDecodeNop = 0,
147 kDisArmV8OpcDecodeLookup,
148 kDisArmV8OpcDecodeCollate,
149 kDisArmV8OpcDecodeMax
150} DISARMV8OPCDECODE;
151
152
153/**
154 * Decoder stage type.
155 */
156typedef enum kDisArmV8DecodeType
157{
158 kDisArmV8DecodeType_Invalid = 0,
159 kDisArmV8DecodeType_Map,
160 kDisArmV8DecodeType_Table,
161 kDisArmV8DecodeType_InsnClass,
162 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
163} kDisArmV8DecodeType;
164
165
166/**
167 * Decode header.
168 */
169typedef struct DISARMV8DECODEHDR
170{
171 /** Next stage decoding type. */
172 kDisArmV8DecodeType enmDecodeType;
173 /** Number of entries in the next decoder stage or
174 * opcodes in the instruction class. */
175 uint32_t cDecode;
176} DISARMV8DECODEHDR;
177/** Pointer to a decode header. */
178typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
179/** Pointer to a const decode header. */
180typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
181typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
182
183
184/**
185 * Instruction class descriptor.
186 */
187typedef struct DISARMV8INSNCLASS
188{
189 /** Decoder header. */
190 DISARMV8DECODEHDR Hdr;
191 /** Pointer to the arry of opcodes. */
192 PCDISARMV8OPCODE paOpcodes;
193 /** The mask of fixed instruction bits. */
194 uint32_t fFixedInsn;
195 /** Opcode decoder function. */
196 DISARMV8OPCDECODE enmOpcDecode;
197 /** The mask of the bits relevant for decoding. */
198 uint32_t fMask;
199 /** Number of bits to shift to get an index. */
200 uint32_t cShift;
201 /** The array of decoding steps. */
202 PCDISARMV8INSNPARAM paParms;
203} DISARMV8INSNCLASS;
204/** Pointer to a constant instruction class descriptor. */
205typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
206
207/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
208#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
209/** The instruction class is using the 64-bit register encoding only. */
210#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
211/** The instruction class is using the 32-bit register encoding only. */
212#define DISARMV8INSNCLASS_F_FORCED_32BIT RT_BIT_32(3)
213
214
215#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
216 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
217#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(a_Name) \
218 DIS_ARMV8_INSN_DECODE_TERM \
219 }; \
220 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
221#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
222 DIS_ARMV8_INSN_DECODE_TERM \
223 }; \
224 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
225#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift) \
226 }; \
227 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
228 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
229 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
230 a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
231 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
232
233/**
234 * Decoder lookup table entry.
235 */
236typedef struct DISARMV8DECODETBLENTRY
237{
238 /** The mask to apply to the instruction. */
239 uint32_t fMask;
240 /** The value the masked instruction must match for the entry to match. */
241 uint32_t fValue;
242 /** The next stage followed when there is a match. */
243 PCDISARMV8DECODEHDR pHdrNext;
244} DISARMV8DECODETBLENTRY;
245typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
246typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
247
248
249#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
250 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
251
252
253/**
254 * Decoder lookup table using masks and values.
255 */
256typedef struct DISARMV8DECODETBL
257{
258 /** The header for the decoder lookup table. */
259 DISARMV8DECODEHDR Hdr;
260 /** Pointer to the individual entries. */
261 PCDISARMV8DECODETBLENTRY paEntries;
262} DISARMV8DECODETBL;
263/** Pointer to a const decode table. */
264typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
265
266
267#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
268 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
269
270#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
271 }; \
272 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
273 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
274
275
276/**
277 * Decoder map when direct indexing is possible.
278 */
279typedef struct DISARMV8DECODEMAP
280{
281 /** The header for the decoder map. */
282 DISARMV8DECODEHDR Hdr;
283 /** The bitmask used to decide where to go next. */
284 uint32_t fMask;
285 /** Amount to shift to get at the index. */
286 uint32_t cShift;
287 /** Pointer to the array of pointers to the next stage to index into. */
288 PPCDISARMV8DECODEHDR papNext;
289} DISARMV8DECODEMAP;
290/** Pointer to a const decode map. */
291typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
292
293#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
294 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
295
296#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
297 }; \
298 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
299 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
300
301#define DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(a_Name, a_idxBit) \
302 }; \
303 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
304 RT_BIT_32(a_idxBit), a_idxBit, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
305
306
307#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
308 }; \
309 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
310 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
311
312#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
313#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
314
315
316/** @name Decoder maps.
317 * @{ */
318extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
319
320extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
321/** @} */
322
323
324/** @} */
325#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
326
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