VirtualBox

Changeset 106754 in vbox


Ignore:
Timestamp:
Oct 28, 2024 2:31:35 PM (4 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
165638
Message:

Disassembler: Decode SIMD ldnp/stnp (no allocate register pair) instructions, bugref:10394

Location:
trunk/src/VBox/Disassembler
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp

    r106751 r106754  
    107107static FNDISPARSEARMV8 disArmV8ParseFpFixupFCvt;
    108108static FNDISPARSEARMV8 disArmV8ParseSimdRegSize;
     109static FNDISPARSEARMV8 disArmV8ParseSimdRegSize32;
    109110static FNDISPARSEARMV8 disArmV8ParseSimdRegSize64;
    110111static FNDISPARSEARMV8 disArmV8ParseSimdRegSize128;
    … …  
    165166    disArmV8ParseFpFixupFCvt,
    166167    disArmV8ParseSimdRegSize,
     168    disArmV8ParseSimdRegSize32,
    167169    disArmV8ParseSimdRegSize64,
    168170    disArmV8ParseSimdRegSize128,
    … …  
    681683static int disArmV8ParseSImmMemOff(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
    682684{
    683     RT_NOREF(pDis, pInsnClass, pf64Bit);
     685    RT_NOREF(pInsnClass, pf64Bit);
    684686
    685687    AssertReturn(pInsnParm->cBits <= 7, VERR_INTERNAL_ERROR_2);
    686688    AssertReturn(   (pOp->fFlags & DISARMV8INSNCLASS_F_FORCED_32BIT)
    687                  || (pOp->fFlags & DISARMV8INSNCLASS_F_FORCED_64BIT),
     689                 || (pOp->fFlags & DISARMV8INSNCLASS_F_FORCED_64BIT)
     690                 || pDis->armv8.cbOperand != 0,
    688691                 VERR_INTERNAL_ERROR_2);
    689692    Assert(pParam->armv8.enmType != kDisArmv8OpParmNone);
    … …  
    691694    pParam->armv8.cb = sizeof(int16_t);
    692695    pParam->armv8.u.offBase = disArmV8ExtractBitVecFromInsnSignExtend(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
    693     pParam->armv8.u.offBase <<= (pOp->fFlags & DISARMV8INSNCLASS_F_FORCED_32BIT) ? 2 : 3;
     696
     697    /** @todo Merge DISARMV8INSNCLASS_F_FORCED_32BIT | DISARMV8INSNCLASS_F_FORCED_64BIT into cbOperand. */
     698    if (pDis->armv8.cbOperand)
     699    {
     700        switch (pDis->armv8.cbOperand)
     701        {
     702            case sizeof(uint8_t): break;
     703            case sizeof(uint16_t): pParam->armv8.u.offBase <<= 1; break;
     704            case sizeof(uint32_t): pParam->armv8.u.offBase <<= 2; break;
     705            case sizeof(uint64_t): pParam->armv8.u.offBase <<= 3; break;
     706            case 16:               pParam->armv8.u.offBase <<= 4; break;
     707            default:
     708                AssertReleaseFailed();
     709        }
     710    }
     711    else
     712        pParam->armv8.u.offBase <<= (pOp->fFlags & DISARMV8INSNCLASS_F_FORCED_32BIT) ? 2 : 3;
    694713    return VINF_SUCCESS;
    695714}
    … …  
    898917    }
    899918
     919    return VINF_SUCCESS;
     920}
     921
     922
     923static int disArmV8ParseSimdRegSize32(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
     924{
     925    RT_NOREF(u32Insn, pOp, pInsnClass, pParam, pInsnParm, pf64Bit);
     926
     927    pDis->armv8.cbOperand = sizeof(uint32_t);
    900928    return VINF_SUCCESS;
    901929}

  • trunk/src/VBox/Disassembler/DisasmInternal-armv8.h

    r106746 r106754  
    8585    kDisParmParseFpFixupFCvt,
    8686    kDisParmParseSimdRegSize,
     87    kDisParmParseSimdRegSize32,
    8788    kDisParmParseSimdRegSize64,
    8889    kDisParmParseSimdRegSize128,

  • trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h

    r106752 r106754  
    516516
    517517/*
    518  * stnp/LDNP - no-allocate variant.
     518 * STNP/LDNP - no-allocate variant.
    519519 *
    520520 * Note: The opc,L bitfields are concatenated to form an index.
    … …  
    540540
    541541/*
     542 * SIMD STNP/LDNP - no-allocate variant.
     543 *
     544 * Note: The opc,L bitfields are concatenated to form an index.
     545 */
     546DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairNoAllocSimd)
     547    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize32,       0,  0, DIS_ARMV8_INSN_PARAM_UNSET),
     548    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
     549    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,      10,  5, 1 /*idxParam*/),
     550    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,           5,  5, 2 /*idxParam*/),
     551    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff,         15,  7, 2 /*idxParam*/),
     552DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegPairNoAllocSimd64)
     553    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize64,       0,  0, DIS_ARMV8_INSN_PARAM_UNSET),
     554    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
     555    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,      10,  5, 1 /*idxParam*/),
     556    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,           5,  5, 2 /*idxParam*/),
     557    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff,         15,  7, 2 /*idxParam*/),
     558DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegPairNoAllocSimd128)
     559    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128,      0,  0, DIS_ARMV8_INSN_PARAM_UNSET),
     560    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
     561    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,      10,  5, 1 /*idxParam*/),
     562    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,           5,  5, 2 /*idxParam*/),
     563    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff,         15,  7, 2 /*idxParam*/),
     564DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairNoAllocSimd)
     565    DIS_ARMV8_OP(           0x2c000000, "stnp",            OP_ARMV8_A64_STNP,      DISOPTYPE_HARMLESS),
     566    DIS_ARMV8_OP(           0x2c400000, "ldnp",            OP_ARMV8_A64_LDNP,      DISOPTYPE_HARMLESS),
     567    DIS_ARMV8_OP_ALT_DECODE(0x6c000000, "stnp",            OP_ARMV8_A64_STNP,      DISOPTYPE_HARMLESS, LdStRegPairNoAllocSimd64),
     568    DIS_ARMV8_OP_ALT_DECODE(0x6c400000, "ldnp",            OP_ARMV8_A64_LDNP,      DISOPTYPE_HARMLESS, LdStRegPairNoAllocSimd64),
     569    DIS_ARMV8_OP_ALT_DECODE(0xac000000, "stnp",            OP_ARMV8_A64_STNP,      DISOPTYPE_HARMLESS, LdStRegPairNoAllocSimd128),
     570    DIS_ARMV8_OP_ALT_DECODE(0xac400000, "ldnp",            OP_ARMV8_A64_LDNP,      DISOPTYPE_HARMLESS, LdStRegPairNoAllocSimd128),
     571DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairNoAllocSimd, 0xffc00000 /*fFixedInsn*/,
     572                                       kDisArmV8OpcDecodeCollate,
     573                                       RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22);
     574
     575
     576/*
    542577 * C4.1.94.21 - Loads and Stores - Load/Store register (immediate post-indexed) variants
    543578 *
    … …  
    551586DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPairNoAlloc)
    552587    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAllocGpr),
    553     DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
     588    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAllocSimd),
    554589DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPairNoAlloc, RT_BIT_32(26), 26);
    555590

  • trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

    r106752 r106754  
    15491549
    15501550
     1551        ldnp s0,   s1, [x0]
     1552        ldnp s30, s31, [x0, #-256]
     1553        ldnp s23, s24, [x0, #252]
     1554
     1555        ldnp d0,   d1, [x0]
     1556        ldnp d30, d31, [x0, #-512]
     1557        ldnp d23, d24, [x0, #504]
     1558
     1559        ldnp q0,   q1, [x0]
     1560        ldnp q30, q31, [x0, #-1024]
     1561        ldnp q23, q24, [x0, #1008]
     1562
     1563
    15511564        ; SIMD memory stores
    15521565        str b0, [x0]
    … …  
    17251738        stur q0,  [sp, #-256]
    17261739        stur q31, [sp, #255]
     1740
     1741
     1742        stnp s0,   s1, [x0]
     1743        stnp s30, s31, [x0, #-256]
     1744        stnp s23, s24, [x0, #252]
     1745
     1746        stnp d0,   d1, [x0]
     1747        stnp d30, d31, [x0, #-512]
     1748        stnp d23, d24, [x0, #504]
     1749
     1750        stnp q0,   q1, [x0]
     1751        stnp q30, q31, [x0, #-1024]
     1752        stnp q23, q24, [x0, #1008]
    17271753
    17281754
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette